JP4438489B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4438489B2
JP4438489B2 JP2004117409A JP2004117409A JP4438489B2 JP 4438489 B2 JP4438489 B2 JP 4438489B2 JP 2004117409 A JP2004117409 A JP 2004117409A JP 2004117409 A JP2004117409 A JP 2004117409A JP 4438489 B2 JP4438489 B2 JP 4438489B2
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semiconductor device
power semiconductor
electrode
solder
switch element
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Expired - Fee Related
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JP2005303018A (en
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満男 山下
良成 池田
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富士電機システムズ株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Abstract

<P>PROBLEM TO BE SOLVED: To effectively carry out heat dissipation from upper and lower sides of a package in the package wherein a lamination structure is adopted. <P>SOLUTION: A first parallel connection circuit is constituted between a first conductor substrate 13a and a second conductor substrate 13b by joining the main electrode of a power semiconductor switch element 11Pa and the electrode of a diode 11Pb each, and a second parallel connection circuit is constituted between a second conductor substrate and a third conductor substrate 13c by joining the main electrode of a power semiconductor switch element 11Na and an electrode of a diode 11Nb each. The first parallel connection circuit and the second parallel connection circuit are connected in series via the second conductor substrate. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

  The present invention relates to a semiconductor device such as a power semiconductor module in which a plurality of vertical semiconductor elements are stored in the same package.

Conventionally, a power semiconductor module in which a plurality of power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and FWDs (Free Wheel Diodes) are housed in the same package has mainly had a resin case package structure.
FIG. 3 is a cross-sectional view showing a conventional example of a power semiconductor module. In FIG. 3, the IGBT 11a, the FWD 11b and the external lead-out terminal 22 as power semiconductor elements are formed on the copper pattern 21a on one surface of the insulating substrate 21 formed by bonding the copper patterns 21a, 21b on both surfaces of the ceramic substrate with solder (not shown). It is joined. The power semiconductor element and the external lead-out terminal are connected by a copper pattern or a bonding wire 23. In this manner, the power semiconductor element and the like are mounted on the insulating substrate and stored in the resin case 24, and a filler (not shown) such as resin is injected into the inside as necessary, and then the resin lid 25 is used. cover. Reference numeral 26 denotes a heat dissipation base bonded to the copper pattern 21b on the other surface of the insulating substrate (Patent Document 1).

When the above power semiconductor module is used by being incorporated in an inverter device, for example, when a portion corresponding to one phase of the inverter device is configured as a module, the power semiconductor element is arranged in a plane in the configuration of FIG. The bottom area of the module will increase. Such a power semiconductor module having a large bottom area requires a large mounting area even when incorporated in the inverter device, resulting in an increase in size of the inverter device.
Therefore, a configuration in which power semiconductor elements are stacked has been proposed in order to reduce the area occupied by the power semiconductor module (Patent Document 2).
FIG. 4 is a cross-sectional view showing another conventional example of a power semiconductor module. In FIG. 4, 31 is an insulating substrate in which copper patterns 31a and 31b are joined to one surface of a ceramic substrate, and IGBT 11Na is placed on the copper patterns 31b via solder balls 14 'on the copper patterns 31a and 31b. FWD11Nb is joined through the solder 12, respectively. The copper pattern 31a is connected to the gate electrode of the IGBT 11Na and is connected to a control terminal (not shown).

The other surfaces of the IGBTs 11Na and FWD11Nb are connected to a copper pattern 32b bonded to one surface of the insulating substrate 32 via the solder 12. Copper patterns 32 a and 32 b are bonded to the other surface of the insulating substrate 32, and the copper patterns 32 b on both surfaces are connected via a through hole 32 c formed in the center of the insulating substrate 32.
IGBTs 11Pa are joined to the copper patterns 32a and 32b joined to the other surface of the insulating substrate 32 via solder balls 14 ', and FWD 11Pb is joined to the copper patterns 32b via the solder 12, respectively. The copper pattern 32a is connected to the gate electrode of the IGBT 11Pa, and is connected to a control terminal (not shown). The other surfaces of the IGBT 11Pa and the FWD 11Pb are joined to the metal wiring board 33 via the solder 12.
In this way, by stacking the upper and lower arms for one phase, the occupation area can be reduced to about ½, the mounting area when incorporated in the inverter device can be reduced, and the inverter device can be miniaturized. It becomes.
JP-A-8-213547 JP 2004-22844

Since power semiconductor chips such as IGBT generate heat due to switching or conduction, measures for heat dissipation from the power semiconductor module are indispensable, and heat cycle or Reliability for power cycle is required.
However, in the configuration described in Patent Document 2, the solder ball 14 'is used for connection between the IGBT and the copper pattern of the insulating substrate, and the electrical connection between the upper and lower arms (between both surfaces of the insulating substrate) is further performed. In order to ensure, a through hole 32c is formed in the insulating substrate.
For this reason, the stress due to the difference in thermal expansion coefficient between the power semiconductor chip and the copper pattern or the ceramic substrate is constantly generated in the joining hole by the solder ball 14 ′ and the through hole formed in the insulating substrate as the power semiconductor chip generates heat. As a result, there is a problem that a crack or peeling occurs at a joint portion of the solder ball 14 ′ or a crack occurs in the insulating substrate.

Further, a resin (such as an epoxy resin) that seals the entire package is injected between the IGBT and the insulating substrate. Since a resin having a large thermal resistance is injected into a portion other than the solder ball 14 'between the power semiconductor chip and the insulating substrate, heat radiation from the insulating substrate side of the package is limited, and sufficient heat radiation can be performed. Therefore, the power semiconductor chip cannot be used up.
In the configuration of Patent Document 2, since the degree of integration in the package is increased and the heat generation density is increased by adopting the laminated structure, sufficient cooling cannot be performed even though heat dissipation (cooling) measures are indispensable. Therefore, there is a problem that it is difficult to ensure long-term reliability of the joint. In particular, heat dissipation becomes a serious problem in a resin-sealed package having a low thermal conductivity.
The present invention has been made in view of the problems in the power semiconductor module described above, and an object of the present invention is to efficiently dissipate heat from the upper and lower surfaces of the semiconductor chip and from the upper and lower surfaces of the package in a package employing a laminated structure. Is.

In order to solve the above-described problems, the present invention provides a first parallel connection circuit in which a main electrode of a power semiconductor switch element and an electrode of a diode are respectively joined between a first metal bar and a second metal bar. A second parallel connection circuit is formed by joining the main electrode of the power semiconductor switching element and the electrode of the diode between the second metal bar and the third metal bar, respectively. And a second parallel connection circuit connected in series via the second metal bar, the first and third metal bars serving as DC input terminals, and the second metal bar serving as an output terminal der, via an insulating layer on the surface of the second conductive plate forming a gate wiring pattern to the gate lines, used to connect the gate electrode of the power semiconductor switching element in the first parallel circuit Oh Ru.
In the above configuration, the first, second, and third metal bars are metal plates, or the first and third metal bars are insulating substrates in which metal foils are bonded to both surfaces of a ceramic substrate. The conductor plate may be a metal plate.

  Furthermore, a region sandwiched between the first metal bar and the third metal bar, where the power semiconductor switch element and the diode are joined, may be sealed with resin.

  According to the power semiconductor module of the present invention, the area of the package can be reduced to about ½ of the conventional size by adopting a structure in which the power semiconductor chips constituting the upper and lower arms are sandwiched between the metal bars. Further, heat can be radiated with high efficiency from the upper and lower surfaces of the power semiconductor chip and the upper and lower surfaces of the package, and a highly reliable semiconductor device can be supplied.

  The present invention will be described below based on the embodiments shown in the drawings.

FIG. 1 is a cross-sectional view showing a first embodiment of the power semiconductor module of the present invention. In FIG. 1, 11 Pa and 11 Na are IGBTs, 11 Pb and 11 Nb are FWDs, and are joined to metal bars 13 a to 13 c via solder 12 and metal balls 14. Cu, Al, Fe, or alloys thereof are used as the metal bar material. The metal ball 14 includes a metal core having a melting point higher than that of the solder 12, a metal core solder ball having a metal core coated with solder, or a simple solder ball. The one using a metal core is advantageous in that a desired solder thickness is ensured. Hereinafter, these are collectively referred to as a metal ball 14.
The collector electrode of IGBT11Pa and the cathode electrode of FWD11Pb are soldered to the metal bar 13a, and the IGBT11Pa emitter electrode and FWD11Pb anode electrode are also soldered to the metal bar 13b. At this time, Sn solder is used as the solder, and the gate electrode of the IGBT 11Pa is soldered to the gate wiring (not shown) on the metal bar 13b via the metal ball. The gate wiring may be formed by applying a resin such as polyimide on the surface of the metal bar 13b to form an insulating layer of about 200 μm and patterning the insulating layer with a copper foil or the like. In addition, you may use a thin plate-shaped heat pipe as the metal bar 13b. By using the heat pipe, the heat inside the power semiconductor module can be effectively released.

The collector electrode of the IGBT 11Na and the cathode electrode of the FWD 11Nb are soldered to the metal bar 13b, and the emitter electrode and the anode electrode are similarly soldered to the metal bar 13c. At this time, Sn solder is used as the solder, and the gate electrode of the IGBT 11Na is soldered to the gate wiring (not shown) on the metal bar 13c via the metal ball.
The gate wiring may be formed of copper foil or the like through an insulating layer, similar to that formed on the surface of the metal bar 13b, or a metal used in discrete products. A lead frame-like metal bar 13b obtained by punching a plate may be used. Since the pattern corresponding to the gate wiring is also punched, an insulating layer on the metal bar 13b is unnecessary. What is necessary is just to cut | disconnect an outer lead part in a desired shape after the below-mentioned resin sealing.

Next, the assembly method will be briefly described. Cream solder is applied to a predetermined portion of the metal bar 13a, or IGBTs 11Pa and FWD11Pb are placed via a solder sheet, and this laminated body is put into a heating furnace to melt and solidify the solder to join them. A jig (not shown) may be used so that the IGBT 11Pa and FWD11Pb do not shift when the solder is melted. Similarly, IGBT11Na and FWD11Nb are joined to the metal bar 13c.
Subsequently, cream solder is applied to predetermined positions on both surfaces of the metal bar 13b, or between the joined body of the metal bar 13a and the IGBT 11Pa, FWD11Pb and the joined body of the metal bar 13c and the IGBT 11Na, FWD11Nb via a solder sheet. Is inserted into the heating furnace again, and the solder on both sides of the metal bar 13b is melted and solidified to complete all joining. The solder used for joining the metal bars 13b may have a lower melting point than the solder used for joining the metal bars 13a and 13c.

As described above, after joining the IGBT 11a and FWD 11b to the metal bars 13a and 13c first, and joining them to the metal bar 13b, the positioning jig used for the assembly can be made simple, It becomes easy to fix the semiconductor chip to a predetermined portion of the metal bars 13a and 13c, and the assembly accuracy can be improved.
Alternatively, all the solder joints may be performed at the same time with the solder used for each joint having the same melting point. Although the positioning jig used for assembly is slightly complicated, the solder joining process can be completed in one time, and the productivity can be improved.
Subsequently, the laminated body in which the above-described solder bonding is completed is fitted into a sealing mold, and a sealing resin 15 such as a molten epoxy resin is poured. A region between the metal bars 13a and 13c and where the semiconductor chip is mounted is sealed. At this time, if the surfaces of the metal bars 13a and 13c that are not soldered are exposed, the heat generated by the semiconductor chip can be easily released from the exposed surfaces.

As described above, the IGBT 11Pa and FWD11Pb and the IGBT 11Na and FWD11Nb are stacked between the metal bars 13a and 13c through the metal bar 13b, and the upper (positive electrode side) arm on the IGBT 11Pa and FWD11Pb, and the lower (negative electrode side) on the IGBT 11Na and FWD11Nb. A power semiconductor module (two-packed laminated package) for one phase is constructed, with the arm configured as a DC input (positive electrode) for the metal bar 13a, an AC output for the metal bar 13b, and a DC input (negative electrode) for the metal bar 13c. To do.
When such a package is used in an inverter device or the like, the exposed surfaces of the metal bars 13a and 13c are joined to the heat radiating fins 17 via the heat radiating sheet 16 having insulation and high thermal conductivity. If an adhesive thing is used for the heat-radiation sheet 16, the heat-radiation fin 17 can be attached easily.

FIG. 2 is a cross-sectional view showing a second embodiment of the power semiconductor module of the present invention. In FIG. 2, 18 and 19 are insulating substrates in which copper patterns 18a, 18b, 19a and 19b as metal foils are bonded to both surfaces of a ceramic substrate. Copper patterns 18a and 19a on one surface of insulating substrates 18 and 19 are formed as circuit patterns. Direct bonding may be used for bonding the ceramic substrate and the metal foil, or bonding may be performed via a brazing material.
The collector electrode of IGBT 11Pa, the cathode electrode of FWD11Pb, and the metal bar 13d serving as the DC input terminal (P) are soldered to the copper pattern 18a of the insulating substrate 18, and the IGBT 11Pa emitter electrode and the FWD11Pb anode electrode are similarly soldered to the metal bar 13b. Be joined. At this time, Sn solder is used as the solder, and the gate electrode of the IGBT 11Pa is soldered to the gate wiring (not shown) on the metal bar 13b via the metal ball. The gate wiring may be formed by applying a resin such as polyimide on the surface of the metal bar 13b to form an insulating layer of about 200 μm and patterning the insulating layer with a copper foil or the like. In addition, you may use a thin plate-shaped heat pipe as the metal bar 13b. By using the heat pipe, the heat inside the power semiconductor module can be effectively released.

The collector electrode of the IGBT 11Na and the cathode electrode of the FWD 11Nb are soldered to the metal bar 13b, and the metal bar 13e, which also becomes the IGBT 11Na emitter electrode, the FWD 11Nb anode electrode, and the DC input terminal (N), is soldered to the copper pattern 19a of the insulating substrate 19. Be joined. At this time, Sn solder is used as the solder, and the gate electrode of the IGBT 11Na is soldered to the copper pattern 19a ′ of the insulating substrate 19 via the metal ball 14.
The portion corresponding to the gate of the IGBT 11Na is not shown in the drawing of the lead-out portion to the outside of the power semiconductor module, but can be pulled out freely by forming a circuit pattern on the insulating substrate 19, and when a lead frame is used. Compared to it, the degree of freedom in design is high.
The method of assembling the power semiconductor module of the second embodiment is the same as that of the first embodiment. The cream is obtained by applying IGBT 11Pa, FWD11Pb, and metal bar 13d on the copper pattern 18a of the insulating substrate 18 at predetermined positions. It mounts via a solder or a solder sheet | seat, this laminated body is each put into a heating furnace, a solder is fuse | melted and solidified and it joins. A jig (not shown) may be used so that the IGBT 11Pa, FWD11Pb, and the metal bar 13d are not smeared when the solder is melted. Similarly, IGBT11Na, FWD11Nb, and metal bar 13e are joined on the copper pattern 19a of the insulating substrate 19.

Subsequently, cream solder is applied to predetermined positions on both sides of the metal bar 13b, or is inserted between the joined body of the insulating substrate 18 and the joined body of the insulating substrate 19 via a solder sheet, and again put into the heating furnace. Then, the solder on both sides of the metal bar 13b is melted and solidified to complete all the joining. The solder used for joining the metal bars 13b may have a lower melting point than the solder used for joining the metal bars 13a and 13c.
As described above, the soldering of the insulating substrate 18 side (upper arm side) and the insulating substrate 19 side (lower arm side) is completed in advance, so that the positioning jig used for assembly can have a simple configuration. The joining accuracy of the chip and the conductor plate can be improved.
Alternatively, solder having the same melting point may be used, and all solder joints may be performed simultaneously. In this case, since the solder joining process can be completed at once, productivity can be improved.

Subsequently, the laminated body in which the above-described solder bonding is completed is fitted into a sealing mold, and a sealing resin 15 such as a molten epoxy resin is poured. A region sandwiched between the insulating substrates 18 and 19 and having a semiconductor chip mounted thereon is sealed. At this time, if the copper patterns 18b and 19b of the insulating substrates 18 and 19 are exposed, the heat generated by the semiconductor chip is easily released from the exposed surface.
Thus, IGBT11Pa, FWD11Pb and IGBT11Na, FWD11Nb are stacked between insulating substrates 18 and 19 via metal bar 13b, and the upper (positive electrode side) arm is formed by IGBT11Pa and FWD11Pb, and the negative electrode side arm is formed by IGBT11Na and FWD11Nb. A power semiconductor module (a two-layer stacked package) for one phase in which the metal bar 13d is a DC input (positive electrode), the metal bar 13b is an AC output, and the metal bar 13e is a DC input (negative electrode). .

Since an insulating substrate is used, the exposed surfaces (copper patterns 18b and 19b) of the insulating substrate are kept insulated from the inside. For this reason, when using such a package by incorporating it in an inverter device or the like, the heat dissipation sheet used in the first embodiment is not necessary. When attaching the radiating fins 17, screw holes (not shown) for fixing the radiating fins may be provided in the sealed resin portion. A desired strength can be obtained by press-fitting a metal tube into the screw hole or integrally forming the resin tube. Alternatively, the power semiconductor module may be sandwiched between the radiating fins on the insulating substrate 18 side and the radiating fins on the insulating substrate 19 side, and the radiating fins may be fixed to each other.
In each of the above-described embodiments, each bonding is performed by soldering. However, the bonding method is not limited to this as long as it is a bonding method for achieving electrical, thermal, and mechanical connection. For example, in Example 1, the metal bars 13a and 13c and the IGBTs 11a and FWD11b are joined by solder. Similarly, in Example 2, the copper patterns 18a and 19a of the insulating substrates 18 and 19 and the IGBTs 11Pa, FWD11Pb, IGBT11Na, The FWD 11Nb and the metal bars 13d and 13e are joined by soldering, but ultrasonic joining may be employed instead of solder joining.

It is sectional drawing which shows the 1st Example of a power semiconductor module. It is sectional drawing which shows the 2nd Example of a power semiconductor module. It is sectional drawing which shows a 1st prior art example. It is sectional drawing which shows a 2nd prior art example.

Explanation of symbols

11a, 11Na, 11Pa IGBT
11b, 11Nb, 11Pb FWD
12 Solder 13a, 13b, 13c, 13d, 13e Metal bar 14 Metal 15 Sealing resin 16 Heat radiation sheet 17 Heat radiation fin 18, 19, 21, 31, 32 Insulating substrate 22 External lead-out terminal 23 Bonding wire 24 Resin case 25 Lid 26 Heat radiation Base 21a, 21b, 31a, 31b Copper pattern 32c Through hole 33 Metal wiring board

Claims (7)

  1. A first parallel connection circuit is formed by bonding a main electrode of a power semiconductor switch element and an electrode of a diode between the first conductor substrate and the second conductor substrate,
    A main parallel electrode of the power semiconductor switch element and an electrode of the diode are respectively joined between the second conductor substrate and the third conductor substrate to constitute a second parallel connection circuit,
    A first parallel connection circuit and a second parallel connection circuit are connected in series via the second conductive substrate,
    In the semiconductor device having the first and third conductor substrates as DC input terminals and the second conductor substrate as an output terminal ,
    A gate wiring pattern is formed on the surface of the second conductor plate via an insulating layer, and a gate electrode of a power semiconductor switch element in the first parallel circuit is connected to the gate wiring pattern. apparatus.
  2.   2. The semiconductor device according to claim 1, wherein the first, second and third conductor substrates are metal plates.
  3.   2. The semiconductor device according to claim 1, wherein the first and third conductive substrates are insulating substrates obtained by bonding metal foils to both surfaces of a ceramic substrate, and the second conductive plate is a metal plate. Semiconductor device.
  4.   4. The semiconductor device according to claim 3, wherein a gate wiring pattern is formed on a metal foil on a bonding surface side of the power semiconductor switch element of a ceramic substrate which is a third conductor plate, and the power semiconductor in the second parallel circuit is formed. A semiconductor device characterized by connecting a gate electrode of a switch element.
  5.   2. The semiconductor device according to claim 1, wherein a region sandwiched between the first conductor substrate and the third conductor substrate, in which the power semiconductor switch element and the diode are joined, is resin-sealed. A semiconductor device.
  6.   5. The semiconductor device according to claim 1, wherein a main electrode of the power semiconductor switch element and an electrode of the diode are solder-bonded to the first, second, and third conductive substrates. 6. Because
      The gate wiring and the gate electrode are connected by a metal core having any one of a metal core having a melting point higher than that of the solder, a metal core solder ball coated with solder around the metal core, and a solder ball. A semiconductor device.
  7.   3. The semiconductor device according to claim 2, wherein a surface of the first and third conductor plates opposite to the joint surface of the power semiconductor switch element is respectively provided with a heat dissipation sheet having insulating properties and thermal conductivity. A semiconductor device comprising a radiation fin.
JP2004117409A 2004-04-13 2004-04-13 Semiconductor device Expired - Fee Related JP4438489B2 (en)

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Cited By (1)

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