JP4438489B2 - Semiconductor device - Google Patents

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JP4438489B2
JP4438489B2 JP2004117409A JP2004117409A JP4438489B2 JP 4438489 B2 JP4438489 B2 JP 4438489B2 JP 2004117409 A JP2004117409 A JP 2004117409A JP 2004117409 A JP2004117409 A JP 2004117409A JP 4438489 B2 JP4438489 B2 JP 4438489B2
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semiconductor
power semiconductor
electrode
solder
metal
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JP2005303018A (en
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満男 山下
良成 池田
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富士電機システムズ株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Abstract

<P>PROBLEM TO BE SOLVED: To effectively carry out heat dissipation from upper and lower sides of a package in the package wherein a lamination structure is adopted. <P>SOLUTION: A first parallel connection circuit is constituted between a first conductor substrate 13a and a second conductor substrate 13b by joining the main electrode of a power semiconductor switch element 11Pa and the electrode of a diode 11Pb each, and a second parallel connection circuit is constituted between a second conductor substrate and a third conductor substrate 13c by joining the main electrode of a power semiconductor switch element 11Na and an electrode of a diode 11Nb each. The first parallel connection circuit and the second parallel connection circuit are connected in series via the second conductor substrate. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

この発明は、複数の縦型半導体素子を同一のパッケージに格納したパワー半導体モジュールなどの半導体装置に関する。   The present invention relates to a semiconductor device such as a power semiconductor module in which a plurality of vertical semiconductor elements are stored in the same package.

IGBT(Insulated Gate bipolar Transistor)やFWD(Free Wheel Diode)などのパワー半導体素子を複数個同一のパッケージに収納してなるパワー半導体モジュールでは、従来は樹脂ケースのパッケージ構造が主であった。
図3は、パワー半導体モジュールの従来例を示す断面図である。図3において、セラミック基板の両面に銅パターン21a,21bを接合してなる絶縁基板21の一方の面の銅パターン21a上に、パワー半導体素子としてIGBT11a,FWD11b並びに外部導出端子22を図示しないはんだで接合している。パワー半導体素子と外部導出端子との間は、銅パターン若しくはボンディングワイヤ23で接続されている。このように、絶縁基板上にパワー半導体素子などを搭載した状態で樹脂ケース24に格納し、必要に応じて内部に樹脂等の充填材(図示せず)を注入した後、樹脂の蓋25で覆う。26は絶縁基板の他方の面の銅パターン21bに接合された放熱ベースである(特許文献1)。
Conventionally, a power semiconductor module in which a plurality of power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and FWDs (Free Wheel Diodes) are housed in the same package has mainly had a resin case package structure.
FIG. 3 is a cross-sectional view showing a conventional example of a power semiconductor module. In FIG. 3, the IGBT 11a, the FWD 11b and the external lead-out terminal 22 as power semiconductor elements are formed on the copper pattern 21a on one surface of the insulating substrate 21 formed by bonding the copper patterns 21a, 21b on both surfaces of the ceramic substrate with solder (not shown). It is joined. The power semiconductor element and the external lead-out terminal are connected by a copper pattern or a bonding wire 23. In this manner, the power semiconductor element and the like are mounted on the insulating substrate and stored in the resin case 24, and a filler (not shown) such as resin is injected into the inside as necessary, and then the resin lid 25 is used. cover. Reference numeral 26 denotes a heat dissipation base bonded to the copper pattern 21b on the other surface of the insulating substrate (Patent Document 1).

上記のパワー半導体モジュールをインバータ装置に組み込んで用いる場合、例えばインバータ装置の1相分に相当する部分をモジュールとして構成すると、図3の構成では、パワー半導体素子を平面的に配置するため、パワー半導体モジュールの底面積が大きくなってしまう。このような底面積の大きなパワー半導体モジュールはインバータ装置に組み込む際においても大きな取り付け面積を必要とするため、結果としてインバータ装置の大型化を招いてしまう。
そこで、パワー半導体モジュールの占有面積を縮小するために、パワー半導体素子を積層する構成が提案されている(特許文献2)。
図4は、パワー半導体モジュールの別の従来例を示す断面図である。図4において、31は、セラミック基板の一方の面に銅パターン31a,31bが接合された絶縁基板であり、銅パターン31a,31b上にはんだボール14’を介してIGBT11Naが、銅パターン31b上にはんだ12を介してFWD11Nbがそれぞれ接合されている。銅パターン31aはIGBT11Naのゲート電極に接続され、図示しない制御端子に接続されている。
When the above power semiconductor module is used by being incorporated in an inverter device, for example, when a portion corresponding to one phase of the inverter device is configured as a module, the power semiconductor element is arranged in a plane in the configuration of FIG. The bottom area of the module will increase. Such a power semiconductor module having a large bottom area requires a large mounting area even when incorporated in the inverter device, resulting in an increase in size of the inverter device.
Therefore, a configuration in which power semiconductor elements are stacked has been proposed in order to reduce the area occupied by the power semiconductor module (Patent Document 2).
FIG. 4 is a cross-sectional view showing another conventional example of a power semiconductor module. In FIG. 4, 31 is an insulating substrate in which copper patterns 31a and 31b are joined to one surface of a ceramic substrate, and IGBT 11Na is placed on the copper patterns 31b via solder balls 14 'on the copper patterns 31a and 31b. FWD11Nb is joined through the solder 12, respectively. The copper pattern 31a is connected to the gate electrode of the IGBT 11Na and is connected to a control terminal (not shown).

IGBT11Na,FWD11Nbの他方の面ははんだ12を介して絶縁基板32の一方の面に接合された銅パターン32bに接続されている。絶縁基板32の他方の面には銅パターン32a,32bが接合されていて、両面の銅パターン32bは、絶縁基板32の中央に形成されたスルーホール32cを介して接続されている。
絶縁基板32の他方の面に接合された銅パターン32a,32bにははんだボール14’を介してIGBT11Paが、同じく銅パターン32bにははんだ12を介してFWD11Pbがそれぞれ接合されている。銅パターン32aはIGBT11Paのゲート電極に接続され、図示しない制御端子に接続されている。IGBT11PaとFWD11Pbの他方の面ははんだ12を介して金属配線板33に接合されている。
このように、1相分の上下アームを積層することによって、占有面積を約1/2とすることができ、インバータ装置に組み込む際の取り付け面積を縮小し、インバータ装置を小型化することが可能となる。
特開平8-213547号公報 特開2004-22844号公報
The other surfaces of the IGBTs 11Na and FWD11Nb are connected to a copper pattern 32b bonded to one surface of the insulating substrate 32 via the solder 12. Copper patterns 32 a and 32 b are bonded to the other surface of the insulating substrate 32, and the copper patterns 32 b on both surfaces are connected via a through hole 32 c formed in the center of the insulating substrate 32.
IGBTs 11Pa are joined to the copper patterns 32a and 32b joined to the other surface of the insulating substrate 32 via solder balls 14 ', and FWD 11Pb is joined to the copper patterns 32b via the solder 12, respectively. The copper pattern 32a is connected to the gate electrode of the IGBT 11Pa, and is connected to a control terminal (not shown). The other surfaces of the IGBT 11Pa and the FWD 11Pb are joined to the metal wiring board 33 via the solder 12.
In this way, by stacking the upper and lower arms for one phase, the occupation area can be reduced to about ½, the mounting area when incorporated in the inverter device can be reduced, and the inverter device can be miniaturized. It becomes.
JP-A-8-213547 JP 2004-22844

IGBT等のパワー半導体チップは、スイッチングや導通により発熱するため、パワー半導体モジュールからの放熱対策が欠かせず、また、パワー半導体チップと回路パターンなどの他の部材との接合個所にはヒートサイクルやパワーサイクルに対する信頼性が求められる。
しかしながら、特許文献2に記載された構成では、IGBTと絶縁基板の銅パターンとの間の接続にはんだボール14’が用いられていて、さらに上下アーム(絶縁基板の両面間)の電気的接続を確保するために、絶縁基板内にスルーホール32cを形成している。
このため、はんだボール14’による接合個所並びに絶縁基板に形成されたスルーホールには、パワー半導体チップの発熱に伴い、パワー半導体チップと銅パターンあるいはセラミック基板との熱膨張係数の相違による応力が絶えず印加されることになり、はんだボール14’の接合個所の亀裂,剥がれが生じる問題や、絶縁基板に亀裂が発生する問題がある。
Since power semiconductor chips such as IGBT generate heat due to switching or conduction, measures for heat dissipation from the power semiconductor module are indispensable, and heat cycle or Reliability for power cycle is required.
However, in the configuration described in Patent Document 2, the solder ball 14 'is used for connection between the IGBT and the copper pattern of the insulating substrate, and the electrical connection between the upper and lower arms (between both surfaces of the insulating substrate) is further performed. In order to ensure, a through hole 32c is formed in the insulating substrate.
For this reason, the stress due to the difference in thermal expansion coefficient between the power semiconductor chip and the copper pattern or the ceramic substrate is constantly generated in the joining hole by the solder ball 14 ′ and the through hole formed in the insulating substrate as the power semiconductor chip generates heat. As a result, there is a problem that a crack or peeling occurs at a joint portion of the solder ball 14 ′ or a crack occurs in the insulating substrate.

また、IGBTと絶縁基板との間にはパッケージ全体を封止する樹脂(エポキシ系の樹脂など)が注入される。パワー半導体チップと絶縁基板との間のはんだボール14’以外の部分には熱抵抗が大きい樹脂が注入されるため、パッケージの絶縁基板側からの放熱が制限され、十分な放熱を行うことができず、パワー半導体チップの能力を使い切ることができない。
特許文献2の構成では、積層構造を採用することによってパッケージ内の集積度が高まり発熱密度が上昇しているため、放熱(冷却)対策が必要不可欠であるにもかかわらず、十分な冷却ができないため、接合部の長期信頼性を確保することが難しいという課題がある。特に熱伝導率が低い樹脂封止パッケージでは放熱は大きな問題となる。
この発明は、上記のパワー半導体モジュールにおける課題に鑑みてなされたものであって、積層構造を採用するパッケージにおいて半導体チップの上下面並びにパッケージの上下面からの放熱を効率良く行うことを課題とするものである。
Further, a resin (such as an epoxy resin) that seals the entire package is injected between the IGBT and the insulating substrate. Since a resin having a large thermal resistance is injected into a portion other than the solder ball 14 'between the power semiconductor chip and the insulating substrate, heat radiation from the insulating substrate side of the package is limited, and sufficient heat radiation can be performed. Therefore, the power semiconductor chip cannot be used up.
In the configuration of Patent Document 2, since the degree of integration in the package is increased and the heat generation density is increased by adopting the laminated structure, sufficient cooling cannot be performed even though heat dissipation (cooling) measures are indispensable. Therefore, there is a problem that it is difficult to ensure long-term reliability of the joint. In particular, heat dissipation becomes a serious problem in a resin-sealed package having a low thermal conductivity.
The present invention has been made in view of the problems in the power semiconductor module described above, and an object of the present invention is to efficiently dissipate heat from the upper and lower surfaces of the semiconductor chip and from the upper and lower surfaces of the package in a package employing a laminated structure. Is.

前記の課題を解決するため、この発明は、第1の金属バーと第2の金属バーとの間にパワー半導体スイッチ素子の主電極ならびにダイオードの電極をそれぞれ接合して第1の並列接続回路を構成し、第2の金属バーと第3の金属バーとの間にパワー半導体スイッチ素子の主電極ならびにダイオードの電極をそれぞれ接合して第2の並列接続回路を構成し、第1の並列接続回路と第2の並列接続回路とを、前記第2の金属バーを介して直列接続し、前記第1,第3の金属バーを直流入力端子とし、該第2の金属バーを出力端子とするものであって、前記第2の導体板の表面に絶縁層を介してゲート配線パターンを形成し、該ゲート配線に、前記第1の並列回路におけるパワー半導体スイッチ素子のゲート電極を接続するものである。
上記の構成において、前記第1,第2,第3の金属バーを金属板とするか、前記第1,第3の金属バーをセラミック基板の両面に金属箔を接合した絶縁基板,第2の導体板を金属板とするとよい。
In order to solve the above-described problems, the present invention provides a first parallel connection circuit in which a main electrode of a power semiconductor switch element and an electrode of a diode are respectively joined between a first metal bar and a second metal bar. A second parallel connection circuit is formed by joining the main electrode of the power semiconductor switching element and the electrode of the diode between the second metal bar and the third metal bar, respectively. And a second parallel connection circuit connected in series via the second metal bar, the first and third metal bars serving as DC input terminals, and the second metal bar serving as an output terminal der, via an insulating layer on the surface of the second conductive plate forming a gate wiring pattern to the gate lines, used to connect the gate electrode of the power semiconductor switching element in the first parallel circuit Oh Ru.
In the above configuration, the first, second, and third metal bars are metal plates, or the first and third metal bars are insulating substrates in which metal foils are bonded to both surfaces of a ceramic substrate. The conductor plate may be a metal plate.

さらに、前記第1の金属バーと第3の金属バーとに挟まれた領域であって、前記パワー半導体スイッチ素子および前記ダイオードが接合された部分を樹脂封止するとよい。   Furthermore, a region sandwiched between the first metal bar and the third metal bar, where the power semiconductor switch element and the diode are joined, may be sealed with resin.

この発明のパワー半導体モジュールによれば、上下アームを構成するパワー半導体チップを金属バーで挟み込む構造とすることでパッケージの面積を従来の1/2程度まで小型化することができる。また、パワー半導体チップの上下面並びにパッケージの上下面から高効率に放熱を行うことができ、信頼性の高い半導体デバイスの供給が可能となる。   According to the power semiconductor module of the present invention, the area of the package can be reduced to about ½ of the conventional size by adopting a structure in which the power semiconductor chips constituting the upper and lower arms are sandwiched between the metal bars. Further, heat can be radiated with high efficiency from the upper and lower surfaces of the power semiconductor chip and the upper and lower surfaces of the package, and a highly reliable semiconductor device can be supplied.

以下にこの発明を、図に示す実施例に基づいて説明する。   The present invention will be described below based on the embodiments shown in the drawings.

図1はこの発明のパワー半導体モジュールの第1の実施例を示す断面図である。図1において、11Pa,11NaはIGBT、11Pb,11NbはFWDであって、はんだ12,金属ボール14を介して金属バー13a〜13cに接合されている。金属バーの材質としてCu,Al,Feあるいはこれらの合金などを用いる。なお、金属ボール14ははんだ12よりも融点の高い金属コアや、金属コアの周囲にはんだを被覆した金属コアはんだボール、あるいは単なるはんだボールを含む。金属コアを用いたものは、所望のはんだ厚を確保する点で有利である。以下において、これらを金属ボール14と総称する。
IGBT11Paのコレクタ電極とFWD11Pbのカソード電極は金属バー13aにはんだ接合され、同じくIGBT11Paエミッタ電極とFWD11Pbアノード電極は金属バー13bにはんだ接合される。このとき、上記はんだにはSn系のはんだを用い、IGBT11Paのゲート電極は金属ボール14を介して金属バー13b上のゲート配線(図示せず)にはんだ接合される。このゲート配線は金属バー13bの表面に例えばポリイミドなどの樹脂を塗布して200μm程度絶縁層を形成し、該絶縁層上に銅箔等でパターニングして形成すればよい。なお、金属バー13bとして薄板状のヒートパイプを用いてもよい。ヒートパイプを用いることにより、パワー半導体モジュール内部の熱を効果的に放出することができる。
FIG. 1 is a cross-sectional view showing a first embodiment of the power semiconductor module of the present invention. In FIG. 1, 11 Pa and 11 Na are IGBTs, 11 Pb and 11 Nb are FWDs, and are joined to metal bars 13 a to 13 c via solder 12 and metal balls 14. Cu, Al, Fe, or alloys thereof are used as the metal bar material. The metal ball 14 includes a metal core having a melting point higher than that of the solder 12, a metal core solder ball having a metal core coated with solder, or a simple solder ball. The one using a metal core is advantageous in that a desired solder thickness is ensured. Hereinafter, these are collectively referred to as a metal ball 14.
The collector electrode of IGBT11Pa and the cathode electrode of FWD11Pb are soldered to the metal bar 13a, and the IGBT11Pa emitter electrode and FWD11Pb anode electrode are also soldered to the metal bar 13b. At this time, Sn solder is used as the solder, and the gate electrode of the IGBT 11Pa is soldered to the gate wiring (not shown) on the metal bar 13b via the metal ball. The gate wiring may be formed by applying a resin such as polyimide on the surface of the metal bar 13b to form an insulating layer of about 200 μm and patterning the insulating layer with a copper foil or the like. In addition, you may use a thin plate-shaped heat pipe as the metal bar 13b. By using the heat pipe, the heat inside the power semiconductor module can be effectively released.

また、IGBT11Naのコレクタ電極とFWD11Nbのカソード電極は金属バー13bにはんだ接合され、同じくエミッタ電極とアノード電極は金属バー13cにはんだ接合される。このとき、上記はんだにはSn系のはんだを用い、IGBT11Naのゲート電極は金属ボール14を介して金属バー13c上のゲート配線(図示せず)にはんだ接合される。
なお、上記ゲート配線は、上述の金属バー13bの表面に形成したものと同様に、絶縁層を介して銅箔等で形成してもよいし、あるいは、ディスクリート製品で使用されているような金属板を打ち抜き加工したリードフレーム状の金属バー13bを用いてもよい。ゲート配線に相当するパターンも打ち抜き加工されているので、金属バー13b上の絶縁層は不要である。後述の樹脂封止の後、所望の形状にアウターリード部を切断すればよい。
The collector electrode of the IGBT 11Na and the cathode electrode of the FWD 11Nb are soldered to the metal bar 13b, and the emitter electrode and the anode electrode are similarly soldered to the metal bar 13c. At this time, Sn solder is used as the solder, and the gate electrode of the IGBT 11Na is soldered to the gate wiring (not shown) on the metal bar 13c via the metal ball.
The gate wiring may be formed of copper foil or the like through an insulating layer, similar to that formed on the surface of the metal bar 13b, or a metal used in discrete products. A lead frame-like metal bar 13b obtained by punching a plate may be used. Since the pattern corresponding to the gate wiring is also punched, an insulating layer on the metal bar 13b is unnecessary. What is necessary is just to cut | disconnect an outer lead part in a desired shape after the below-mentioned resin sealing.

次に、組立方法について簡単に説明する。金属バー13aの所定個所にクリームはんだを塗布し、あるいははんだシートを介してIGBT11Pa,FWD11Pbを載置し、この積層体を加熱炉に投入してはんだを溶融・固化させて両者を接合する。はんだ溶融時にIGBT11PaやFWD11Pbがずれないよう、図示しない治具を用いるとよい。同様に金属バー13cにIGBT11Na,FWD11Nbを接合する。
つづいて、金属バー13bの両面の所定個所にクリームはんだを塗布し、あるいははんだシートを介して、金属バー13aとIGBT11Pa,FWD11Pbの接合体と、金属バー13cとIGBT11Na,FWD11Nbの接合体との間に介挿し、再び加熱炉に投入して金属バー13bの両面のはんだを溶融・固化させてすべての接合を完了させる。金属バー13bの接合に用いるはんだは、金属バー13a,13cの接合に用いたはんだより融点の低いものを用いるとよい。
Next, the assembly method will be briefly described. Cream solder is applied to a predetermined portion of the metal bar 13a, or IGBTs 11Pa and FWD11Pb are placed via a solder sheet, and this laminated body is put into a heating furnace to melt and solidify the solder to join them. A jig (not shown) may be used so that the IGBT 11Pa and FWD11Pb do not shift when the solder is melted. Similarly, IGBT11Na and FWD11Nb are joined to the metal bar 13c.
Subsequently, cream solder is applied to predetermined positions on both surfaces of the metal bar 13b, or between the joined body of the metal bar 13a and the IGBT 11Pa, FWD11Pb and the joined body of the metal bar 13c and the IGBT 11Na, FWD11Nb via a solder sheet. Is inserted into the heating furnace again, and the solder on both sides of the metal bar 13b is melted and solidified to complete all joining. The solder used for joining the metal bars 13b may have a lower melting point than the solder used for joining the metal bars 13a and 13c.

上記のように、先に、金属バー13a,13cへIGBT11a,FWD11bを接合した後、両者を金属バー13bに接合することにより、組立に用いる位置決め治具を簡単な構成とすることができ、各半導体チップを金属バー13a,13cの所定の個所に固定することが容易となり、組立精度を向上させることができる。
あるいは、各接合に用いるはんだを同融点として、すべてのはんだ接合を同時に行ってもよい。組立に用いる位置決め治具が若干複雑になるものの、はんだ接合工程を1回で完了させることができ、生産性を向上させることができる。
つづいて、上記のはんだ接合が完了した積層体を封止型に嵌装し、溶融したエポキシ樹脂などの封止樹脂15を流し込む。金属バー13aと13cとの間であって、半導体チップが実装された領域を封止する。このとき、金属バー13a,13cのはんだ接合されていない面を露出するようにすると、半導体チップが発生する熱を露出面より放出しやすくなる。
As described above, after joining the IGBT 11a and FWD 11b to the metal bars 13a and 13c first, and joining them to the metal bar 13b, the positioning jig used for the assembly can be made simple, It becomes easy to fix the semiconductor chip to a predetermined portion of the metal bars 13a and 13c, and the assembly accuracy can be improved.
Alternatively, all the solder joints may be performed at the same time with the solder used for each joint having the same melting point. Although the positioning jig used for assembly is slightly complicated, the solder joining process can be completed in one time, and the productivity can be improved.
Subsequently, the laminated body in which the above-described solder bonding is completed is fitted into a sealing mold, and a sealing resin 15 such as a molten epoxy resin is poured. A region between the metal bars 13a and 13c and where the semiconductor chip is mounted is sealed. At this time, if the surfaces of the metal bars 13a and 13c that are not soldered are exposed, the heat generated by the semiconductor chip can be easily released from the exposed surfaces.

このように、IGBT11Pa,FWD11PbとIGBT11Na,FWD11Nbとを金属バー13bを介して金属バー13a,13c間に積層し、IGBT11PaとFWD11Pbで上(正極側)アーム,IGBT11NaとFWD11Nbとで下(負極側)アームを構成し、金属バー13aを直流入力(正極),金属バー13bを交流出力,金属バー13cを直流入力(負極)とする1相分のパワー半導体モジュール(2個組み積層型パッケージ)を構成する。
このようなパッケージをインバータ装置などに組み込んで用いる場合は、金属バー13a,13cの露出面に絶縁性があり熱伝導性の高い放熱シート16を介して放熱フィン17を接合する。放熱シート16に粘着性のものを用いれば、放熱フィン17を容易に取り付けることができる。
As described above, the IGBT 11Pa and FWD11Pb and the IGBT 11Na and FWD11Nb are stacked between the metal bars 13a and 13c through the metal bar 13b, and the upper (positive electrode side) arm on the IGBT 11Pa and FWD11Pb, and the lower (negative electrode side) on the IGBT 11Na and FWD11Nb. A power semiconductor module (two-packed laminated package) for one phase is constructed, with the arm configured as a DC input (positive electrode) for the metal bar 13a, an AC output for the metal bar 13b, and a DC input (negative electrode) for the metal bar 13c. To do.
When such a package is used in an inverter device or the like, the exposed surfaces of the metal bars 13a and 13c are joined to the heat radiating fins 17 via the heat radiating sheet 16 having insulation and high thermal conductivity. If an adhesive thing is used for the heat-radiation sheet 16, the heat-radiation fin 17 can be attached easily.

図2はこの発明のパワー半導体モジュールの第2の実施例を示す断面図である。図2において、18,19はセラミック基板の両面に金属箔としての銅パターン18a,18b,19a,19bが接合された絶縁基板である。絶縁基板18,19の一方の面の銅パターン18a,19aは、回路パターンとして形成されている。セラミック基板と金属箔との接合には、直接接合を用いてもよいし、ロウ材を介して接合してもよい。
IGBT11Paのコレクタ電極,FWD11Pbのカソード電極,直流入力端子(P)となる金属バー13dは、絶縁基板18の銅パターン18aにはんだ接合され、同様にIGBT11Paエミッタ電極とFWD11Pbアノード電極は金属バー13bにはんだ接合される。このとき、上記はんだにはSn系のはんだを用い、IGBT11Paのゲート電極は金属ボール14を介して金属バー13b上のゲート配線(図示せず)にはんだ接合される。このゲート配線は金属バー13bの表面に例えばポリイミドなどの樹脂を塗布して200μm程度絶縁層を形成し、該絶縁層上に銅箔等でパターニングして形成すればよい。なお、金属バー13bとして薄板状のヒートパイプを用いてもよい。ヒートパイプを用いることにより、パワー半導体モジュール内部の熱を効果的に放出することができる。
FIG. 2 is a cross-sectional view showing a second embodiment of the power semiconductor module of the present invention. In FIG. 2, 18 and 19 are insulating substrates in which copper patterns 18a, 18b, 19a and 19b as metal foils are bonded to both surfaces of a ceramic substrate. Copper patterns 18a and 19a on one surface of insulating substrates 18 and 19 are formed as circuit patterns. Direct bonding may be used for bonding the ceramic substrate and the metal foil, or bonding may be performed via a brazing material.
The collector electrode of IGBT 11Pa, the cathode electrode of FWD11Pb, and the metal bar 13d serving as the DC input terminal (P) are soldered to the copper pattern 18a of the insulating substrate 18, and the IGBT 11Pa emitter electrode and the FWD11Pb anode electrode are similarly soldered to the metal bar 13b. Be joined. At this time, Sn solder is used as the solder, and the gate electrode of the IGBT 11Pa is soldered to the gate wiring (not shown) on the metal bar 13b via the metal ball. The gate wiring may be formed by applying a resin such as polyimide on the surface of the metal bar 13b to form an insulating layer of about 200 μm and patterning the insulating layer with a copper foil or the like. In addition, you may use a thin plate-shaped heat pipe as the metal bar 13b. By using the heat pipe, the heat inside the power semiconductor module can be effectively released.

また、IGBT11Naのコレクタ電極とFWD11Nbのカソード電極は金属バー13bにはんだ接合され、同じくIGBT11Naエミッタ電極,FWD11Nbアノード電極,直流入力端子(N)となる金属バー13eは絶縁基板19の銅パターン19aにはんだ接合される。このとき、上記はんだにはSn系のはんだを用い、IGBT11Naのゲート電極は金属ボール14を介して絶縁基板19の銅パターン19a’にはんだ接合される。
なお、IGBT11Naのゲートに対応する部分については、パワー半導体モジュール外への引き出し部の図示は省略するが、絶縁基板19の回路パターンの形成により自在に引き出すことができ、リードフレームを用いた場合に比べ、設計の自由度が高い。
第2実施例のパワー半導体モジュールの組立方法も第1の実施例と同様であって、絶縁基板18の銅パターン18a上にIGBT11Pa,FWD11Pb,金属バー13dを、をそれぞれ所定の位置に塗布したクリームはんだもしくははんだシートを介して載置し、この積層体をそれぞれ加熱炉に投入し、はんだを溶融・固化させて接合する。はんだ溶融時にIGBT11Pa,FWD11Pb,金属バー13dがすれないよう、図示しない治具を用いるとよい。同様に絶縁基板19の銅パターン19a上にIGBT11Na,FWD11Nb,金属バー13eを接合する。
The collector electrode of the IGBT 11Na and the cathode electrode of the FWD 11Nb are soldered to the metal bar 13b, and the metal bar 13e, which also becomes the IGBT 11Na emitter electrode, the FWD 11Nb anode electrode, and the DC input terminal (N), is soldered to the copper pattern 19a of the insulating substrate 19. Be joined. At this time, Sn solder is used as the solder, and the gate electrode of the IGBT 11Na is soldered to the copper pattern 19a ′ of the insulating substrate 19 via the metal ball 14.
The portion corresponding to the gate of the IGBT 11Na is not shown in the drawing of the lead-out portion to the outside of the power semiconductor module, but can be pulled out freely by forming a circuit pattern on the insulating substrate 19, and when a lead frame is used. Compared to it, the degree of freedom in design is high.
The method of assembling the power semiconductor module of the second embodiment is the same as that of the first embodiment. The cream is obtained by applying IGBT 11Pa, FWD11Pb, and metal bar 13d on the copper pattern 18a of the insulating substrate 18 at predetermined positions. It mounts via a solder or a solder sheet | seat, this laminated body is each put into a heating furnace, a solder is fuse | melted and solidified and it joins. A jig (not shown) may be used so that the IGBT 11Pa, FWD11Pb, and the metal bar 13d are not smeared when the solder is melted. Similarly, IGBT11Na, FWD11Nb, and metal bar 13e are joined on the copper pattern 19a of the insulating substrate 19.

つづいて、金属バー13bの両面の所定個所にクリームはんだを塗布し、あるいははんだシートを介して、絶縁基板18の接合体と絶縁基板19の接合体との間に介挿し、再び加熱炉に投入して金属バー13bの両面のはんだを溶融・固化させてすべての接合を完了させる。金属バー13bの接合に用いるはんだは、金属バー13a,13cの接合に用いたはんだより融点の低いものを用いるとよい。
このように、予め絶縁基板18側(上アーム側),絶縁基板19側(下アーム側)のはんだ接合を完了させることにより、組立に用いる位置決め治具を簡単な構成とすることができ、半導体チップや導体板の接合精度を向上させることができる。
あるいは、同融点のはんだを用い、すべてのはんだ接合を同時に行ってもよい。この場合は、はんだ接合工程を1回で完了させることができるため、生産性を向上させることができる。
Subsequently, cream solder is applied to predetermined positions on both sides of the metal bar 13b, or is inserted between the joined body of the insulating substrate 18 and the joined body of the insulating substrate 19 via a solder sheet, and again put into the heating furnace. Then, the solder on both sides of the metal bar 13b is melted and solidified to complete all the joining. The solder used for joining the metal bars 13b may have a lower melting point than the solder used for joining the metal bars 13a and 13c.
As described above, the soldering of the insulating substrate 18 side (upper arm side) and the insulating substrate 19 side (lower arm side) is completed in advance, so that the positioning jig used for assembly can have a simple configuration. The joining accuracy of the chip and the conductor plate can be improved.
Alternatively, solder having the same melting point may be used, and all solder joints may be performed simultaneously. In this case, since the solder joining process can be completed at once, productivity can be improved.

つづいて、上記のはんだ接合が完了した積層体を封止型に嵌装し、溶融したエポキシ樹脂などの封止樹脂15を流し込む。絶縁基板18,19に挟まれた領域であって、半導体チップが実装された領域を封止する。このとき、絶縁基板18,19の銅パターン18b,19bを露出するようにすると、半導体チップが発生する熱を露出面より放出しやすくなる。
このように、IGBT11Pa,FWD11PbとIGBT11Na,FWD11Nbとを金属バー13bを介して絶縁基板18,19間に積層し、IGBT11PaとFWD11Pbで上(正極側)アーム,IGBT11NaとFWD11Nbとで(負極側)アームを構成し、金属バー13dを直流入力(正極),金属バー13bを交流出力,金属バー13eを直流入力(負極)とする1相分のパワー半導体モジュール(2個組み積層型パッケージ)を構成する。
Subsequently, the laminated body in which the above-described solder bonding is completed is fitted into a sealing mold, and a sealing resin 15 such as a molten epoxy resin is poured. A region sandwiched between the insulating substrates 18 and 19 and having a semiconductor chip mounted thereon is sealed. At this time, if the copper patterns 18b and 19b of the insulating substrates 18 and 19 are exposed, the heat generated by the semiconductor chip is easily released from the exposed surface.
Thus, IGBT11Pa, FWD11Pb and IGBT11Na, FWD11Nb are stacked between insulating substrates 18 and 19 via metal bar 13b, and the upper (positive electrode side) arm is formed by IGBT11Pa and FWD11Pb, and the negative electrode side arm is formed by IGBT11Na and FWD11Nb. A power semiconductor module (a two-layer stacked package) for one phase in which the metal bar 13d is a DC input (positive electrode), the metal bar 13b is an AC output, and the metal bar 13e is a DC input (negative electrode). .

絶縁基板を用いているため、絶縁基板の露出面(銅パターン18b,19b)は内部のとは絶縁が保たれている。このため、このようなパッケージをインバータ装置などに組み込んで用いる場合、第1の実施例で用いた放熱シートは不要である。放熱フィン17の取り付けにあたっては、封止した樹脂部に放熱フィンの固定用のビス穴(図示せず)を設けてもよい。ビス穴内に金属管を圧入若しくは樹脂に一体に形成することで所望の強度を得ることができる。あるいは、絶縁基板18側の放熱フィンと絶縁基板19側の放熱フィンとでパワー半導体モジュールを挟み込み、放熱フィン同士を相互に固定してもよい。
なお、上記の各実施例においては、各接合をはんだによって行っているが、電気的・熱的・機械的な接続を図る接合方法であればこれに限るものではない。例えば、実施例1において、金属バー13a,13cとIGBT11a,FWD11bとの間をはんだによって接合し、同じく実施例2においては、絶縁基板18,19の銅パターン18a,19aとIGBT11Pa,FWD11Pb,IGBT11Na,FWD11Nb,金属バー13d,13eとの間をはんだによって接合しているが、はんだ接合に代えて超音波接合を採用してもよい。
Since an insulating substrate is used, the exposed surfaces (copper patterns 18b and 19b) of the insulating substrate are kept insulated from the inside. For this reason, when using such a package by incorporating it in an inverter device or the like, the heat dissipation sheet used in the first embodiment is not necessary. When attaching the radiating fins 17, screw holes (not shown) for fixing the radiating fins may be provided in the sealed resin portion. A desired strength can be obtained by press-fitting a metal tube into the screw hole or integrally forming the resin tube. Alternatively, the power semiconductor module may be sandwiched between the radiating fins on the insulating substrate 18 side and the radiating fins on the insulating substrate 19 side, and the radiating fins may be fixed to each other.
In each of the above-described embodiments, each bonding is performed by soldering. However, the bonding method is not limited to this as long as it is a bonding method for achieving electrical, thermal, and mechanical connection. For example, in Example 1, the metal bars 13a and 13c and the IGBTs 11a and FWD11b are joined by solder. Similarly, in Example 2, the copper patterns 18a and 19a of the insulating substrates 18 and 19 and the IGBTs 11Pa, FWD11Pb, IGBT11Na, The FWD 11Nb and the metal bars 13d and 13e are joined by soldering, but ultrasonic joining may be employed instead of solder joining.

パワー半導体モジュールの第1の実施例を示す断面図である。It is sectional drawing which shows the 1st Example of a power semiconductor module. パワー半導体モジュールの第2の実施例を示す断面図である。It is sectional drawing which shows the 2nd Example of a power semiconductor module. 第1の従来例を示す断面図である。It is sectional drawing which shows a 1st prior art example. 第2の従来例を示す断面図である。It is sectional drawing which shows a 2nd prior art example.

符号の説明Explanation of symbols

11a,11Na,11Pa IGBT
11b,11Nb,11Pb FWD
12 はんだ
13a,13b,13c,13d,13e 金属バー
14 金属
15 封止樹脂
16 放熱シート
17 放熱フィン
18,19,21,31,32 絶縁基板
22 外部導出端子
23 ボンディングワイヤ
24 樹脂ケース
25 蓋
26 放熱ベース
21a,21b,31a,31b 銅パターン
32c スルーホール
33 金属配線板
11a, 11Na, 11Pa IGBT
11b, 11Nb, 11Pb FWD
12 Solder 13a, 13b, 13c, 13d, 13e Metal bar 14 Metal 15 Sealing resin 16 Heat radiation sheet 17 Heat radiation fin 18, 19, 21, 31, 32 Insulating substrate 22 External lead-out terminal 23 Bonding wire 24 Resin case 25 Lid 26 Heat radiation Base 21a, 21b, 31a, 31b Copper pattern 32c Through hole 33 Metal wiring board

Claims (7)

  1. 第1の導体基板と第2の導体基板との間にパワー半導体スイッチ素子の主電極ならびにダイオードの電極をそれぞれ接合して第1の並列接続回路を構成し、
    第2の導体基板と第3の導体基板との間にパワー半導体スイッチ素子の主電極ならびにダイオードの電極をそれぞれ接合して第2の並列接続回路を構成し、
    第1の並列接続回路と第2の並列接続回路とを、前記第2の導体基板を介して直列接続し、
    前記第1,第3の導体基板を直流入力端子とし、該第2の導体基板を出力端子とした半導体装置において、
    前記第2の導体板の表面に絶縁層を介してゲート配線パターンを形成し、該ゲート配線パターンに、前記第1の並列回路におけるパワー半導体スイッチ素子のゲート電極を接続したことを特徴とする半導体装置。
    A first parallel connection circuit is formed by bonding a main electrode of a power semiconductor switch element and an electrode of a diode between the first conductor substrate and the second conductor substrate,
    A main parallel electrode of the power semiconductor switch element and an electrode of the diode are respectively joined between the second conductor substrate and the third conductor substrate to constitute a second parallel connection circuit,
    A first parallel connection circuit and a second parallel connection circuit are connected in series via the second conductive substrate,
    In the semiconductor device having the first and third conductor substrates as DC input terminals and the second conductor substrate as an output terminal ,
    A gate wiring pattern is formed on the surface of the second conductor plate via an insulating layer, and a gate electrode of a power semiconductor switch element in the first parallel circuit is connected to the gate wiring pattern. apparatus.
  2. 請求項1に記載の半導体装置において、前記第1,第2,第3の導体基板は金属板であることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the first, second and third conductor substrates are metal plates.
  3. 請求項1に記載の半導体装置において、前記第1,第3の導体基板はセラミック基板の両面に金属箔を接合した絶縁基板であり、第2の導体板は金属板であることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the first and third conductive substrates are insulating substrates obtained by bonding metal foils to both surfaces of a ceramic substrate, and the second conductive plate is a metal plate. Semiconductor device.
  4. 請求項3に記載の半導体装置において、第3の導体板であるセラミック基板の前記パワー半導体スイッチ素子の接合面側の金属箔に、ゲート配線パターンを形成し、前記第2の並列回路におけるパワー半導体スイッチ素子のゲート電極を接続したことを特徴とする半導体装置。  4. The semiconductor device according to claim 3, wherein a gate wiring pattern is formed on a metal foil on a bonding surface side of the power semiconductor switch element of a ceramic substrate which is a third conductor plate, and the power semiconductor in the second parallel circuit is formed. A semiconductor device characterized by connecting a gate electrode of a switch element.
  5. 請求項1に記載の半導体装置において、前記第1の導体基板と第3の導体基板とに挟まれた領域であって、前記パワー半導体スイッチ素子および前記ダイオードが接合された部分を樹脂封止したことを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein a region sandwiched between the first conductor substrate and the third conductor substrate, in which the power semiconductor switch element and the diode are joined, is resin-sealed. A semiconductor device.
  6. 請求項1または請求項4のいずれか一項に記載の半導体装置において、前記パワー半導体スイッチ素子の主電極および前記ダイオードの電極を前記第1,第2,第3の導体基板にはんだ接合するものであって、  5. The semiconductor device according to claim 1, wherein a main electrode of the power semiconductor switch element and an electrode of the diode are solder-bonded to the first, second, and third conductive substrates. 6. Because
    前記ゲート配線と前記ゲート電極との間を、前記はんだより融点の高い金属コア,金属コアの周囲にはんだを被覆した金属コアはんだボール,はんだボールの何れかからなる金属ボールによって接続したことを特徴とする半導体装置。  The gate wiring and the gate electrode are connected by a metal core having any one of a metal core having a melting point higher than that of the solder, a metal core solder ball coated with solder around the metal core, and a solder ball. A semiconductor device.
  7. 請求項2に記載の半導体装置において、前記第1,第3の導体板の前記パワー半導体スイッチ素子の接合面とは反対側の面に、絶縁性ならびに熱伝導性を有する放熱シートを介してそれぞれ放熱フィンを備えることを特徴とする半導体装置。  3. The semiconductor device according to claim 2, wherein a surface of the first and third conductor plates opposite to the joint surface of the power semiconductor switch element is respectively provided with a heat dissipation sheet having insulating properties and thermal conductivity. A semiconductor device comprising a radiation fin.
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