JP4635564B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP4635564B2
JP4635564B2 JP2004320322A JP2004320322A JP4635564B2 JP 4635564 B2 JP4635564 B2 JP 4635564B2 JP 2004320322 A JP2004320322 A JP 2004320322A JP 2004320322 A JP2004320322 A JP 2004320322A JP 4635564 B2 JP4635564 B2 JP 4635564B2
Authority
JP
Japan
Prior art keywords
electrode
power semiconductor
conductor substrate
diode
metal bar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004320322A
Other languages
Japanese (ja)
Other versions
JP2006134990A (en
Inventor
満男 山下
良成 池田
Original Assignee
富士電機システムズ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機システムズ株式会社 filed Critical 富士電機システムズ株式会社
Priority to JP2004320322A priority Critical patent/JP4635564B2/en
Publication of JP2006134990A publication Critical patent/JP2006134990A/en
Application granted granted Critical
Publication of JP4635564B2 publication Critical patent/JP4635564B2/en
Application status is Expired - Fee Related legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Description

  The present invention relates to a semiconductor device such as a power semiconductor module in which a plurality of vertical semiconductor elements are stored in the same package.

Conventionally, a power semiconductor module in which a plurality of power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and FWDs (Free Wheel Diodes) are housed in the same package has mainly had a resin case package structure.
FIG. 5 is a cross-sectional view showing a conventional example of a power semiconductor module. In FIG. 5, the IGBT 11a, the FWD 11b and the external lead-out terminal 22 as power semiconductor elements are formed on the copper pattern 21a on one surface of the insulating substrate 21 formed by bonding the copper patterns 21a and 21b on both surfaces of the ceramic substrate with solder (not shown). It is joined. The power semiconductor element and the external lead-out terminal are connected by a copper pattern or a bonding wire 23. In this manner, the power semiconductor element and the like are mounted on the insulating substrate and stored in the resin case 24, and a filler (not shown) such as resin is injected into the inside as necessary, and then the resin lid 25 is used. cover. Reference numeral 26 denotes a heat dissipation base bonded to the copper pattern 21b on the other surface of the insulating substrate (Patent Document 1).

When the above power semiconductor module is used by being incorporated in an inverter device, for example, if a portion corresponding to one phase of the inverter device is configured as a module, in the configuration of FIG. The bottom area of the module will increase. Such a power semiconductor module having a large bottom area requires a large mounting area even when incorporated in the inverter device, resulting in an increase in size of the inverter device.
Therefore, a configuration in which power semiconductor elements are stacked has been proposed in order to reduce the area occupied by the power semiconductor module (Patent Document 2).
FIG. 6 is a sectional view showing another conventional example of a power semiconductor module. In FIG. 6, reference numeral 31 denotes an insulating substrate in which copper patterns 31a and 31b are joined to one surface of a ceramic substrate. The IGBT 11Na is placed on the copper patterns 31b via solder balls 14 'on the copper patterns 31a and 31b. FWD11Nb is joined through the solder 12, respectively. The copper pattern 31a is connected to the gate electrode of the IGBT 11Na and is connected to a control terminal (not shown).

The other surfaces of the IGBTs 11Na and FWD11Nb are connected to a copper pattern 32b bonded to one surface of the insulating substrate 32 via the solder 12. Copper patterns 32 a and 32 b are bonded to the other surface of the insulating substrate 32, and the copper patterns 32 b on both surfaces are connected via a through hole 32 c formed in the center of the insulating substrate 32.
IGBTs 11Pa are joined to the copper patterns 32a and 32b joined to the other surface of the insulating substrate 32 via solder balls 14 ', and FWD 11Pb is joined to the copper patterns 32b via the solder 12, respectively. The copper pattern 32a is connected to the gate electrode of the IGBT 11Pa, and is connected to a control terminal (not shown). The other surfaces of the IGBT 11Pa and the FWD 11Pb are joined to the metal wiring board 33 via the solder 12.
In this way, by stacking the upper and lower arms for one phase, the occupation area can be reduced to about ½, the mounting area when incorporated in the inverter device can be reduced, and the inverter device can be miniaturized. It becomes.
JP-A-8-213547 JP 2004-22844

Since power semiconductor chips such as IGBT generate heat due to switching or conduction, measures for heat dissipation from the power semiconductor module are indispensable, and heat cycle or Reliability for power cycle is required.
However, in the configuration described in Patent Document 2, the solder ball 14 'is used for connection between the IGBT and the copper pattern of the insulating substrate, and the electrical connection between the upper and lower arms (between both surfaces of the insulating substrate) is further performed. In order to ensure, a through hole 32c is formed in the insulating substrate.
For this reason, the stress due to the difference in thermal expansion coefficient between the power semiconductor chip and the copper pattern or the ceramic substrate is constantly generated in the joining hole by the solder ball 14 ′ and the through hole formed in the insulating substrate as the power semiconductor chip generates heat. As a result, there is a problem that a crack or peeling occurs at a joint portion of the solder ball 14 ′ or a crack occurs in the insulating substrate.

Further, a resin (such as an epoxy resin) that seals the entire package is injected between the IGBT and the insulating substrate. Since a resin having a high thermal resistance is injected into a portion other than the solder ball 14 'between the power semiconductor chip and the insulating substrate, heat radiation from the insulating substrate side of the package is limited, and sufficient heat radiation can be performed. Therefore, the power semiconductor chip cannot be used up.
In the configuration of Patent Document 2, since the degree of integration in the package is increased and the heat generation density is increased by adopting the laminated structure, sufficient cooling cannot be performed even though a heat dissipation (cooling) measure is indispensable. Therefore, there is a problem that it is difficult to ensure long-term reliability of the joint. In particular, when both surfaces of the power semiconductor chip are solder-bonded, the power semiconductor chip is restrained, so that the stress applied to the solder joint portion is increased and the deterioration of the joint portion is accelerated.

  The present invention has been made in view of the above-mentioned problems in the power semiconductor module, and in a package employing a laminated structure, the electrical connection between the upper and lower surfaces of the semiconductor chip is kept good, and the upper and lower surfaces of the semiconductor chip and It is an object to improve the reliability of a semiconductor device by efficiently radiating heat from the upper and lower surfaces of the package.

In order to solve the above-described problems, the present invention provides a first parallel connection circuit in which a main electrode of a power semiconductor switch element and an electrode of a diode are brought into contact with each other between a first conductor substrate and a second conductor substrate. A second parallel connection circuit in which the main electrode of the power semiconductor switch element and the electrode of the diode are in contact with each other between the second conductor substrate and the third conductor substrate, a first parallel connection circuit, Two parallel connection circuits connected in series via the second conductor substrate, and a region sandwiched between the first and third conductor substrates, the power semiconductor element and the diode There a sealing resin for sealing the arrangement portion, consists, first, the third conductor substrate and DC input terminals, Ru der which the conductors substrate of the second output terminal.
Also, the contact between the main electrode and the diode electrode facing the conductor substrate of the power semiconductor element, said all SANYO due by pressure contact contraction pressure at the time of curing of the sealing resin, the said conductor substrate have good the protrusion electrodes and the opposing portions of the main electrodes and diodes of the power semiconductor element is formed.

Furthermore, a concave portion and / or a convex portion that fits with the sealing resin is formed in a portion of the conductor substrate that is resin-sealed and in which the power semiconductor element and the diode are not disposed. and, wherein the power semiconductor element and one surface electrodes formed on the diode, but it may also be configured joined to a conductor substrate opposite faces.
Here, the first, second, and third conductive substrates are made of metal plates, or the first and third conductive substrates are insulating substrates in which metal foils are bonded to both surfaces of a ceramic substrate. The two conductor plates can be made of a metal plate.

  According to the power semiconductor module of the present invention, the power semiconductor chip constituting the upper and lower arms is sandwiched between the metal bar and the insulating substrate, and the electrode formed on the surface of the power semiconductor chip is connected by contact, so that a good electrical In addition to providing a simple connection, the area of the package can be reduced to about half of the conventional size. Further, heat can be radiated with high efficiency from the upper and lower surfaces of the power semiconductor chip and the upper and lower surfaces of the package, and a highly reliable semiconductor device can be supplied.

  The present invention will be described below based on the embodiments shown in the drawings.

  FIG. 1 is a cross-sectional view showing a first embodiment of the power semiconductor module of the present invention. In FIG. 1, 11 Pa and 11 Na are IGBTs, 11 Pb and 11 Nb are FWDs, 12 is solder, 13 a to 13 c are metal bars serving as external lead terminals of the power semiconductor module, and 14 is a metal ball 14. As a material of the metal bar 13, Cu, Al, Fe, or an alloy thereof is used. Protrusions 13b-1, 13b-2, 13c-1, and 13c-2 are formed on the metal bars 13b and 13c to come into contact with the surface electrodes of the IGBTs 11a and FWD11b. The metal ball 14 includes a metal core having a melting point higher than that of the solder 12, a metal core solder ball in which the metal core is coated with solder, or a simple solder ball. The one using a metal core is advantageous in that a desired solder thickness is ensured. Hereinafter, these are collectively referred to as a metal ball 14.

The collector electrode of the IGBT 11Pa and the cathode electrode of the FWD 11Pb are joined to the metal bar 13a by the solder 12, and the IGBT 11Pa emitter electrode and the anode electrode of the FWD 11Pb are in contact with the protrusions 13b-1 and 13b-2 of the metal bar 13b. At this time, Sn solder is used as the solder, and the gate electrode of the IGBT 11Pa is connected to the gate wiring (not shown) on the metal bar 13b via the metal ball 14.
Here, it is desirable that the metal ball is previously soldered to the gate wiring on the metal bar 13b. Usually, since the gate pad area of the IGBT 11a is not large, it is more stable if it is fixed to the gate wiring on the metal bar 13b by soldering. However, if the IGBT 11a gate pad is subjected to a solderable surface treatment such as nickel plating, the metal ball can be soldered to the gate pad.

The gate wiring may be formed by applying a resin such as polyimide on the surface of the metal bar 13b to form an insulating layer of about 200 μm and patterning the insulating layer with a copper foil or the like. In addition, you may use a thin plate-shaped heat pipe as the metal bar 13b. By using the heat pipe, the heat inside the power semiconductor module can be effectively released.
The collector electrode of the IGBT 11Na and the cathode electrode of the FWD 11Nb are soldered to the metal bar 13b, and the emitter electrode and the anode electrode are in contact with the protrusions 13c-1 and 13c-2 of the metal bar 13c. At this time, Sn solder is used as the solder, and the gate electrode of the IGBT 11Na is solder-connected to the gate wiring (not shown) on the metal bar 13c via the metal ball 14.

The gate wiring may be formed of copper foil or the like through an insulating layer, similar to that formed on the surface of the metal bar 13b, or a metal used in discrete products. A lead frame-like metal bar 13b obtained by punching a plate may be used. Since the pattern corresponding to the gate wiring is also punched, an insulating layer on the metal bar 13b is unnecessary. What is necessary is just to cut | disconnect an outer lead part in a desired shape after the below-mentioned resin sealing.
Next, the assembly method will be briefly described. Cream solder is applied to a predetermined portion of the metal bar 13a, or IGBTs 11Pa and FWD11Pb are placed via a solder sheet, and this laminated body is put into a heating furnace to melt and solidify the solder to join them. A jig (not shown) may be used so that the IGBT 11Pa and FWD11Pb do not shift when the solder is melted. Similarly, IGBT11Na and FWD11Nb are joined to the metal bar 13b.

Subsequently, the metal ball 14 is placed on the gate electrode of the IGBT 11Pa joined to the metal bar 13a, and the emitter electrode of the IGBT 11Pa and the anode electrode of the FWD 11Pb are in contact with the protrusions 13b-1 and 13b-2 of the metal bar 13b, respectively. In this manner, the metal bar 13b is placed.
Similarly, the metal ball 14 is placed on the gate electrode of the IGBT 11Na joined to the metal bar 13b so that the emitter electrode of the IGBT 11Na and the anode electrode of the FWD 11Nb are in contact with the protrusions 13c-1 and 13c-2 of the metal bar 13c, respectively. Then, the metal bar 13c is placed to form a stacked body of metal bars and semiconductor chips bonded to the metal bars. As described above, by bonding one surface of the semiconductor chip to the metal bar in advance, alignment when forming the laminated body becomes easy, and when performing resin sealing in the next process, The fitting work is also facilitated.

Subsequently, the above laminate is fitted into a sealing mold, and a sealing resin 15 such as a molten epoxy resin is poured. The resin 15 is between the metal bars 13a and 13c and seals the region where the semiconductor chip is mounted.
Since the sealing resin contracts when cured, a contracting force is generated along with the contraction of the sealing resin, and the contracting force acts in the direction of pulling the metal bars 13a and 13c toward the inside of the module. Accordingly, the protrusion of the metal bar is pressed against the electrode of the semiconductor chip, and both are brought into pressure contact and are electrically and thermally connected. Incidentally, when an epoxy resin is used as the sealing resin, the temperature at the time of curing is about 200 ° C., and there is a temperature difference of 175 ° C. from room temperature (25 ° C.). The linear expansion coefficient of the epoxy resin 20 ppm / ° C., when the Young's modulus and 2000kgf / mm 2 (19613N / mm 2), the temperature difference between the curing initiation to room temperature, 7 kgf / mm 2 in (68.6N / mm 2) A compressive stress is applied, and the protrusion of the metal bar is pressed against the electrode of the semiconductor chip. When the electrode of the semiconductor chip is made of aluminum, it is desirable to set the pressure within the range of elastic deformation of aluminum so that the electrode is not damaged.

The protrusions (13b-1, 13b-2, 13c-1, 13c-2) formed on the metal bars 13b, 13c make good contact with the surface electrode of the opposing semiconductor chip and damage the surface electrode. In order to avoid this, a smooth and flat shape is preferable. The protrusion may be formed by pressing when forming the metal bars 13b and 13c, or may be a protrusion having a desired height by an etching technique. The height of the protrusion may be selected in order to obtain a desired withstand voltage (creeping distance) with a portion other than the electrode portion of the semiconductor chip without damaging the surface protective film other than the electrode portion of the semiconductor chip. The height may be about 100 μm.
Thus, the resin-sealed power semiconductor module has the surface electrode of the semiconductor chip and the metal bar stacked in contact with each other, and is pressed and contacted by the shrinkage pressure of the sealing resin. Therefore, even if the structure inside the module expands due to heat generated by the operation of the power semiconductor module (drive of the power semiconductor chip), the metal bar and the power semiconductor chip are not joined, so the electrode bar is powered. It can shrink on the electrode surface of the semiconductor chip, and no stress is applied to the electrode surface.

Here, in the above example, one surface of the semiconductor chip is bonded to the metal bar in advance and laminated to form a stacked body. However, the bonding between the semiconductor chip and the metal bar is omitted, and the stacked layers are sequentially stacked. A body may be formed and fitted into a sealing mold. In this case, it is preferable to provide a protrusion on each portion of the metal bar that contacts the surface electrode (emitter, collector, etc.) of the semiconductor chip. Moreover, productivity is improved by simplifying the joining process. In addition, when solder bonding is used for bonding, distortion due to the difference in thermal expansion coefficient between the semiconductor chip and the metal bar may remain in the bonded portion, but the influence of such thermal history can also be avoided.
Adding inorganic particles (alumina, aluminum nitride, silicon nitride, silicon carbide, etc.) to the resin used for sealing increases the thermal conductivity of the sealing resin and is effective for heat dissipation from the sealing resin. is there.

When the above-described laminated body is resin-sealed, if the surfaces of the metal bars 13a and 13c that are not connected to the semiconductor chip are exposed, the heat generated by the semiconductor chip is easily released from the exposed surface.
As described above, the IGBT 11Pa and FWD11Pb and the IGBT 11Na and FWD11Nb are stacked between the metal bars 13a and 13c through the metal bar 13b, and the upper (positive electrode side) arm on the IGBT 11Pa and FWD11Pb, and the lower (negative electrode side) on the IGBT 11Na and FWD11Nb. A power semiconductor module (two-packed laminated package) for one phase is constructed, with the arm configured as a DC input (positive electrode) for the metal bar 13a, an AC output for the metal bar 13b, and a DC input (negative electrode) for the metal bar 13c. To do.
When such a package is used in an inverter device or the like, the exposed surfaces of the metal bars 13a and 13c are joined to the heat radiating fins 17 via the heat radiating sheet 16 having insulation and high thermal conductivity. If an adhesive thing is used for the heat-radiation sheet 16, the heat-radiation fin 17 can be attached easily.

Here, the configuration in which the IGBT collector electrode and the FWD cathode electrode are soldered to the metal bar has been described as an example, but the IGBT emitter electrode and the FWD anode electrode may be soldered to the metal bar.
Moreover, you may join by ultrasonic joining instead of solder joining.
FIG. 2 is a modification example of the shape of the metal bar, and the metal bar 13c is described as an example. The following configuration is not limited to the metal bar 13c, and of course, can be applied to the metal bars 13a and 13b to that effect.
FIG. 2A is an example for effectively utilizing the contraction pressure at the time of resin sealing as the contact pressure between the power semiconductor chip and the metal bar. In FIG. 2A, 101 is a recess formed on the surface of the metal bar 13c that is filled with resin, and 102 is a recess formed on the side surface of the metal bar 13c that is covered with the sealing resin. is there. Both are for increasing the contact area between the metal bar and the sealing resin, and the cured sealing resin can be fitted to obtain strong adhesion, and the shrinkage when the sealing resin is cured The force can be efficiently used as a pressing force to the electrode surface.

The recess 101 has a shape that expands in the depth direction with respect to the opening, thereby improving the adhesion. The recess 102 has the same shape or a recess closer to the inside of the power semiconductor module as shown in FIG. As long as the surface of the metal bar is not obtuse with the side surface of the metal bar, it is sufficient.
Any of the above-mentioned recesses can be formed on the metal bar by grinding, drawing, pressing, or the like. In order to make the opening narrow like the recess 101, it is possible to make the opening narrow by applying pressure from the side surface of the metal bar after forming the recess as described above.
FIG. 2B is another example for effectively utilizing the contraction pressure at the time of resin sealing as the contact pressure between the power semiconductor chip and the metal bar. In FIG. 2B, reference numeral 103 denotes a substantially T-shaped pin, which is joined to the metal bar 13c by solder 104. By the pin 103, the cured sealing resin can be fitted to obtain strong adhesion, and the shrinkage force when the sealing resin is cured can be efficiently used as the pressing force to the electrode surface.

FIG. 2C is a modification for reliably connecting the gate electrode of the IGBT and the gate wiring formed on the metal bar. A recess 105 is formed in the metal bar 13c, and a gate wiring is formed through an insulating layer (both not shown). A metal ball enters the recess 105 to facilitate positioning with the gate electrode of the IGBT and to perform reliable connection.
The deformation of the metal bar shown in FIG. 2 may be appropriately combined.

FIG. 3 is a cross-sectional view showing a second embodiment of the power semiconductor module of the present invention. The same components as those in FIG. In FIG. 3, reference numerals 18 and 19 denote insulating substrates in which copper patterns 18a, 18b, 19a, and 19b as metal foils are bonded to both surfaces of a ceramic substrate mainly made of alumina, aluminum nitride, silicon nitride, or the like. Copper patterns 18a and 19a on one surface of insulating substrates 18 and 19 are formed as circuit patterns. Direct bonding may be used for bonding the ceramic substrate and the metal foil, or bonding may be performed via a brazing material.
The metal bar 13d that becomes the collector electrode of the IGBT 11Pa, the cathode electrode of the FWD 11Pb, and the DC input terminal (P) is soldered to the copper pattern 18a of the insulating substrate 18. The emitter electrode of the IGBT 11Pa and the anode electrode of the FWD 11Pb are in contact with the protrusions 13b-1 and 13b-2 of the metal bar 13b as in the first embodiment. At this time, Sn solder is used as the solder.
The metal bar 13b is formed with protrusions 13b-1 and 13b-2 for making contact with the surface electrodes of the IGBT 11Pa and FWD11Pb, and the protrusion for making contact with the surface electrode of the IGBT 11Na and FWD11Nb also on the copper pattern 19a of the insulating substrate 19. 19a-1 and 19a-2 are formed.

The collector electrode of IGBT11Pa and the cathode electrode of FWD11Pb are joined to the copper pattern 18a of the insulating substrate 18 by solder 12, and the IGBT11Pa emitter electrode and the anode electrode of FWD11Pb are in contact with the protrusions 13b-1 and 13b-2 of the metal bar 13b. . At this time, Sn solder is used as the solder, and the gate electrode of the IGBT 11Pa is connected to the gate wiring (not shown) on the metal bar 13b via the metal ball 14. The gate wiring may be formed by applying a resin such as polyimide on the surface of the metal bar 13b to form an insulating layer of about 200 μm and patterning the insulating layer with a copper foil or the like. In addition, you may use a thin plate-shaped heat pipe as the metal bar 13b. By using the heat pipe, the heat inside the power semiconductor module can be effectively released.
The collector electrode of the IGBT 11Na and the cathode electrode of the FWD 11Nb are soldered to the metal bar 13b, and the emitter electrode and the anode electrode are in contact with the protrusions 13c-1 and 13c-2 of the metal bar 13c. At this time, Sn solder is used as the solder, and the gate electrode of the IGBT 11Na is connected to the gate wiring (not shown) on the metal bar 13c via the metal ball.

The portion corresponding to the gate of the IGBT 11Na is not shown in the drawing of the lead-out portion to the outside of the power semiconductor module, but can be pulled out freely by forming a circuit pattern on the insulating substrate 19, and when a lead frame is used. Compared to it, the degree of freedom in design is high.
A method for assembling the power semiconductor module of the second embodiment will be briefly described. First, the IGBT 11Pa, FWD11Pb, and the metal bar 13d are placed on the copper pattern 18a of the insulating substrate 18 via cream solder or solder sheet respectively applied at predetermined positions, and this laminate is put into a heating furnace. The solder is melted and solidified to join. A jig (not shown) may be used so that the IGBT 11Pa, FWD11Pb, and the metal bar 13d are not smeared when the solder is melted. Similarly, IGBT11Na and FWD11Nb are joined to the metal bar 13b, and the metal bar 13e is joined to the copper pattern 19a of the insulating substrate 19.

Subsequently, the metal ball 14 is placed on the gate electrode of the IGBT 11Pa joined to the copper pattern 18a of the insulating substrate 18, and the emitter electrode of the IGBT 11Pa and the anode electrode of the FWD 11Pb are the protrusions 13b-1 and 13b-2 of the metal bar 13b. The metal bar 13b is placed so as to come into contact with each other.
Similarly, the metal ball 14 is placed on the gate electrode of the IGBT 11Na joined to the metal bar 13b, and the emitter electrode of the IGBT 11Na and the anode electrode of the FWD 11Nb are formed on the protrusions 19a-1 and 19a-2 of the copper pattern 19a of the insulating substrate 19. A metal bar 13c is placed so as to be in contact with each other, and a stacked body of metal chips and a semiconductor chip bonded to the metal bars is formed. As described above, by bonding one surface of the semiconductor chip to the metal bar and the insulating substrate in advance, the alignment when forming the laminated body is facilitated, and the sealing is performed when the resin sealing is performed in the next process. The fitting work to the mold is also easy.

Subsequently, the above laminate is fitted into a sealing mold, and a sealing resin 15 such as a molten epoxy resin is poured. The resin 15 is between the insulating substrates 18 and 19 and seals the region where the semiconductor chip is mounted.
Since the sealing resin contracts upon curing, a contracting force is generated along with the contraction of the sealing resin, and the contracting force acts in a direction to draw the insulating substrates 18 and 19 toward the inside of the module. Accordingly, the metal bar and the protrusion of the copper pattern are pressed against the electrode of the semiconductor chip, and both are brought into pressure contact and are electrically and thermally connected. As described in Example 1, when an epoxy resin is used as the sealing resin, shrinkage due to a temperature difference from the start of curing to room temperature becomes a pressing force during curing.
The protrusions (13b-1, 13b-2, 19a-1, 19a-2) formed on the metal bar 13b and the copper pattern 19a make good contact with the surface electrode of the opposing semiconductor chip, and the surface electrode In order to prevent damage, it is preferable to have a smooth and flat shape. The protrusion may be formed by pressing when forming the metal bar 13b, or may be a protrusion having a desired height by an etching technique. Further, a copper pattern in which protrusions are formed in advance by pressing or etching may be bonded to the ceramic substrate, or may be formed by etching after bonding the copper pattern to the ceramic substrate. The height of the protrusion may be selected in order to obtain a desired withstand voltage (creeping distance) with a portion other than the electrode portion of the semiconductor chip without damaging the surface protective film other than the electrode portion of the semiconductor chip. The height may be about 100 μm.

Thus, the resin-sealed power semiconductor module has the surface electrode of the semiconductor chip and the metal bar stacked in contact with each other, and is pressed and contacted by the shrinkage pressure of the sealing resin. Therefore, even if the structure inside the module expands due to heat generated by the operation of the power semiconductor module (drive of the power semiconductor chip), the metal bar and the power semiconductor chip are not joined, so the electrode bar is powered. It can shrink on the electrode surface of the semiconductor chip, and no stress is applied to the electrode surface.
Here, in the above example, one surface of the semiconductor chip is previously bonded to the copper pattern and the metal bar of the insulating substrate, and this is laminated to form a laminate, but the bonding between the semiconductor chip and the copper pattern / metal bar is performed. May be omitted, and a laminated body may be formed sequentially and fitted into a sealing mold. In this case, it is preferable to provide a protrusion on each portion of the copper pattern / metal bar that contacts the surface electrode (emitter, collector, etc.) of the semiconductor chip. Productivity is improved by simplifying the joining process. In addition, when solder bonding is used for bonding, distortion due to the difference in thermal expansion coefficient between the semiconductor chip and the copper pattern / metal bar may remain in the bonded portion, but the influence of such thermal history can be avoided. it can.

Adding inorganic particles (alumina, aluminum nitride, silicon nitride, silicon carbide, etc.) to the resin used for sealing increases the thermal conductivity of the sealing resin and is effective for heat dissipation from the sealing resin. is there.
When the laminated body is resin-sealed, if the surfaces (copper patterns 18b and 19b) of the insulating substrates 18 and 19 to which the semiconductor chips are not connected are exposed, the heat generated by the semiconductor chips is exposed from the exposed surfaces. Easy to release.
In this way, IGBT11Pa, FWD11Pb and IGBT11Na, FWD11Nb are stacked between insulating substrates 18 and 19 via metal bar 13b, and the upper (positive electrode side) arm at IGBT11Pa and FWD11Pb, and the lower (negative electrode side) at IGBT11Na and FWD11Nb. A power semiconductor module (a two-layer stacked package) for one phase is configured, with the arm configured as a metal bar 13d as a DC input (positive electrode), the metal bar 13b as an AC output, and the metal bar 13e as a DC input (negative electrode) To do.

  Since an insulating substrate is used, the exposed surfaces (copper patterns 18b and 19b) of the insulating substrate are kept insulated from the inside. For this reason, when such a package is incorporated in an inverter device or the like, the heat dissipation sheet used in the first embodiment is not necessary. When attaching the radiating fins 17, screw holes (not shown) for fixing the radiating fins may be provided in the sealed resin portion. A desired strength can be obtained by press-fitting a metal tube into the screw hole or integrally forming the resin tube. Alternatively, the power semiconductor module may be sandwiched between the heat dissipating fins on the insulating substrate 18 side and the heat dissipating fins on the insulating substrate 19 side, and the heat dissipating fins may be fixed to each other. In particular, when the module is sandwiched and clamped by two radiating fins, a clamping force for fixing the radiating fin is applied between the electrode and the protrusion in addition to the shrinkage force of the sealing resin, thereby obtaining a better connection. be able to.

Here, the configuration in which the IGBT collector electrode and the FWD cathode electrode are soldered to the metal bar has been described as an example, but the IGBT emitter electrode and the FWD anode electrode may be soldered to the metal bar.
Moreover, you may join by ultrasonic joining instead of solder joining.
FIG. 4 is a modified example of the shape of the insulating substrate, and the insulating substrate 19 is described as an example. The following configuration is not limited to the metal bar 13c, and can naturally be applied to the insulating substrate 18 to that effect.
FIG. 4A is an example for effectively utilizing the contraction pressure at the time of resin sealing as the contact pressure between the power semiconductor chip and the metal bar. In FIG. 2A, reference numeral 201 denotes a recess formed on the surface of the portion of the insulating substrate 19 where the copper pattern 19a is filled with resin. This is to increase the contact area between the copper pattern and the sealing resin. The hardened sealing resin can be fitted to obtain strong adhesion, and the shrinkage force when the sealing resin is cured is efficient. In particular, the pressing force can be applied to the electrode surface. Adhesion can be enhanced by forming the recess 201 in a shape that extends in the depth direction with respect to the opening.

The recess 201 can be formed on the copper pattern 19a by grinding, drawing, pressing, or the like. To narrow the opening as shown in FIG. 4A, after forming the recess as described above, The opening can be narrowed by applying pressure from the side of the metal bar. In order to prevent damage to the ceramic substrate, it is preferable to form a recess before bonding the copper pattern to the ceramic substrate.
FIG. 4B is another example for effectively utilizing the contraction pressure during resin sealing as the contact pressure between the power semiconductor chip and the metal bar. In FIG. 4B, reference numeral 203 denotes a substantially T-shaped pin, which is joined to the copper pattern 19a by solder 204. The pin 203 allows the hardened sealing resin to be fitted to obtain strong adhesion, and the shrinkage force when the sealing resin is hardened can be efficiently used as the pressing force to the electrode surface.

FIG. 4C is a modification for reliably connecting the gate electrode of the IGBT and the gate wiring formed on the metal bar. A recess 205 is formed in the copper pattern 19a, and a gate wiring is formed through an insulating layer (both not shown). A metal ball enters the recess 205 to facilitate positioning with the gate electrode of the IGBT and to perform reliable connection.
The deformation of the metal bar shown in FIG. 4 may be appropriately combined.

It is sectional drawing which shows the 1st Example of a power semiconductor module. It is a figure which shows the modification of a metal bar. It is sectional drawing which shows the 2nd Example of a power semiconductor module. It is a figure which shows the modification of a metal bar. It is sectional drawing which shows a 1st prior art example. It is sectional drawing which shows a 2nd prior art example.

Explanation of symbols

11a, 11Na, 11Pa IGBT
11b, 11Nb, 11Pb FWD
12 Solder 13a, 13b, 13c, 13d, 13e Metal bar 14 Metal 15 Sealing resin 16 Heat radiation sheet 17 Heat radiation fin 18, 19, 21, 31, 32 Insulating substrate 22 External lead-out terminal 23 Bonding wire 24 Resin case 25 Lid 26 Heat radiation Base 21a, 21b, 31a, 31b Copper pattern 32c Through hole 33 Metal wiring board 101, 102, 105, 201, 205 Recess 103, 203 Pin

Claims (6)

  1. A first parallel connection circuit in which a main electrode of a power semiconductor switch element and an electrode of a diode are brought into contact with each other between a first conductor substrate and a second conductor substrate;
    A second parallel connection circuit in which the main electrode of the power semiconductor switch element and the electrode of the diode are respectively contacted between the second conductor substrate and the third conductor substrate;
    A series connection circuit formed by connecting a first parallel connection circuit and a second parallel connection circuit in series via the second conductor substrate;
    A sealing resin that seals a portion where the power semiconductor element and the diode are arranged in a region sandwiched between the first and third conductive substrates,
    The first and third conductor substrates are used as DC input terminals, the second conductor substrate is used as an output terminal ,
    A semiconductor device, wherein a protrusion is formed on a portion of the conductor substrate facing the main electrode of the power semiconductor element and the electrode of the diode .
  2. A first parallel connection circuit in which a main electrode of a power semiconductor switching element and an electrode of a diode are brought into contact with each other between a first conductor substrate and a second conductor substrate;
      A second parallel connection circuit in which the main electrode of the power semiconductor switch element and the electrode of the diode are brought into contact with each other between the second conductor substrate and the third conductor substrate;
      A series connection circuit formed by connecting a first parallel connection circuit and a second parallel connection circuit in series via the second conductor substrate;
      A sealing resin that seals a portion where the power semiconductor element and the diode are disposed in a region sandwiched between the first and third conductive substrates,
      The first and third conductor substrates are used as DC input terminals, the second conductor substrate is used as an output terminal,
      A concave portion and / or a convex portion that fits with the sealing resin is formed in a portion of the conductor substrate that is resin-sealed and in which the power semiconductor element and the diode are not disposed. Semiconductor device.
  3. The contact between the main electrode and the diode electrode facing the conductor substrate of the power semiconductor device, according to claim 1 or claim, wherein the is due to contraction pressure during curing of the sealing resin pressure contact 2. The semiconductor device according to 2 .
  4. A concave portion and / or a convex portion that fits with the sealing resin is formed in a portion of the conductor substrate that is resin-sealed and in which the power semiconductor element and the diode are not disposed. The semiconductor device according to claim 1 .
  5. The contact between the main electrode of the power semiconductor element and the conductive substrate facing the electrode of the diode is a pressure contact due to the contraction pressure when the sealing resin is cured,
      Further, a concave portion and / or a convex portion that fits with the sealing resin is formed in a portion of the conductor substrate that is resin-sealed and in which the power semiconductor element and the diode are not disposed. The semiconductor device according to claim 1.
  6.   6. The semiconductor device according to claim 1, wherein an electrode formed on one surface of the power semiconductor element and the diode is bonded to an opposing conductive substrate.
JP2004320322A 2004-11-04 2004-11-04 Semiconductor device Expired - Fee Related JP4635564B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004320322A JP4635564B2 (en) 2004-11-04 2004-11-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004320322A JP4635564B2 (en) 2004-11-04 2004-11-04 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2006134990A JP2006134990A (en) 2006-05-25
JP4635564B2 true JP4635564B2 (en) 2011-02-23

Family

ID=36728281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004320322A Expired - Fee Related JP4635564B2 (en) 2004-11-04 2004-11-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JP4635564B2 (en)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2202793A3 (en) 2006-06-09 2010-11-10 Honda Motor Co., Ltd. Semiconductor device
JP4820233B2 (en) * 2006-08-09 2011-11-24 本田技研工業株式会社 Semiconductor device
JP4878520B2 (en) * 2006-08-09 2012-02-15 本田技研工業株式会社 Semiconductor device
JP2009043820A (en) 2007-08-07 2009-02-26 Rohm Co Ltd High-efficiency module
US8450845B2 (en) 2008-04-09 2013-05-28 Fuji Electric Co., Ltd. Semiconductor device
JP5067267B2 (en) 2008-06-05 2012-11-07 三菱電機株式会社 Resin-sealed semiconductor device and manufacturing method thereof
WO2010110445A1 (en) * 2009-03-26 2010-09-30 本田技研工業株式会社 Semiconductor device, and apparatus and method for manufacturing semiconductor device
JP5404124B2 (en) * 2009-03-26 2014-01-29 本田技研工業株式会社 Semiconductor device
JP2010239033A (en) * 2009-03-31 2010-10-21 Honda Motor Co Ltd Semiconductor device, and method of manufacturing the same
US8724325B2 (en) 2009-05-19 2014-05-13 Hamilton Sundstrand Corporation Solid state switch arrangement
JP5544767B2 (en) * 2009-06-17 2014-07-09 トヨタ自動車株式会社 Semiconductor device
JP5600931B2 (en) * 2009-12-11 2014-10-08 株式会社豊田中央研究所 Power converter
JP5452210B2 (en) * 2009-12-21 2014-03-26 株式会社日立製作所 Semiconductor device and manufacturing method thereof
US8513784B2 (en) * 2010-03-18 2013-08-20 Alpha & Omega Semiconductor Incorporated Multi-layer lead frame package and method of fabrication
JP5444584B2 (en) * 2010-05-21 2014-03-19 株式会社 日立パワーデバイス Semiconductor device and manufacturing method thereof
JP5489911B2 (en) 2010-08-18 2014-05-14 三菱電機株式会社 Semiconductor power module
EP2628173A2 (en) * 2010-10-13 2013-08-21 ABB Research Ltd. Semiconductor module and method of manufacturing a semiconductor module
JP5846123B2 (en) 2010-11-29 2016-01-20 トヨタ自動車株式会社 Power module
JP5947537B2 (en) 2011-04-19 2016-07-06 トヨタ自動車株式会社 Semiconductor device and manufacturing method thereof
US8878347B2 (en) 2011-05-16 2014-11-04 Toyota Jidosha Kabushiki Kaisha Power module
KR101343199B1 (en) 2011-12-07 2013-12-19 삼성전기주식회사 Semiconductor device package
KR20130069108A (en) * 2011-12-16 2013-06-26 삼성전기주식회사 Semiconductor package
CN102693969B (en) * 2012-06-18 2014-12-24 南京银茂微电子制造有限公司 Insulated gate bipolar translator (IGBT) power module
JP5357315B1 (en) 2012-09-19 2013-12-04 マイクロモジュールテクノロジー株式会社 Semiconductor device
JP2014082274A (en) * 2012-10-15 2014-05-08 Toyota Industries Corp Semiconductor device
US9386698B2 (en) 2013-02-28 2016-07-05 Shindengen Electric Manufacturing Co., Ltd. Module, module combined body and module production method
JP2014183078A (en) * 2013-03-18 2014-09-29 Mitsubishi Electric Corp Semiconductor device
JP5700092B2 (en) * 2013-09-06 2015-04-15 トヨタ自動車株式会社 Semiconductor device
DE112014001487T5 (en) * 2013-10-03 2015-12-10 Fuji Electric Co., Ltd. Semiconductor module
JP2015153932A (en) * 2014-02-17 2015-08-24 トヨタ自動車株式会社 semiconductor module
JP2014140080A (en) * 2014-05-07 2014-07-31 Rohm Co Ltd High-efficiency module
DE102014209690B4 (en) * 2014-05-21 2020-02-20 Robert Bosch Gmbh Kommutierungszelle
US9706643B2 (en) * 2014-06-19 2017-07-11 Panasonic Intellectual Property Management Co., Ltd. Electronic device and method for manufacturing the same
JP6517642B2 (en) * 2015-09-11 2019-05-22 株式会社東芝 Semiconductor device, inverter circuit, and drive device
EP3176822A1 (en) * 2015-12-04 2017-06-07 Robert Bosch Gmbh Electrically and thermally efficient power bridge
JP6254300B2 (en) 2016-01-31 2017-12-27 新電元工業株式会社 Semiconductor module
CN108475672A (en) 2016-01-31 2018-08-31 新电元工业株式会社 Semiconductor module
CN105590930B (en) * 2016-02-02 2018-05-08 中国第一汽车股份有限公司 A kind of used in new energy vehicles IGBT power module
JP2017143207A (en) * 2016-02-12 2017-08-17 株式会社豊田自動織機 Semiconductor module
KR101786343B1 (en) 2016-05-04 2017-10-18 현대자동차주식회사 Power module of double-faced cooling
FR3073978A1 (en) * 2017-11-17 2019-05-24 Institut Vedecom Electronic power module and electronic system comprising such an electronic module

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004047850A (en) * 2002-07-15 2004-02-12 Mitsubishi Electric Corp Power semiconductor device
JP4438489B2 (en) * 2004-04-13 2010-03-24 富士電機システムズ株式会社 Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004047850A (en) * 2002-07-15 2004-02-12 Mitsubishi Electric Corp Power semiconductor device
JP4438489B2 (en) * 2004-04-13 2010-03-24 富士電機システムズ株式会社 Semiconductor device

Also Published As

Publication number Publication date
JP2006134990A (en) 2006-05-25

Similar Documents

Publication Publication Date Title
EP2779230B1 (en) Power overlay structure and method of making same
US10290565B2 (en) Semiconductor device and method for manufacturing semiconductor device
JP5572678B2 (en) Semiconductor device including a clad base plate
EP3008753B1 (en) Power module
US8673691B2 (en) Method for manufacturing a semiconductor device
US8432030B2 (en) Power electronic package having two substrates with multiple semiconductor chips and electronic components
US8183094B2 (en) Method of manufacturing a semiconductor device having a semiconductor chip and resin sealing portion
US8890310B2 (en) Power module package having excellent heat sink emission capability and method for manufacturing the same
US9035453B2 (en) Semiconductor device
DE102007046021C5 (en) Method for connecting a semiconductor chip to a ceramic substrate
US5856913A (en) Multilayer semiconductor device having high packing density
DE10066441B4 (en) Semiconductor device with radiating components
US6448645B1 (en) Semiconductor device
US8952520B2 (en) Power semiconductor device
US8309399B2 (en) Power semiconductor module and method of manufacturing the same
US5767573A (en) Semiconductor device
JP3923258B2 (en) Power control system electronic circuit device and manufacturing method thereof
CN1265451C (en) Semiconductor device and manufactoring method thereof
CN100343987C (en) Semiconductor device having metal plates and semiconductor chip
JP4634497B2 (en) Power semiconductor module
EP0931346B1 (en) Microelectronic component with a sandwich design
JP5241177B2 (en) Semiconductor device and manufacturing method of semiconductor device
US20110187003A1 (en) Power semiconductor device
JP4450230B2 (en) Semiconductor device
US8659147B2 (en) Power semiconductor circuit device and method for manufacturing the same

Legal Events

Date Code Title Description
RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20060703

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20060704

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070914

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20080204

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20081216

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20090219

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20091112

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20091225

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100216

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100414

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20101026

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20101108

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131203

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131203

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131203

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees