JP3879150B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3879150B2
JP3879150B2 JP21232596A JP21232596A JP3879150B2 JP 3879150 B2 JP3879150 B2 JP 3879150B2 JP 21232596 A JP21232596 A JP 21232596A JP 21232596 A JP21232596 A JP 21232596A JP 3879150 B2 JP3879150 B2 JP 3879150B2
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Prior art keywords
electrode
high thermal
thermal conductive
semiconductor chip
insulating substrate
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JPH1056131A (en
Inventor
文雄 小原
規仁 戸倉
友則 木村
正人 水越
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株式会社デンソー
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device configured by housing one or a plurality of semiconductor chips such as power MOSFETs and IGBTs in a package.
[0002]
[Prior art]
Since semiconductor chips such as power MOSFETs and IGBTs are elements that control a large current, they generate a large amount of self heat. For this reason, when accommodating the said semiconductor chip in a package, it is comprised so that cooling property (heat dissipation) may fully be improved. For example, in the case of an IGBT module configured by accommodating a plurality of IGBT chips in a package, the IGBT module is provided with an insulating substrate made of high thermal conductivity ceramic, and the IGBT chips are mounted on the insulating substrate, and each IGBT is mounted. A main electrode provided on the lower surface (lower main surface) of the chip is connected to a copper thick film provided on the insulating substrate by soldering.
[0003]
The main electrode and the control electrode provided on the upper surface (upper main surface) of each IGBT chip are connected to the copper thick film provided on the insulating substrate by wire bonding. Furthermore, the insulating substrate is soldered to a copper heat sink. Thereby, the heat generated from each IBGT chip is transmitted to the heat radiating plate through the insulating substrate and is radiated. Such an IBGT module is used in an inverter main circuit of an inverter device of several tens to several hundreds of A class.
[0004]
[Problems to be solved by the invention]
In the case of the IBGT module having the above-described conventional configuration, the heat generated from each IBGT chip is dissipated from the insulating substrate provided on the lower surface side of each IBGT chip, that is, the structure mainly dissipated from the lower surface side of each IBGT chip. It is. In this structure, since heat is only radiated from one surface of each IBGT chip, there is a limit to improving heat dissipation, and it is difficult to reduce the size of the entire IGBT module.
[0005]
On the other hand, if heat is dissipated from both the upper and lower surfaces (two main surfaces) of the semiconductor chip, the heat dissipation can be greatly increased. An example of this configuration is a thyristor package. This package has a structure in which a thyristor chip is sandwiched between two electrode blocks that serve both as electrodes and heat dissipation. In this configuration, the heat generated from the thyristor chip is transferred from the upper and lower surfaces to the electrode block and dissipated. In the case of the thyristor, in order to establish an electrical connection between the electrode of the thyristor chip and the electrode block, the thyristor chip is sandwiched between the electrode blocks and pressed with a considerably large force.
[0006]
However, a semiconductor chip having a MOS gate structure such as an IGBT chip has a characteristic that it is vulnerable to stress. For this reason, the structure which pressurizes the said semiconductor chip with an electrode block cannot be employ | adopted. In view of this, a configuration in which a semiconductor chip is sandwiched between two highly heat-conductive insulating substrates without applying pressure is disclosed in, for example, Japanese Patent Application Laid-Open No. 59-31042. In the case of Japanese Patent Application Laid-Open No. 59-31042, the lower surface side of the semiconductor chip is fixed to the electrode provided on the insulating substrate, so that the heat generated from the semiconductor chip is radiated smoothly.
[0007]
However, on the upper surface side of the semiconductor chip, since the electrode on the upper surface side and the electrode provided on the insulating substrate are connected by the bonding pad and the metal bump, the area of the connection portion is reduced. For this reason, the electrical resistance is increased, which is disadvantageous for flowing a large current, and heat generated from the semiconductor chip is difficult to be transmitted to the insulating substrate, resulting in a problem that heat dissipation is reduced.
[0008]
Accordingly, an object of the present invention is to improve heat dissipation, to realize downsizing, and to quickly dissipate heat from two main surfaces of the semiconductor chip even if the semiconductor chip has a structure that is weak against stress. An object of the present invention is to provide a semiconductor device that can be used.
[0009]
[Means for Solving the Problems]
  According to the invention of claim 1,Made of aluminum nitride or aluminaSince the semiconductor chip is sandwiched between the two high thermal conductive insulating substrates and the electrode of the semiconductor chip and the electrode pattern of the high thermal conductive insulating substrate are joined by brazing, the heat generated in the semiconductor chip is generated in the semiconductor chip. The heat is smoothly transmitted from the two main surfaces to the two high thermal conductive insulating substrates, and heat is quickly radiated. Thereby, the structure of the semiconductor device can be miniaturized. Further, since the electrode of the semiconductor chip and the electrode pattern of the high thermal conductive insulating substrate are joined by brazing, it is not necessary to pressurize the semiconductor chip, and the area of the joined (connected) portion is increased, and the electrical resistance and Thermal resistance can be reduced. Furthermore, since the convex portion is provided on the surface on the side sandwiching the semiconductor chip in at least one of the high thermal conductive insulating substrates, and the tip of the convex portion is joined to the other high thermal conductive insulating substrate, the convex portion is A spacer can be used to maintain the distance between the two high thermal conductive insulating substrates, and the spacer need not be provided separately.
[0010]
  According to the invention of claim 2,Made of aluminum nitride or aluminaA configuration in which at least one of the high thermal conductive insulating substrates is provided with a convex portion on a surface sandwiching the semiconductor chip, and a concave portion in which the convex portion is fitted is provided on the other surface of the high thermal conductive insulating substrate between which the semiconductor chip is sandwiched. Therefore, when the convex portion is joined to the concave portion, the two high thermal conductive insulating substrates can be positioned.
[0011]
  In invention of Claim 3In this case, the brazing material for brazing the main electrode on one main surface of the semiconductor chip and the electrode pattern of the high thermal conductive insulating substrate is made of a low melting point conductive material that softens or liquefies at the semiconductor chip operating temperature. According to this configuration, since the brazing material is softened or liquefied during the operation of the semiconductor chip, fatigue does not accumulate at the joint portion, and thermal stress is not applied to the joint portion. Thereby, it is possible to realize a semiconductor device having a configuration strong against thermal cycles. In the case of this configuration, the two high thermal conductive insulating substrates are joined to each other by the convex portions provided on at least one of them, so that one main electrode of the semiconductor chip and the electrode pattern of the high thermal conductive insulating substrate Even if the brazing material for brazing is softened or liquefied, the strength of the entire semiconductor device (the bonding strength of the two high thermal conductive insulating substrates) does not decrease.
[0012]
  According to the invention of claim 4, as the low melting point conductive material, indiumOrGariuTheSince it is configured to be used, it is possible to easily realize a configuration in which the brazing material is softened or liquefied during the operation of the semiconductor chip.
[0013]
  In invention of Claim 5According to the present invention, a convex portion is provided at a portion of the electrode pattern of one high thermal conductive insulating substrate that is not bonded to the electrode of the semiconductor chip, and this convex portion is configured to be bonded to the electrode pattern of the other high thermal conductive insulating substrate. Therefore, a complicated circuit (for example, a three-phase inverter main circuit) can be configured with a simple electrode pattern.
[0014]
  According to the invention of claim 6,Since the semiconductor chip is sandwiched between two high thermal conductive insulating substrates so that the two main surfaces are opposite to each other, the plurality of semiconductor chips are separated by two high thermal conductive insulations. When sandwiched between the substrates, the shape of the electrode pattern disposed on each opposing surface of the high thermal conductive insulating substrate can be made relatively simple.
[0015]
  Claim7According to the invention ofTerminals for connecting external wiring are provided on the electrode pattern of the high thermal conductive insulating substrate so as to be parallel to the plate surface of the high thermal conductive insulating substrate and to extend outward. Thereby, normally, a separate terminal for external wiring connection can be provided, and the work of connecting the terminal and the electrode pattern can be eliminated, so that the reliability can be increased. Moreover, since the terminal for connecting the external wiring extends in a direction parallel to the plate surface of the high thermal conductive insulating substrate, avoid interference between the cooler attached to the high thermal conductive insulating substrate and the wiring connected to the terminal as much as possible. It becomes possible.
[0016]
  According to the invention of claim 8, the main electrode terminals connected to the main electrode of the semiconductor chip among the terminals for external wiring connection are provided so as to extend in the same direction, and among the terminals for external wiring connection, A control electrode terminal connected to the control electrode of the semiconductor chip was provided so as to extend in the direction opposite to the main electrode terminal. In the case of this configuration, it becomes easy to separate the control wiring and the power wiring, and the configuration is strong against noise, and it is easy to ensure that the cooling air flow path does not interfere with the wiring. Become. In addition, there is an effect of reducing the internal inductance of the semiconductor device.
In the invention of claim 9, a high thermal conductive insulating substrate is provided.In place of the aluminum nitride or the alumina, a composite formed using any one of copper, silicon carbide ceramics, silicon carbide impregnated with metal, or silicon carbide added metal cast A material and an insulating member were combined. According to this configuration, the high thermal conductivity member is excellent as a heat dissipation member.
[0017]
  Claim10In this invention, the main electrode on the main surface side of the semiconductor chip on which the control electrode is provided and the electrode pattern of the high thermal conductive insulating substrate are joined by metal bumps provided densely on the main electrode. It was set as the structure to do. According to this configuration, since there is no possibility that the brazing material (joining material) protrudes, it is suitable for the case where the semiconductor chip is relatively small. In this configuration, since the metal bumps are densely provided, the current capacity is increased and the thermal resistance is also reduced, so that the problem that occurs in the configuration in which one or several metal bumps are joined can be solved. . If the metal bump is made of gold or solder (claims)11), Providing the metal bumps in a dense manner can be easily realized.
[0018]
  Claim12According to the invention, the height of the joint portion with the electrode of the semiconductor chip in the electrode pattern of the high thermal conductive insulating substrate is made higher than that of the non-joint portion, and the size of the joint portion is set to the electrode of the semiconductor chip. Therefore, it is possible to prevent the solder from wrapping around during soldering and to avoid the guard ring of the semiconductor chip.
[0019]
  Claim13According to the invention, since the insulating resin is filled between the two high thermal conductive insulating substrates, the gap between the two high thermal conductive insulating substrates can be easily sealed.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment in which the present invention is applied to an IGBT module will be described with reference to FIGS. 1 and 2 are diagrams showing a schematic overall configuration of the IGBT module 1 of the first embodiment. As shown in FIGS. 1 and 2, the IGBT module 1 includes, for example, six IGBT chips 4 and, for example, six free wheel diode chips 5 (hereinafter referred to as FWD) between two high thermal conductive insulating substrates 2 and 3. (Referred to as a chip 5) (only three are shown in FIG. 1). In this case, the IGBT chip 4 and the FWD chip 5 constitute a semiconductor chip. Here, the specific configuration of the IGBT module 1 will be described in detail later. First, the IGBT chip 4 and the FWD chip 5 will be described.
[0021]
As shown in FIGS. 9 and 10, the IGBT chip 4 is formed in a rectangular (substantially square) plate shape as a whole, and has an upper surface 4a and a lower surface 4b as two main surfaces. A collector electrode 6 is formed on the entire lower surface 4 b (one main surface) of the IGBT chip 4. The upper surface 4a (the other main surface) of the IGBT chip 4 is formed with a substantially rectangular annular guard ring 7 at the periphery thereof, and a small rectangular gate electrode 8 is formed at the central portion thereof. An emitter electrode 9 is formed in a region between the gate electrode 8. In this case, the collector electrode 6 and the emitter electrode 9 constitute the main electrode, and the gate electrode 8 constitutes the control electrode.
[0022]
The FWD chip 5 is formed in a rectangular (substantially rectangular) plate shape as a whole. On the entire lower surface 5b of the FWD chip 5, a back surface side electrode 10 is formed. A substantially rectangular annular guard ring 11 is formed on the peripheral surface of the upper surface 5 a of the FWD chip 5, and a surface side electrode 12 is formed inside the guard ring 11.
[0023]
Now, a specific configuration of the IGBT module 1 will be described with reference to FIGS. First, the two high thermal conductive insulating substrates 2 and 3 are each made of, for example, an aluminum nitride substrate. As shown in FIG. 3A and FIG. 7, on the lower surface (the surface on the side sandwiching the semiconductor chip) of the upper high thermal conductivity insulating substrate 2 of the two high thermal conductivity insulating substrates 2, 3, Electrode patterns 13, 14, and 15 are disposed. These electrode patterns 13, 14 and 15 are made of a plate material such as copper or aluminum (for example, a plate material having a thickness of about 0.5 mm), and are directly attached to the lower surface of the high thermal conductive insulating substrate 2 by, for example, fusion. ing. In this case, instead of fusion, it may be configured to be attached by brazing (for example, soldering).
[0024]
Here, each shape of the electrode patterns 13, 14, 15 will be described. First, as shown in FIG. 7, the electrode pattern 13 is provided with a substantially rectangular substrate portion 13a and a left end portion of the substrate portion 13a in FIG. The external wiring connection terminal 13b that protrudes and the external wiring connection terminal 13c that protrudes to the right at the right end of the substrate portion 13a in FIG. 7 and protrudes from the high thermal conductive insulating substrate 2 are configured. . The substrate portion 13a is provided with three joint portions 13d having a substantially square shape projecting downward, and three joint portions 13e having a substantially rectangular shape are projecting downward. Furthermore, three elongated cutouts 13f are formed so as to reach the center of the three joints 13d.
[0025]
In this case, the size of the three joint portions 13d is set to be substantially equal to or slightly smaller than the emitter electrode 9 of the IGBT chip 4, and the protruding height dimension of each joint portion 13d is set to about 0.5 mm, for example. Has been. The size of the three joints 13e is set to be approximately equal to or slightly smaller than the surface side electrode 12 of the FWD chip 5, and the protruding height of each joint 13e is set to about 0.5 mm, for example. Has been. A brazing material (for example, a solder material) 16 is attached to each lower surface of the joint portions 13d and 13e by printing or plating (see FIG. 3A).
[0026]
Further, as shown in FIG. 7, the electrode pattern 15 includes an elongated substrate portion 15a, three branch portions 15b branched into the substrate portion 15a and disposed in the three cutout portions 13f of the electrode pattern 13. The external wiring connection terminal 15c protrudes from the high thermal conductive insulating substrate 2 and protrudes rightward from the right end portion of the substrate portion 15a in FIG. A joint portion 15d protrudes downward from each tip portion of the three branch portions 15b. In this case, the size of the three junctions 15d is set to be substantially equal to or slightly smaller than the gate electrode 8 of the IGBT chip 4, and the protruding height dimension of each junction 15d is set to about 0.5 mm, for example. Has been. Metal bumps (not shown) made of solder or gold are formed on each lower surface of the joint 15d.
[0027]
On the other hand, as shown in FIG. 7, the electrode pattern 14 is provided with a substantially rectangular substrate portion 14a and a left end portion of the substrate portion 14a in FIG. The external wiring connection terminal 14b that protrudes and the external wiring connection terminal 14c that protrudes rightward at the right end of the substrate portion 14a in FIG. 7 and protrudes from the high thermal conductive insulating substrate 2 are configured. . Three IGBT chips 4 and three FWD chips 5 are brazed (for example, soldered) to the substrate portion 14a. In this case, as shown in FIG. 3A, the collector electrode 6 of each IGBT chip 4 is joined to the substrate portion 14a via a brazing material (for example, solder material) 18. Similarly, the back surface side electrode 10 of each FWD chip 5 is joined to the substrate portion 14a via a brazing material (for example, solder material) 18.
[0028]
Next, as shown in FIG. 3C and FIG. 6, electrode patterns 19 and 20 are disposed on the upper surface of the lower high thermal conductive insulating substrate 3 (the surface on the side sandwiching the semiconductor chip). . These electrode patterns 19 and 20 are made of a plate material such as copper or aluminum (for example, a plate material having a thickness of about 0.5 mm), and are directly attached to the upper surface of the high thermal conductive insulating substrate 3 by, for example, fusion. . In this case, instead of fusion, it may be configured to be attached by brazing (for example, soldering).
[0029]
Here, the shape of the electrode pattern 19 will be described first. As shown in FIG. 6, the electrode pattern 19 protrudes rightward from the substantially square substrate portion 19a and the right end portion in FIG. 6 of the substrate portion 19a and protrudes from the high thermal conductive insulating substrate 3. The external wiring connection terminal 19b and the external wiring connection terminal 19c projecting leftward from the left end portion in FIG. 6 of the substrate portion 19a and protruding from the high thermal conductive insulating substrate 3 are configured. In the lower half of the substrate portion 19a in FIG. 5, three joint portions 19d having a substantially square shape project upward, and three joint portions 19e having a substantially rectangular shape are formed upward. Further, three elongated portions 19f are formed so as to reach the respective central portions of the three joint portions 19d.
[0030]
In this case, the size of the three joint portions 19d is set to be approximately equal to or slightly smaller than the emitter electrode 9 of the IGBT chip 4, and the protruding height dimension of each joint portion 19d is set to about 0.5 mm, for example. Has been. The size of the three joints 19e is set to be approximately equal to or slightly smaller than the surface side electrode 12 of the FWD chip 5, and the protruding height of each joint 19e is set to about 0.5 mm, for example. Has been. A brazing material (for example, solder material) 16 is attached to each upper surface of the joint portions 19d and 19e by printing or plating (see FIG. 3C).
[0031]
Further, the three IGBT chips 4 and the three FWD chips 5 are brazed (for example, soldered) to the upper half portion of the substrate portion 19a in FIG. In this case, as shown in FIG. 3C, the collector electrode 6 of each IGBT chip 4 is joined to the substrate portion 19a via a brazing material (for example, solder material) 18. Similarly, the back surface side electrode 10 of each FWD chip 5 is joined to the substrate portion 19a via a brazing material (for example, solder material) 18.
[0032]
On the other hand, as shown in FIG. 6, the electrode pattern 20 has substantially the same shape as the electrode pattern 15, and has an elongated substrate portion 20a and three notches 19f branched from the substrate portion 20a. 6 and the external wiring connection terminal 20c that protrudes leftward from the left end of the substrate 20a in FIG. 6 and protrudes leftward from the high thermal conductive insulating substrate 3. Has been. A joint portion 20d protrudes upward from each tip portion of the three branch portions 20b. In this case, the size of the three junctions 20d is set to be approximately equal to or slightly smaller than the gate electrode 8 of the IGBT chip 4, and the protruding height dimension of each junction 20d is set to about 0.5 mm, for example. Has been. Metal bumps (not shown) made of gold or solder are formed on each lower surface of the joint portion 20d.
[0033]
In the case of the above configuration, the external wiring connection terminals 13b, 14b, and 19b constitute main electrode terminals, and the external wiring connection terminals 13c, 14c, 15c, 19c, and 20c constitute control electrode terminals. .
[0034]
Next, the two high thermal conductive insulating substrates 2 and 3 formed in advance as described above are aligned as shown in FIG. 3B, and between the two high thermal conductive insulating substrates 2 and 3. 6 IGBT chips 4 and 6 FWD chips 5 are sandwiched. As a result, the joints 13d and 13e of the electrode pattern 13 of the upper high thermal conductive insulating substrate 2, the emitter electrode 9 of the IGBT chip 4 on the lower high thermal conductive insulating substrate 3 side, and the surface side electrode 12 of the FWD chip 5 are obtained. The bonding portion 15d of the electrode pattern 15 of the upper high thermal conductive insulating substrate 2 and the gate electrode 8 of the IGBT chip 4 on the lower high thermal conductive insulating substrate 3 side are in contact with each other through the brazing filler metal 16. Touch.
[0035]
At the same time, the joint portions 19d and 19e of the electrode pattern 19 of the lower high thermal conductive insulating substrate 3, the emitter electrode 9 of the IGBT chip 4 on the upper high thermal conductive insulating substrate 2 side, and the surface side electrode 12 of the FWD chip 5 The bonding portion 20d of the electrode pattern 20 of the lower high thermal conductive insulating substrate 3 and the gate electrode 8 of the IGBT chip 4 on the lower high thermal conductive insulating substrate 3 side are in contact with each other through the brazing filler metal 16. Touch.
[0036]
Subsequently, reflow is performed by heating each contact portion with a hot plate or a heating furnace. As a result, the abutting portions are brazed (specifically, soldered) and joined to form a configuration as shown in FIGS. 2 and 3B. The bonding between the gate electrode 8 of the IGBT chip 4 and the bonding portion 15e of the electrode pattern 15 and the bonding between the gate electrode 8 of the IGBT chip 4 and the bonding portion 20d of the electrode pattern 20 are performed by metal bumps. .
[0037]
In performing brazing, a low melting point brazing material (low melting point soldering material) is used as the brazing material 16 to be brazed later, and a high melting point brazing material (high melting point soldering material) is used as the brazing material 18 to be brazed first. Is used. With this configuration, the brazing material 16 reflows at a temperature lower than the melting point of the previously joined brazing material 18 at the time of subsequent brazing, so that the previously joined brazing material 18 does not melt.
[0038]
FIGS. 3A, 3B, and 3C are views in which the dimension in the thickness direction (vertical direction in FIG. 3) is considerably enlarged. FIG. 4 shows a diagram in which the dimension in the thickness direction is substantially matched to the actual dimension. As shown in FIG. 4, in the state where the six IGBT chips 4 and the six FWD chips 5 are sandwiched between the two high thermal conductive insulating substrates 2 and 3, the high thermal conductive insulating substrates 2, 3 are used. The interval is configured to be about 1 mm, for example.
[0039]
Then, after performing the above-described bonding, the insulating resin 21 is filled between the two high thermal conductive insulating substrates 2 and 3 and cured (see FIG. 5). Thereby, the IGBT module 1 is completed. As the insulating resin 21, for example, an epoxy resin or a silicone resin containing a filler is preferably used.
[0040]
FIG. 8 shows an electrical circuit diagram of the IGBT module 1 manufactured as described above. As shown in FIG. 8, the collector of the first IGBT 22 is connected to the terminal 23a and the terminal 24a, the emitter of the first IGBT 22 is connected to the terminal 23b and the terminal 24c, and the gate of the first IGBT 22 is connected to the terminal 24b. Connected. Then, both ends of the first FWD 25 are connected to the collector and emitter of the first IGBT 22 with the polarity shown in the figure. In addition, the collector of the second IGBT 26 is connected to the emitter of the first IGBT 22 (ie, the terminal 23b and the terminal 24c), the emitter of the second IGBT 26 is connected to the terminal 23c and the terminal 24e, and the gate of the second IGBT 26 is connected. Is connected to the terminal 24d. Then, both ends of the second FWD 27 are connected to the collector and emitter of the second IGBT 26 with the polarity shown in the drawing.
[0041]
In the case of this configuration, the first IGBT 22 is configured by connecting in parallel three IGBT chips 4 (specifically, three IGBT chips 4 previously soldered to the high thermal conductive insulating substrate 2). ing. Similarly, the second IGBT 26 is configured by connecting three IGBT chips 4 (specifically, three IGBT chips 4 previously soldered to the high thermal conductive insulating substrate 3) in parallel. Yes. The reason why the three IGBT chips 4 are connected in parallel is to increase the current capacity. Therefore, the number of IGBT chips 4 to be connected in parallel may be appropriately determined according to the current capacity specification.
[0042]
Further, terminals 23a to 23c in the electric circuit diagram of FIG. 8 constitute main electrode terminals, that is, power terminals, and terminals 24a to 24e constitute control electrode terminals, that is, control terminals. The correspondence relationship between the terminals 23a to 23c and 24a to 24e in the electric circuit diagram of FIG. 8 and the external wiring connection terminals of the IGBT module 1 is as follows. That is, the terminal 23a is the external wiring connection terminal 14b, the terminal 23b is the external wiring connection terminal 19b, the terminal 23c is the external wiring connection terminal 13b, and the terminal 24a is the external wiring connection terminal 14c. The terminal 24b is an external wiring connection terminal 20c, the terminal 24c is an external wiring connection terminal 19c, the terminal 24d is an external wiring connection terminal 15c, and the terminal 24e is an external wiring connection terminal 13c.
[0043]
According to this embodiment having such a configuration, the IGBT chip 4 and the FWD chip 5 are sandwiched between the two high thermal conductive insulating substrates 2 and 3, and the electrodes of the IGBT chip 4 and the FWD chip 5 and the high thermal conductive insulating substrate are sandwiched. The IGBT module 1 was configured by joining a few electrode patterns to each other by brazing (for example, soldering). Thereby, the heat generated in the IGBT chip 4 is smoothly transmitted from the upper surface 4a and the lower surface 4b of the IGBT chip 4 to the two high thermal conductive insulating substrates 2 and 3, and is quickly radiated. As a result, the configuration of the IGBT module 1 can be greatly reduced in size. Since the electrodes of the IGBT chip 4 and the electrode patterns of the high thermal conductive insulating substrates 2 and 3 are joined by brazing, it is not necessary to pressurize the IGBT chip 4, and the area of the joined (connected) portion is large. Become. Thereby, the current resistance and the thermal resistance can be reduced, and a large current can flow.
[0044]
In the above embodiment, the IGBT chip 4 and the FWD chip 5 are sandwiched between the two high thermal conductive insulating substrates 2 and 3 so that the directions of the two main surfaces are opposite to each other. . Specifically, the three IGBT chips 4 previously soldered to the high thermal conductive insulating substrate 2 and the three IGBT chips 4 soldered to the high thermal conductive insulating substrate 3 are opposite to each other. It has become a relationship. Thus, for example, when six IGBT chips 4 are sandwiched between two high thermal conductive insulating substrates 2 and 3, electrode patterns 13 and 14 disposed on the opposing surfaces of the high thermal conductive insulating substrates 2 and 3, respectively. , 15, 19, and 20 can be made relatively simple.
[0045]
Furthermore, in the above embodiment, the external wiring connection terminals 13b, 13c, 14b, 14c, 15c, 19b, 19c, and 20c are provided on the electrode patterns 13, 14, 15, 19, and 20 of the high thermal conductive insulating substrates 2 and 3, respectively. It provided so that it might become parallel to the plate | board surface (surface in which the electrode pattern was arrange | positioned) of the high heat conductive insulating substrates 2 and 3 and was extended outside. Thereby, normally, a separate terminal for connecting external wiring can be provided, and the work of connecting the terminal and the electrode pattern can be eliminated, so that the reliability can be increased. In the above embodiment, the external wiring connection terminals 13b, 13c, 14b, 14c, 15c, 19b, 19c, and 20c extend in a direction parallel to the plate surfaces of the high thermal conductive insulating substrates 2 and 3, so that high thermal conductivity is achieved. It is easy to avoid interference between the coolers attached to the outer surfaces of the conductive insulating substrates 2 and 3 and the wirings connected to the terminals 13b, 13c, 14b, 14c, 15c, 19b, 19c, and 20c.
[0046]
In particular, in the above embodiment, the main electrode terminals 13b, 14b, 19b connected to the main electrodes 6, 9 of the IGBT chip 4 among the external wiring connection terminals are provided so as to extend in the same direction, and the IGBT chip 4 The control electrode terminals 15c and 20c connected to the control electrode 8 are provided so as to extend in the opposite direction to the main electrode terminals 13b, 14b and 19b. According to this configuration, it is easy to separate the control wiring and the power wiring, so that the configuration is strong against noise and the cooling air flow path is ensured not to interfere with the wiring. And the cooling performance is improved. Further, the effect of reducing the internal inductance of the IGBT module 1 can be obtained.
[0047]
In the above embodiment, the high thermal conductive insulating substrates 2 and 3 are made of aluminum nitride. In this case, since the thermal expansion coefficient of aluminum nitride is close to the thermal expansion coefficient of silicon constituting the IGBT chip 4 and the FWD chip 5, they are disposed on the IGBT chip 4 and the FWD chip 5 and the high thermal conductive insulating substrates 2 and 3. Thermal stress acting between the electrode patterns 13, 14, 15, 19, and 20 can be reduced.
[0048]
Furthermore, in the said Example, the junction parts 13d, 13e, 15d joined to the electrode of the IGBT chip | tip 4 and the FWD chip | tip 5 of the electrode patterns 13, 14, 15, 19, and 20 of the high heat conductive insulating substrates 2 and 3; The height of 19d, 19e, and 20d is configured to be higher than that of the non-joined portion, and the size of each joint portion is configured to be the same as or smaller than the electrodes of the chips 4 and 5, so that the solder wraps around during soldering. In addition to being able to prevent, the guard rings 7 and 11 of the chips 4 and 5 can be avoided and bonded. This facilitates the soldering operation. In the above-described embodiment, the height of each joint is set to about 0.5 mm. This is because the 600V IGBT module 1 has a configuration in which a gap is filled with an epoxy resin to obtain a required withstand voltage. is there. Therefore, the height dimension of each joint may be determined as appropriate according to the required pressure resistance.
[0049]
In the above embodiment, when the chips 4 and 5 are brazed (soldered) to the electrode patterns of the high thermal conductive insulating substrates 2 and 3, the brazing materials 16 and 18 are attached to the joint portions of the electrode patterns by printing or the like. However, instead of this, the brazing materials 16 and 18 may be attached to the electrodes (pads) of the chips 4 and 5 by printing or the like. A brazing foil (solder foil) may be sandwiched between the joints.
[0050]
Further, in the above embodiment, after the chips 4 and 5 are soldered to the respective surfaces of the high thermal conductive insulating substrates 2 and 3, the high thermal conductive insulating substrates 2 and 3 are combined and the soldering operation is performed once again. However, instead of this, by performing the soldering operation once in a state where the chips 4 and 5 are sandwiched between the high thermal conductive insulating substrates 2 and 3, the chips 4 and 5 are bonded to the high thermal conductive insulating substrate 2. 3 may be configured to be soldered. In the case of this configuration, the same (melting temperature) solder material is used as the solder materials (brazing materials) 16 and 18. A spacer is inserted between the two high thermal conductive insulating substrates 2 and 3. The thickness dimension of the spacer is determined in consideration of the thickness of the chips 4 and 5 and the thickness of the solder after reflow.
[0051]
Further, the thermal expansion coefficient of the spacer is preferably the same as or slightly larger than the average thermal expansion coefficient of each component housed between the high thermal conductive insulating substrates 2 and 3. Further, at the time of the soldering, the chips 4 and 5 are floated in the melted solder during the reflow. In this case, since the joint part joined to the electrode on the surface side of each chip 4 and 5 in the electrode pattern is higher (protruding) than the non-joint part, solder does not flow out of the joint part. . Thereby, even if the position of each chip | tip 4 and 5 has shifted | deviated somewhat, each chip | tip 4 and 5 comes to be positioned in the position corresponding to a junction part by the surface tension of solder.
[0052]
On the other hand, in the said Example, the structure which joins the junction part 15e of the gate electrode 8 and the electrode pattern 15 of the IGBT chip | tip 4 and the junction part 15d of the IGBT chip | tip 4 and the electrode pattern 20 by a metal bump. However, the present invention is not limited to this, and may be configured to be soldered if solderable. Since the current flowing through the gate electrode 8 of the IGBT chip 4 is very small, there is no problem even if the gate electrode 8 and the joint portion of the electrode pattern are joined by a normal metal bump (one metal bump). It does not occur.
[0053]
Further, in the above embodiment, the main electrode on the upper surface side of the chip 4 and the joint portion of the electrode pattern of the high thermal conductive insulating substrates 2 and 3 are joined by soldering, but this is not restrictive. Specifically, a configuration in which several tens to several hundreds of metal bumps are densely formed on the main electrode on the upper surface side of the chip 4 and bonded via these dense metal bumps is preferable. As a material for the metal bump, gold or solder is preferable. When gold bumps are formed, tin is vapor-deposited on the surface (electrode pattern bonding portion) to be bonded to the gold bumps, and bonded by a eutectic reaction between gold and tin.
[0054]
According to this configuration, since there is no possibility that the brazing material (bonding material) protrudes, it is suitable for the case where the semiconductor chip 4 is relatively small. In the case of this configuration, since a large number of metal bumps are provided densely, the current capacity is increased and the thermal resistance is reduced, so that the same effect as that of the first embodiment can be obtained.
[0055]
Moreover, in the said Example, although the main electrode of the lower surface side of the chip | tip 4 and the electrode pattern of the high thermal conductive insulating substrates 2 and 3 were joined by soldering, it is not restricted to this, The said main electrode and the said electrode If it is possible to directly bond the pattern by fusion or the like, the pattern may be directly bonded.
[0056]
In the above-described embodiment, the six IGBT chips 4 are accommodated between the high thermal conductive insulating substrates 2 and 3. However, the present invention is not limited to this, and is accommodated between the high thermal conductive insulating substrates 2 and 3. The number of semiconductor chips to be used may be one or plural (2 to 5 or 7 or more).
[0057]
FIGS. 13 and 14 show a second embodiment of the present invention, and the differences from the first embodiment will be described. The same parts as those in the first embodiment are denoted by the same reference numerals. In the second embodiment, as shown in FIG. 13, at both ends of the surface on the side sandwiching the IGBT chip 4 in the lower high thermal conductivity insulating substrate 3 which is at least one of the high thermal conductivity insulating substrates 2 and 3. Protrusions 28a and 28b are provided. And the front-end | tip part of this convex part 28a, 28b was set as the structure joined to the surface of the side which pinches | interposes the IGBT chip | tip 4 in the other high thermal conductive insulating board 2 which is the other (refer FIG. 14).
[0058]
According to the above configuration, since the convex portions 28a and 28b can be used as a spacer for maintaining the distance between the two high thermal conductive insulating substrates 2 and 3, it is not necessary to provide a separate spacer and the number of components is reduced. can do. The configuration of the second embodiment other than that described above is the same as that of the first embodiment.
[0059]
Further, in the second embodiment, the convex portions 28a and 28b protrude from only one high thermal conductive insulating substrate 3, but instead, the third embodiment shown in FIG. 15 and FIG. As shown in the example, convex portions 28a and 28b and convex portions 29a and 29b are provided on both of the two high thermal conductive insulating substrates 2 and 3, and the respective tip portions of the convex portions 28a and 28b and the convex portions 29a and 29b are provided. May be configured to be joined to each other. Even if comprised in this way, the same effect as a 2nd Example can be acquired.
[0060]
FIGS. 17 and 18 show a fourth embodiment of the present invention, and differences from the second embodiment will be described. The same parts as those in the second embodiment are denoted by the same reference numerals. In the fourth embodiment, convex portions 30a and 30b are provided at both ends of the lower surface of the upper high thermal conductive insulating substrate 2. Further, recessed portions 31 a and 31 b which are lowered by one step are provided at both end portions of the upper surface of the lower high thermal conductive insulating substrate 3. When the two high thermal conductive insulating substrates 2 and 3 are put together, the tips of the convex portions 30a and 30b are fitted and joined to the concave portions 31a and 31b (see FIG. 18).
[0061]
Therefore, in the fourth embodiment, the convex portions 30a, 30b of one high thermal conductive insulating substrate 2 and the concave portions 31a, 31b of the other high thermal conductive insulating substrate 3 are fitted and joined. Two high thermal conductive insulating substrates 2 and 3 can be positioned.
[0062]
In the case of the second to fourth embodiments, the convex portions 28a, 28b, 29a, 29b, 30a, and 30b are used as spacers, and the two high thermal conductive insulating substrates 2 and 3 are joined by these convex portions. Therefore, as a brazing material (solder material) used for brazing (soldering) the main electrode on one main surface of the IGBT chip 4 and the joint portion of the electrode pattern, the IGBT chip 4 is softened or liquefied at the operating temperature of the IGBT chip 4. It is possible to use a brazing material (solder material) made of a low melting point conductive material.
[0063]
According to this configuration, since the brazing material (solder material) is softened or liquefied during the operation of the IGBT chip 4, fatigue does not accumulate at the joint portion and thermal stress is not applied to the joint portion. Even if the brazing material (solder material) is softened or liquefied, the two high thermal conductive insulating substrates 2 and 3 are joined by the convex portions 28a, 28b, 29a, 29b, 30a, and 30b, so that the strength is high. There is no problem. Thereby, the IGBT module 1 of a structure strong against a heat cycle is realizable. In the case of the above configuration, it is preferable to use indium, gallium, or low-temperature solder as the low melting point conductive material.
[0064]
19 to 23 show a fifth embodiment of the present invention, and different points from the first embodiment will be described. The same parts as those in the first embodiment are denoted by the same reference numerals. In the fifth embodiment, the high thermal conductive insulating substrate is configured by combining a high thermal conductive member and an insulating member. Specifically, as shown in FIG. 21, the upper high thermal conductive insulating substrate 32 is composed of an insulating member such as an aluminum nitride substrate 33 and a high thermal conductive member such as a copper plate 34. . The aluminum nitride substrate 33 is thinner than the high thermal conductive insulating substrate (aluminum nitride substrate) 2 of the first embodiment, and a copper film 35 is formed on the upper surface in FIG. In the case of this configuration, the copper plate 34 is bonded to the upper surface of the copper film 35 of the aluminum nitride substrate 33 in FIG.
[0065]
The size of the copper plate 34 is configured to be slightly larger than the aluminum nitride substrate 33. On the lower surface in FIG. 21 of the aluminum nitride substrate 33, electrode patterns 13, 14, 15, IGBT chip 4 and FWD chip 5 are provided in the same manner as the high thermal conductive insulating substrate 2 of the first embodiment. It has been.
[0066]
On the other hand, the lower high thermal conductive insulating substrate 36 is made of an insulating member such as an aluminum nitride substrate 37 and a high thermal conductive member such as a copper plate 38 in the same manner as the upper high thermal conductive insulating substrate 32. It is composed of The aluminum nitride substrate 37 is thinner than the high thermal conductive insulating substrate (aluminum nitride substrate) 3 of the first embodiment, and a copper film 39 is formed on the lower surface in FIG. A copper plate 38 is bonded to the lower surface of the copper film 39 of the aluminum nitride substrate 37 in FIG. 21 by brazing (a brazing material 38a). The size of the copper plate 38 is slightly larger than that of the aluminum nitride substrate 37. Further, on the upper surface in FIG. 21 of the substrate 37 made of aluminum nitride, the electrode patterns 19 and 20, the IGBT chip 4 and the FWD chip 5 are provided in the same manner as the high thermal conductive insulating substrate 3 of the first embodiment. Yes.
[0067]
The operation of joining the two high thermal conductive insulating substrates 32 and 36 together by brazing is the same as the joining operation of the first embodiment. By this joining, the configuration shown in FIGS. 20 and 22 is obtained. Then, by filling (injecting) an insulating resin 21 such as an epoxy resin or a silicone resin between the two high thermal conductive insulating substrates 32 and 36 bonded together, the IGBT module 1 as shown in FIG. Manufactured.
[0068]
The configuration of the fifth embodiment other than that described above is the same as that of the first embodiment. Therefore, also in the fifth embodiment, the same operational effects as in the first embodiment can be obtained. In particular, in the fifth embodiment, since the high thermal conductive insulating substrates 32 and 36 are formed by joining the copper plates 34 and 38 and the aluminum nitride substrates 33 and 37, the aluminum nitride substrates 33 and 37 are thin. That is, it is possible to use an inexpensive one, and furthermore, since the copper plates 34 and 38 are inexpensive, the manufacturing cost of the high thermal conductive insulating substrates 32 and 36 can be reduced.
[0069]
In the fifth embodiment, the aluminum nitride substrates 33 and 37 are used as the insulating member. However, instead of this, a ceramic substrate such as an alumina substrate may be used. In the fifth embodiment, the copper plates 34 and 38 are used as the high thermal conductivity members. However, the present invention is not limited to this, and a structure using a composite material of silicon carbide and aluminum may be used. In the case of this configuration, when an aluminum film is formed on the aluminum nitride substrates 33 and 37 instead of the copper films 35 and 39, the composite material of silicon carbide and aluminum is fused to the aluminum film. Is easy. Further, as the high thermal conductive member, any one of copper, silicon carbide ceramics, silicon carbide impregnated with metal, or composite material formed by casting metal added with silicon carbide It is also preferable to adopt a configuration using
[0070]
24 and 25 show a sixth embodiment of the present invention, and the differences from the fifth embodiment will be described. The same parts as those in the fifth embodiment are denoted by the same reference numerals. In the sixth embodiment, as shown in FIG. 24, convex portions 40a and 40b are provided at both ends of the upper surface of the copper plate 38 of the lower high thermal conductive insulating substrate 36 where the aluminum nitride substrate 37 is not present. . And the front-end | tip part of this convex part 40a, 40b was comprised so that it might join to the both ends which do not have the board | substrate 33 made from aluminum nitride in the lower surface of the copper plate 34 of the upper high heat conductive insulating board 32, for example by brazing (FIG. 25).
[0071]
According to the above configuration, since the convex portions 40a and 40b can be used as a spacer for keeping the distance between the two high thermal conductive insulating substrates 32 and 36, it is not necessary to provide a separate spacer, and the number of components is reduced. can do. The configuration of the sixth embodiment other than that described above is the same as that of the fifth embodiment.
[0072]
Moreover, in the said 6th Example, it was set as the structure which protruded only by the copper plate 38 of one high heat conductive insulation board 36, but it has the structure which protrudes 40a, 40b, it replaces with this and shows to FIG.26 and FIG.27. As in the seventh embodiment, convex portions 40a and 40b and convex portions 41a and 41b are provided on both of the copper plates 34 and 38 of the two high thermal conductive insulating substrates 32 and 36, and the convex portions 40a and 40b You may comprise so that each front-end | tip part of part 41a, 41b may mutually be joined. Even if comprised in this way, the same effect as the 6th example can be obtained.
[0073]
28 and 29 show an eighth embodiment of the present invention, and differences from the sixth embodiment will be described. The same parts as those in the sixth embodiment are denoted by the same reference numerals. In the eighth embodiment, convex portions 42a and 42b are provided at both ends of the lower surface of the copper plate 34 of the upper high thermal conductive insulating substrate 32. Further, recessed portions 43a and 43b which are lowered by one step are provided at both ends of the upper surface of the copper plate 38 of the lower high thermal conductive insulating substrate 36. When the two high thermal conductive insulating substrates 32 and 36 are put together, the tips of the convex portions 42a and 42b are fitted and joined to the concave portions 43a and 43b (see FIG. 29). Therefore, in the eighth embodiment, the two high thermal conductive insulating substrates 32 and 36 can be positioned by fitting and joining the convex portions 42a and 42b and the concave portions 43a and 43b.
[0074]
30 and 31 show a ninth embodiment of the present invention, and differences from the first embodiment will be described. The same parts as those in the first embodiment are denoted by the same reference numerals. In the ninth embodiment, when the two high thermal conductive insulating substrates 2 and 3 are joined together, the electrode pattern of one high thermal conductive insulating substrate 2 and the electrode of the other high thermal conductive insulating substrate 3 are combined. It is comprised so that a pattern may be joined.
[0075]
Specifically, as shown in FIG. 30, a convex portion 46 is provided in a portion of the electrode pattern 44 of one high thermal conductive insulating substrate 2 that is not joined to the electrode of the semiconductor chip 45, and the convex portion 46 is provided on the other side. For example, the electrode pattern 47 of the high thermal conductive insulating substrate 3 is joined by brazing. According to this configuration, it is easy to form a complicated circuit (for example, a three-phase inverter main circuit) that needs to connect the electrode patterns 44 and 47 of the two high thermal conductive insulating substrates 2 and 3. It is possible to configure the electrode patterns 44 and 47 with various shapes.
[0076]
When a plurality of IGBT chips 4 are accommodated between the two high thermal conductive insulating substrates 2 and 3 as the semiconductor chip 45 as in the first embodiment, the shape of the electrode patterns 44 and 47 is What is necessary is just to comprise in the shape substantially the same as each electrode pattern of 1 Example, and should just determine each shape of the electrode patterns 44 and 47 as needed.
[0077]
FIGS. 32 to 38 show a tenth embodiment of the present invention, and differences from the first embodiment will be described. In the tenth embodiment, the two high thermal conductive insulating substrates 48 and 49 are composed of insulating members 50 and 51 and electrodes 52, 53, 54, 55 and 56 embedded in the insulating members 50 and 51. It is configured. First, the upper high thermal conductive insulating substrate 48 will be described with reference to FIG.
[0078]
The high thermal conductive insulating substrate 48 is configured by embedding three copper plate electrodes 52, 53, and 54 in an insulating member 50 made of a ceramic material such as aluminum nitride or alumina. As shown in FIG. 37, the first electrode 52 includes three chip mounting plate portions 52a, 52b, and 52c for mounting a semiconductor chip, and upper ends of these chip mounting plate portions 52a, 52b, and 52c in FIG. The connection part 52d which connects a part, and the terminal 52e for external wiring connection projected from this connection part 52d toward the upper direction in FIG. 37 are comprised. An IGBT chip 57 and an FWD chip 58 are brazed (for example, soldered) to the three chip mounting plate portions 52a, 52b, and 52c, respectively. In this case, the collector electrode on the back surface side of each IGBT chip 57 is brazed.
[0079]
As shown in FIG. 37, the second electrode 53 includes three bonding plate portions 53a and 53b having bonding portions for bonding to the electrodes of the semiconductor chip attached to the lower high thermal conductive insulating substrate 49. 53c, a connecting portion 53d for connecting the upper end portions in FIG. 37 of these joining plate portions 53a, 53b, and 53c, and an external wiring connecting terminal 53e protruding upward from the connecting portion 53d in FIG. It is composed of The bonding plate portions 53a, 53b, and 53c have a substantially square shape for bonding to the emitter electrode of the IGBT chip 57 and a substantially rectangular shape for bonding to the surface side electrode of the FWD chip 58, respectively. The formed joint part 53g is provided so as to protrude slightly downward (for example, about 0.5 mm). A brazing material (for example, a solder material) is attached to each lower surface of the joint portions 53f and 53g by printing or plating. Moreover, the notch part 53h is each formed in the upper end part in FIG. 37 of the said 3 joining board part 53a, 53b, 53c.
[0080]
Further, as shown in FIGS. 32 and 37, the third electrode 54 includes three elongated branch plate portions 54a, 54b, 54c disposed in the three cutout portions 53h of the second electrode 53, and A connecting portion 54d for connecting the upper end portions in FIG. 37 of these branch plate portions 54a, 54b, 54c, and an external wiring connecting terminal 54e protruding from the right end portion in FIG. It is composed of At each tip of the branch plate portions 54a, 54b, 54c, a joint portion 54f for joining to the gate electrode of the IGBT chip 57 is provided so as to slightly protrude downward (for example, about 0.5 mm). Yes. Metal bumps made of solder or gold are formed on each lower surface of the joint portion 54f.
[0081]
When manufacturing the high thermal conductivity insulating substrate 48, the insulating member 50 is formed by sintering in a form in which a hollow portion for embedding the three electrodes 52, 53, 54 is formed in advance. Then, after the three electrodes 52, 53, 54 are accommodated in the insulating member 50, a brazing material is soaked in the gap and fixed. In this case, as the brazing material, a brazing material (hard brazing material) having a melting point higher than that of the brazing material used when joining the semiconductor chips is used. When the work of embedding the three electrodes 52, 53, 54 in the insulating member 50 is completed, an insulating material made of, for example, aluminum nitride is formed on the upper surface of the high thermal conductivity insulating substrate 48 (electrodes 52, 53, 54) in FIG. A film 60 is formed. Subsequently, after the insulating film 60 is formed, the IGBT chip 57 and the FWD chip 58 are brazed to the first electrode 52.
[0082]
On the other hand, the lower high thermal conductive insulating substrate 49 is configured by embedding two copper plate electrodes 55 and 56 in an insulating member 51 made of a ceramic material such as aluminum nitride or alumina. As shown in FIG. 38, the first electrode 55 includes a substrate portion 55a and an external wiring connection terminal 55b projecting downward from the lower end portion of the substrate portion 55a in FIG. Yes. Three IGBT chips 57 and FWD chips 58 are brazed to the substrate portion 55a so as to correspond to the three joint portions 53f and 53g of the second electrode 53 of the upper high thermal conductive insulating substrate 48, respectively. Has been. In this case, the collector electrode on the back surface side of each IGBT chip 57 is brazed.
[0083]
The substrate portion 55a has a substantially square shape so as to correspond to each of the three IGBT chips 57 and the FWD chip 58 brazed to the first electrode 52 of the upper high thermal conductive insulating substrate 48. The three joint portions 55c and the three joint portions 55d having a substantially rectangular shape are provided so as to protrude slightly (for example, about 0.5 mm) downward. A brazing material (for example, a solder material) is attached to each upper surface of the joint portions 55c and 55d by printing or plating (see FIG. 34). Further, a notch 55e is formed at each of the lower end portions in FIG. 38 of the three joint portions 55c of the substrate portion 55a.
[0084]
Further, as shown in FIGS. 32 and 38, the second electrode 56 includes three elongated branch plate portions 56a, 56b, 56c disposed in the three cutout portions 55e of the first electrode 55, and A connecting portion 56d for connecting the lower end portions in FIG. 38 of the branch plate portions 56a, 56b, and 56c, and an external wiring connecting terminal 56e that protrudes leftward from the right end portion in FIG. 32 of the connecting portion 56d. It is composed of A junction portion 56f (see FIG. 38) for joining to the gate electrode of the IGBT chip 57 slightly protrudes (for example, about 0.5 mm) at each tip portion of the branch plate portions 56a, 56b, and 56c. It is provided as follows. Metal bumps made of solder or gold are formed on the upper surfaces of the joint portions 56f.
[0085]
The high thermal conductivity insulating substrate 49 is manufactured in the same manner as the upper high thermal conductivity insulating substrate 48. When the work of embedding the two electrodes 55 and 56 in the insulating member 51 is completed, the insulating film 61 made of, for example, aluminum nitride is formed on the lower surface in FIG. 34 of the high thermal conductive insulating substrate 49 (electrodes 52, 53, 54). Form. Subsequently, after the insulating film 61 is formed, the IGBT chip 57 and the FWD chip 58 are brazed to the first electrode 55.
[0086]
Next, the two high thermal conductive insulating substrates 48 and 49 formed as described above are combined as shown in FIG. The IGBT chip 57 and the six FWD chips 58 are sandwiched. As a result, the joint portions 53f and 53g of the electrode 53 of the upper high thermal conductive insulating substrate 48, the emitter electrode of the IGBT chip 57 on the lower high thermal conductive insulating substrate 49 side, and the surface side electrode of the FWD chip 58 are connected. The joint 54f of the electrode 54 of the upper high thermal conductive insulating substrate 48 and the gate electrode of the IGBT chip 57 on the lower high thermal conductive insulating substrate 49 are in contact with each other.
[0087]
At the same time, the joint portions 55c and 55d of the electrode 55 of the lower high thermal conductive insulating substrate 49, the emitter electrode of the IGBT chip 57 on the upper high thermal conductive insulating substrate 48 side, and the surface side electrode of the FWD chip 58 are brazed. The junction 56f of the electrode 56 of the lower high thermal conductivity insulating substrate 49 and the gate electrode of the IGBT chip 57 on the upper higher thermal conductivity insulating substrate 48 side are in contact with each other.
[0088]
Subsequently, reflow is performed by heating each contact portion with a hot plate or a heating furnace. As a result, the contact portions are brazed (specifically, soldered) and joined, resulting in the form shown in FIGS. 33 and 35. Note that the junction between the gate electrode of the IGBT chip 57 and the junction 54f of the electrode 53 and the junction between the gate electrode of the IGBT chip 57 and the junction 56f of the electrode pattern 56 are performed through metal bumps.
[0089]
Note that FIG. 34 is a view that is considerably enlarged in the thickness direction (vertical direction in the drawing), and FIG. After the brazing and bonding described above, an insulating resin 62 made of, for example, an epoxy resin or a silicone resin is filled between the two high thermal conductive insulating substrates 48 and 49 and cured. Thereby, the IGBT module 63 is completed. When the cooler is attached to the IGBT module 63, the cooler is attached to the upper and lower surfaces of the high thermal conductive insulating substrates 48 and 49, that is, the upper surface of the insulating film 60 and the lower surface of the insulating film 61, respectively.
[0090]
Since the tenth embodiment is configured as described above, the heat generated from the IGBT chip 57 passes through the electrodes 52, 53, 55 brazed to the upper and lower main surfaces of the IGBT chip 57. The heat is quickly dissipated, and almost the same effect as the first embodiment can be obtained.
[0091]
In the above embodiment, the electrodes 52, 53, 54, 55, and 56 are made of copper. However, the present invention is not limited to this, and the electrodes 52, 53, 54, 55, and 56 may be made of a metal containing Mo or W. When such a metal electrode is used, the thermal expansion coefficient matching with the insulating members 50 and 51 is improved.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view of an IGBT module showing a first embodiment of the present invention.
FIG. 2 is a perspective view of an IGBT module.
FIG. 3 is an enlarged longitudinal sectional view showing a manufacturing process.
FIG. 4 is a longitudinal sectional view of an IGBT module.
FIG. 5 is a longitudinal sectional view of an IGBT module filled with an insulating resin.
FIG. 6 is a top view of the lower high thermal conductive insulating substrate.
FIG. 7 is a bottom view of the upper high thermal conductive insulating substrate.
[Fig. 8] Electrical circuit diagram
FIG. 9 is a perspective view of an IGBT chip.
FIG. 10 is a longitudinal sectional view of an IGBT chip.
FIG. 11 is a perspective view of an FWD chip.
FIG. 12 is a vertical sectional view of an FWD chip.
FIG. 13 is a view corresponding to FIG. 1 showing a second embodiment of the present invention.
14 is equivalent to FIG.
FIG. 15 is a view corresponding to FIG. 1 showing a third embodiment of the present invention.
FIG. 16 is a diagram corresponding to FIG.
FIG. 17 is a view corresponding to FIG. 1, showing a fourth embodiment of the present invention.
18 is equivalent to FIG.
FIG. 19 is a view corresponding to FIG. 1, showing a fifth embodiment of the present invention.
FIG. 20 is a view corresponding to FIG.
FIG. 21 is a view corresponding to FIG.
22 is equivalent to FIG.
FIG. 23 is a view corresponding to FIG.
FIG. 24 is a view corresponding to FIG. 1, showing a sixth embodiment of the present invention.
FIG. 25 is a view corresponding to FIG.
FIG. 26 is a view corresponding to FIG. 1 showing a seventh embodiment of the present invention.
FIG. 27 is a view corresponding to FIG.
FIG. 28 is a view corresponding to FIG. 1 showing an eighth embodiment of the present invention.
29 is equivalent to FIG.
FIG. 30 is an exploded longitudinal sectional view showing a ninth embodiment of the present invention.
FIG. 31 is a longitudinal sectional view.
FIG. 32 is a view corresponding to FIG. 1, showing a tenth embodiment of the present invention.
33 is a view corresponding to FIG.
34 is a view corresponding to FIG.
FIG. 35 is equivalent to FIG.
36 is a view corresponding to FIG.
FIG. 37 is a view corresponding to FIG.
FIG. 38 is a diagram corresponding to FIG.
[Explanation of symbols]
1 is an IGBT module (semiconductor device), 2 is a highly thermally conductive insulating substrate, 4 is an IGBT chip (semiconductor chip), 4a is an upper surface (main surface), 4b is a lower surface (main surface), and 5 is an FWD chip (semiconductor). Chip), 6 is a collector electrode (main electrode), 7 is a guard ring, 8 is a gate electrode (control electrode), 9 is an emitter electrode (main electrode), 10 is a back side electrode, 11 is a guard ring, and 12 is a front side. Electrode, 13 is an electrode pattern, 13b is an external wiring connection terminal (main electrode terminal), 13c is an external wiring connection terminal (control electrode terminal), 13d and 13e are joint portions, 14 is an electrode pattern, and 14b is an external device. Wiring connection terminal (main electrode terminal), 14c is an external wiring connection terminal (control electrode terminal), 14d is a joint, 15 is an electrode pattern, 15c is an external wiring connection terminal (control electrode terminal), 15d Joint part, 19 is an electrode pattern, 19b is an external wiring connection terminal (main electrode terminal), 19c is an external wiring connection terminal (control electrode terminal), 19d and 19e are joint parts, 20 is an electrode pattern, and 20c is External wiring connection terminal (control electrode terminal), 20d is a joint portion, 21 is an insulating resin, 28a and 28b are convex portions, 29a and 29b are convex portions, 30a and 30b are convex portions, 31a and 31b are concave portions, and 32 Is a high thermal conductive insulating substrate, 33 is an aluminum nitride substrate (insulating member), 34 is a copper plate (high thermal conductive member), 34a is a brazing material, 35 is a copper film, 36 is a high thermal conductive insulating substrate, and 37 is nitrided An aluminum substrate (insulating member), 38 is a copper plate (high thermal conductivity member), 38a is a brazing material, 39 is a copper film, 40a and 40b are convex portions, 41a and 41b are convex portions, 42a and 42b are convex portions, 43a, 43b Recess, 44 is electrode pattern, 45 is semiconductor chip, 46 is convex, 47 is electrode pattern, 48 and 49 are high thermal conductive insulating substrates, 57 is IGBT chip, 58 is FWD chip, 63 is IGBT module (semiconductor device) Indicates.

Claims (13)

  1. One or more semiconductor chips having a main electrode on one main surface and a main electrode and a control electrode on the other main surface;
    Two high thermal conductive insulating substrates made of aluminum nitride or alumina, which are provided so as to sandwich the semiconductor chip, and are provided with electrode patterns for bonding to the electrodes of the semiconductor chip on each sandwiching surface, are provided. ,
    The electrode of the semiconductor chip and the electrode pattern of the high thermal conductivity insulating substrate are joined by brazing,
    A semiconductor device, wherein a convex portion is provided on a surface sandwiching the semiconductor chip in at least one of the high thermal conductive insulating substrates, and a tip portion of the convex portion is joined to the other high thermal conductive insulating substrate.
  2. One or more semiconductor chips having a main electrode on one main surface and a main electrode and a control electrode on the other main surface;
    Two high thermal conductive insulating substrates made of aluminum nitride or alumina, which are provided so as to sandwich the semiconductor chip, and are provided with electrode patterns for bonding to the electrodes of the semiconductor chip on each sandwiching surface, are provided. ,
    The electrode of the semiconductor chip and the electrode pattern of the high thermal conductivity insulating substrate are joined by brazing,
    A convex portion is provided on the surface on the side of sandwiching the semiconductor chip in at least one of the high thermal conductivity insulating substrates, and the concave portion is engaged with the surface on the side of sandwiching the semiconductor chip in the other high thermal conductivity insulating substrate. And the convex portion is joined to the concave portion.
  3.   The brazing material for brazing the main electrode on one main surface of the semiconductor chip and the electrode pattern of the high thermal conductive insulating substrate is made of a low melting point conductive material that softens or liquefies at the semiconductor chip operating temperature. The semiconductor device according to claim 1, wherein:
  4. The low melting point conductive material, a semiconductor device according to claim 3, wherein the indium or Gallium.
  5. One or more semiconductor chips having a main electrode on one main surface and a main electrode and a control electrode on the other main surface;
    Two high thermal conductive insulating substrates made of aluminum nitride or alumina, which are provided so as to sandwich the semiconductor chip, and are provided with electrode patterns for bonding to the electrodes of the semiconductor chip on each sandwiching surface, are provided. ,
    The electrode of the semiconductor chip and the electrode pattern of the high thermal conductivity insulating substrate are joined by brazing,
    Protrusion is provided in the part of the electrode pattern of one high thermal conductive insulating substrate that is not bonded to the electrode of the semiconductor chip, and this convex part is configured to be bonded to the electrode pattern of the other high thermal conductive insulating substrate. A semiconductor device characterized by the above.
  6.   6. The semiconductor according to any one of claims 1 to 5, wherein the semiconductor chips are sandwiched between the two high thermal conductive insulating substrates so that semiconductor chips in which directions of two main faces are opposite to each other are mixed. apparatus.
  7.   7. The electrode pattern of the high thermal conductivity insulating substrate is provided with a terminal for connecting an external wiring so as to be parallel to the plate surface of the high thermal conductivity insulating substrate and to extend outward. The semiconductor device according to any one of the above.
  8. Among the external wiring connection terminals, the main electrode terminals connected to the main electrode of the semiconductor chip are provided to extend in the same direction, and
    8. The semiconductor according to claim 7, wherein a control electrode terminal connected to a control electrode of the semiconductor chip among the terminals for connecting the external wiring is provided so as to extend in a direction opposite to the main electrode terminal. apparatus.
  9. Any of the high thermal conductivity insulating substrate, wherein instead of the aluminum nitride or the alumina, copper, silicon carbide ceramic, which metal is impregnated with silicon carbide, although the metal addition of silicon carbide and casting 9. The semiconductor device according to claim 1, wherein the semiconductor device is configured by combining a composite material formed using the above and an insulating member .
  10. The main electrode on the main surface side of the semiconductor chip on which the control electrode is provided and the electrode pattern of the high thermal conductive insulating substrate are joined by metal bumps provided densely on the main electrode. The semiconductor device according to claim 1 or 2 .
  11. The semiconductor device according to claim 10 , wherein the metal bump is made of gold or solder .
  12. Of the electrode pattern of the high thermal conductivity insulating substrate, the height of the joint portion with the electrode of the semiconductor chip is higher than that of the non-joint portion, and the size is the same as or smaller than the electrode of the semiconductor chip. the semiconductor device according to any one of claims 1 to 11, characterized in that it is configured to.
  13. The semiconductor device according to any one of between the two high thermal conductivity insulating substrates, claims 1, characterized in that filled with insulating resin 12.
JP21232596A 1996-08-12 1996-08-12 Semiconductor device Expired - Fee Related JP3879150B2 (en)

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