JP4902560B2 - Power semiconductor module - Google Patents

Power semiconductor module Download PDF

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JP4902560B2
JP4902560B2 JP2008015756A JP2008015756A JP4902560B2 JP 4902560 B2 JP4902560 B2 JP 4902560B2 JP 2008015756 A JP2008015756 A JP 2008015756A JP 2008015756 A JP2008015756 A JP 2008015756A JP 4902560 B2 JP4902560 B2 JP 4902560B2
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substrate
metal base
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JP2009177038A (en
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昭浩 丹波
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株式会社日立製作所
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Description

  The present invention relates to a power semiconductor module, and more particularly to an IGBT module structure.

  The mounting form of a power semiconductor module such as an IGBT module is as follows. Circuit of a so-called insulating metal substrate in which a copper foil as a circuit pattern is bonded to a heat dissipation base via a resin insulating layer, or a so-called metal-bonded ceramic substrate in which a metal plate such as a copper plate as a circuit pattern is bonded to ceramics The power semiconductor chip is soldered to the pattern. The bonded power semiconductor chip is electrically connected to an insulating metal substrate or a circuit pattern of a metal-bonded ceramic substrate by means such as aluminum wire bonding or lead frame solder bonding. Furthermore, in the case of a metal-bonded ceramic substrate mainly used in a large-capacity module, it is generally soldered to a metal base such as copper which is a heat sink.

  The above structure is housed in a resin case in which main terminals and control terminals are insert-molded, and the whole is sealed with a resin such as silicone gel. In addition, as a recent sealing form, a structure in which the whole is transfer-molded with an epoxy resin is also realized. In this case, there is no resin case, and the power semiconductor element is transfer-molded together with the terminals constituted by the lead frame.

  In power semiconductors such as IGBTs, on-voltage reduction and switching speed reduction for reducing switching loss are steadily progressing to reduce loss. When the switching speed is increased, di / dt, which is a current time change at the time of switching, increases, and a surge voltage and Vs are generated due to the parasitic inductance and Ls of the main wiring. Vs = Ls × di / dt. Since Vs increases the switching loss, the effect of reducing the loss by increasing the switching speed is diminished. Furthermore, when the sum of the power supply voltage and Vs exceeds the withstand voltage of the power semiconductor chip, there is a problem that the power semiconductor chip is destroyed.

  In order to avoid this, in designing the power semiconductor module, maximum attention is paid to the reduction of the parasitic inductance Ls. That is, in addition to considering shortening the wiring length, the wiring is made as close to the metal base as possible, and the inductance is reduced by the effect of canceling the magnetic flux due to the eddy current in the metal base. Furthermore, by superimposing the power supply wiring and the ground wiring in the resin case as much as possible, the magnetic flux of the current in the opposite direction is reduced in inductance by the canceling effect. However, in spite of such a structure being devised to reduce the inductance, in practice, in order to reduce Vs at the time of switching, di / dt is reduced by contriving such as increasing the gate resistance. Is currently used. In other words, the current situation is that the performance of the power semiconductor element is not fully utilized.

  As described above, in the power semiconductor module, reducing the inductance is an extremely important issue in order to maximize the performance of the power semiconductor chip. In order to reduce the inductance, a structure shown in FIG. 10 and the like has been proposed. In die bonding of the IGBT chip 1001 of the upper arm and the IGBT chip 1002 of the lower arm, the front and back are bonded in reverse. In the case of the IGBT chip 1002, the collector electrode which is the chip back surface electrode is bonded to the substrate 1005 with the solder 1010 as in the conventional case, whereas the IGBT chip 1001 is bonded to the emitter electrode which is the chip surface electrode with the solder 1008. That is, bonding is performed face down.

  At the same time, the gate electrode 1007 is also bonded to the substrate 1005. Of course, generally, the collector electrode is bonded to the substrate 1005 in both the upper and lower arms. By adopting such a die bonding configuration, the power supply wiring 1003 is bonded to the collector electrode of the IGBT chip 1001 with the solder 1006 and directly pulled out to the outside. Conventionally, by adopting a configuration in which the circuit pattern on the ceramic substrate 1005 is vertically raised and pulled out to the outside, the wiring length is shortened and the inductance is reduced. Similarly, the ground wiring 1004 is bonded to the IGBT 1002 emitter electrode with solder 1013 and directly pulled out. Further, the upper and lower arm IGBTs 1001 and 1002 are connected to the output pattern 1009 without wiring. By adopting such a structure, connection wiring from the emitter electrode of the upper arm IGBT chip 1001 to the substrate 1005, which has been necessary in the past, is no longer necessary, and the inductance of this portion can be reduced.

  In a power semiconductor module, Vs is most problematic in a phenomenon called reverse recovery. For example, in the case of an IGBT module, when the IGBT is turned on, a through current flows instantaneously in the opposite direction to the free wheeling diode (FWD) of the opposite arm where the reflux current was flowing, and a large Vs is generated at the time of recovery (when the current disappears) It occurs. Therefore, the most important thing is to reduce the inductance of the current path from the power supply pattern to the IGBT, the anti-arm FWD, and the ground pattern. In the above-described mounting form using the upper and lower arm chip inversion mounting, only consideration is given to reducing the inductance of the power supply and ground wiring, and reverse recovery such as the connection form of the IGBT and the arm FWD is not considered. . Furthermore, the IGBT chip 1001 soldered to the substrate 1005 face down has a problem that the thermal resistance is increased because the bonding area contributing to heat radiation is small compared to the IGBT chip 1002 of the conventional bonding method. This is because, since there is no circuit pattern, the surface of the IGBT chip where the collector voltage holding region, the gate pattern, etc. are present is different from the back surface of the IGBT chip where the entire chip can be bonded.

  As another technique, a method of stacking and mounting power semiconductor chips of upper and lower arms has been proposed as a mounting form for realizing a small size and low inductance of a power semiconductor module. Also in this case, there is a problem that the lower arm chip that mainly dissipates heat from the emitter electrode has a higher thermal resistance than the upper arm chip.

JP 2000-49281 A JP 2002-95268 A JP 2006-49542 A

  The problem to be solved by the present invention is that the flip-chip mounted element has a bonding area in the flip side mounting of the upper and lower arm elements using flip-chip (face-down) mounting which is extremely effective for reducing the inductance of the power semiconductor module. Therefore, it is to avoid the problem that the thermal resistance is increased as compared with the anti-arm element not flip-chip mounted.

  In order to achieve the above object, according to the present invention, the upper arm semiconductor element is bonded to the power circuit pattern on the ceramic substrate as in the conventional structure, and the lower arm semiconductor element is inverted between the upper arm semiconductor element and the front and back surfaces. Bonded to the ground pattern of the ceramic substrate (flip chip mounting), and the ground pattern passes through the ceramic of the ceramic substrate and is connected to the heat dissipation base bonded to the back surface of the ceramic substrate It is.

  That is, the main feature is that the upper arm element is insulated from the heat dissipation base, and the lower arm element is non-insulated to the heat dissipation base. Furthermore, the heat dissipation base is a metal base with fins, covered with a resin water channel cover, and directly water-cooled.

  In order to achieve the above object, the present invention provides at least a semiconductor element of an upper arm connected between a power supply wiring and an output wiring for switching current, and a lower arm connected between an output wiring and a ground wiring for switching current. In a power semiconductor module comprising a semiconductor element, an insulating substrate with a circuit pattern to which the conductor element is bonded and electrically connected, and a metal base bonded to or integrated with the back surface of the insulating substrate with a circuit pattern, The surface of the upper arm semiconductor element is bonded to a power supply wiring pattern on the insulating substrate with circuit pattern, and the lower arm semiconductor element has a surface opposite to the upper arm element on the ground wiring of the insulating substrate with circuit pattern. Bonded to the pattern, the ground wiring pattern penetrates the insulating layer of the insulating substrate with the circuit pattern and insulates to the metal base. Connected, the metal base whole is obtained is characterized in that is covered with an insulating casing to provide a space for the cooling medium.

  In the power semiconductor module of the present invention, the semiconductor element is an IGBT and a diode connected in reverse parallel to the IGBT, the insulating substrate with a circuit pattern is a metal pattern which is a circuit pattern on the front surface, and a heat dissipation base on the back surface. A so-called metal-bonded ceramic substrate having a metal plate for bonding, wherein the metal base is a finned metal base having fins on the back surface, and the semiconductor element is cooled by applying a liquid to the metal base. It is what.

  In the power semiconductor module of the present invention, the metal-bonded ceramic substrate is a copper-bonded silicon nitride substrate, and the ground material bonded to the substrate surface is connected to the back copper plate. And the material of the finned metal base is copper or a copper alloy.

  The power semiconductor module of the present invention is characterized in that a coating layer other than the metal base material is present on the surface where the metal base and the cooling liquid are in contact.

  In order to achieve the above object, the present invention provides at least a semiconductor element of an upper arm connected between a power supply wiring and an output wiring for switching current, and a lower arm connected between an output wiring and a ground wiring for switching current. In a power semiconductor module including a semiconductor element and a metal base for cooling the semiconductor element, a surface of the semiconductor element of the upper arm is bonded to one side of the output wiring, and the lower arm of the lower arm is bonded to the opposite surface of the output wiring. The surface of the semiconductor element is bonded, the metal base insulated from the coolant is bonded to the opposite surface of the semiconductor element of the upper arm, and the metal base is bonded to the opposite surface of the semiconductor element of the lower arm. The metal base for cooling the semiconductor element of the arm is covered with an insulating case so as to have a space for a cooling medium. Than is.

  In the power semiconductor module of the present invention, the semiconductor element of the upper and lower arms is an IGBT and a diode connected in reverse parallel to the IGBT, and the IGBT and diode of the upper and lower arm bonded to both surfaces of the output wiring, A diode of a pair arm is adhered to the substantially opposite surface of the IGBT.

  In the power semiconductor module of the present invention, the IGBT and diode of the upper arm are bonded to a power circuit pattern on a ceramic substrate having a metal plate on the front and back surfaces, and the back surface of the ceramic substrate is bonded to the metal base. And is insulated from the cooling medium.

  In the power semiconductor module of the present invention, the metal base is a finned metal base, and the contact surface of the upper arm IGBT and the metal base cooling medium for cooling the diode is coated with an insulating material. It is characterized by being insulated from an external cooling medium.

  The power semiconductor module of the present invention is characterized in that the insulating coating layer of the metal base with fins is an epoxy resin.

  The power semiconductor module of the present invention is characterized in that the epoxy resin layer, which is the metal-based coating layer, is the same as the epoxy resin that seals the IGBT and the diode.

  The power semiconductor module of the present invention is characterized in that the refrigerant is a liquid.

  The non-insulation of the flip-chip mounted lower arm semiconductor element up to the finned metal base makes it possible to eliminate the thermal resistance of the insulating layer, which accounts for a large proportion of the thermal resistance of the power semiconductor module, resulting in a significantly lower thermal resistance. Therefore, it is possible to cancel the high thermal resistance due to the reduction of the bonding area, which is a disadvantage of flip chip mounting, and to achieve a thermal resistance equal to or lower than that of the upper arm element.

  In addition, the semiconductor device of the upper arm has an effect of maintaining the conventional miniaturization by adopting the internal insulation type mounting as in the conventional module.

  Furthermore, by covering the copper base with fins with a resin water channel cover, it is possible to make a configuration that does not have any disadvantages compared with the conventional product thermally, so that the module can be mounted on a power conversion device such as an inverter. .

  In the present invention, the low thermal resistance and low inductance of the power semiconductor module are realized in a mounting form in which the power semiconductor elements of the upper and lower arms are mounted upside down and the power semiconductor elements of the lower arm are non-insulated up to the radiation fins. . Thus, flip chip mounting is used to reduce the inductance by shortening the main circuit wiring to the ultimate, and the power semiconductor element of the lower arm mounted on the flip chip has a small contact area for heat dissipation, The thermal resistance is reduced for insulation. Detailed embodiments and other features of the above will be described in detail in the following examples.

The first embodiment will be described in detail with reference to FIGS. 1 to 6 and FIG. 11. It is an Example for the one-phase circuit of a three-phase IGBT module (6 in 1 IGBT module). FIG. 1 is a conceptual schematic diagram (cross-sectional schematic diagram) of the basic structure of the present invention. As the concept of the present invention will become apparent to ignore planar arrangement, shows an implementation of the upper and lower arms IGBT101,102, FWD (F ree W heeling D iode) 103,104.

  FIG. 2 shows a circuit diagram for one phase of the three-phase inverter circuit. FIG. 3 shows a schematic plan view when a circuit for one phase is realized by the copper-coated silicon nitride substrate 301, the IGBTs 101 and 102, the FWDs 103 and 104, the lead frame 306 which is the output wiring, and the like. FIG. 11 is a schematic cross-sectional view taken along the line AA in FIG. FIG. 4 is a schematic plan view when the circuit corresponding to FIG. 3 is a conventional mounting form. FIG. 5 shows a reverse recovery current path 501 in the cross-sectional structure schematic diagram shown in FIG. 1, and FIG. 6 shows a reverse recovery current path 601 in the conventional structure shown in FIG. Is.

  First, the basic structure concept of the present invention (the present embodiment) will be described in detail with reference to the schematic cross-sectional structure diagram of FIG. A power supply (hereinafter referred to as P) pattern 112 (201 in the circuit diagram of FIG. 2) is attached to the surface of the copper-coated silicon nitride substrate 105, and the upper arm IGBT 101 and FWD 103 are mounted on the P pattern 112 as before. The collector electrode and the cathode electrode, which are the back electrodes of the chip, are bonded with high melting point solders 118 and 120 having a melting point exceeding 300 ° C. The thickness of the solder 118, 120 is about 0.1 mm. Copper posts 114 and 115 are formed in the silicon nitride substrate 105 through the substrate. The thickness of the silicon nitride layer 116 of the silicon nitride substrate 105 is 0.32 mm, the thickness of the P pattern 112 is 0.5 mm, and the thickness of the back surface copper plate 113 for substrate solder bonding is 0.4 mm. Therefore, the thickness of the copper posts 114 and 115 is approximately 1.2 mm. On the copper posts 114 and 115, the anode electrode and the emitter electrode of the lower arm FWD104 and IGBT 102 are soldered with high melting point solders 119 and 121 like the upper arm. Similarly, the thickness is about 0.1 mm.

As shown in the circuit diagram of FIG. 2, the anodes and emitters of the FWD 104 and the IGBT 102 are connected to the ground wiring 202. IGBT is a high withstand voltage element, on the surface of the FWD, the electric field relaxation region called FLR (F ield L imiting R ing ) is present around the chip. The anode and emitter regions exist inside this FLR region. Furthermore, gate electrodes and the like exist on the surface of the IGBT chip. Therefore, unlike the collector and cathode electrodes on the entire back surface of the chip, the area of the emitter and anode electrodes is small. In order to express this, in FIG. 1, the widths of the copper posts 114 and 115 and the solders 119 and 121 are expressed narrower than the chip. The entire surface of the upper and lower arms bonded to the silicon nitride substrate 105 and not bonded to the IGBT or FWD substrate is connected to a copper lead frame 109 which is an output wiring (reference numeral 203 in the circuit diagram of FIG. 2), a high melting point solder 122, 123, 124 and 125 are bonded. The thickness is about 0.1 mm as before. That is, the solder 122 is an emitter electrode adhesive solder, the solder 123 is a collector electrode adhesive solder, the solder 124 is a cathode electrode adhesive solder, and the solder 125 is an anode electrode adhesive solder. The reason why the widths of the solders 122 and 125 are drawn small is exactly the same as that of the lower arm solders 119 and 121 described above. In the IGBT and FWD described above, the collector and cathode electrodes have an Al / Ti / Ni / Au laminated structure from the Si side, and the emitter and anode electrodes also have an Al / Ni / Au laminated structure from the Si side. . The thickness of the lead frame 109 is about 0.5 mm. Considering electrical resistance, it is desirable to have a thicker thickness. However, considering the fact that it adheres to multiple chips, this thickness is used because it becomes difficult to adhere when the rigidity increases. Further, the lead frame 109 rises at the chip end between the chips. This is because, for example, in the case of an IGBT, if the lead frame 109, which is an emitter potential, and the tip corner portion, which is a collector potential, are close to each other, it is difficult to discharge at that portion and to maintain a high breakdown voltage.

  The finned copper base 106 is bonded to the back surface of the silicon nitride substrate 105 with a low melting point solder 130 having a melting point of about 180 ° C. The thickness of the solder 130 is about 0.2 mm. The finned copper base has a structure that assumes water cooling. In other words, the height of the fin is low unlike the air-cooled fin. The thickness of the flat plate portion of the finned copper base 106 is 3 mm, the fin 108 is a straight fin, and the height / thickness / interval of the fins is 8 mm / 1 mm / 1.5 mm, respectively. In this embodiment, straight fins are used. Of course, there is no problem with pin fins.

  With the structure described above, the emitters and anodes of the lower arm IGBT 102 and FWD 104 are electrically connected to the finned copper base 106. That is, in the present invention, since the finned copper base 106 becomes a ground circuit, a large current is passed through the finned copper base 106. Therefore, unlike the conventional power semiconductor module, the finned copper base 106 cannot be covered with the conductor channel cover. Therefore, in this embodiment, the water channel 131 is formed by covering with the water channel cover 107 made of PPS resin. Terminals 110 and 111 are a power supply terminal and a ground terminal, respectively, and are bonded to the P pattern 112 and the finned copper base 106 with low melting point solders 117 and 126. The gate power supply method of the upper arm IGBT 101 is connected to a gate circuit pattern (not shown) on the silicon nitride substrate 105 by aluminum wire bonding as in the past, and the gate power supply of the lower arm IGBT 102 is connected to the gate circuit pattern on the silicon nitride substrate 105. 128 is bonded with solder 127. The entire sealing is transfer-molded with an epoxy resin 129 so that various control terminals (not shown) in addition to the terminals 109, 110, and 111 are exposed to the outside. The linear expansion coefficient (α) of the mold resin is about 16 ppm / K. Sealing with an epoxy resin may be potting instead of transfer molding. Further, it is of course possible to use a more general silicone gel instead of an epoxy resin. However, in the present invention, the lower arm element is directly solder-bonded to a thick copper plate, unlike the upper arm element. Therefore, unlike the case of bonding onto the ceramic substrate, the thermal strain of the bonded solder layer increases. This is because Si has a large α mismatch of about 3 ppm / K, whereas copper has a large of about 17 ppm / K. Therefore, since there is a concern about a decrease in the solder life, the epoxy resin sealing that has the effect of reducing the thermal strain of the solder has a better sealing structure.

  The planar structure will be described in detail with reference to FIG. The rated voltage / current of this example is 600V / 300A, respectively. Each of the IGBTs 101 and 102 and the FWDs 103 and 104 constitutes each arm with one chip. The IGBT chip size is approximately 13 mm square, and the FWD chip size is approximately 13 mm × 8 mm. The approximate size of the silicon nitride substrate 301 is 40 mm × 45 mm. FIG. 11 shows a schematic diagram of the AA cross section of FIG. In FIG. 3, the copper pattern for bonding the lower arm element, that is, the pattern electrically connected to the finned copper base has a three-layer structure unlike the copper posts 114 and 115 in FIG. Similar to the P pattern 302, a ground (hereinafter referred to as N) pattern 1103 is also affixed on the silicon nitride substrate 301, and this N pattern 1103 is short-circuited to the back copper plate 1104 by an electrode 1102 that penetrates the silicon nitride 1101. . The gate of the upper arm IGBT 101 is connected to the gate pattern 309 on the substrate by an aluminum wire 307, and the aluminum wire 308 as a control emitter wiring is also connected to the control emitter pattern 310 on the substrate. As described in FIG. 1, the flip-arm mounted lower arm IGBT 102 is bonded to the gate pattern 303 and the control emitter pattern 304 with solder.

  In the conceptual schematic diagram of FIG. 1, the output terminal 109 is led out of the module directly from the chip. The output circuit wiring 306 drawn transparently so that the IGBT and FWD arrangement can be seen is once bonded to the output circuit pattern 305 on the silicon nitride substrate 301 with solder 318. Since the components are closed only within the silicon nitride substrate 301, the inspection and the like are easy to implement, and the structure is more realistic. With the above configuration, the output of the upper arm element can be connected to the lower arm element without connecting to the circuit pattern on the substrate, and further, the ground of the lower arm element can be connected from the chip surface to the circuit pattern on the substrate. As a result, the substrate has been greatly reduced in size. Furthermore, since the length of the energization wiring can be greatly shortened, a significant reduction in inductance is realized.

  The structure of the present embodiment has been described above. The features are the downsizing of the substrate, the low inductance of the main wiring, and the low thermal resistance of the flip chip mounted chip. Therefore, in order to quantitatively explain the effects of low inductance and miniaturization, the substrate structure designed by the prior art will be described using the schematic plan view of FIG. 4 as a comparison.

  The chip ratings of the IGBT 401 and FWD 402 are the same as those in the above-described embodiment (FIG. 3). The upper arm IGBT 401 and FWD 402 chips are solder-bonded to the P pattern 405 of the silicon nitride substrate 404. The emitter electrode on the surface of the IGBT chip 401 and the anode electrode on the surface of the FWD chip 402 are connected to the output pattern 409 by an aluminum wire 403. The IGBT 403 is controlled with an aluminum wire 406 connected to the gate and a wire 407 controlled emitter. The lower arm IGBT 412 and FWD 410 are also basically mounted in the same structure. Instead of the P pattern, die bonding is performed to the output pattern 409, and instead of the output pattern 409, wire bonding is performed to the N pattern 408. The schematic shape of the substrate 404 is 40 mm × 60 mm, and it can be seen that it is about 1.3 times larger than that in FIG.

Next, the parasitic inductance that is a feature of the structure of the present invention will be described. FIG. 5 and FIG. 6 show a path through which a reverse recovery current flows for a moment when a reverse current flows through the lower arm FWD when a return current flows through the FWD of the lower arm and the upper arm IGBT turns on. It is. FIG. 6 shows the case of the conventional structure shown in FIG. 4, and FIG. 5 shows the case of the present invention shown in FIG. In the present invention, the path should be shown in the case of FIG. 3 which is easy to compare with the circuit of FIG. 4, but in the case of the present invention, the current from the P terminal to the N terminal flows in an overlapping manner. However, since it is difficult to express, it is expressed in FIG. 5 which is a sectional view. In the case of the conventional structure shown in FIG. 6, when expressed excluding IGBT and FWD, the current is
(1) P pattern 405 → (2) Aluminum wire 403 → (3) Output pattern 409 →
(4) Aluminum wire 411 (FWD 410 to N pattern 408) → (5) N pattern 408
And flow. On the other hand, in the case of FIG. 5, in order to accurately evaluate FIG.
(1) P pattern 112 → (2) Output wiring 109 (between adjacent IGBT and FWD) → (3) Finned copper base 106
And flow. Thus, it can be seen that the parasitic inductance component is halved by the present invention. Furthermore, in the case of the present invention, as shown in FIG. 5, the directions flow in close proximity and opposite to each other, so that the magnetic flux canceling effect is very large, and the resulting low inductance effect is also great.

  The inductance measured from the turn-on waveform of the upper arm IGBT was 20 nH in the case of the conventional example of FIG. 6, whereas it was 7 nH in the case of the present embodiment shown in FIGS. Was realized. That is, it has been found that it can greatly contribute to the reduction of switching loss.

  The evaluation results of thermal resistance will be described below. The thermal resistance is a case of water cooling, and is the total thermal resistance (hereinafter referred to as Rth (jw)), that is, the thermal resistance from the IGBT junction to the cooling water. The cooling water is an ethylene glycol 50 vol% aqueous solution, the temperature is 75 ° C., and the flow rate is 10 L / min. In the case of the upper arm IGBT having a conventional mounting structure, Rth (j−w) = 0.2 K / W. When flip chip mounting is performed on a silicon nitride substrate without applying the present invention, Rth (j−w) is 0.24 K / W, and Rth (j−w) increases significantly. On the other hand, in the case of the present invention, it was found that Rth (jw) of the lower arm IGBT is 0.19 K / W, which can be reduced from 0.2 K / W of the conventional mounting structure.

  As described above, according to the structure of the present invention, epoch-making reduction in inductance can be realized by using flip chip mounting, and the increase in thermal resistance, which is a disadvantage of flip chip mounting, can be solved, and the performance of the IGBT module can be dramatically improved. There was found.

  Example 2 will be described using the schematic cross-sectional structure diagram of FIG. As described above, a feature of the present invention is that a low thermal resistance is realized by using a ground circuit pattern as a finned copper base and non-insulating the lower arm element up to the radiation fin. Since the non-insulated copper base with fins is insulated by the resin channel cover, there is no problem in mounting to the apparatus. However, there is a concern that the finned copper base will corrode because the cooling water contacts a non-insulated object that is energized with a large current. This is because a slight potential difference occurs in the copper base when a large current is applied. This is a concern of so-called electric corrosion. In this embodiment, in order to cope with this, the coating layer 701 is formed on the water contact surface of the finned copper base 702. The coating layer may be insulative or non-insulating, and non-insulating is desired in view of increasing thermal resistance. This is because insulating materials generally have a low thermal conductivity.

  Example 3 will be described in detail with reference to the schematic sectional view of FIG. The present embodiment is an embodiment in which the structure of the first embodiment is further reduced in inductance and size.

  The upper arm IGBT 101 and FWD 103 are mounted on the substrate and copper base in the same manner as in the first embodiment. That is, the collector electrode of the IGBT 101 and the cathode electrode of the FWD 103 are bonded to the P pattern 806 on the copper-coated silicon nitride substrate 801 with the solder 118 and 120. The solder material and thickness are also the same. The substrate 801 on which the chip is mounted is bonded to the finned copper base 816 with solder 809. The fin 817 shape of the finned copper base 816 is the same as that of the first embodiment, and the number of fins 817 is less than that of the first embodiment. That is, in Example 1, the upper and lower arm elements are radiated by a single heat radiating plate, but in this example, since the heat radiating plate is dedicated to the upper and lower arms, the size of each radiating plate is smaller than that of Example 1. The image is halved. The output wiring 802 is bonded to the surfaces of the IGBT 101 and FWD 103 that are not bonded to the substrate 801 with solders 122 and 125.

  The feature of this embodiment is that the lower arm IGBT 102 and the FWD 104 are bonded onto the output wiring 802. The cathode electrode of FWD 104 is bonded to the upper side of IGBT 101 with solder 810, and the collector electrode of IGBT 102 is bonded to the upper side of FWD 103 with solder 812. The heat dissipation of the IGBT 102 and the FWD 104 is realized by bonding the finned copper base 814 to the emitter electrode and the anode electrode with solders 813 and 811. That is, as in the first embodiment, the lower arm element is not insulated up to the radiation fin 815. Accordingly, although not shown, the water channel cover of the finned copper base 814 is formed of an insulating material such as resin. The N terminal 804 is bonded to the finned copper base 814 with solder 818, and the P terminal 803 is bonded to the P pattern 806 on the substrate 801 with solder 805. Then, as in Example 1, sealing is realized by transfer molding with an epoxy resin 819.

  As described above, the present embodiment is characterized in that the planar dimensions are reduced by stacking and the wiring inductance can be further reduced. In the first embodiment, the inductance of the output wiring 109 is slightly present, but in the present embodiment in which the upper and lower arm elements are stacked and mounted, this inductance does not exist. As in Example 1, the inductance measured from the turn-on waveform of the upper arm IGBT was 5 nH, which could be further reduced than in Example 1.

  Rah (j-w) is basically the same as that of the first embodiment, but since IGBT and FWD are stacked and mounted, a low thermal resistance can be expected depending on the respective heat generation states.

  Example 4 will be described in detail using the schematic cross-sectional structure diagram of FIG. As in the third embodiment, the present embodiment is an embodiment in which upper and lower arm chips are stacked and mounted. Unlike the third embodiment, the upper arm chip is mounted and radiated.

  In the third embodiment, the upper arm chip was mounted in the same manner as in the past, in which the upper arm chip was solder bonded to the P pattern on the silicon nitride substrate bonded to the heat dissipation base. On the other hand, in this embodiment, the upper arm IGBT 101 and the FWD 103 are directly bonded to the finned copper base 901 with the collector electrode and the cathode electrode by the solder 118 and 120. That is, the IGBT 101 and the FWD 103 are not insulated up to the copper base with fins, like the lower arm. When the upper arm is non-insulated, the high voltage is insulated outside the module, so that the insulation distance must be increased, which is not practical. Therefore, in this embodiment, the fin 902 is included, and the entire back surface of the finned copper base 901 is covered with an epoxy resin 903 which is a sealing resin. With this structure, the upper arm element and the cooling water are insulated, and a module that is functionally different from the conventional insulation method can be realized. The thickness of the epoxy resin layer covering the fin portion is 0.2 mm, and the thermal conductivity is 2 W / m · K. With this structure and physical properties, it is possible to realize the same thermal resistance as the conventional structure.

The cross-sectional model which showed the basic structure of this invention. Example 1 The circuit diagram for one phase of an inverter main circuit. An explanatory view showing one example of the present invention (planar schematic diagram). Example 1 The plane schematic diagram of the conventional mounting form. The cross-sectional schematic diagram which showed the reverse recovery electric current path | route of this invention. The plane schematic diagram which showed the conventional reverse recovery electric current path | route. BRIEF DESCRIPTION OF THE DRAWINGS Explanatory drawing which showed one Example of this invention (cross-sectional schematic diagram). (Example 2) BRIEF DESCRIPTION OF THE DRAWINGS Explanatory drawing which showed one Example of this invention (cross-sectional schematic diagram). (Example 3) BRIEF DESCRIPTION OF THE DRAWINGS Explanatory drawing which showed one Example of this invention (cross-sectional schematic diagram). Example 4 The cross-sectional schematic diagram of a conventional structure. Explanatory drawing which showed one Example of this invention (AA cross-sectional schematic diagram of FIG. 3). Example 1

Explanation of symbols

101,1001 IGBT chip (upper arm)
102,412,1002 IGBT chip (lower arm)
103 Free Wheeling Diode (FWD) chip (upper arm)
104,410 FWD chip (lower arm)
105, 301, 404, 801, 1005 Copper-coated ceramic substrate 106, 702, 814, 816, 901 Finned copper base 107, 815, 817, 902 Fin 108 Channel cover 109, 203, 802 Output wiring & terminals 110, 201, 803, 1003 Power supply terminal (P terminal)
111, 202, 804, 1004 Ground terminal (N terminal)
112, 302, 405, 806 Ceramic substrate power circuit (P) pattern 113, 808, 1104 Ceramic substrate back surface copper plate 114 Ceramic substrate through electrode (FWD)
115,1102 Ceramic substrate through electrode (IGBT)
116,807,1101 Ceramics 117,126,805,818 Terminal adhesive solder 118,123,812,1006,1010 IGBT collector adhesive solder 119,125,811 FWD anode adhesive solder 120,124,810 FWD cathode adhesive solder 121,122 , 813, 1008, 1013 IGBT emitter adhesive solder 127, 1007, 1011 IGBT gate adhesive solder 128, 303, 309 Ceramic substrate gate pattern 129, 819, 903 Sealed epoxy resin 130, 809 Ceramic substrate adhesive solder 131 Cooling channel 304, 310 Ceramic substrate control emitter pattern 305, 409, 1009 Ceramic substrate output pattern 306 Output wiring (lead frame)
307, 406 IGBT gate wire 308, 407 IGBT control emitter wire 401 IGBT chip 402 FWD chip 403, 411 Aluminum wire 408, 1103 Ceramic substrate ground pattern 501, 601 Recovery current path 701 Antirust coating layer

Claims (4)

  1. At least, the arms of the semiconductor element on switching the current is connected between the power supply wiring and output wiring, the semiconductor device of the lower arm switching the connected current between the output and ground wirings, said semiconductors elements are adhesive electrically the circuit pattern with an insulating substrate connected, either bonded to the circuit pattern with an insulating base plate back surface, or in the power semiconductor module having a metal base which is integral,
    The surface of the semiconductor element of the upper arm is bonded to a power supply wiring pattern on the insulating substrate with the circuit pattern,
    The semiconductor element of the lower arm has a surface opposite to the upper arm element bonded to a ground wiring pattern of the insulating substrate with a circuit pattern,
    The ground wiring pattern penetrates the insulating layer of the insulating substrate with circuit pattern, and is electrically connected to the metal base,
    The power metal module, wherein the entire metal base is covered with an insulating case so as to provide a space for a cooling medium.
  2. In claim 1,
    The semiconductor element is an IGBT and a diode connected in reverse parallel to the IGBT, and the insulating substrate with a circuit pattern has a metal pattern that is a circuit pattern on the surface and a metal plate for bonding a heat dissipation base on the back surface. A power semiconductor module comprising a ceramic substrate, wherein the metal base is a finned metal base having fins on the back surface, and the semiconductor element is cooled by applying a liquid to the metal base.
  3. In claim 2,
    The metal-bonded ceramic substrate is a copper-bonded silicon nitride substrate, and there is a copper material penetrating silicon nitride to connect the ground pattern bonded to the substrate surface to the back copper plate, and the finned metal base The power semiconductor module is made of copper or a copper alloy.
  4. In claim 2 or 3,
    A power semiconductor module, wherein a coating layer other than the metal base material is present on a surface where the metal base and the cooling liquid are in contact.
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