JP5777203B2 - Power module - Google Patents

Power module Download PDF

Info

Publication number
JP5777203B2
JP5777203B2 JP2011062820A JP2011062820A JP5777203B2 JP 5777203 B2 JP5777203 B2 JP 5777203B2 JP 2011062820 A JP2011062820 A JP 2011062820A JP 2011062820 A JP2011062820 A JP 2011062820A JP 5777203 B2 JP5777203 B2 JP 5777203B2
Authority
JP
Japan
Prior art keywords
electrode pad
substrate
wiring layer
metal wiring
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2011062820A
Other languages
Japanese (ja)
Other versions
JP2012199400A (en
Inventor
修一 村山
修一 村山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nichicon Capacitor Ltd
Original Assignee
Nichicon Capacitor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nichicon Capacitor Ltd filed Critical Nichicon Capacitor Ltd
Priority to JP2011062820A priority Critical patent/JP5777203B2/en
Publication of JP2012199400A publication Critical patent/JP2012199400A/en
Application granted granted Critical
Publication of JP5777203B2 publication Critical patent/JP5777203B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Description

本発明は、複数の半導体チップと該半導体チップの放熱機構を備えたパワーモジュールに関する。   The present invention relates to a power module including a plurality of semiconductor chips and a heat dissipation mechanism for the semiconductor chips.

従来の一般的なパワーモジュールとしては、例えば図５に記載のものが知られている。同図に示すように、従来のパワーモジュール１００は、基板１０１と、該基板１０１表面の金属配線層１０２に半田接続された複数の半導体チップ１０３（一例として、ＩＧＢＴ１０３ａ、ダイオード１０３ｂ）と、基板１０１の裏面側に設けられた放熱フィン１０８と、基板１０１を収容するハウジングとしての樹脂ケース１０４を備えている。   As a conventional general power module, for example, the one shown in FIG. 5 is known. As shown in the figure, a conventional power module 100 includes a substrate 101, a plurality of semiconductor chips 103 (for example, an IGBT 103a and a diode 103b) solder-connected to a metal wiring layer 102 on the surface of the substrate 101, and a substrate 101. And a resin case 104 serving as a housing for housing the substrate 101.

各半導体チップ１０３の表面電極は、金属配線層１０２の電極部１０５、他の半導体チップ１０３の表面電極または樹脂ケース１０４に設けられた電極部１０６にＡｌワイヤでボンディングされている。樹脂ケース１０４にはリードがインサート成形されており、これにより樹脂ケース１０４の電極部１０６が外部に引き出されている。また、樹脂ケース１０４内は、硬化した後も比較的柔軟な充填樹脂１０７（例えば、シリコンゲル）が充填されている。充填樹脂１０７を充填するのは、耐環境性能を高めるためである。充填樹脂１０７の充填は、上記Ａｌワイヤボンディングの後に行われる。   The surface electrode of each semiconductor chip 103 is bonded to the electrode portion 105 of the metal wiring layer 102, the surface electrode of another semiconductor chip 103, or the electrode portion 106 provided on the resin case 104 with an Al wire. Leads are insert-molded in the resin case 104, whereby the electrode portion 106 of the resin case 104 is drawn out. The resin case 104 is filled with a relatively soft filling resin 107 (for example, silicon gel) even after being cured. The reason why the filling resin 107 is filled is to improve environmental resistance. The filling resin 107 is filled after the Al wire bonding.

ところで、このパワーモジュール１００では、主に放熱フィン１０８により半導体チップ１０３の放熱が行われるが、半導体チップ１０３と放熱フィン１０８の間には基板１０１が存在しているため放熱効率が悪いという問題があった。なお、半導体チップ１０３の放熱はＡｌワイヤを介しても行われるが、その放熱量は微量である。   By the way, in this power module 100, the semiconductor chip 103 is radiated mainly by the radiating fins 108. However, since the substrate 101 exists between the semiconductor chip 103 and the radiating fins 108, there is a problem that the radiating efficiency is poor. there were. The semiconductor chip 103 is radiated through an Al wire, but the amount of radiated heat is very small.

また、このパワーモジュール１００では、ボンディング性を考慮して線径１００〜５００μｍのＡｌワイヤが用いられるが、該Ａｌワイヤの許容電流条件を満たし、かつ半導体チップ１０３に必要な電流を供給するためには、１電極あたりのワイヤ本数を複数本にしなければならず、生産性が低いという問題もあった。   In this power module 100, an Al wire having a wire diameter of 100 to 500 μm is used in consideration of bonding properties. In order to satisfy the allowable current condition of the Al wire and supply a necessary current to the semiconductor chip 103. Has a problem that the number of wires per electrode must be plural, and the productivity is low.

そこで、図６に示すように、特許文献１に記載のパワーモジュール２００は、第１の基板２０１と、第１の基板２０１に対向する第２の基板２０２と、第１の基板２０１上に接続された半導体チップ２０４と、半導体チップ２０４の表面電極と第２の基板２０２に設けられた回路パターンとを接続する球状の接続導体２０３を備えている。このパワーモジュール２００によれば、複数本のＡｌワイヤをボンディングしなくても接続導体２０３を通じて十分な電流を供給することができるので、生産性を向上させることができる。また、このパワーモジュール２００によれば、第１の基板２０１および第２の基板２０２の両方に放熱フィンを取り付けることにより、放熱効率を高めることもできる。   Therefore, as illustrated in FIG. 6, the power module 200 described in Patent Document 1 is connected to the first substrate 201, the second substrate 202 facing the first substrate 201, and the first substrate 201. And a spherical connection conductor 203 that connects the surface electrode of the semiconductor chip 204 and the circuit pattern provided on the second substrate 202. According to the power module 200, a sufficient current can be supplied through the connection conductor 203 without bonding a plurality of Al wires, so that productivity can be improved. Further, according to the power module 200, the heat radiation efficiency can be enhanced by attaching the heat radiation fins to both the first substrate 201 and the second substrate 202.

特開２００５−１９７４３５号公報Japanese Patent Laid-Open No. 2005-197435

しかしながら、この従来のパワーモジュール２００では、水平位置がずれた状態で第２の基板２０２が取り付けられるということが起こり得る。この場合は、本来接続されるべき半導体チップ２０４の表面電極と第２の基板２０２の回路パターンが接続されなかったり、接続されるべきでない表面電極と回路パターンが接続されたりする接続異常が発生し、パワーモジュールとしての機能が損なわれるおそれがある。   However, in this conventional power module 200, the second substrate 202 may be attached with the horizontal position shifted. In this case, a connection abnormality occurs in which the surface electrode of the semiconductor chip 204 to be originally connected and the circuit pattern of the second substrate 202 are not connected, or the surface electrode and the circuit pattern that should not be connected are connected. The function as a power module may be impaired.

本発明は上記事情に鑑みてなされたものであって、その課題とするところは、半導体チップを挟む２つの基板の水平位置をセルフアライメントすることにより、半導体チップと基板との間で接続異常が発生するのを防ぐことができるパワーモジュールを提供することにある。   The present invention has been made in view of the above circumstances, and the problem is that self-alignment of the horizontal positions of the two substrates sandwiching the semiconductor chip causes a connection abnormality between the semiconductor chip and the substrate. It is an object of the present invention to provide a power module capable of preventing the occurrence.

上記課題を解決するために、本発明に係るパワーモジュールは、
第１金属配線層を有する第１基板と、第２金属配線層を有する第２基板と、表面側電極が第２金属配線層に半田接続され、かつ裏面側電極が第１金属配線層に半田接続された複数の半導体チップとを備えたパワーモジュールであって、
第１金属配線層は第１電極パッドを含み、第２金属配線層は平坦な第１電極パッドに対向する平坦な第２電極パッドを含み、第１電極パッドおよび第２電極パッドの間に配置され、該第１電極パッドおよび第２電極パッドを電気的に接続する金属で表面が覆われた導電性球と、第１電極パッドおよび第２電極パッドを半田接続する半田部とをさらに備え、
導電性球が、半田部内部に収容され、導電性球の直径が、複数の半導体チップのうち最も厚みが大きなチップの厚みに対して０．２ｍｍ〜０．６ｍｍを加えた値に設定され、第１電極パッドおよび第２電極パッドを構成する辺のうち最も長い長辺の半分の長さを径寸法としたとき、該径寸法が、導電性球の半径の１．５倍以上かつ２．５倍以下に設定され、半田部の表面が、懸垂曲線を描いていることを特徴とする。 In order to solve the above problems, the power module according to the present invention is:
A first substrate having a first metal wiring layer, a second substrate having a second metal wiring layer, a front side electrode soldered to the second metal wiring layer, and a back side electrode soldered to the first metal wiring layer A power module comprising a plurality of connected semiconductor chips,
The first metal wiring layer includes a first electrode pad, the second metal wiring layer includes a flat second electrode pad facing the flat first electrode pad, and is disposed between the first electrode pad and the second electrode pad. A conductive sphere whose surface is covered with a metal that electrically connects the first electrode pad and the second electrode pad, and a solder portion that solder-connects the first electrode pad and the second electrode pad,
The conductive sphere is accommodated inside the solder portion, and the diameter of the conductive sphere is set to a value obtained by adding 0.2 mm to 0.6 mm to the thickness of the largest thickness among the plurality of semiconductor chips, when a half the length of the longest long side of the sides of the first electrode pad and the second electrode pad and diameter, the diameter is more than 1.5 times the radius of the conductive balls and 2 It is set to 5 times or less, and the surface of the solder part has a hanging curve .

この構成では、第１電極パッドおよび第２電極パッドを電気的に接続する導電性球が、第１電極パッドおよび第２電極パッドを半田接続する半田部内部に収容されている。このため、該半田部に形成されるメニスカスに起因して生ずる力（以下「メニスカス力」という）が第１電極パッドと第２電極パッド、すなわち半導体チップの裏面側にある第１基板と表面側にある第２基板とを水平移動させるように作用し、第１基板および第２基板の水平位置がセルフアライメントされる。したがって、この構成によれば、半導体チップと第１基板および第２基板との間で接続異常が発生するのを防ぐことができる。また、この構成によれば、メニスカス力を効果的に発生させることができるとともに、十分なアライメント量を確保することができる。 In this configuration, the conductive sphere that electrically connects the first electrode pad and the second electrode pad is accommodated inside the solder portion that solder-connects the first electrode pad and the second electrode pad. For this reason, the force generated by the meniscus formed in the solder part (hereinafter referred to as “meniscus force”) is the first electrode pad and the second electrode pad, that is, the first substrate on the back side of the semiconductor chip and the surface side. The horizontal position of the first substrate and the second substrate is self-aligned. Therefore, according to this configuration, it is possible to prevent a connection abnormality from occurring between the semiconductor chip and the first substrate and the second substrate. Further, according to this configuration, a meniscus force can be effectively generated and a sufficient alignment amount can be ensured.

また、上記パワーモジュールは、導電性球の表面に半田との濡れ性を向上させるための表面処理が施されていることが好ましい。このように構成すれば、導電性球が転がり易くなり、セルフアライメントをより円滑に行うことができる。   The power module preferably has a surface treatment for improving wettability with solder on the surface of the conductive sphere. If comprised in this way, it will become easy to roll an electroconductive ball | bowl and self-alignment can be performed more smoothly.

本発明によれば、半導体チップと該半導体チップを挟む２つの基板のとの間で接続異常が発生するのを防ぐことができるパワーモジュールを提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the power module which can prevent that a connection abnormality generate | occur | produces between a semiconductor chip and two board | substrates which pinch | interpose this semiconductor chip can be provided.

本発明の一実施形態に係るパワーモジュールであって、（Ａ）は平面図、（Ｂ）は断面図である。It is a power module which concerns on one Embodiment of this invention, Comprising: (A) is a top view, (B) is sectional drawing. 本発明の一実施形態に係るパワーモジュールの金属球周辺を拡大した断面図である。It is sectional drawing to which the metal sphere periphery of the power module which concerns on one Embodiment of this invention was expanded. 本発明におけるセルフアライメントの原理を説明するための図である。It is a figure for demonstrating the principle of the self-alignment in this invention. 本発明におけるセルフアライメントの原理を説明するための図である。It is a figure for demonstrating the principle of the self-alignment in this invention. 従来のパワーモジュールであって、（Ａ）は平面図、（Ｂ）は断面図である。It is a conventional power module, (A) is a top view, (B) is sectional drawing. 従来の別のパワーモジュールの断面図である。It is sectional drawing of another conventional power module.

以下、添付図面を参照しつつ、本発明に係るパワーモジュールの好ましい実施形態について説明する。   Hereinafter, preferred embodiments of a power module according to the present invention will be described with reference to the accompanying drawings.

図１（Ａ）に本発明の一実施形態に係るパワーモジュールの平面図、図１（Ｂ）に断面図を示す。ただし、図１（Ａ）では理解を容易にするために一部の部材（後述する第２基板４、第２金属配線層５、第２放熱フィン９）を省略している。また、図１（Ｂ）は図１（Ａ）のＡ−Ａ’断面図である。   FIG. 1A is a plan view of a power module according to one embodiment of the present invention, and FIG. However, in FIG. 1A, some members (a second substrate 4, a second metal wiring layer 5, and a second radiation fin 9 described later) are omitted for easy understanding. FIG. 1B is a cross-sectional view taken along the line A-A ′ of FIG.

図１に示すように、本実施形態に係るパワーモジュール１は、表面に第１金属配線層３が形成された第１基板２と、裏面に第２金属配線層５が形成された第２基板４と、表面側電極が第２金属配線層５に半田接続され、かつ裏面側電極が第１金属配線層３に半田接続された複数の半導体チップ６と、第１基板２および第２基板４を収容するハウジングとしての樹脂ケース７と、第１基板２の裏面に取り付けられた第１放熱フィン８と、第２基板４の表面に取り付けられた第２放熱フィン９と備えている。   As shown in FIG. 1, the power module 1 according to this embodiment includes a first substrate 2 having a first metal wiring layer 3 formed on the front surface and a second substrate having a second metal wiring layer 5 formed on the back surface. 4, a plurality of semiconductor chips 6 in which the front-side electrode is solder-connected to the second metal wiring layer 5 and the back-side electrode is solder-connected to the first metal wiring layer 3, and the first substrate 2 and the second substrate 4 A resin case 7 as a housing for housing the first substrate 2, a first radiation fin 8 attached to the back surface of the first substrate 2, and a second radiation fin 9 attached to the surface of the second substrate 4.

半導体チップ６は、ＩＧＢＴ６ａおよびダイオード６ｂを含んでいる。このうち、ＩＧＢＴ６ａは、表面側電極としてのエミッタ端子およびゲート端子が第２金属配線層５に接続され、裏面側電極としてのコレクタ端子が第１金属配線層３に接続されている。また、ダイオード６ｂは、表面側電極としてのアノード端子が第２金属配線層５に接続され、裏面側電極としてのカソード端子が第１金属配線層３に接続されている。半導体チップ６としては、この他、ＭＯＳＦＥＴ等を使用することができる。使用する半導体チップ６の種別は、パワーモジュール１の特性等に応じて適宜決定される。   The semiconductor chip 6 includes an IGBT 6a and a diode 6b. Among these, the IGBT 6 a has an emitter terminal and a gate terminal as front surface side electrodes connected to the second metal wiring layer 5, and a collector terminal as a back surface side electrode connected to the first metal wiring layer 3. The diode 6 b has an anode terminal as a front side electrode connected to the second metal wiring layer 5 and a cathode terminal as a back side electrode connected to the first metal wiring layer 3. In addition, a MOSFET or the like can be used as the semiconductor chip 6. The type of the semiconductor chip 6 to be used is appropriately determined according to the characteristics of the power module 1 and the like.

第１基板２および第２基板４は、例えば、アルミナ系セラミック、窒化アルミニウム、窒化珪素等のセラミック材料からなり、平面視矩形状を有している。樹脂ケース７との接続部を設けるために、第２基板４は第１基板２より長辺寸法が大きくなっている。   The first substrate 2 and the second substrate 4 are made of a ceramic material such as alumina-based ceramic, aluminum nitride, or silicon nitride, and have a rectangular shape in plan view. In order to provide a connection portion with the resin case 7, the second substrate 4 has a longer side dimension than the first substrate 2.

第１金属配線層３は、第１基板２の表面に銅、アルミニウム等の金属をメタライズすることにより形成したもので、その最表面には、半田に対する濡れ性を向上させるためのＮｉめっきまたはＡｕめっきが施されている。また、第１金属配線層３には、ＩＧＢＴ６ａを接続するための電極パッド３ａ、ダイオード６ｂを接続するための電極パッド３ｂ、金属球１０（本発明の「導電性球」に相当）を接続するための第１電極パッド３ｃおよび各電極パッドを相互に接続する配線部（不図示）が含まれている。金属球１０については、後で詳細に説明する。   The first metal wiring layer 3 is formed by metallizing a metal such as copper or aluminum on the surface of the first substrate 2, and the outermost surface thereof is Ni-plated or Au for improving the wettability with respect to solder. Plating is applied. Further, the first metal wiring layer 3 is connected with an electrode pad 3a for connecting the IGBT 6a, an electrode pad 3b for connecting the diode 6b, and a metal ball 10 (corresponding to the “conductive ball” of the present invention). For this purpose, a first electrode pad 3c and a wiring part (not shown) for connecting the electrode pads to each other are included. The metal ball 10 will be described later in detail.

第２金属配線層５は、第１金属配線層３と同様に形成される。また、第２金属配線層５には、ＩＧＢＴ６ａを接続するための電極パッド５ａ、ダイオード６ｂを接続するための電極パッド５ｂ、金属球１０を接続するための第２電極パッド５ｃ、各電極パッドを相互に接続する配線部（不図示）、および外部引出パッド５ｄが含まれている。このうち、第２電極パッド５ｃは第１電極パッド３ｃに対向した位置に設けられ、その形状および寸法は第１電極パッド３ｃの形状および寸法と同一である。   The second metal wiring layer 5 is formed in the same manner as the first metal wiring layer 3. The second metal wiring layer 5 includes an electrode pad 5a for connecting the IGBT 6a, an electrode pad 5b for connecting the diode 6b, a second electrode pad 5c for connecting the metal ball 10, and each electrode pad. A wiring portion (not shown) connected to each other and an external lead pad 5d are included. Among these, the 2nd electrode pad 5c is provided in the position facing the 1st electrode pad 3c, The shape and dimension are the same as the shape and dimension of the 1st electrode pad 3c.

半導体チップ６と第１金属配線層３とを接続する半田および半導体チップ６と第２金属配線層５とを接続する半田（以下、まとめて「基板−チップ間半田」という）の厚みは、温度サイクル等によって生じる疲労クラックを抑制する観点から厚い方が好ましいが、一方で半田は熱伝導係数が低いため、厚くしすぎると放熱効率が低下してしまう。このため、基板−チップ間半田の厚みは、０．１ｍｍ以上かつ０．３ｍｍ以下であることが好ましい。また、半導体チップ６が第１基板２と第２基板４との間で安定した位置を維持することと、半導体チップ６の上下の半田の信頼性を高めるために、半導体チップ６と第１金属配線層３とを接続する半田と半導体チップ６と第２金属配線層５とを接続する半田とを同一厚みとすることが好ましい。   The thicknesses of the solder for connecting the semiconductor chip 6 and the first metal wiring layer 3 and the solder for connecting the semiconductor chip 6 and the second metal wiring layer 5 (hereinafter collectively referred to as “substrate-chip solder”) are as follows: From the viewpoint of suppressing fatigue cracks caused by cycles or the like, a thicker one is preferable. On the other hand, since solder has a low thermal conductivity coefficient, if it is too thick, the heat dissipation efficiency is lowered. For this reason, it is preferable that the thickness of the board-chip solder is 0.1 mm or more and 0.3 mm or less. Further, in order to maintain the semiconductor chip 6 in a stable position between the first substrate 2 and the second substrate 4 and to improve the reliability of the solder above and below the semiconductor chip 6, the semiconductor chip 6 and the first metal It is preferable that the solder connecting the wiring layer 3 and the solder connecting the semiconductor chip 6 and the second metal wiring layer 5 have the same thickness.

第１基板２および第２基板４の間には、充填樹脂１１が充填されている。図１から明らかなように、本実施形態に係るパワーモジュール１はＡｌワイヤを必要としない。したがって、本発明ではＡｌワイヤの膨張・収縮を考慮する必要はないので、柔軟性の高いシリコンゲルではなくより硬質なエポキシ樹脂を充填樹脂１１として充填することができる。なお、充填樹脂１１は毛細管力により隅々にまで拡がるので、粘度の高いエポキシ樹脂を使用しても、充填されない部分が生じることはない。   A filling resin 11 is filled between the first substrate 2 and the second substrate 4. As is clear from FIG. 1, the power module 1 according to the present embodiment does not require an Al wire. Therefore, in the present invention, since it is not necessary to consider the expansion / contraction of the Al wire, a harder epoxy resin can be filled as the filling resin 11 instead of a highly flexible silicon gel. In addition, since the filling resin 11 spreads to every corner by the capillary force, even if an epoxy resin having a high viscosity is used, an unfilled portion does not occur.

樹脂ケース７は、外部接続リード１２を一体成型したインサートケースとなっており、図１（Ｂ）に示すように、樹脂ケース７の内側に設けられた内部接続端子１３（外部接続リード１２の一端）および第２基板４に形成された外部引出パッド５ｄは、屈曲部を有する接続ダンパリード１４により接続されている。また、接続ダンパリード１４周辺には、エポキシ樹脂ではなく柔軟性の高いシリコン樹脂が充填されている。屈曲部を有する接続ダンパリード１４で接続を行ったのは、樹脂ケース７とセラミック材料からなる第１基板２および第２基板４の熱膨張係数差に起因する応力を吸収させるためである。   The resin case 7 is an insert case in which the external connection lead 12 is integrally molded. As shown in FIG. 1B, the internal connection terminal 13 (one end of the external connection lead 12) provided inside the resin case 7 is provided. ) And the external lead pad 5d formed on the second substrate 4 are connected by a connection damper lead 14 having a bent portion. Further, the periphery of the connection damper lead 14 is filled with a highly flexible silicon resin instead of an epoxy resin. The connection is made with the connection damper lead 14 having the bent portion in order to absorb the stress caused by the difference in thermal expansion coefficient between the resin case 7 and the first substrate 2 and the second substrate 4 made of the ceramic material.

第１放熱フィン８および第２放熱フィン９は、放熱接着剤によりそれぞれ第１基板２および第２基板４に接続されている。第１放熱フィン８および第２放熱フィン９の材料は、Ａｌ系合金、銅系合金、セラミック系合金から適宜選択することができる。特に、セラミック系合金を選択した場合は、第１基板２および第２基板４との熱膨張係数差が少なく、接続部にかかる応力が低くなるという利点がある。放熱接着剤としてはシリコングリースを使用するのが一般的であるが、これには限定されない。   The first radiating fins 8 and the second radiating fins 9 are connected to the first substrate 2 and the second substrate 4 by a radiating adhesive, respectively. The material of the 1st radiation fin 8 and the 2nd radiation fin 9 can be suitably selected from Al system alloy, copper system alloy, and ceramic system alloy. In particular, when a ceramic alloy is selected, there is an advantage that the difference in thermal expansion coefficient between the first substrate 2 and the second substrate 4 is small, and the stress applied to the connection portion is reduced. Silicon grease is generally used as the heat dissipation adhesive, but is not limited thereto.

このように、本実施形態では、半導体チップ６の表裏の電極が放熱性の高い基板２、４に半田で接続され、半導体チップ６の発熱を表裏の両方向に熱伝導させ、第１放熱フィン８と第２放熱フィン９とから放熱させることが可能となっている。このため、半導体チップ６の温度上昇を効果的に抑制することができる。   As described above, in the present embodiment, the front and back electrodes of the semiconductor chip 6 are connected to the substrates 2 and 4 having high heat dissipation properties by soldering, and the heat generated in the semiconductor chip 6 is conducted in both the front and back directions, so It is possible to dissipate heat from the second radiating fins 9. For this reason, the temperature rise of the semiconductor chip 6 can be effectively suppressed.

パワーモジュール１は、第１電極パッド３ｃおよび第２電極パッド５ｃの双方に接し、第１電極パッド３ｃと第２電極パッド５ｃとの間で数１０Ａオーダーの大電流を通流可能にする金属球１０をさらに備えている。大電流を通流させた際の発熱を抑えるために、金属球１０は電気伝導率が高い銅を主材料としている。また、金属球１０は、後で述べる理由から、半田との濡れ性を向上させるための表面処理がなされていることが好ましい。このような表面処理としては、例えば、Ｓｎ系メッキ、Ａｇ系メッキ等がある。   The power module 1 is in contact with both the first electrode pad 3c and the second electrode pad 5c, and allows a large current on the order of several tens of A to flow between the first electrode pad 3c and the second electrode pad 5c. 10 is further provided. In order to suppress heat generation when a large current is passed, the metal ball 10 is mainly made of copper having high electrical conductivity. Moreover, it is preferable that the metal ball 10 is subjected to a surface treatment for improving the wettability with the solder for the reason described later. Examples of such surface treatment include Sn-based plating and Ag-based plating.

図２は、金属球１０周辺を拡大した断面図である。同図に示すように、第１電極パッド３ｃおよび第２電極パッド５ｃは、その最表面において金属球１０に接している。したがって、パッド間距離ｈは金属球１０の直径２Ｒ（金属球１０の半径をＲとする）に等しい。金属球１０の直径２Ｒは、基板−チップ間半田の厚みを、０．１ｍｍ以上かつ０．３ｍｍ以下とすると、半導体チップ６上下の半田厚みを考慮して、第１基板２と第２基板４とにより挟持される複数の半導体チップ６のうちで最も厚みが大きなチップの厚みに対して、０．２ｍｍ〜０．６ｍｍを加えた値に設定することが好ましい。   FIG. 2 is an enlarged cross-sectional view around the metal ball 10. As shown in the figure, the first electrode pad 3c and the second electrode pad 5c are in contact with the metal ball 10 on the outermost surface. Therefore, the inter-pad distance h is equal to the diameter 2R of the metal sphere 10 (the radius of the metal sphere 10 is R). The diameter 2R of the metal ball 10 is such that when the thickness of the solder between the substrate and the chip is 0.1 mm or more and 0.3 mm or less, the first substrate 2 and the second substrate 4 are considered in consideration of the solder thickness above and below the semiconductor chip 6. It is preferable to set a value obtained by adding 0.2 mm to 0.6 mm to the thickness of the chip having the largest thickness among the plurality of semiconductor chips 6 sandwiched between the two.

また、第１電極パッド３ｃと第２電極パッド５ｃの間には第１電極パッド３ｃおよび第２電極パッド５ｃを半田接続する半田部１５が設けられており、金属球１０はこの半田部１５内部に収容されている。本実施形態に係るパワーモジュール１は、かかる構成を採用したことにより、半田部１５の溶融時に第１電極パッド３ｃと第２電極パッド５ｃの水平位置を自動的に調整することができる（以下、セルフアライメントという）。   In addition, a solder part 15 for soldering the first electrode pad 3c and the second electrode pad 5c is provided between the first electrode pad 3c and the second electrode pad 5c. Is housed in. By adopting such a configuration, the power module 1 according to the present embodiment can automatically adjust the horizontal positions of the first electrode pad 3c and the second electrode pad 5c when the solder portion 15 is melted (hereinafter, referred to as “the solder module 15”). Self-alignment).

なお、セルフアライメントを効果的に機能させるためには、全ての基板−チップ間半田を同一組成とすることが好ましい。これにより、半田を溶融させる際に、半導体チップ６と第１金属配線層３とを接続する半田と半導体チップ６と第２金属配線層５とを接続する半田とを同時に溶融させ、セルフアライメントを有効に機能させることができる。   In order to make the self-alignment function effectively, it is preferable that all the board-chip solders have the same composition. Thereby, when melting the solder, the solder for connecting the semiconductor chip 6 and the first metal wiring layer 3 and the solder for connecting the semiconductor chip 6 and the second metal wiring layer 5 are simultaneously melted to perform self-alignment. It can function effectively.

セルフアライメントは、図３に示す原理により行われる。すなわち、金属球１０が第２電極パッド５ｃの中心部で接していない状態（水平方向において第１電極パッド３ｃの中心位置と第２電極パッド５ｃの中心位置とがずれている状態）においては、溶融した半田部１５の第２電極パッド５ｃ近傍にγ２のメニスカス力（表面張力ともいう）が生じる。そして、このメニスカス力により金属球１０が時計回りに回転し、第２電極パッド５ｃ（第２基板４）が右方向に移動し、最終的に、第１電極パッド３ｃと第２電極パッド５ｃが正対位置に対向し、かつ金属球１０が第１電極パッド３ｃおよび第２電極パッド５ｃの中心部に接した状態となる。金属球１０および第１電極パッド３ｃが第１電極パッド３ｃの中心部で接していない場合も、同様に、第１電極パッド３ｃ（第１基板２）が水平方向に移動して、金属球１０と第１電極パッド３ｃとが第１電極パッド３ｃの中心部で接した状態となる。 Self-alignment is performed according to the principle shown in FIG. That is, in a state where the metal ball 10 is not in contact with the center portion of the second electrode pad 5c (a state where the center position of the first electrode pad 3c and the center position of the second electrode pad 5c are shifted in the horizontal direction). A γ 2 meniscus force (also referred to as surface tension) is generated in the vicinity of the second electrode pad 5 c of the melted solder portion 15. The meniscus force causes the metal ball 10 to rotate clockwise, the second electrode pad 5c (second substrate 4) moves to the right, and finally the first electrode pad 3c and the second electrode pad 5c are moved to each other. The metal sphere 10 is in contact with the center of the first electrode pad 3c and the second electrode pad 5c. Similarly, even when the metal sphere 10 and the first electrode pad 3c are not in contact with each other at the center of the first electrode pad 3c, the first electrode pad 3c (first substrate 2) moves in the horizontal direction, and the metal sphere 10 And the first electrode pad 3c are in contact with each other at the center of the first electrode pad 3c.

なお、セルフアライメント中、メニスカス力により第１電極パッド３ｃと第２電極パッド５ｃは互いに近づこうとする。しかしながら、第１電極パッド３ｃと第２電極パッド５ｃの間には金属球１０が挟まれているため、パッド間距離ｈは金属球１０の直径２Ｒに維持される。金属球１０にＳｎ系メッキ、Ａｇ系メッキ等の表面処理を行ったのは、半田との濡れ性を向上させ、溶融した半田部１５に埋もれた金属球１０が回転するときの転がり抵抗を少なくするためである。   During self-alignment, the first electrode pad 3c and the second electrode pad 5c tend to approach each other due to the meniscus force. However, since the metal sphere 10 is sandwiched between the first electrode pad 3c and the second electrode pad 5c, the inter-pad distance h is maintained at the diameter 2R of the metal sphere 10. The surface treatment such as Sn plating or Ag plating was performed on the metal ball 10 to improve the wettability with the solder and to reduce the rolling resistance when the metal ball 10 buried in the molten solder portion 15 rotates. It is to do.

ここで、メニスカス力を有効に働かせるためには、半田部１５の表面が懸垂曲線を描くことが必要である。したがって、図２に示すように、第１電極パッド３ｃおよび第２電極パッド５ｃの径寸法（第１電極パッド３ｃおよび第２電極パッド５ｃが平面視矩形状を有している場合は、その最も長い長辺を半分にした寸法、正方形であればそのまま一辺を半分にした寸法）は、金属球半径Ｒの１．５倍以上としなければならない。   Here, in order to make the meniscus force work effectively, the surface of the solder portion 15 needs to draw a suspension curve. Therefore, as shown in FIG. 2, the diameter dimension of the first electrode pad 3c and the second electrode pad 5c (if the first electrode pad 3c and the second electrode pad 5c have a rectangular shape in plan view, the most The dimension obtained by halving the long long side, or the dimension obtained by halving one side in the case of a square) must be 1.5 times the radius R of the metal sphere.

極端な例として、図４は第１電極パッド３ｃの径寸法と金属球半径Ｒをほぼ等しくした場合である。この場合、半田部１５に生じるメニスカス力は金属球１０を第１電極パッド３ｃに押し付ける力としてのみ働く。つまり、メニスカス力は、金属球１０を回転させて第１電極パッド３ｃ（第１基板２）の水平位置をセルフアライメントするようには働かない。   As an extreme example, FIG. 4 shows a case where the diameter of the first electrode pad 3c and the radius R of the metal sphere are substantially equal. In this case, the meniscus force generated in the solder portion 15 works only as a force for pressing the metal ball 10 against the first electrode pad 3c. That is, the meniscus force does not work to rotate the metal ball 10 and self-align the horizontal position of the first electrode pad 3c (first substrate 2).

一方で、金属球１０の回転による十分な基板移動を許容するとともに、メニスカス力を有効に働かせるという阻害させない観点からは、第１電極パッド３ｃおよび第２電極パッド５ｃの径寸法は、金属球半径Ｒとメニスカス距離（水平方向における金属球１０の外縁から電極パッド端縁までの距離）１．５Ｒとの和、すなわち金属球半径Ｒの２．５倍まで確保できれば十分である。ここで、少なくとも、半田部１５の表面が懸垂曲線を描きセルフアライメントを機能させるには、上記したように、第１電極パッド３ｃおよび第２電極パッド５ｃの径寸法は、金属球半径Ｒの１．５倍以上とする必要がある。一方で、あまり電極パッド面積を大きくすると、パワーモジュールの小型化に支障があるだけでなく、金属球１０の回転モーメントが低下してセルフアライメントが働きにくくなる。   On the other hand, from the viewpoint of allowing sufficient movement of the substrate due to the rotation of the metal sphere 10 and preventing the meniscus force from acting effectively, the diameter dimensions of the first electrode pad 3c and the second electrode pad 5c are set to the radius of the metal sphere. It is sufficient to secure the sum of R and the meniscus distance (the distance from the outer edge of the metal sphere 10 to the electrode pad edge in the horizontal direction) 1.5R, that is, 2.5 times the radius R of the metal sphere. Here, in order for at least the surface of the solder portion 15 to draw a suspension curve and to function self-alignment, the diameter of the first electrode pad 3c and the second electrode pad 5c is 1 of the metal ball radius R as described above. It is necessary to make it 5 times or more. On the other hand, if the electrode pad area is too large, not only will the power module be reduced in size, but also the rotational moment of the metal ball 10 will be reduced, making it difficult for self-alignment to work.

以上から、第１電極パッド３ｃおよび第２電極パッド５ｃの径寸法を金属球半径Ｒの１．５倍以上かつ２．５倍以下に設定すれば、半導体チップ６の実装密度の低下によりパワージュールが大型化するのを抑えつつ、十分なアライメント量（第１電極パッド３ｃおよび第２電極パッド５ｃの水平移動量）を確保することができる。   From the above, if the diameter dimensions of the first electrode pad 3c and the second electrode pad 5c are set to be 1.5 times or more and 2.5 times or less of the metal sphere radius R, the power joule is reduced due to a decrease in the mounting density of the semiconductor chip 6. A sufficient amount of alignment (the amount of horizontal movement of the first electrode pad 3c and the second electrode pad 5c) can be ensured while suppressing an increase in size.

以上、本発明の好ましい実施形態について説明したが、本発明はこの構成に限定されるものではない。   As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to this structure.

例えば、上記実施形態における半導体チップ６の種別および配置、第１電極パッド３ｃおよび第２電極パッド５ｃの形状はすべて一例であり、任意に変更することができる。例えば、第１電極パッド３ｃおよび第２電極パッド５ｃの形状として、長方形のほか正方形等の四角形を含む多角形、円形を採用することができる。ただし、第１電極パッド３ｃおよび第２電極パッド５ｃの形状については、上記の条件を満たすよう注意が必要である。例えば、第１電極パッド３ｃおよび第２電極パッド５ｃが円形状であれば、そのパッド半径である径寸法を金属球半径Ｒの１．５倍以上とする必要がある。   For example, the type and arrangement of the semiconductor chip 6 and the shapes of the first electrode pad 3c and the second electrode pad 5c in the above embodiment are all examples, and can be arbitrarily changed. For example, as the shapes of the first electrode pad 3c and the second electrode pad 5c, a polygon or a circle including a rectangle such as a square as well as a rectangle can be adopted. However, care must be taken to satisfy the above-described conditions for the shapes of the first electrode pad 3c and the second electrode pad 5c. For example, if the first electrode pad 3c and the second electrode pad 5c are circular, the diameter, which is the pad radius, needs to be 1.5 times or more the metal sphere radius R.

また、上記実施形態では、熱伝導率および電気伝導率が高く、比較的安価で、しかも加工性に優れた銅を金属球１０の主材料としたが、金属球１０を構成する金属は、銀（Ａg）または高純度アルミニウムを主材料としたものであってもよい。また、導電性球は、導電性プラスチックまたはカーボンコンポジット等に上記金属からなるメッキ皮膜を形成したものであってもよい。   Moreover, in the said embodiment, although heat conductivity and electrical conductivity were high, copper which was comparatively cheap and excellent in workability was used as the main material of the metal sphere 10, the metal which comprises the metal sphere 10 is silver. The main material may be (Ag) or high-purity aluminum. The conductive sphere may be a conductive plastic or carbon composite or the like formed with a plating film made of the above metal.

１ パワーモジュール
２ 第１基板
３ 第１金属配線層
３ａ 電極パッド（ＩＧＢＴ用）
３ｂ 電極パッド（ダイオード用）
３ｃ 第１電極パッド（金属球用）
４ 第２基板
５ 第２金属配線層
５ａ 電極パッド（ＩＧＢＴ用）
５ｂ 電極パッド（ダイオード用）
５ｃ 第２電極パッド（金属球用）
５ｄ 外部引出パッド
６ 半導体チップ
６ａ ＩＧＢＴ
６ｂ ダイオード
７ 樹脂ケース
８ 第１放熱フィン
９ 第２放熱フィン
１０ 金属球（導電性球）
１１ 充填樹脂
１２ 外部接続リード
１３ 内部接続端子
１４ 接続ダンパリード
１５ 半田部 DESCRIPTION OF SYMBOLS 1 Power module 2 1st board | substrate 3 1st metal wiring layer 3a Electrode pad (for IGBT)
3b Electrode pad (for diode)
3c 1st electrode pad (for metal ball)
4 Second substrate 5 Second metal wiring layer 5a Electrode pad (for IGBT)
5b Electrode pad (for diode)
5c Second electrode pad (for metal balls)
5d External lead pad 6 Semiconductor chip 6a IGBT
6b Diode 7 Resin case 8 First radiation fin 9 Second radiation fin 10 Metal sphere (conductive sphere)
11 Filling resin 12 External connection lead 13 Internal connection terminal 14 Connection damper lead 15 Solder part

Claims (3)

第１金属配線層を有する第１基板と、第２金属配線層を有する第２基板と、表面側電極が前記第２金属配線層に半田接続され、かつ裏面側電極が前記第１金属配線層に半田接続された複数の半導体チップとを備えたパワーモジュールであって、
前記第１金属配線層は平坦な第１電極パッドを含み、
前記第２金属配線層は前記第１電極パッドに対向する平坦な第２電極パッドを含み、
前記第１電極パッドおよび第２電極パッドの間に配置され、該第１電極パッドおよび第２電極パッドを電気的に接続する金属で表面が覆われた導電性球と、
前記第１電極パッドおよび前記第２電極パッドを半田接続する半田部と、
をさらに備え、
前記導電性球が、前記半田部内部に収容され、
前記導電性球の直径が、前記複数の半導体チップのうち最も厚みが大きなチップの厚みに対して０．２ｍｍ〜０．６ｍｍを加えた値に設定され、
前記第１電極パッドおよび第２電極パッドを構成する辺のうち最も長い長辺の半分の長さを径寸法としたとき、前記径寸法が、前記導電性球の半径の１．５倍以上かつ２．５倍以下に設定され、
前記半田部の表面が、懸垂曲線を描いている
ことを特徴とするパワーモジュール。 A first substrate having a first metal wiring layer, a second substrate having a second metal wiring layer, a front side electrode being solder-connected to the second metal wiring layer, and a back side electrode being the first metal wiring layer A power module comprising a plurality of semiconductor chips solder-connected to
The first metal wiring layer includes a flat first electrode pad;
The second metal wiring layer includes a flat second electrode pad facing the first electrode pad;
A conductive sphere disposed between the first electrode pad and the second electrode pad and having a surface covered with a metal that electrically connects the first electrode pad and the second electrode pad;
A solder part for soldering the first electrode pad and the second electrode pad;
Further comprising
The conductive sphere is accommodated inside the solder part,
The diameter of the conductive sphere is set to a value obtained by adding 0.2 mm to 0.6 mm to the thickness of the largest chip among the plurality of semiconductor chips,
When the half the length of the longest long side of the sides of the first electrode pad and the second electrode pad and a diameter, the diameter is the radius of 1.5 times or more before Kishirube conductive spheres And 2.5 times or less ,
The power module , wherein the surface of the solder portion has a hanging curve . 前記導電性球の表面に、半田との濡れ性を向上させるための表面処理が施されていることを特徴とする請求項１に記載のパワーモジュール。 The power module according to claim 1, wherein a surface treatment for improving wettability with solder is applied to a surface of the conductive sphere . 前記第１基板の両主面のうち前記第１金属配線層が形成されていない面に第１放熱フィンが取り付けられ、前記第２基板の両主面のうち前記第２金属配線層が形成されていない面に第２放熱フィンが取り付けられていることを特徴とする請求項１または２に記載のパワーモジュール。 A first radiating fin is attached to a surface of the first substrate on which the first metal wiring layer is not formed, and a second metal wiring layer is formed on the main surface of the second substrate. The power module according to claim 1, wherein a second heat dissipating fin is attached to the surface that is not .
JP2011062820A 2011-03-22 2011-03-22 Power module Active JP5777203B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011062820A JP5777203B2 (en) 2011-03-22 2011-03-22 Power module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011062820A JP5777203B2 (en) 2011-03-22 2011-03-22 Power module

Publications (2)

Publication Number Publication Date
JP2012199400A JP2012199400A (en) 2012-10-18
JP5777203B2 true JP5777203B2 (en) 2015-09-09

Family

ID=47181333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011062820A Active JP5777203B2 (en) 2011-03-22 2011-03-22 Power module

Country Status (1)

Country Link
JP (1) JP5777203B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107567657A (en) * 2015-05-08 2018-01-09 敏捷电源开关三维集成Apsi3D Semiconductor power device and the method for assembling semiconductor power device
KR101876237B1 (en) * 2015-12-15 2018-07-10 현대오트론 주식회사 Power module and method for manufacturing thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3022178B2 (en) * 1994-06-21 2000-03-15 日産自動車株式会社 Power device chip mounting structure
JP3879150B2 (en) * 1996-08-12 2007-02-07 株式会社デンソー Semiconductor device
JP4478049B2 (en) * 2005-03-15 2010-06-09 三菱電機株式会社 Semiconductor device
JP4421528B2 (en) * 2005-07-28 2010-02-24 シャープ株式会社 Solder mounting structure, manufacturing method thereof, and use thereof

Also Published As

Publication number Publication date
JP2012199400A (en) 2012-10-18

Similar Documents

Publication Publication Date Title
US7772692B2 (en) Semiconductor device with cooling member
JP6195689B1 (en) Power module
WO2011136358A1 (en) Led module
JP2002151633A (en) Resin-sealed semiconductor device
JP2012191002A (en) Semiconductor device
US9324929B2 (en) Wiring substrate
JP2005116702A (en) Power semiconductor module
JP4458028B2 (en) Semiconductor device
JP2008135627A (en) Semiconductor device
JP5777203B2 (en) Power module
JP2006190728A (en) Electric power semiconductor device
JP5681025B2 (en) Power module
US20200350274A1 (en) Chip package device
JP2008098285A (en) Semiconductor device
US11798873B2 (en) Semiconductor assembly
JP5998033B2 (en) Semiconductor device and manufacturing method thereof
JP2010219554A (en) Semiconductor device and electronic controller using the same
JP7459539B2 (en) semiconductor equipment
JP2019050297A (en) Semiconductor device
JP3883531B2 (en) Semiconductor device
CN214226906U (en) Chip heat radiation structure, packaged chip and electronic equipment
JP2005268496A (en) Semiconductor device
JP2012199283A (en) Semiconductor device
JP5946128B2 (en) Power module
JP5892655B2 (en) Power module design method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130910

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140107

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140618

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140805

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20141008

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20141202

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20150701

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20150703

R150 Certificate of patent or registration of utility model

Ref document number: 5777203

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250