JP2005116702A - Power semiconductor module - Google Patents

Power semiconductor module Download PDF

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Publication number
JP2005116702A
JP2005116702A JP2003347356A JP2003347356A JP2005116702A JP 2005116702 A JP2005116702 A JP 2005116702A JP 2003347356 A JP2003347356 A JP 2003347356A JP 2003347356 A JP2003347356 A JP 2003347356A JP 2005116702 A JP2005116702 A JP 2005116702A
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semiconductor element
high thermal
thermal conductor
semiconductor module
power semiconductor
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Yoshinari Ikeda
良成 池田
Takashi Fujii
岳志 藤井
Katsuhiko Yoshihara
克彦 吉原
Yuji Iizuka
祐二 飯塚
Mitsuo Yamashita
満男 山下
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Fuji Electric Co Ltd
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Fuji Electric Holdings Ltd
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Priority to JP2003347356A priority Critical patent/JP2005116702A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a power semiconductor module that can reduce the surface temperature of a semiconductor device and uniformize its in-plane temperature distribution. <P>SOLUTION: The power semiconductor module temporarily suspends heat generated in a semiconductor device 13 by means of a high thermal conductivity body 20 so as to suppress the surface temperature rise of the semiconductor device 13. Especially, the thermal conductivity of the body 20 is higher than that of the semiconductor device 13, so that the generated heat is conducted swiftly, resulting in permitting temperature suppression effect exhibited. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、発熱性の半導体素子を絶縁基板上に構成された回路パターンに接合して構成されるパワー半導体モジュールに関する。   The present invention relates to a power semiconductor module configured by bonding a heat-generating semiconductor element to a circuit pattern formed on an insulating substrate.

近年、ＩＧＢＴ（Insulated Gate Bipolar Transistor）モジュールなどのパワー半導体モジュールのパッケージ構造は、図８に示すようなケース構造と呼ばれるものが主流となっている。同図（Ａ）は、そのＩＧＢＴモジュールの主要部を表す平面図であり、同図（Ｂ）は、そのＡ−Ａ断面に相当する矢視断面図である。   In recent years, a package structure of a power semiconductor module such as an IGBT (Insulated Gate Bipolar Transistor) module has been mainly used as a case structure as shown in FIG. FIG. 2A is a plan view showing the main part of the IGBT module, and FIG. 2B is a cross-sectional view taken along the line AA.

これらの図に示されるように、ＩＧＢＴモジュールは、ヒートシンク１１１，絶縁基板１１２及び半導体素子１１３を半田１１４により一体的に接合して、この一体となった構造物を樹脂成形されたケース１１５に接着し、さらに配線用の複数のワイヤ１１６を接続することにより構成されている。そして、これら絶縁基板１１２，半導体素子１１３及びワイヤ１１６を水分，湿気，塵などから保護するために、ケース１１５内はゲル１１７で封止されている。   As shown in these drawings, in the IGBT module, the heat sink 111, the insulating substrate 112, and the semiconductor element 113 are integrally joined by the solder 114, and the integrated structure is bonded to the resin-molded case 115. In addition, a plurality of wiring wires 116 are connected. In order to protect the insulating substrate 112, the semiconductor element 113, and the wire 116 from moisture, moisture, dust, and the like, the inside of the case 115 is sealed with a gel 117.

このＩＧＢＴモジュールの電気的接続については、同図に示すように、半導体素子１１３の表面電極にワイヤ１１６がボンディングされる一方、裏面電極が絶縁基板１１２上の回路パターン１１８（主にＣｕで構成）に半田接合されている。また、複数の回路パターン１１８の間や、各回路パターン１１８と外部電極用端子１１９との間にもワイヤ１１６がボンディングされ、電気的な接続が確保されている。   As for the electrical connection of the IGBT module, as shown in the figure, the wire 116 is bonded to the front surface electrode of the semiconductor element 113, while the back surface electrode is a circuit pattern 118 (mainly composed of Cu) on the insulating substrate 112. Are soldered together. Further, the wires 116 are bonded between the plurality of circuit patterns 118 and between each circuit pattern 118 and the external electrode terminal 119 to ensure electrical connection.

しかしながら、ワイヤ１１６による電気配線では半導体素子１１３で発生した熱を放熱させる作用が少ない。また、半導体素子１１３で発生した熱は絶縁基板１１２にて拡散してヒートシンク１１１に伝導されて放熱されるが、特に半導体素子１１３の中央部は端部に比べて発生した熱が絶縁基板１１２内で広がり難い。このため、実使用時に半導体素子１１３の中心部の温度が極端に上昇し、パワー半導体モジュールの性能及び信頼性を低下させてしまうといった問題があった。   However, the electrical wiring using the wires 116 has little effect of radiating the heat generated in the semiconductor element 113. The heat generated in the semiconductor element 113 is diffused in the insulating substrate 112 and is conducted to the heat sink 111 to be dissipated. In particular, the heat generated in the central portion of the semiconductor element 113 is larger in the insulating substrate 112 than in the end portion. It is difficult to spread. For this reason, there has been a problem that the temperature of the central portion of the semiconductor element 113 is extremely increased during actual use, thereby reducing the performance and reliability of the power semiconductor module.

こうした中、例えば半導体素子の表面電極に金属板を接合し、この金属板を介して半導体素子で発生した熱を放熱する技術が提案されている（例えば特許文献１）。
特開２０００−６８４４７号公報 Under such circumstances, for example, a technique has been proposed in which a metal plate is joined to a surface electrode of a semiconductor element and heat generated in the semiconductor element is radiated through the metal plate (for example, Patent Document 1).
JP 2000-68447 A

しかしながら、上記特許文献には、導電性の良い金属板を用いるとあるのみで、放熱に関するその金属板の具体的特性については触れられておらず、どの程度の放熱効果があるかについても開示されていない。   However, the above-mentioned patent document only uses a metal plate with good electrical conductivity, and does not touch on the specific characteristics of the metal plate with respect to heat dissipation, and discloses how much heat dissipation is effective. Not.

一方、上記問題を解決するためには、パワー半導体モジュールにおいて電流のオン／オフにより温度負荷が繰返される実使用時に生じる半田接合部の歪みを低減させ、その半田接合部の電気的安定性（電流の流れの均一化），熱的な性能（表面温度分布の均一化）と、その長期信頼性を確保する必要がある。そして、その長期信頼性を確保するためには、半導体素子の表面温度の低減、さらにその面内温度分布の均一化を如何に実現するかが課題となる。   On the other hand, in order to solve the above problem, in the power semiconductor module, distortion of the solder joint that occurs during actual use in which the temperature load is repeated due to current on / off is reduced, and the electrical stability (current) of the solder joint is reduced. And the long-term reliability of the thermal performance (uniform surface temperature distribution). And in order to ensure the long-term reliability, it becomes a subject how to implement | achieve reduction of the surface temperature of a semiconductor element, and also uniformization of the in-plane temperature distribution.

本発明はこのような点に鑑みてなされたものであり、半導体素子の表面温度の低減、及びその面内温度分布の均一化を実現できるパワー半導体モジュールを提供することを目的とする。   The present invention has been made in view of these points, and an object of the present invention is to provide a power semiconductor module that can reduce the surface temperature of a semiconductor element and make the in-plane temperature distribution uniform.

本発明では上記問題を解決するために、絶縁基板の表面に形成された回路パターンの所定位置に半導体素子をロー付接合して構成されるパワー半導体モジュールにおいて、前記半導体素子の前記絶縁基板とは反対側に形成された表面電極に、前記半導体素子の熱伝導率以上の熱伝導率を有する高熱伝導体をロー付接合したことを特徴とするパワー半導体モジュールが提供される。   In the present invention, in order to solve the above problem, in a power semiconductor module configured by brazing a semiconductor element to a predetermined position of a circuit pattern formed on the surface of the insulating substrate, the insulating substrate of the semiconductor element is defined as A power semiconductor module is provided in which a high thermal conductor having a thermal conductivity equal to or higher than the thermal conductivity of the semiconductor element is brazed to a surface electrode formed on the opposite side.

ここでいう「ロー付接合」には、半田接合その他のロー材による接合が含まれる。また、絶縁基板やこれに接合される半導体素子は一つであっても複数含まれていてもよい。
このようなパワー半導体モジュールによれば、高熱伝導体により半導体素子で発生した熱を一時的に保留し、半導体素子の表面温度の上昇を抑制することができる。特に、高熱伝導体の熱伝導率が半導体素子の熱伝導率以上になっているため、その発生熱を速やかに伝導させて温度抑制効果を発揮させることができる。 Here, “joining with brazing” includes joining by soldering or other brazing material. In addition, the insulating substrate and the semiconductor element bonded thereto may be one or plural.
According to such a power semiconductor module, it is possible to temporarily hold the heat generated in the semiconductor element by the high thermal conductor and suppress an increase in the surface temperature of the semiconductor element. In particular, since the thermal conductivity of the high thermal conductor is equal to or higher than the thermal conductivity of the semiconductor element, the generated heat can be conducted quickly and the temperature suppressing effect can be exhibited.

一般的には、半導体素子の熱伝導率は１００Ｗ／ｍ・Ｋ程度のものがほとんどであるため、高熱伝導体として、その熱伝導率が１００Ｗ／ｍ・Ｋ以上であるものを選択するのが好ましい。   In general, most of the semiconductor devices have a thermal conductivity of about 100 W / m · K. Therefore, a high thermal conductor having a thermal conductivity of 100 W / m · K or more is selected. preferable.

この場合、高熱伝導体における半導体素子の表面電極との接合面積が大きいほど熱伝導が良くなり、半導体素子の表面温度の低減効果を発揮する傾向にあるが、発明者らの解析により、ある接合面積以上になるとその効果が収束する傾向にあることが分かった。すなわち、後述する実施の形態でも述べるように、その接合面積が半導体素子の中心部を含め表面電極全体の面積の４０％以上となるように構成するとよい。   In this case, the larger the bonding area with the surface electrode of the semiconductor element in the high thermal conductor, the better the heat conduction, and the effect of reducing the surface temperature of the semiconductor element tends to be exerted. It turns out that the effect tends to converge when the area is exceeded. That is, as described in the embodiments described later, the junction area may be 40% or more of the total area of the surface electrode including the central portion of the semiconductor element.

同様に、発明者らの解析により、高熱伝導体の厚みが、半導体素子の厚みと、半導体素子との間に介装されるロー材の厚みとを合計した厚み以上となるように構成されていると、高熱伝導体による温度抑制効果を大きく発揮させることができる。具体的には、後述する実施の形態から、高熱伝導体の厚みが０．２５ｍｍ以上となるように構成されるのが好ましい。   Similarly, according to the analysis by the inventors, the thickness of the high thermal conductor is configured to be equal to or greater than the sum of the thickness of the semiconductor element and the thickness of the brazing material interposed between the semiconductor element. When it is, the temperature suppression effect by a high heat conductor can be exhibited largely. Specifically, it is preferable that the thickness of the high thermal conductor is 0.25 mm or more from the embodiments described later.

さらに、高熱伝導体が、半導体素子と絶縁基板の回路パターンとを接続する電気伝導体を構成するようにしてもよい。
このように構成すれば、高熱伝導体において半導体素子から受け取った熱を、絶縁基板側に伝導して放熱することができ、半導体素子の表面温度の速やかな低減を実現することができる。 Further, the high thermal conductor may constitute an electrical conductor that connects the semiconductor element and the circuit pattern of the insulating substrate.
If comprised in this way, the heat received from the semiconductor element in the high thermal conductor can be conducted and radiated to the insulating substrate side, and a rapid reduction of the surface temperature of the semiconductor element can be realized.

例えば、高熱伝導体をリードフレームとして構成することができ、その厚みが最小となる部分の厚さが０．２５ｍｍ以上となるように構成すれば、表面温度の良好な低減効果が得られる。   For example, a high thermal conductor can be formed as a lead frame, and if the thickness of the portion where the thickness is minimized is 0.25 mm or more, a good effect of reducing the surface temperature can be obtained.

本発明のパワー半導体モジュールによれば、高熱伝導体により半導体素子での発生熱を保留することができるため、その半導体素子の表面温度を低減させることができる。その結果、半導体素子の表面の温度勾配が小さくなり、その面内温度分布の均一化を実現することができる。   According to the power semiconductor module of the present invention, the generated heat in the semiconductor element can be retained by the high thermal conductor, so that the surface temperature of the semiconductor element can be reduced. As a result, the temperature gradient on the surface of the semiconductor element is reduced, and the in-plane temperature distribution can be made uniform.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。
［第１の実施の形態］
まず、本発明の第１の実施の形態について説明する。尚、本実施の形態のパワー半導体モジュールは、半導体素子としてＩＧＢＴを用いたものであり、図１はそのパワー半導体モジュール（ＩＧＢＴモジュール）の構造を表す断面図である。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[First Embodiment]
First, a first embodiment of the present invention will be described. In addition, the power semiconductor module of this Embodiment uses IGBT as a semiconductor element, FIG. 1 is sectional drawing showing the structure of the power semiconductor module (IGBT module).

図１に示すように、本実施の形態のパワー半導体モジュール１は、長方形板状の絶縁基板１１の表面に形成された回路パターン１２の所定位置に、複数の発熱性の半導体素子１３（ＩＧＢＴ：本実施の形態では熱伝導率約８５Ｗ／ｍ・Ｋ）を半田５１を介して半田接合して構成されている（図８（ａ）と同様）。尚、図１においては、その複数の半導体素子１３の一つが表示されている。   As shown in FIG. 1, the power semiconductor module 1 of the present embodiment has a plurality of exothermic semiconductor elements 13 (IGBT: IGBT) at predetermined positions of a circuit pattern 12 formed on the surface of a rectangular plate-like insulating substrate 11. In this embodiment, a thermal conductivity of about 85 W / m · K) is soldered via a solder 51 (similar to FIG. 8A). In FIG. 1, one of the plurality of semiconductor elements 13 is displayed.

絶縁基板１１の裏面には、この絶縁基板１１よりも大きな長方形板状の銅（Ｃｕ）板からなるヒートシンク１４が半田５２を介して半田接合されており、そのヒートシンク１４の上端縁に沿って半導体素子１３を取り囲むように、樹脂成形されたケース１５が接着されている。ケース１５の内壁には外部接続端子として、エミッタ用端子２１やコレクタ用端子２２等が設けられており、それぞれ複数本のアルミワイヤ３１，３２等を介して絶縁基板１１の回路パターン１２に電気的に接続されている。   A heat sink 14 made of a rectangular copper (Cu) plate larger than the insulating substrate 11 is solder-bonded to the back surface of the insulating substrate 11 via solder 52, and a semiconductor is formed along the upper edge of the heat sink 14. A resin-molded case 15 is bonded so as to surround the element 13. The inner wall of the case 15 is provided with an emitter terminal 21 and a collector terminal 22 as external connection terminals, which are electrically connected to the circuit pattern 12 of the insulating substrate 11 via a plurality of aluminum wires 31 and 32, respectively. It is connected to the.

半導体素子１３の表面電極は、図示しないアルミ（Ａｌ）で成膜されているが、無電解Ｎｉ／Ａｕめっき処理を施しているため、半田接合が可能となっている。そして、半導体素子１３の絶縁基板１１とは反対側に形成された表面電極には、低電気抵抗率で高熱伝導率を有する銅からなる長方形板状の高熱伝導体２０が半田５３を介して半田接合されている。この高熱伝導体２０は、半導体素子１３の表面に形成されたエミッタ電極に接続されており、その上面にはエミッタ電流を絶縁基板１１側に流すアルミワイヤ３３の一端がボンディングされ、その他端が回路パターン１２に接続されている。半導体素子１３の裏面にはコレクタ電極が形成されており、半田５１を介して絶縁基板１１の回路パターン１２に接続されている。   Although the surface electrode of the semiconductor element 13 is formed of aluminum (Al) (not shown), since it is subjected to electroless Ni / Au plating, solder bonding is possible. Then, on the surface electrode formed on the side opposite to the insulating substrate 11 of the semiconductor element 13, a rectangular plate-shaped high thermal conductor 20 made of copper having low electrical resistivity and high thermal conductivity is soldered via the solder 53. It is joined. The high thermal conductor 20 is connected to an emitter electrode formed on the surface of the semiconductor element 13, and one end of an aluminum wire 33 for passing an emitter current to the insulating substrate 11 side is bonded to the upper surface thereof, and the other end is connected to a circuit. Connected to the pattern 12. A collector electrode is formed on the back surface of the semiconductor element 13 and is connected to the circuit pattern 12 of the insulating substrate 11 via the solder 51.

また、半導体素子１３の表面にはゲート電極も形成されており、このゲート電極と回路パターン１２とをつなぐアルミワイヤ３４がボンディングされている。このゲート電極と電気的に接続される回路パターン１２の部分からは、さらにアルミワイヤ３５が延出しており、その先端がケース１５の内壁に設けられた図示しないゲート用端子に接続されている。つまり、各アルミワイヤによって電気配線が形成されている。   A gate electrode is also formed on the surface of the semiconductor element 13, and an aluminum wire 34 connecting the gate electrode and the circuit pattern 12 is bonded. An aluminum wire 35 further extends from the portion of the circuit pattern 12 that is electrically connected to the gate electrode, and its tip is connected to a gate terminal (not shown) provided on the inner wall of the case 15. That is, electric wiring is formed by each aluminum wire.

さらに、これら絶縁基板１１，半導体素子１３，高熱伝導体２０及び各アルミワイヤを水分，湿気，塵などから保護するために、ケース１５内はゲル１７で封止されている。
次に、本実施の形態の高熱伝導体２０を設けたことによる温度低減効果について説明する。図２は、ＦＥＭ（有限要素法）による解析結果であり、高熱伝導体２０の接合面積と半導体素子１３の表面温度との関係を示している。同図において、横軸は、半導体素子１３の表面電極の面積（活性面積）に対する高熱伝導体２０の接合面積の比率（％）を表し、縦軸は、半導体素子１３の表面温度（℃）を表している。 Further, the inside of the case 15 is sealed with a gel 17 in order to protect the insulating substrate 11, the semiconductor element 13, the high thermal conductor 20, and each aluminum wire from moisture, moisture, dust, and the like.
Next, the temperature reduction effect by providing the high thermal conductor 20 of this Embodiment is demonstrated. FIG. 2 is an analysis result by FEM (finite element method), and shows the relationship between the junction area of the high thermal conductor 20 and the surface temperature of the semiconductor element 13. In the figure, the horizontal axis represents the ratio (%) of the junction area of the high thermal conductor 20 to the area (active area) of the surface electrode of the semiconductor element 13, and the vertical axis represents the surface temperature (° C.) of the semiconductor element 13. Represents.

このＦＥＭ解析の解析条件としては、高熱伝導体２０を厚さ１．０ｍｍ，熱伝導率３９０Ｗ／ｍ・Ｋの銅で形成し、半導体素子１３を一辺９．２５ｍｍ，厚さ１００μｍの正方形板状のものとした。また、半導体素子１３の発生熱量を１６０Ｗ，パワー半導体モジュール１の周囲温度を２５℃、冷却については強制空冷とした（以下の解析についても全て同条件である）。   As analysis conditions for this FEM analysis, the high thermal conductor 20 is formed of copper having a thickness of 1.0 mm and a thermal conductivity of 390 W / m · K, and the semiconductor element 13 is a square plate having a side of 9.25 mm and a thickness of 100 μm. It was a thing. Further, the generated heat amount of the semiconductor element 13 was 160 W, the ambient temperature of the power semiconductor module 1 was 25 ° C., and the cooling was forced air cooling (the same applies to the following analysis).

同図によれば、高熱伝導体２０の接合面積が大きいほど表面温度を低減できることが分かり、特に、高熱伝導体２０の接合面積が半導体素子１３の表面電極の面積に対する面積比で４０％以上であれば、表面温度を大幅（１５℃以上）に低減できることが分かる。また、同面積比が４０％以上になると、その表面温度が収束していることも分かる。   According to the figure, it can be seen that the surface temperature can be reduced as the junction area of the high thermal conductor 20 is increased. If it exists, it turns out that surface temperature can be reduced significantly (15 degreeC or more). It can also be seen that when the area ratio is 40% or more, the surface temperature converges.

次に、図３は、上述した接合面積比（図２参照）が７８％の場合と、０％の場合（つまり、高熱伝導体２０が無い場合）についての半導体素子１３の表面の温度分布を示している。同図において、横軸は、半導体素子１３の表面における幅方向の位置（一端縁からの距離）を表し、縦軸は、その表面温度（℃）を表している。   Next, FIG. 3 shows the temperature distribution on the surface of the semiconductor element 13 when the above-mentioned junction area ratio (see FIG. 2) is 78% and 0% (that is, when there is no high thermal conductor 20). Show. In the figure, the horizontal axis represents the position in the width direction (distance from one edge) on the surface of the semiconductor element 13, and the vertical axis represents the surface temperature (° C.).

同図によれば、半導体素子１３の表面電極に高熱伝導体２０を半田接合した場合のほうが、高熱伝導体２０を接合していない場合に比べてその半導体素子１３の表面温度が大きく低下していることが分かる。また、高熱伝導体２０を接合した場合のほうが表面温度分布の差が小さく、表面温度分布が均一化される傾向にあることが分かる。   According to the figure, the surface temperature of the semiconductor element 13 is much lower when the high thermal conductor 20 is soldered to the surface electrode of the semiconductor element 13 than when the high thermal conductor 20 is not bonded. I understand that. It can also be seen that when the high thermal conductor 20 is bonded, the difference in surface temperature distribution is smaller and the surface temperature distribution tends to be uniform.

次に、図４は、高熱伝導体２０の厚さを変化させた場合の表面温度の変化を示している。同図において、横軸は、高熱伝導体２０の厚さ（ｍｍ）を表し、縦軸は、表面温度（℃）を表している。   Next, FIG. 4 shows changes in the surface temperature when the thickness of the high thermal conductor 20 is changed. In the figure, the horizontal axis represents the thickness (mm) of the high thermal conductor 20, and the vertical axis represents the surface temperature (° C.).

同図によれば、高熱伝導体２０の厚さが０．２５ｍｍ以上のときに特に表面温度の低減効果が大きいことが分かる。
以上に説明したように、本実施の形態のパワー半導体モジュール１は、高熱伝導体２０により半導体素子１３で発生した熱を一時的に保留し、半導体素子１３の表面温度の上昇を抑制することができる。特に、高熱伝導体２０の熱伝導率が半導体素子１３の熱伝導率よりも大きいため、その発生熱を速やかに伝導させて温度抑制効果を発揮させることができる。 According to the figure, it can be seen that the effect of reducing the surface temperature is particularly great when the thickness of the high thermal conductor 20 is 0.25 mm or more.
As described above, the power semiconductor module 1 according to the present embodiment temporarily holds the heat generated in the semiconductor element 13 by the high thermal conductor 20 and suppresses an increase in the surface temperature of the semiconductor element 13. it can. In particular, since the thermal conductivity of the high thermal conductor 20 is larger than the thermal conductivity of the semiconductor element 13, the generated heat can be quickly conducted to exert a temperature suppressing effect.

その結果、半導体素子１３と絶縁基板１１との接合部の熱応力による歪を低減することもでき、信頼性の高い接合が可能となる。
［第２の実施の形態］
次に、本発明の第２の実施の形態について説明する。図５は、本実施の形態にかかるパワー半導体モジュールの構造を表す断面図である。尚、本実施の形態は、高熱伝導体の構成を除けば上記第１の実施の形態の構成と同様であるため、同様の構成部分については同一の符号を付す等してその説明を省略する。 As a result, distortion due to thermal stress at the joint between the semiconductor element 13 and the insulating substrate 11 can be reduced, and highly reliable joining is possible.
[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 5 is a cross-sectional view showing the structure of the power semiconductor module according to the present embodiment. Since the present embodiment is the same as the configuration of the first embodiment except for the configuration of the high thermal conductor, the same components are denoted by the same reference numerals and the description thereof is omitted. .

図５に示すように、本実施の形態のパワー半導体モジュール２０１においては、高熱伝導体２２０を二股のリードフレーム（電気伝導体）として構成している。その材質は銅（Ｃｕ）であり、第１の実施の形態と同様である。   As shown in FIG. 5, in the power semiconductor module 201 of the present embodiment, the high thermal conductor 220 is configured as a bifurcated lead frame (electric conductor). The material is copper (Cu), which is the same as in the first embodiment.

すなわち、高熱伝導体２２０は、上記高熱伝導体２０と同形状の本体２２１の側方に、半田５４を介して絶縁基板１１の回路パターン１２に電気的に接続されるリードフレーム部２２２を有している。この本体２２１とリードフレーム部２２２とはその上端縁が架橋部２２３によって接続されている。   That is, the high thermal conductor 220 has a lead frame portion 222 that is electrically connected to the circuit pattern 12 of the insulating substrate 11 via the solder 54 on the side of the main body 221 having the same shape as the high thermal conductor 20. ing. The upper end edge of the main body 221 and the lead frame portion 222 are connected by a bridging portion 223.

次に、本実施の形態の高熱伝導体２２０を設けたことによる放熱効果について説明する。図６は、ＦＥＭによる解析結果であり、高熱伝導体２２０の厚さと半導体素子１３の表面温度との関係を示している。同図において、横軸は、高熱伝導体２２０において厚みが最小となる架橋部２２３の厚さ（ｍｍ）を表し、縦軸は、半導体素子１３の表面温度（℃）を表している。尚、このＦＥＭ解析の解析条件については、高熱伝導体２２０の形状を除いて第１の実施の形態の場合と同様である。   Next, the heat radiation effect by providing the high thermal conductor 220 of the present embodiment will be described. FIG. 6 is an analysis result by FEM, and shows the relationship between the thickness of the high thermal conductor 220 and the surface temperature of the semiconductor element 13. In the figure, the horizontal axis represents the thickness (mm) of the bridging portion 223 having the smallest thickness in the high thermal conductor 220, and the vertical axis represents the surface temperature (° C.) of the semiconductor element 13. The analysis conditions for this FEM analysis are the same as those in the first embodiment except for the shape of the high thermal conductor 220.

同図によれば、架橋部２２３が厚くなるほど表面温度が低下することが分かる。尚、信頼性試験の一つであるパワーサイクル試験では、表面温度が５℃下がると接合部の寿命は２倍になると推定される（例えば富士時報 Vol.74, No.2, pp145-148, 2001）。   According to the figure, it can be seen that the surface temperature decreases as the bridging portion 223 becomes thicker. In the power cycle test, which is one of the reliability tests, it is estimated that the life of the joint is doubled when the surface temperature drops by 5 ° C (for example, Fuji Time Report Vol.74, No.2, pp145-148, 2001).

ここで、同図において、高熱伝導体２２０を設けない場合（架橋部２２３の厚みが０）と比較して、表面温度が５℃程度低減される厚さは０．２５ｍｍ程度ということになる。このため、架橋部２２３の厚さが０．２５ｍｍ以上あれば、パワー半導体モジュール２０１の寿命を大きく延ばすことができることが分かる。   Here, in the same figure, the thickness at which the surface temperature is reduced by about 5 ° C. is about 0.25 mm as compared with the case where the high thermal conductor 220 is not provided (the thickness of the bridging portion 223 is 0). For this reason, if the thickness of the bridge | crosslinking part 223 is 0.25 mm or more, it turns out that the lifetime of the power semiconductor module 201 can be extended significantly.

次に、図７は、高熱伝導体２２０による半導体素子１３の小型化の可能性を検討した解析結果である。すなわち、本実施の形態において、仮に従来のワイヤボンディング配線（アルミワイヤのみで高熱伝導体２２０がない場合）と同様の表面温度を許容した場合に、半導体素子１３をどの程度小型化できるかを検証したものである。   Next, FIG. 7 is an analysis result of examining the possibility of miniaturization of the semiconductor element 13 by the high thermal conductor 220. That is, in this embodiment, it is verified how small the semiconductor element 13 can be when the same surface temperature as that of the conventional wire bonding wiring (when only the aluminum wire is used and the high thermal conductor 220 is not allowed) is allowed. It is a thing.

ここでは、高熱伝導体２２０の半導体素子１３の表面電極の面積に占める接合面積の面積比を８０％、高熱伝導体２２０の本体２２１の厚さを１．０ｍｍとし、架橋部２２３の厚さを０．０５〜１．０ｍｍで変化させて解析を行った。   Here, the area ratio of the bonding area occupying the area of the surface electrode of the semiconductor element 13 of the high thermal conductor 220 is 80%, the thickness of the main body 221 of the high thermal conductor 220 is 1.0 mm, and the thickness of the bridging portion 223 is The analysis was performed while changing the thickness from 0.05 to 1.0 mm.

同図によれば、架橋部２２３の厚さを０．２５ｍｍ以上にすることで、従来の半導体素子の大きさの８０％以下にすることができ、つまり２０％以上の小型化が可能なことが分かる。さらに、架橋部２２３の厚さを０．５ｍｍとすると、３０％程度の小型化が可能となることが分かる。これは、本発明を利用することで、省スペースに対応したパワー半導体モジュールも提供可能であることを示している。   According to the figure, by setting the thickness of the bridging portion 223 to 0.25 mm or more, the size of the conventional semiconductor element can be reduced to 80% or less, that is, the size can be reduced by 20% or more. I understand. Furthermore, when the thickness of the bridging portion 223 is 0.5 mm, it can be seen that the size can be reduced by about 30%. This indicates that a power semiconductor module corresponding to space saving can be provided by using the present invention.

以上に説明したように、本実施の形態のパワー半導体モジュール２０１は、二股のリードフレームとして構成した高熱伝導体２２０により、半導体素子１３で発生した熱を絶縁基板１１側に伝導して放熱することができ、半導体素子１３の表面温度をより速やかに低減することができる。その結果、半導体素子１３と絶縁基板１１との接合部の熱応力による歪を低減することもでき、信頼性の高い接合が可能となる。   As described above, the power semiconductor module 201 of the present embodiment conducts heat generated in the semiconductor element 13 to the insulating substrate 11 side and dissipates it by the high thermal conductor 220 configured as a bifurcated lead frame. The surface temperature of the semiconductor element 13 can be reduced more quickly. As a result, distortion due to thermal stress at the joint between the semiconductor element 13 and the insulating substrate 11 can be reduced, and highly reliable joining is possible.

また、仮に半導体素子１３の温度低減を意図しない場合でも、その温度上昇の抑制効果を利用することで、半導体素子１３の小型化を可能にし、省スペース化を実現することができる。   Even if the temperature of the semiconductor element 13 is not intended to be reduced, the semiconductor element 13 can be reduced in size and space can be saved by utilizing the effect of suppressing the temperature rise.

以上、本発明の好適な実施の形態について説明したが、本発明はその特定の実施の形態に限定されるものではなく、本発明の精神の範囲内での変化変形が可能であることはいうまでもない。   The preferred embodiment of the present invention has been described above, but the present invention is not limited to the specific embodiment, and it can be changed and modified within the spirit of the present invention. Not too long.

例えば、上記実施の形態では、高熱伝導体２０，２２０として銅からなるものを示したが、低電気抵抗率で高熱伝導率を有するものとして、銀（Ａｇ）やアルミニウム（Ａｌ）等の他の金属からなるものや、このような金属を含有した導電性セラミック等からなるものでもよい。   For example, in the above embodiment, the high thermal conductors 20 and 220 are made of copper. However, the high thermal conductors 20 and 220 have a low electrical resistivity and a high thermal conductivity. It may be made of a metal or a conductive ceramic containing such a metal.

また、上記第２の実施の形態では、高熱伝導体２２０を二股のリードフレームとして構成した例を示したが、三股以上のリードフレームとして構成することもできる。   In the second embodiment, the example in which the high thermal conductor 220 is configured as a bifurcated lead frame has been described. However, the high thermal conductor 220 may be configured as a trifurcated lead frame.

発熱性の半導体素子を備えたパワー半導体モジュールであって、その半導体素子の温度上昇の抑制が要求されるものに対して適用することができる。   The present invention can be applied to a power semiconductor module including a heat-generating semiconductor element that requires suppression of a temperature rise of the semiconductor element.

第１の実施の形態にかかるパワー半導体モジュールの構造を表す断面図である。It is sectional drawing showing the structure of the power semiconductor module concerning 1st Embodiment. 第１の実施の形態の効果に関する解析結果を表す説明図である。It is explanatory drawing showing the analysis result regarding the effect of 1st Embodiment. 第１の実施の形態の効果に関する解析結果を表す説明図である。It is explanatory drawing showing the analysis result regarding the effect of 1st Embodiment. 第１の実施の形態の効果に関する解析結果を表す説明図である。It is explanatory drawing showing the analysis result regarding the effect of 1st Embodiment. 第２の実施の形態にかかるパワー半導体モジュールの構造を表す断面図である。It is sectional drawing showing the structure of the power semiconductor module concerning 2nd Embodiment. 第２の実施の形態の効果に関する解析結果を表す説明図である。It is explanatory drawing showing the analysis result regarding the effect of 2nd Embodiment. 第２の実施の形態の効果に関する解析結果を表す説明図である。It is explanatory drawing showing the analysis result regarding the effect of 2nd Embodiment. 従来のパワー半導体モジュールの構造を表す平面図及び断面図である。It is the top view and sectional drawing showing the structure of the conventional power semiconductor module.

符号の説明Explanation of symbols

１，２０１ パワー半導体モジュール
１１ 絶縁基板
１２ 回路パターン
１３ 半導体素子
１４ ヒートシンク
１５ ケース
２０，２２０ 高熱伝導体
３１，３２，３３，３４，３５ アルミワイヤ
５１，５２，５３，５４ 半田
２２１ 本体
２２２ リードフレーム部
２２３ 架橋部
1,201 Power semiconductor module 11 Insulating substrate 12 Circuit pattern 13 Semiconductor element 14 Heat sink 15 Case 20, 220 High thermal conductor 31, 32, 33, 34, 35 Aluminum wire 51, 52, 53, 54 Solder 221 Main body 222 Lead frame portion 223 Cross-linking part

Claims (7)

絶縁基板の表面に形成された回路パターンの所定位置に半導体素子をロー付接合して構成されるパワー半導体モジュールにおいて、
前記半導体素子の前記絶縁基板とは反対側に形成された表面電極に、前記半導体素子の熱伝導率以上の熱伝導率を有する高熱伝導体をロー付接合したことを特徴とするパワー半導体モジュール。 In a power semiconductor module configured by brazing a semiconductor element at a predetermined position of a circuit pattern formed on the surface of an insulating substrate,
A power semiconductor module, wherein a high thermal conductor having a thermal conductivity equal to or higher than that of the semiconductor element is brazed to a surface electrode formed on the opposite side of the semiconductor element from the insulating substrate. 前記高熱伝導体の熱伝導率が１００Ｗ／ｍ・Ｋ以上であることを特徴とする請求項１記載のパワー半導体モジュール。   The power semiconductor module according to claim 1, wherein the high thermal conductor has a thermal conductivity of 100 W / m · K or more. 前記高熱伝導体における前記半導体素子の表面電極との接合面積が、前記表面電極全体の面積の４０％以上となるように構成されたことを特徴とする請求項１又は請求項２に記載のパワー半導体モジュール。   3. The power according to claim 1, wherein a junction area of the high thermal conductor with a surface electrode of the semiconductor element is 40% or more of an area of the entire surface electrode. Semiconductor module. 前記高熱伝導体の厚みが、前記半導体素子の厚みと、前記半導体素子との間に介装されるロー材の厚みとを合計した厚み以上となるように構成されたことを特徴とする請求項１〜３のいずれかに記載のパワー半導体モジュール。   The thickness of the high thermal conductor is configured to be equal to or greater than a total thickness of a thickness of the semiconductor element and a thickness of a brazing material interposed between the semiconductor element. The power semiconductor module in any one of 1-3. 前記高熱伝導体の厚みが０．２５ｍｍ以上となるように構成されたことを特徴とする請求項１〜３のいずれかに記載のパワー半導体モジュール。   The power semiconductor module according to claim 1, wherein the high thermal conductor is configured to have a thickness of 0.25 mm or more. 前記高熱伝導体が、前記半導体素子と前記絶縁基板の前記回路パターンとを接続する電気伝導体を構成することを特徴とする請求項１〜５のいずれかに記載のパワー半導体モジュール。   The power semiconductor module according to claim 1, wherein the high thermal conductor constitutes an electrical conductor that connects the semiconductor element and the circuit pattern of the insulating substrate. 前記高熱伝導体がリードフレームとして構成されており、その厚みが最小となる部分の厚さが０．２５ｍｍ以上となるように構成されたことを特徴とする請求項６記載のパワー半導体モジュール。
The power semiconductor module according to claim 6, wherein the high thermal conductor is configured as a lead frame, and a thickness of a portion where the thickness is minimum is 0.25 mm or more.
JP2003347356A 2003-10-06 2003-10-06 Power semiconductor module Pending JP2005116702A (en)

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US7705443B2 (en) 2006-10-16 2010-04-27 Fuji Electric Device Technology Co., Ltd. Semiconductor device with lead frame including conductor plates arranged three-dimensionally
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US10002845B2 (en) 2014-10-17 2018-06-19 Fuji Electric Co., Ltd. Lead-free soldering method and soldered article
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