JP2009076675A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2009076675A
JP2009076675A JP2007244260A JP2007244260A JP2009076675A JP 2009076675 A JP2009076675 A JP 2009076675A JP 2007244260 A JP2007244260 A JP 2007244260A JP 2007244260 A JP2007244260 A JP 2007244260A JP 2009076675 A JP2009076675 A JP 2009076675A
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Japan
Prior art keywords
electrode
semiconductor chip
semiconductor device
leg
lead
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JP2007244260A
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Yoshinori Endo
佳紀 遠藤
Eitaro Miyake
英太郎 三宅
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Toshiba Corp
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Toshiba Corp
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Priority to JP2007244260A priority Critical patent/JP2009076675A/en
Publication of JP2009076675A publication Critical patent/JP2009076675A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device. <P>SOLUTION: The semiconductor device has a conductive base 11; a semiconductor chip 14 having a first electrode 12 formed on a first surface and a second electrode 13 formed on a second surface opposed to the first surface, the second surface side being mounted on the conductive base 11; and a plate-like connection conductor 17 such that one end portion 17a is opposed to the first electrode 12 of the semiconductor chip at an interval, a plurality of leg-shaped wiring leads 15a to 15d extending from the one end portion 17a and bent toward the first electrode 12 are connected to the first electrode 12, and the other end portion 17b is connected to an external electrode lead 16. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

近年、大規模集積回路（ＬＳＩ）等の動作電圧の低電圧化に伴い、動作電流が大電流化している。ＬＳＩに低電圧・大電流を供給する電源に用いられる半導体装置（スイッチング素子）では、半導体チップを外部に接続するための配線構造の低抵抗化が要求されている。   In recent years, as the operating voltage of a large scale integrated circuit (LSI) or the like is lowered, the operating current is increased. In a semiconductor device (switching element) used for a power supply that supplies a low voltage and a large current to an LSI, a reduction in resistance of a wiring structure for connecting a semiconductor chip to the outside is required.

低抵抗な配線構造として、ボンディングワイヤに代えて、ストラップ状の金属板などを半導体チップにハンダ接合したものがあるが、金属板と半導体チップの熱膨張係数の差に起因して、通電時のヒートサイクル耐量が低下し、信頼性が乏しくなるという問題がある。   As a low-resistance wiring structure, there is one in which a strap-like metal plate or the like is soldered to a semiconductor chip instead of a bonding wire, but due to the difference in thermal expansion coefficient between the metal plate and the semiconductor chip, There exists a problem that heat cycle tolerance falls and reliability becomes poor.

これに対して、通電時のヒートサイクルの信頼性の向上を図った半導体装置が知られている（例えば、特許文献１参照。）。   On the other hand, a semiconductor device that improves the reliability of the heat cycle during energization is known (see, for example, Patent Document 1).

特許文献１に開示された半導体装置は、絶縁基板と、絶縁基板上にマウントされた半導体チップと、半導体チップの少なくとも一方の主電極面に面接合され、通電、伝熱経路部材として低線膨張係数の導電板に高導電、高伝熱性の柱状ポスト電極を分散して貫通植設した構造の接続体とを具備し、接続体を介して半導体チップを配線部材ないし絶縁基板に接合している。
この柱状ポスト電極を分散して貫通植設した構造の接続体により、通電性と伝熱性を確保し、信頼性の向上を図っている。 The semiconductor device disclosed in Patent Document 1 is surface-bonded to an insulating substrate, a semiconductor chip mounted on the insulating substrate, and at least one main electrode surface of the semiconductor chip, and has low linear expansion as an energization and heat transfer path member. A high-conductivity, high-heat-conducting columnar post electrode dispersed on a coefficient conductive plate, and a connection body having a through-planting structure, and a semiconductor chip is bonded to a wiring member or an insulating substrate via the connection body .
The connection body having a structure in which the pillar-shaped post electrodes are dispersed and embedded is used to ensure electrical conductivity and heat transfer and to improve reliability.

然しながら、特許文献１に開示された半導体装置は、導電板の熱膨張係数が必ずしも半導体チップと等しくないので、熱膨張係数の差に起因する熱応力が生じ、信頼性に影響を及ぼす恐れが残留している問題がある。
また、接続体の構造が複雑で、半導体装置の組み立てが難しくなる問題がある。接続体に使用できる材料も限られるので、製造コストが高くなる問題がある。
特開２００７−４２７３８号公報 However, in the semiconductor device disclosed in Patent Document 1, since the thermal expansion coefficient of the conductive plate is not necessarily equal to that of the semiconductor chip, thermal stress due to the difference in thermal expansion coefficient is generated, which may affect reliability. There is a problem.
Further, there is a problem that the structure of the connection body is complicated and it is difficult to assemble the semiconductor device. Since the materials that can be used for the connection body are also limited, there is a problem that the manufacturing cost increases.
JP 2007-42738 A

本発明は、信頼性の高い半導体装置を提供する。   The present invention provides a highly reliable semiconductor device.

本発明の一態様の半導体装置は、導電性を有する基台と、第１の面に形成された第１電極及び前記第１の面と対向する第２の面に形成された第２電極を有し、前記第２の面側が前記基台上に載置された半導体チップと、一端部が前記半導体チップの第１電極と離間して対向するとともに、前記一端部から延伸し、前記第１電極側に折れ曲がった複数の脚状の配線リードが前記第１電極に接続され、他端部が外部電極リードに接続された板状の接続導体と、を具備することを特徴としている。   A semiconductor device according to one embodiment of the present invention includes a conductive base, a first electrode formed on a first surface, and a second electrode formed on a second surface facing the first surface. The second surface side of the semiconductor chip is placed on the base, and one end portion of the semiconductor chip is spaced from and opposed to the first electrode of the semiconductor chip, and extends from the one end portion. A plurality of leg-like wiring leads bent to the electrode side are connected to the first electrode, and a plate-like connection conductor having the other end connected to the external electrode lead is provided.

本発明によれば、信頼性の高い半導体装置が得られる。   According to the present invention, a highly reliable semiconductor device can be obtained.

以下、本発明の実施例について図面を参照しながら説明する。   Embodiments of the present invention will be described below with reference to the drawings.

本発明の実施例に係る半導体装置について、図１および図２を参照して説明する。図１は本発明の実施例に係る半導体装置を示す図で、図１（ａ）はその外囲器を省略した平面図、図１（ｂ）は図１（ａ）のＡ−Ａ線に沿って切断し、矢印方向に眺めた断面図、図２は半導体装置の要部を示す図で、図２（ａ）はその平面図、図２（ｂ）は図２（ａ）のＢ−Ｂ線に沿って切断し、矢印方向に眺めた断面図、図３（ｃ）はその斜視図である。   A semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention. FIG. 1 (a) is a plan view in which the envelope is omitted, and FIG. 1 (b) is a line AA in FIG. 1 (a). FIG. 2 is a diagram showing a main part of the semiconductor device, FIG. 2A is a plan view thereof, and FIG. 2B is a cross-sectional view taken along line B- in FIG. Sectional drawing cut | disconnected along the B line | wire and looked at the arrow direction, FIG.3 (c) is the perspective view.

図１に示すように、本実施例の半導体装置１０は、導電性を有する基台１１（以後導電性基台とも言う）と、第１の面に形成された第１電極１２及び第１の面と対向する第２の面に形成された第２電極１３を有し、第２の面側が導電性基台１１上に載置された半導体チップ１４と、一端部が半導体チップ１４の第１電極１２から高さＨだけ離間して対向するとともに、一端部から延伸し、第１電極１２側に折れ曲がった複数の脚状の配線リード１５ａ、１５ｂ、１５ｃ、１５ｄ（以後、単に配線リードとも言う）が第１電極１２に接続され、他端部がインナーリード（外部電極リード）１６に接続された板状の接続導体１７と、を具備している。   As shown in FIG. 1, a semiconductor device 10 of this embodiment includes a conductive base 11 (hereinafter also referred to as a conductive base), a first electrode 12 formed on a first surface, and a first electrode. A semiconductor chip 14 having a second electrode 13 formed on a second surface facing the surface, the second surface side being placed on the conductive base 11, and one end portion of the first chip of the semiconductor chip 14. A plurality of leg-like wiring leads 15a, 15b, 15c, 15d (hereinafter also simply referred to as wiring leads) that are spaced apart from the electrode 12 by a height H and that extend from one end and are bent toward the first electrode 12 side. ) Is connected to the first electrode 12, and the plate-like connection conductor 17 is connected to the inner lead (external electrode lead) 16 at the other end.

更に、インナーリード１６から延伸したアウターリード（外部電極リード）１８と、導電性基台１１の底面（半導体チップ１４が載置された面と反対の面）を露出して、導電性基台１１及び半導体チップ１４及びインナーリード１６及び接続導体１７を一体にモールドした樹脂１９とを具備している。   Furthermore, the outer lead (external electrode lead) 18 extended from the inner lead 16 and the bottom surface of the conductive base 11 (the surface opposite to the surface on which the semiconductor chip 14 is placed) are exposed to expose the conductive base 11. And a resin 19 in which the semiconductor chip 14, the inner lead 16, and the connection conductor 17 are integrally molded.

導電性基台１１は、例えばニッケルメッキされた銅または銅合金からなり、半導体チップ１４の発熱を外部に放散する放熱板および第２電極１３を外部に接続する電極端子として機能している。   The conductive base 11 is made of, for example, nickel-plated copper or copper alloy, and functions as a heat radiating plate for radiating the heat generated by the semiconductor chip 14 to the outside and an electrode terminal for connecting the second electrode 13 to the outside.

半導体チップ１４は、例えば表面（第１の面）にソース電極が形成され、裏面（第２の面）にドレイン電極が形成され、表面の一部にゲート電極（図示せず）が形成された縦型のパワーＭＯＳトランジスタである。   For example, the semiconductor chip 14 has a source electrode formed on the front surface (first surface), a drain electrode formed on the back surface (second surface), and a gate electrode (not shown) formed on a part of the surface. This is a vertical power MOS transistor.

ソース電極上に第１電極１２（接続パッド）が形成され、ドレイン電極上に第２電極１３（接続パッド）が形成されている。
第１電極１２および第２電極１３は、例えば厚さ２〜６μｍ程度のアルミニウム（Ａｌ）膜である。 A first electrode 12 (connection pad) is formed on the source electrode, and a second electrode 13 (connection pad) is formed on the drain electrode.
The first electrode 12 and the second electrode 13 are, for example, aluminum (Al) films having a thickness of about 2 to 6 μm.

半導体チップ１４は、導電性接合材（図示せず）、例えばハンダ、銀ペーストにより導電性基台１１に接合されている。   The semiconductor chip 14 is bonded to the conductive base 11 with a conductive bonding material (not shown), for example, solder or silver paste.

図２に示すように、接続導体１７は、例えばニッケルメッキされた銅または銅合金からなり、一端部１７ａの長手方向の一方の側面から脚状の配線リード１５ａ、１５ｂがそれぞれ延伸し、一方の側面と対向する他方の側面から脚状の配線リード１５ｃ、１５ｄがそれぞれ延伸している。   As shown in FIG. 2, the connection conductor 17 is made of, for example, nickel-plated copper or a copper alloy, and leg-like wiring leads 15a and 15b extend from one side surface in the longitudinal direction of the one end portion 17a. Leg-like wiring leads 15c and 15d extend from the other side surface facing the side surface.

脚状の配線リード１５ａ、１５ｂ、１５ｃ、１５ｄは、それぞれ第１電極１２側に末広がり状に折り曲げられている（山折り）。
更に、脚状の配線リード１５ａ、１５ｂ、１５ｃ、１５ｄの先端部は、それぞれ第１電極１２と対向するように折り曲げられている（谷折り）。
これにより、脚状の配線リード１５ａの接続位置と脚状の配線リード１５ｂの接続位置との間隔Ｗ０は、接続導体１７の幅Ｗ１より大きくなる。
接続導体１７の一端部１７ａの下面と脚状の配線リード１５ａ〜１５ｄの先端部の下面との距離が高さＨである。 The leg-shaped wiring leads 15a, 15b, 15c, and 15d are each bent in a divergent shape toward the first electrode 12 (mountain fold).
Further, the end portions of the leg-shaped wiring leads 15a, 15b, 15c, and 15d are bent so as to face the first electrode 12 (valley fold).
Thereby, the interval W0 between the connection position of the leg-shaped wiring lead 15a and the connection position of the leg-shaped wiring lead 15b is larger than the width W1 of the connection conductor 17.
The distance between the lower surface of the one end portion 17a of the connection conductor 17 and the lower surfaces of the tip portions of the leg-shaped wiring leads 15a to 15d is the height H.

接続導体１７の他端部１７ｂは、上方に折り曲げられ（谷折り）、その先端部はインナーリード１６と対向するように折り曲げられている（山折り）。   The other end portion 17b of the connecting conductor 17 is bent upward (valley fold), and the tip end portion is bent so as to face the inner lead 16 (mountain fold).

脚状の配線リード１５ａ、１５ｂ、１５ｃ、１５ｄは、導電性接合材（図示せず）、例えばハンダ、銀ペーストにより第１電極１２に接合されている。
脚状の配線リード１５ａ、１５ｂ、１５ｃ、１５ｄが第１電極１２に接合される位置は、半導体チップ１４の中心部と半導体チップ１４のエッジとの中間点近傍が好ましい。
これは、接合位置を半導体チップ１４上にできるだけ均一に配置し、電流が一部に集中しないようにするためである。
種々検討したところ、脚状の配線リードの接続位置の間隔は、おおよそＬ／４から３Ｌ／４の範囲にあれば、電流集中の抑制に効果的であった。 The leg-shaped wiring leads 15a, 15b, 15c, and 15d are bonded to the first electrode 12 by a conductive bonding material (not shown) such as solder or silver paste.
The position where the leg-shaped wiring leads 15 a, 15 b, 15 c, 15 d are joined to the first electrode 12 is preferably in the vicinity of an intermediate point between the center of the semiconductor chip 14 and the edge of the semiconductor chip 14.
This is because the bonding positions are arranged as uniformly as possible on the semiconductor chip 14 so that the current is not concentrated in part.
As a result of various studies, if the interval between the connection positions of the leg-shaped wiring leads is approximately in the range of L / 4 to 3L / 4, it is effective in suppressing current concentration.

ここでは、半導体チップ１４のサイズをＬとすると、脚状の配線リード１５ａの接続位置と脚状の配線リード１５ｃの接続位置との間隔Ｗ０をＬ／２程度としている。脚状の配線リード１５ｂと脚状の配線リード１５ｄについても同様である。
脚状の配線リード１５ａの接続位置と脚状の配線リード１５ｂの接続位置との間隔はＬ／２程度としている。脚状の配線リード１５ｃと脚状の配線リード１５ｄについても同様である。 Here, when the size of the semiconductor chip 14 is L, the interval W0 between the connection position of the leg-shaped wiring lead 15a and the connection position of the leg-shaped wiring lead 15c is set to about L / 2. The same applies to the leg-shaped wiring lead 15b and the leg-shaped wiring lead 15d.
The distance between the connection position of the leg-shaped wiring lead 15a and the connection position of the leg-shaped wiring lead 15b is about L / 2. The same applies to the leg-shaped wiring lead 15c and the leg-shaped wiring lead 15d.

図３は半導体装置１０の製造工程を順に示す断面図である。
始めに、図３（ａ）に示すように、導電性基台１１上に、ハンダ３０を介して半導体チップ１４を載置し、加熱して半導体チップ１４を導電性基台１１に接合する。 FIG. 3 is a cross-sectional view sequentially showing the manufacturing process of the semiconductor device 10.
First, as shown in FIG. 3A, the semiconductor chip 14 is placed on the conductive base 11 via the solder 30, and heated to join the semiconductor chip 14 to the conductive base 11.

次に、図３（ｂ）に示すように、予めプレスして折り曲げ加工された接続導体１７を用意し、接続導体１７の一端部１７ａの脚状の配線リード１５ａ〜１５ｄが半導体チップ１４の第１電極１２上に接合され、接続導体１７の他端部１７ｂがインナーリード１６上に接合されるように位置決めを行なう。   Next, as shown in FIG. 3B, a connection conductor 17 that is pre-pressed and bent is prepared, and the leg-shaped wiring leads 15 a to 15 d of the one end portion 17 a of the connection conductor 17 are the first ones of the semiconductor chip 14. Positioning is performed so that the other end 17 b of the connecting conductor 17 is bonded onto the inner lead 16.

次に、ハンダ３１、ハンダ３２を介して接続導体１７を載置し、加熱して接続導体１７の一端部１７ａの脚状の配線リード１５ａ〜１５ｄを第１電極１２に、接続導体１７の他端部１７ｂをインナーリード１６に接合する。   Next, the connection conductor 17 is placed via the solder 31 and the solder 32, and heated to convert the leg-like wiring leads 15a to 15d of the one end portion 17a of the connection conductor 17 to the first electrode 12 and the connection conductor 17 and the like. The end portion 17 b is joined to the inner lead 16.

次に、導電性基台１１の底面を露出して、導電性基台１１と、半導体チップ１４と、インナーリード１６と、接続導体１７とを、樹脂１９で一体にモールドすることにより、図１に示す半導体装置１０が得られる。   Next, the bottom surface of the conductive base 11 is exposed, and the conductive base 11, the semiconductor chip 14, the inner leads 16, and the connection conductors 17 are integrally molded with the resin 19, whereby FIG. The semiconductor device 10 shown in FIG.

図４は本実施例の効果を比較例と対比して示す図で、図４（ａ）が本実施例を示す図、図４（ｂ）が比較例を示す図である。ここで比較例とは、接続導体１７の一端部１７ａの全面が、半導体チップ１４の第１電極１２に接合されている場合を意味している。
図４（ｃ）は参考として、接続導体１７が半導体チップ１４の第１電極１２に接続されていない場合を示している。始めに、比較例について説明する。 FIG. 4 is a diagram showing the effect of the present embodiment in comparison with the comparative example. FIG. 4A is a diagram illustrating the present embodiment, and FIG. 4B is a diagram illustrating the comparative example. Here, the comparative example means a case where the entire surface of the one end portion 17 a of the connection conductor 17 is joined to the first electrode 12 of the semiconductor chip 14.
For reference, FIG. 4C shows a case where the connection conductor 17 is not connected to the first electrode 12 of the semiconductor chip 14. First, a comparative example will be described.

図４（ｃ）に示すように、半導体装置１０に温度サイクルを与える信頼性試験（ＴＣＴ：thermal Cyclic Test）を行うと、導電性基台１１と半導体チップ１４との熱膨張係数の差（銅：１７×１０−６／Ｋ、Ｓｉ：３．５×１０−６／Ｋ）に起因して、半導体装置１０に反りが生じる。 As shown in FIG. 4C, when a reliability test (TCT: Thermal Cyclic Test) for giving a temperature cycle to the semiconductor device 10 is performed, the difference in thermal expansion coefficient between the conductive base 11 and the semiconductor chip 14 (copper : 17 × due to 10 -6 /K,Si:3.5×10 -6 / K), warpage occurs in the semiconductor device 10.

ここで、反りは、半導体装置１０を高温状態から低温状態に降温したときの反りの変化量で示している。即ち、導電性基台１１の熱膨張係数が半導体チップ１４の熱膨張係数より大きいので、導電性基台１１が半導体チップ１４より多く収縮し、半導体チップ１４側に凸状の反りが発生する。   Here, the warpage is indicated by the amount of change in warpage when the semiconductor device 10 is cooled from a high temperature state to a low temperature state. That is, since the thermal expansion coefficient of the conductive base 11 is larger than the thermal expansion coefficient of the semiconductor chip 14, the conductive base 11 contracts more than the semiconductor chip 14, and a convex warp occurs on the semiconductor chip 14 side.

図４（ｂ）に示すように、比較例では、接続導体１７の一端部１７ａの全面が半導体チップ１４の第１電極１２に接合さているので、半導体チップ１４は接続導体１７に拘束されて、反りの発生は抑制される。   As shown in FIG. 4B, in the comparative example, since the entire surface of the one end portion 17a of the connection conductor 17 is joined to the first electrode 12 of the semiconductor chip 14, the semiconductor chip 14 is restrained by the connection conductor 17, The occurrence of warpage is suppressed.

その結果、導電性基台１１と半導体チップ１４との間のハンダ３０に応力が集中し、ハンダ３０の脆化が急速に進む現象が生じる。従って、ハンダ３０が剥離し、半導体装置１０の信頼性が著しく損なわれる問題が生じる。 As a result, stress concentrates on the solder 30 between the conductive base 11 and the semiconductor chip 14, and a phenomenon occurs in which the solder 30 is rapidly embrittled. Therefore, there arises a problem that the solder 30 is peeled off and the reliability of the semiconductor device 10 is significantly impaired.

一方、図４（ａ）に示すように、本実施例では、接続導体１７の一端部１７ａから延伸し、第１電極１２側へ折れ曲がった脚状の配線リード１５ａ〜１５ｄが半導体チップ１４の第１電極１２に接合されているので、半導体チップ１４は接続導体１７に殆ど拘束されず、反りの発生は抑制されない。反りは、図（ｃ）に近い状況になる。   On the other hand, as shown in FIG. 4A, in this embodiment, leg-shaped wiring leads 15a to 15d extending from one end portion 17a of the connection conductor 17 and bent toward the first electrode 12 side are the first ones of the semiconductor chip 14. Since it is bonded to one electrode 12, the semiconductor chip 14 is hardly restrained by the connection conductor 17, and the occurrence of warpage is not suppressed. The warping becomes a situation similar to FIG.

その結果、導電性基台１１と半導体チップ１４との間のハンダ３０に加わる応力が緩和され、ハンダ３０の脆化が抑えられる。従って、半導体装置１０の信頼性が損なわれることは皆無である。   As a result, the stress applied to the solder 30 between the conductive base 11 and the semiconductor chip 14 is relaxed, and the embrittlement of the solder 30 is suppressed. Therefore, the reliability of the semiconductor device 10 is never impaired.

以上説明したように、本実施例の半導体装置１０は、一端部１７ａから延伸し、第１電極１２側へ折れ曲がり、第１電極１２に接続された脚状の配線リード１５ａ〜１５ｄを有する接続導体１７を具備している。   As described above, the semiconductor device 10 of the present embodiment extends from the one end portion 17 a, bends toward the first electrode 12, and has the leg-shaped wiring leads 15 a to 15 d connected to the first electrode 12. 17.

その結果、接続導体１７は、半導体チップ１４の通電時のヒートサイクルによる反りの発生を拘束しないので、ハンダ３０に加わる応力が緩和される。従って、信頼性の高い半導体装置が得られる。   As a result, the connection conductor 17 does not restrain the occurrence of warp due to the heat cycle when the semiconductor chip 14 is energized, so that the stress applied to the solder 30 is relieved. Therefore, a highly reliable semiconductor device can be obtained.

ここでは、接続導体１７が４本の脚状の配線リード１５ａ〜１５ｄを有する場合について説明したが、脚状の配線リードの接合位置を半導体チップ１４上にできるだけ均一に配置できればよく、その数には特に制限は無い。   Here, the case where the connection conductor 17 has the four leg-shaped wiring leads 15a to 15d has been described. There are no particular restrictions.

例えば、図５は接続導体１７を示す図で、図５（ａ）は接続導体１７が３本の脚状の配線リード４０ａ〜４０ｃを有する場合を示す平面図、図５（ｂ）は接続導体１７が５本の脚状の配線リード４１ａ〜４１ｅを有する場合を示す平面図、図５（ｃ）は接続導体１７が６本の脚状の配線リード４２ａ〜４２ｆを有する場合を示す平面図である。   For example, FIG. 5 is a diagram showing the connection conductor 17, FIG. 5A is a plan view showing the case where the connection conductor 17 has three leg-like wiring leads 40 a to 40 c, and FIG. 5B is a connection conductor. FIG. 5C is a plan view showing a case where the connection conductor 17 has six leg-shaped wiring leads 42a to 42f. is there.

また、図５（ｄ）は接続導体１７の一端部１７ａの両側面から延伸した脚状の配線リード４３ａ〜４３ｄと、一端部１７ａの端面から延伸した脚状の配線リード４３ｅを有する場合を示す平面図である。半導体チップ１４が横長の形状の場合などに適している。   FIG. 5D shows a case where leg-shaped wiring leads 43a to 43d extending from both side surfaces of the one end portion 17a of the connecting conductor 17 and leg-shaped wiring leads 43e extending from the end surface of the one end portion 17a are shown. It is a top view. This is suitable when the semiconductor chip 14 has a horizontally long shape.

脚状の配線リード１５ａ〜１５ｄが、接続導体１７の一端部１７ａの両側面から延伸し、第１電極１２側に末広がり状に折り曲げられている場合について説明したが、折り曲げ形状については特に制限はない。   The case where the leg-shaped wiring leads 15a to 15d are extended from both side surfaces of the one end portion 17a of the connecting conductor 17 and bent toward the first electrode 12 side has been described. However, the bent shape is not particularly limited. Absent.

例えば、図６は接続導体１７を示す図で、図６（ａ）は第１電極１２側にほぼ垂直に折り曲げられた脚状の配線リード５０ａ〜５０ｄを有する接続導体１７を示す平面図、図６（ｂ）は図６（ａ）のＣ−Ｃ線に沿って切断し、矢印方向に眺めた断面図である。   For example, FIG. 6 is a diagram showing the connection conductor 17, and FIG. 6A is a plan view showing the connection conductor 17 having leg-like wiring leads 50 a to 50 d bent almost perpendicularly to the first electrode 12 side. 6 (b) is a cross-sectional view taken along the line CC of FIG. 6 (a) and viewed in the direction of the arrow.

図６（ｃ）は第１電極１２側に逆末広がり状に折り曲げられた脚状の配線リード５１ａ〜５１ｄを有する接続導体１７を示す平面図、図６（ｄ）は図６（ｃ）のＤ−Ｄ線に沿って切断し、矢印方向に眺めた断面図である。   FIG. 6C is a plan view showing the connection conductor 17 having leg-like wiring leads 51a to 51d bent in an inversely widening manner toward the first electrode 12, and FIG. 6D is a view of D in FIG. 6C. It is sectional drawing cut | disconnected along the -D line and looked at the arrow direction.

図６に示すように、間隔Ｗ０が一定なので、末広がり状から垂直、更に逆末広がり状に折り曲げると、接続導体１７の幅もＷ１からＷ２、更にＷ３と広くする（Ｗ１＜Ｗ２＜Ｗ３）ことができ、より低抵抗の接続導体１７が得られる利点がある。   As shown in FIG. 6, since the interval W0 is constant, the width of the connecting conductor 17 can be widened from W1 to W2 and further to W3 (W1 <W2 <W3) when bent from a divergent shape to a vertical direction and further to a reverse divergent shape. This is advantageous in that the connection conductor 17 having a lower resistance can be obtained.

半導体チップ１４がブロック状の導電性基台１１（半導体チップを載置する部位の厚さとリード端子の厚さが異なる、所謂異形フレーム）に接合されている場合について説明したが、平板状のリードフレーム（以後、単にリードフレームという）を用いても構わない。   Although the case where the semiconductor chip 14 is bonded to the block-shaped conductive base 11 (so-called irregular frame in which the thickness of the portion on which the semiconductor chip is placed differs from the thickness of the lead terminal) has been described, the flat lead A frame (hereinafter simply referred to as a lead frame) may be used.

図７はリードフレームを用いた半導体装置を示す図で、図７（ａ）はその外囲器の一部が切り欠きされた平面図、図７（ｂ）は図７（ａ）のＥ−Ｅ線に沿って切断し、矢印方向に眺めた断面図である。   7A and 7B are diagrams showing a semiconductor device using a lead frame. FIG. 7A is a plan view in which a part of the envelope is cut out, and FIG. 7B is an E-line in FIG. 7A. It is sectional drawing cut | disconnected along the E line and looked at the arrow direction.

図７示すように、半導体装置６０は、例えば半導体チップ１４の表面に複数の電極、例えばゲート電極Ｇとソース電極Ｓ、および裏面に単一の電極、例えばドレイン電極Ｄ（図示せず）を有するｎチャンネル縦型絶縁ゲート電界効果トランジスタ、例えばパワーＭＯＳトランジスタを８ピンのスモールアウトラインパッケージ（ＳＯＰ：Small Outline Package）に収納した場合の例である。   As shown in FIG. 7, the semiconductor device 60 has, for example, a plurality of electrodes such as a gate electrode G and a source electrode S on the surface of the semiconductor chip 14, and a single electrode such as a drain electrode D (not shown) on the back surface. This is an example in which an n-channel vertical insulated gate field effect transistor, for example, a power MOS transistor is housed in an 8-pin small outline package (SOP).

半導体装置６０の半導体チップ１４は、ニッケルまたは半田メッキされた銅製のリードフレーム６１上にドレイン電極Ｄを下向きにして載置されている。
ドレイン電極Ｄは、リードフレーム６１のマウントベッド６１ａに導電性接着剤で固着され、複数のリード端子６２に接続されている。 The semiconductor chip 14 of the semiconductor device 60 is placed on a lead frame 61 made of nickel or solder plated copper with the drain electrode D facing downward.
The drain electrode D is fixed to the mount bed 61 a of the lead frame 61 with a conductive adhesive and connected to the plurality of lead terminals 62.

接続導体１７の一端部１７ａの脚状の配線リード１５ａ〜１５ｄは、ソース電極Ｓに接続されている。
接続導体１７の他端部１７ｂは、下方に折り曲げられている（山折り）。その先端部はリード端子６３と対向するように折り曲げられ（谷折り）、リード端子６３に超音波接合されている。ゲート電極Ｇは、ワイヤ６４を介してリード端子６５に接続されている。 Leg-shaped wiring leads 15 a to 15 d at one end 17 a of the connection conductor 17 are connected to the source electrode S.
The other end 17b of the connecting conductor 17 is bent downward (mountain fold). The distal end portion is bent so as to face the lead terminal 63 (valley fold), and is ultrasonically bonded to the lead terminal 63. The gate electrode G is connected to the lead terminal 65 through the wire 64.

そして、これら全体が樹脂６６でモールドされて、ＳＯＰ型の半導体装置６０を構成している。   These are entirely molded with a resin 66 to constitute an SOP type semiconductor device 60.

本発明の実施例に係る半導体装置を示す図で、図１（ａ）はその外囲器を省略した平面図、図１（ｂ）は図１（ａ）のＡ−Ａ線に沿って切断し、矢印方向に眺めた断面図。1A and 1B are diagrams illustrating a semiconductor device according to an embodiment of the present invention, in which FIG. 1A is a plan view in which the envelope is omitted, and FIG. 1B is cut along line AA in FIG. Sectional view seen in the direction of the arrow. 本発明の実施例に係る半導体装置の要部を示す図で、図２（ａ）はその平面図、図２（ｂ）は図２（ａ）のＢ−Ｂ線に沿って切断し、矢印方向に眺めた断面図、図２（ｃ）はその斜視図。FIG. 2A is a plan view of a semiconductor device according to an embodiment of the present invention, FIG. 2A is a plan view thereof, and FIG. 2B is a cross-sectional view taken along line BB in FIG. Sectional view seen in the direction, FIG. 本発明の実施例に係る半導体装置の製造工程を順に示す断面図。Sectional drawing which shows the manufacturing process of the semiconductor device based on the Example of this invention in order. 本発明の実施例に係る半導体装置の効果を比較例と対比して示す図で、図４（ａ）が本実施例を示す断面図、図４（ｂ）が比較例を示す断面図。FIG. 4A is a cross-sectional view illustrating the effect of the semiconductor device according to the embodiment of the present invention in comparison with the comparative example, FIG. 4A is a cross-sectional view illustrating the present embodiment, and FIG. 4B is a cross-sectional view illustrating the comparative example. 本発明の実施例に係る半導体装置の別の接続導体を示す図。The figure which shows another connection conductor of the semiconductor device which concerns on the Example of this invention. 本発明の実施例に係る半導体装置の更に別の接続導体を示す図。The figure which shows another connection conductor of the semiconductor device which concerns on the Example of this invention. 本発明の実施例に係る別の半導体装置を示す図で、図７（ａ）はその外囲器の一部が切り欠きされた平面図、図７（ｂ）は図７（ａ）のＥ−Ｅ線に沿って切断し、矢印方向に眺めた断面図。7A and 7B are diagrams showing another semiconductor device according to the embodiment of the present invention, in which FIG. 7A is a plan view in which a part of the envelope is cut away, and FIG. 7B is an E of FIG. 7A. Sectional drawing cut | disconnected along E line and looked at the arrow direction.

符号の説明Explanation of symbols

１０、６０ 半導体装置
１１ 導電性基台
１２ 第１電極
１３ 第２電極
１４ 半導体チップ
１５ａ〜１５ｄ、４０ａ〜４０ｃ、４１ａ〜４１ｅ、４２ａ〜４２ｆ、４３ａ〜４３ｅ、５０ａ〜５０ｄ、５１ａ〜５１ｄ 脚状の配線リード
１６ インナーリード
１７ 接続導体
１７ａ 接続導体の一端部
１７ｂ 接続導体の他端部
１８ アウターリード
１９、６６ 樹脂
３０、３１、３２ ハンダ
６１ リードフレーム
６１ａ マウントベッド
６２、６３、６５ リード端子
６４ ワイヤ 10, 60 Semiconductor device 11 Conductive base 12 First electrode 13 Second electrode 14 Semiconductor chips 15a-15d, 40a-40c, 41a-41e, 42a-42f, 43a-43e, 50a-50d, 51a-51d Leg shape Wiring lead 16 Inner lead 17 Connecting conductor 17a Connecting conductor one end 17b Connecting conductor other end 18 Outer lead 19, 66 Resin 30, 31, 32 Solder 61 Lead frame 61a Mount bed 62, 63, 65 Lead terminal 64 Wire

Claims (5)

導電性を有する基台と、
第１の面に形成された第１電極及び前記第１の面と対向する第２の面に形成された第２電極を有し、前記第２の面側が前記基台上に載置された半導体チップと、
一端部が前記半導体チップの第１電極と離間して対向するとともに、前記一端部から延伸し、前記第１電極側に折れ曲がった複数の脚状の配線リードが前記第１電極に接続され、他端部が外部電極リードに接続された板状の接続導体と、
を具備することを特徴とする半導体装置。 A conductive base;
A first electrode formed on a first surface and a second electrode formed on a second surface opposite to the first surface, wherein the second surface side is placed on the base; A semiconductor chip;
A plurality of leg-shaped wiring leads extending from the one end and bent toward the first electrode are connected to the first electrode while one end is opposed to the first electrode of the semiconductor chip. A plate-like connection conductor whose end is connected to the external electrode lead; and
A semiconductor device comprising: 前記基台はリード端子及びマウントベッドを有するリードフレームであり、前記半導体チップが前記マウントベッド上に載置され、前記接続導体の他端部が前記リード端子に接続されていることを特徴とする請求項１に記載の半導体装置。   The base is a lead frame having a lead terminal and a mount bed, the semiconductor chip is placed on the mount bed, and the other end of the connection conductor is connected to the lead terminal. The semiconductor device according to claim 1. 前記脚状の配線リードが、前記接続導体の前記一端部の側面から延伸し、前記第１電極側に折り曲げられていることを特徴とする請求項１または請求項２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the leg-shaped wiring lead extends from a side surface of the one end portion of the connection conductor and is bent toward the first electrode. 前記脚状の配線リードの先端部が、前記第１電極と対向するように更に折り曲げられていることを特徴とする請求項１乃至請求項３のいずれか１項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein a distal end portion of the leg-shaped wiring lead is further bent so as to face the first electrode. 5. 前記脚状の配線リードが前記第１電極に接続される位置は、前記半導体チップの中心部と前記半導体チップのエッジとの中間点近傍にあることを特徴とする請求項１または請求項２に記載の半導体装置。   The position where the leg-shaped wiring lead is connected to the first electrode is in the vicinity of an intermediate point between the center of the semiconductor chip and the edge of the semiconductor chip. The semiconductor device described.
JP2007244260A 2007-09-20 2007-09-20 Semiconductor device Pending JP2009076675A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012253187A (en) * 2011-06-02 2012-12-20 Toyota Motor Corp Semiconductor device
JP2014175364A (en) * 2013-03-06 2014-09-22 Shindengen Electric Mfg Co Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012253187A (en) * 2011-06-02 2012-12-20 Toyota Motor Corp Semiconductor device
JP2014175364A (en) * 2013-03-06 2014-09-22 Shindengen Electric Mfg Co Ltd Semiconductor device

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