JP2003218306A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device at a low cost wherein electric insulation is superior between a main electrode and a control electrode and between copper wiring connected with the main electrode and the control electrode and withstand voltage structure, and to provide a manufacturing method of the semiconductor device. <P>SOLUTION: An insulating sheet 6 wherein apertures 7, 8 are formed in parts positioned above an emitter electrode 4 and a gate electrode 5 is stuck on an IGBT chip 1. Copper wirings 11, 12 formed on a surface of a wiring board 13 are fixed to the emitter electrode 4 and the gate electrode 5 by using solder 9 and solder 10 as sticking agents, on the emitter electrode 4 and the gate electrode 5 positioned in the apertures 7, 8 of the insulating sheet 6. Lateral spreads of the solder 9 and the solder 10 are prevented by the insulating sheet 6, insulation between the emitter electrode 4 and the gate electrode 5 is ensured, and insulation between the copper wirings 11, 12 and a guard ring 3 is ensured. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a module structure such as an IGBT (Insulated Gate Bipolar Transistor) module and a manufacturing method thereof.

[0002]

2. Description of the Related Art As shown in FIG. 8, power semiconductor devices (semiconductor devices) such as IGBT modules are usually
On the copper wiring 65 formed on the wiring board 66, I shown in FIG.
A back surface electrode of a semiconductor chip 51 (hereinafter referred to as a chip) such as a GBT chip is entirely soldered and fixed, and a main electrode 54 and a gate electrode 55 which are front surface electrodes of the chip 51 are
By bonding one or a plurality of aluminum wires 73 and 74, they are respectively connected to the external lead terminals which are the emitter terminal 68 and the gate terminal 69. Usually, a plurality of chips 51 are stored in the package.

[0003]

The aluminum wire bonding described above has the following problems. 1) As the chip capacity increases, the number of wires required to secure the necessary current capacity increases, and the bonding man-hours and the equipment investment for the wire bonder increase, resulting in high cost. 2) It is structurally difficult to sufficiently secure the cross-sectional area of the wire 73 and the copper wiring pattern on the wiring board, and as a result, the heat generation of the element and the response characteristic may be deteriorated due to the increase of the wiring resistance and the wiring inductance. There is. 3) Even if an attempt is made to increase the diameter of the wires 73 used to reduce the number of the wires 73, the bonding conditions for bonding the thick wires become strict and the chips may be damaged.

In order to solve these problems, instead of wire bonding, a structure in which copper lead frames 68 and 69 are directly bonded to the main electrode 54 and control electrode 55 of the chip 51 as shown in FIG. Is disclosed. However, when the lead frames 68 and 69 are connected to the main electrodes of the chips as shown in FIG. 9, the lead frames 68 and 69 are circled 74 in order to relieve the stress generated in the chips 51 by the lead frames 68 and 69. However, the manufacturing cost is high because the structure must be complicated as shown in FIG. The lead frame 6 has this complicated structure.
This is for giving flexibility to 8 and 69.

Further, when the copper wiring formed on the wiring circuit board is directly joined to the main electrodes and control electrodes on the chip surface by soldering or the like, the solder spreads in the lateral direction and the distance between the chip surface and the wiring circuit board is increased. By making it extremely short, the electrical insulation between the main electrode and the control electrode formed on the chip surface, the electrical insulation between the copper wiring connecting to the main electrode and the control electrode, and the withstand voltage structure (guard ring, etc.) Is reduced.

An object of the present invention is to solve the above-mentioned problems, and at a low cost, electrically insulate between a main electrode and a control electrode, a main electrode, a copper wiring connected to the control electrode, and a withstand voltage structure. An object of the present invention is to provide a semiconductor device having excellent properties and a manufacturing method thereof.

[0007]

To achieve the above object, a main electrode and a control electrode formed on the same plane of a semiconductor chip, a breakdown voltage structure formed on the semiconductor chip, and the main electrode are connected. In a semiconductor device having a module structure including a first outer lead-out conductor and a second outer lead-out conductor connected to the control electrode, an insulating film formed on the entire surface of a semiconductor chip and having openings for main electrodes and control electrodes. Formed on the insulating film at the opening of the insulating film, fixed to the main electrode via a fixing material, fixed to the first outer lead conductor formed on the insulating film, and fixed to the control electrode And a second outer lead conductor that is formed.

The insulating film may be an organic insulating film. The thickness of the insulating film may be 50 to 100 μm. Further, the first and second outer lead-out conductors may be wires of a lead frame or a printed circuit board. The fixing material is preferably solder or solder paste.

Further, a main electrode and a control electrode formed on the same plane of the semiconductor chip, a breakdown voltage structure formed on the semiconductor chip, and a first outer lead conductor connected to the main electrode.
In a method of manufacturing a semiconductor device having a module structure including a second outer lead conductor connected to the control electrode, a step of forming a main electrode and a control electrode on a semiconductor wafer on which a breakdown voltage structure and an active region are formed; A step of forming an insulating film having openings for main electrodes and control electrodes on the entire surface of the wafer; a step of cutting the semiconductor wafer into chips; and a main electrode formed on the chipped semiconductor chips. The control electrode and the second outer lead conductor are fixed to the first outer lead conductor and the second outer lead conductor respectively with a fixing material.

[0010]

1 to 3 show a first embodiment of the present invention.
FIG. 1 is a plan view of a semiconductor chip, FIG. 2 is a plan view of an insulating sheet, and FIG. 3 is a cross-sectional view of essential parts of the semiconductor device. 1 to 3, I shown in FIG.
On the GBT chip 1, the insulating sheet 6 shown in FIG. 2 having the openings 7 and 8 at the positions located on the emitter electrode 4 and the gate electrode 5 is attached. The opening 7 of this insulating sheet,
The solder 9, 10 (solder paste or the like), which is a fixing material, is attached to the emitter electrode 4 and the gate electrode 5 located at 8 a little higher than the thickness of the insulating sheet, and the wiring board 13
Copper wirings 11 and 12 (corresponding to the first and second outer lead conductors) formed on the surface of the substrate, the emitter electrode 4, and the gate electrode 5
And are fixed via solder 9 and 10. The back surface of the IGBT chip is fixed to the copper wiring 15 formed on the front surface of the wiring board 16 via the solder 17. The wiring board 16 and the copper base 21 (cooling conductor) are fixed to each other with solder 17. Copper wiring 1
1, 12, 15 and emitter terminal 18, gate terminal 19,
The collector terminal 18 is fixed, and the plastic case 22 is fixed to the copper base 21. The wiring board 13 and the copper wiring 1
1 and 12 are wired circuit boards (Direct Bondin)
g Copper substrate, etc.).

The main purpose of the insulating gate 6 is to ensure electrical insulation between the copper wirings 11 and 12 which are external lead-out members and the guard ring 3 provided on the outer peripheral portion of the IGBT chip. It must be able to withstand the electric field applied during that period without long-term deterioration. Normally, the voltage during this period is several tens of V to several kV, and thus the insulation thickness may be selected according to the rating of the device. When a polyimide resin film is used as the organic insulating film, the withstand voltage is usually 100 kV /
The thickness may be about 50 mm, such as about mm.

However, the actual thickness of the insulating film should be determined in consideration of the availability and processability of the film, and in practice it is preferably about 50 to 100 μm. 1
Films having a thickness of more than 00 μm have poor processability as a film material, resulting in high cost, and it is difficult to obtain a film thickness of more than 100 μm by a coating method. Also, 50μ
If it is less than m, the reliability of electrical insulation may not be sufficiently obtained.

Therefore, the material of the insulating sheet 6 is 50
A polyimide resin sheet having a thickness of μm to 100 μm is desirable, but the thickness is not limited to this. In addition, the resin material is not limited to polyimide resin, but organic insulating materials such as polyethylene terephthalate resin, polyetheretherketone resin, polyetherimide resin, polysulfone resin, and other engineering plastic resin sheets, depending on the required heat resistance temperature and dielectric strength. Can be used.

As a method of sticking, it is desirable to use a heat-fusible adhesive in the process or to utilize the heat-fusible property of the sheet itself, but a thermosetting adhesive may be used. The insulating sheet 6 ensures the insulation between the main electrode, which is an emitter electrode, and the control electrode, which is a gate electrode. Further, since the insulating sheet 6 has a structure which is adhered immediately above the guard ring portion, the copper wiring 11 fixed to the emitter electrode 4 and the guard ring 3 having a withstand voltage structure are
It is insulated by this insulating sheet 6.

As described above, by sticking the insulating sheet 6 having the openings 7 and 8 on the surface of the IGBT chip 1, it is possible to prevent the solders 9 and 10 from spreading in the lateral direction, and the emitter electrode 4 can be prevented. The electrical insulation between a certain main electrode and the control electrode which is the gate electrode 5 can be reliably ensured. Further, the insulating sheet 6 ensures the electrical insulation between the copper wirings 11 and 12 respectively connected to the emitter electrode 4 and the gate electrode 5 and the guard ring 3 which is a withstand voltage structure.

The dimensions of the openings 7 and 8 are for joining the main electrode and the control electrode to the external lead conductors respectively, so that the dimensions of the openings are equivalent to the areas of the main electrode and the control electrode. Good. Practically, it is preferable that the opening area is 30 to 100% of the area of the main electrode and the control electrode. In the case where the main electrode is divided into a plurality of cells, the opening for the main electrode may be a plurality of openings corresponding to each cell.

Further, copper wirings 11 and 1 which are externally derived conductors.
The structure of No. 2 can be made into a simple flat plate shape (conventionally, it has a complicated bending structure as shown by a circle 72 in FIG. 9). In this way, the copper wirings 11 and 1 which are externally derived conductors
The manufacturing cost can be reduced by simplifying the shape of 2. FIG. 4 is a cross-sectional view of essential parts of a semiconductor device according to the second embodiment of the present invention. The difference from the first embodiment is that a thick insulating layer 23 is formed at other locations except for the emitter electrode 4 and the gate electrode 5, instead of a structure in which an insulating material such as the insulating sheet 6 is attached. Is. The insulating layer 23 may be made of any curable resin (organic insulating material) capable of forming a pattern on the surface of the IGBT chip 1, but is preferably a heat-resistant heat-resistant resin such as epoxy resin, polyimide resin, bismaleimide resin or the like. A curable resin is good.

The pattern can be formed by screen printing, spin coating, vacuum printing or the like. If a plurality of openings 7 are formed for one emitter electrode 4 instead of a single opening 7 of the emitter electrode 4, stress such as thermal stress applied to the joint with the solder 9 is relaxed. can do.

When a plurality of openings are formed by using a liquid insulating material for forming the insulating layer 23,
The degree of freedom of the plane pattern of the opening is improved. Of course, a plurality of openings 8 of the gate electrode 5 may be formed. According to the present invention, similar to the first embodiment, at a low cost, the insulation between the emitter electrode 4 and the gate electrode 5 and the copper wirings 11 and 12 connected to the emitter electrode 4 and the gate electrode 5 and the guard ring 3 are provided. The insulation of can be surely secured.

FIG. 5 shows a method of manufacturing a semiconductor device according to a third embodiment of the present invention, and FIGS. 5A to 5D are sectional views showing steps in the order of steps. This is a method of manufacturing the semiconductor device of FIG. An insulating layer 23 with the emitter electrode and the gate electrode exposed is formed on the surface of the wafer 100 on the emitter electrode side in which a large number of IGBT units having p-type diffusion regions and n-type diffusion regions are integrated (FIG. 8A).

Next, the wafer 100 is cut along the cutting line 24 to form an IGBT chip (FIG. 2 (b)). Next, the openings 9 are filled with solder 9 and 10 (FIG. 7C). Next, the emitter electrodes and gate electrodes (not shown) and the copper wirings 11 and 12 formed on the wiring board 13 are fixed to each other with solder 9 and 10. On the other hand, IGBT chip 1
The back surface of the above is also fixed to the copper wiring 15 formed on the wiring board 16 via solder (not shown) ((d) of the same figure).

Next, as shown in FIG. 4, the copper base 21, the emitter terminal 18, the gate terminal 19 and the collector terminal 20 are fixed, and the plastic case 22 is covered to complete the semiconductor device. In this way, by collectively forming the insulating layer 23 in the wafer state before cutting the chips, the cost of forming the insulating layer 23 can be significantly reduced. The insulating layer 23 is formed by the method described with reference to FIG. Further, instead of the insulating layer 23, there is also a method of sticking the insulating sheet 13 shown in FIG.

FIG. 6 is a cross-sectional view of essential parts of a semiconductor device according to the fourth embodiment of the present invention. The difference from the above-mentioned embodiment is that a conductor such as a lead frame is used instead of the copper wiring formed on the wiring board. FIG. 6 is a sectional view of an essential part corresponding to FIG. In this case, since the lead frames 24, 25 (corresponding to the first and second outer lead conductors) are arranged on the insulating sheet 6, the lead frames 24, 25 can be made extremely thin. Therefore, a flat lead frame may be used instead of the curved and complicated structure shown in FIG.
Cost reduction can be achieved. In addition, the insulation between the main electrode and the control electrode and the insulation between the main electrode and the control electrode can be ensured.

[0024]

According to the present invention, the main electrode and the control electrode are electrically connected to the external lead conductor through the opening of the insulating film formed on the semiconductor chip, and the external lead conductor is placed on the insulating film. In this case, the insulation between the main electrode and the control electrode and the insulation between the main electrode and the external lead conductor connected to the control electrode and the withstand voltage structure can be easily ensured.

Further, since the thin outer lead-out conductor is formed on the insulating film, the shape of the outer lead-out conductor can be simplified and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor chip of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view of an insulating sheet of the semiconductor device of the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of essential parts of a semiconductor device according to a first embodiment of the present invention

FIG. 4 is a cross-sectional view of essential parts of a semiconductor device according to a second embodiment of the present invention.

5A to 5D are sectional views showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention, in which FIGS.

FIG. 6 is a cross-sectional view of essential parts of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 7 is a plan view of the IGBT chip.

FIG. 8 is a sectional view of a main part of a conventional semiconductor device.

FIG. 9 is a sectional view of an essential part of another conventional semiconductor device.

[Explanation of symbols]

1 IGBT chip 2 Active area 3 guard ring 4 Emitter electrode 5 Gate electrode 6 Insulation sheet 7, 8 openings 9, 10, 14, 17 solder 11, 12, 15 Copper wiring 13, 16 wiring board 18 Emitter terminal 19 Gate terminal 20 collector terminal 21 copper base 22 plastic cases 23 Insulation layer 24, 25 lead frame

Claims (6)

[Claims] 1. A main electrode and a control electrode formed on the same plane of a semiconductor chip, a breakdown voltage structure formed on the semiconductor chip, a first external lead conductor connected to the main electrode, and a control electrode. In a semiconductor device having a module structure including a second external lead conductor, an insulating film formed on the entire surface of a semiconductor chip and having a main electrode and a control electrode opened, and a fixing material at the opening of the insulating film. Via a first outer lead conductor fixed to the main electrode and formed on the insulating film, and a second outer lead conductor fixed to the control electrode and formed on the insulating film. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein the insulating film is an organic insulating film. 3. The insulating film has a thickness of 50 μm to 100 μm.
The semiconductor device according to claim 1, wherein 4. The semiconductor device according to claim 1, wherein the first and second outer lead conductors are wires of a lead frame or a printed circuit board. 5. The semiconductor device according to claim 1, wherein the fixing material is solder or solder paste. 6. A main electrode and a control electrode formed on the same plane of a semiconductor chip, a breakdown voltage structure formed on the semiconductor chip, a first outer lead conductor connected to the main electrode, and a control electrode. In a method of manufacturing a semiconductor device having a module structure including a second outer lead conductor, a step of forming a main electrode and a control electrode on a semiconductor wafer on which a breakdown voltage structure and an active region are formed; A step of forming an insulating film having openings at the electrodes and the control electrodes; a step of cutting the semiconductor wafer into chips; a main electrode and a control electrode formed on the chipped semiconductor chips; 1. A method of manufacturing a semiconductor device, comprising the steps of: fixing each of the first outer lead conductor and the second outer lead conductor with a fixing material.