JP2009152364A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which eliminates breakage withstand is ensured, breakage of an interlayer dielectric and an electrode associated with bonding, while ensuring bonding strength, and improves electrical characteristics, and also to provide a method of manufacturing such semiconductor device. <P>SOLUTION: A semiconductor element 1 mounted on the semiconductor device includes an interlayer dielectric 12 having an extending section 121, a connecting section 122 and an opening 123. The extending section 121 covers a gate electrode 116 and extends in a second direction. The connecting section 122 connects, at fixed intervals in the second direction, the extending sections 121 which are adjacent to each other in a firsts direction. The opening 123 has its opening shape defined by the extending section 121 and the connecting section 122 and exposes the main surface of a base region 112 and the main surface of an emitter region 113. A second width dimension 122W in the second direction below the connecting section 122 is set larger than a first width dimension 121W in the first direction in the emitter region 113 below the extending section 121 of the interlayer dielectric 12. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which external wiring is connected to an electrode of a semiconductor element and a manufacturing method thereof.

  Semiconductor elements (semiconductor chips) such as IGBTs (insulated gate bipolar transistors) and power MOSFETs (metal oxide semiconductor field effect transistors) are incorporated in semiconductor devices. This type of semiconductor element is a switching device that can control a large current at high speed.

  A semiconductor element such as an IGBT includes a collector region, a base region, an emitter region, a gate insulating film, and a gate electrode. The collector region is formed by epitaxial growth on one main surface of the substrate or diffusion or the like on one main surface portion of the substrate. The base region is formed on the other main surface portion of the substrate. The emitter region is formed on the surface portion of the base region. The gate insulating film is formed at least on the surface of the base region, and the gate electrode is formed on the gate insulating film.

  By forming the gate electrode in a stripe shape, a high breakdown voltage and a small gate capacitance can be achieved. In an IGBT employing this structure, the gate electrode extends on the main surface of the substrate in the gate length direction, and a plurality of gate electrodes are arranged at regular intervals in the gate width direction. A part of the surface of the emitter region and the base region is exposed in a stripe shape in the gate length direction so as to sandwich the electrode. An emitter electrode (emitter wiring) is electrically connected to the emitter region and the base region where the surface is exposed. The emitter electrode is formed on an interlayer insulating film sandwiched between the gate electrode, and the interlayer insulating film covers the gate electrode and corresponds to a region where the above-mentioned emitter region and base region are partially exposed (corresponding to Striped openings (contact openings) in the gate length direction. That is, in the cross-section cut in the gate width direction, the planar shape of the convex interlayer insulating film having a gap between adjacent interlayer insulating films due to the above-described opening is a stripe shape similar to the planar shape of the gate electrode. An IGBT adopting such a stripe structure can increase the contact area between the emitter region and the base region and the emitter electrode and increase the current capacity, thereby reducing the occurrence of electric field concentration and increasing the current. In addition, a high breakdown voltage can be realized.

  The emitter electrode of the IGBT is electrically connected to the emitter lead (external terminal) through a bonding wire, and the gate lead is also electrically connected to the gate electrode through the bonding wire. In the collector region, for example, a collector electrode provided on the other main surface of the substrate is electrically connected to a collector lead. Bonding wires are generally bonded by thermocompression bonding using ultrasonic vibration using a wire bonding apparatus. The IGBT is resin-sealed together with the inner part of each lead and assembled as a semiconductor device.

This type of semiconductor device is described in, for example, Patent Document 1 and Patent Document 2 below.
Japanese Patent Laid-Open No. 10-22322 JP 2002-222826 A

  However, in the semiconductor device described above, no consideration has been given to the following points. When a bonding wire is bonded directly to the emitter electrode directly above the IGBT having a stripe structure by the energy of ultrasonic vibration, the interlayer insulating film and the gate electrode of the IGBT (cell) below it are peeled off or broken. Specifically, in the IGBT, since the planar shape of the gate electrode and the interlayer insulating film has a stripe shape elongated in the gate length direction, the mechanical strength of the gate electrode and the interlayer insulating film is weak, and the bonding area with the base In addition, since the shape protrudes from the main surface of the substrate, the interlayer insulating film and the gate electrode are peeled off or broken when the bonding wire is bonded. In particular, the above problem is likely to occur when stress in the gate width direction is generated in the interlayer insulating film.

  The present invention has been made to solve the above problems. Accordingly, the present invention provides a semiconductor device and a method for manufacturing the same that can ensure breakdown resistance and can prevent breakdown of an interlayer insulating film and electrodes due to bonding while ensuring bonding strength. That is. Furthermore, this invention is providing the semiconductor device with the favorable electrical property of a semiconductor element, and its manufacturing method. Furthermore, this invention is providing the semiconductor device which can reduce manufacturing cost, and its manufacturing method.

  In order to solve the above-described problem, a first feature according to an embodiment of the present invention is that a semiconductor device includes a first semiconductor region of a first conductivity type and a plurality of first semiconductor regions arranged in a first direction. A plurality of second semiconductor regions having a second conductivity type opposite to the first conductivity type and having a second conductivity type opposite to the first conductivity type, and a plurality of layers disposed in the first direction in the second semiconductor region; The second main surface is exposed in the second semiconductor region, the third semiconductor region having the first conductivity type, and the third semiconductor region of the second semiconductor region adjacent to each other in the first direction. A control electrode disposed between the second semiconductor region and the other third semiconductor region, and an extending portion covering the control electrode and extending in a second direction intersecting the first direction, By the connecting part and the extending part and the connecting part that connect the extending parts adjacent to each other in the first direction at a constant interval in the second direction. An interlayer insulating film having a mouth shape and having an opening exposing the first main surface of the second semiconductor region and the second main surface of the third semiconductor region, and disposed on the interlayer insulating film; An electrode electrically connected to the first main surface of the second semiconductor region and the second main surface of the third semiconductor region through the opening of the interlayer insulating film, and a third semiconductor under the extending portion The second width dimension in the second direction of the third semiconductor region under the connecting portion is larger than the first width dimension in the first direction of the region.

  In the semiconductor device according to the first feature, it is preferable that the opening portion penetrates the third semiconductor region.

In the semiconductor device according to the first feature, the first width dimension and the second width dimension are:
It is preferable that the relational expression of the second width dimension <2.0 × first width dimension−2.6 × first width dimension is satisfied.

  In the semiconductor device according to the first feature, between the third semiconductor region of the second semiconductor region and another third semiconductor region of another second semiconductor region adjacent in the first direction. A hole extending through the second semiconductor region from the first main surface of the second semiconductor region to the first semiconductor region side and extending in the second direction, a side surface of the hole, and a bottom surface of the hole It is preferable that the control electrode is embedded in the hole with the insulating film interposed therebetween.

  Moreover, in the semiconductor device according to the first feature, the connecting portion of the interlayer insulating film is preferably disposed in a region immediately below the bonding area of the electrode.

  A second feature according to the embodiment of the present invention is that, in the method of manufacturing a semiconductor device, a plurality of first semiconductor regions of the first conductivity type and a plurality of first semiconductor regions are arranged in the first direction. A second semiconductor region exposed and having a second conductivity type opposite to the first conductivity type, and a plurality of second semiconductor regions disposed in the first direction in the second semiconductor region, and the second semiconductor region A second semiconductor surface having a second main surface exposed therein and having a first conductivity type; and another second semiconductor adjacent to the third semiconductor region of the second semiconductor region in the first direction. Forming a control electrode disposed between the other third semiconductor region and the extending portion extending over the control electrode and extending in a second direction that intersects the first direction The extending portions adjacent to each other in the first direction are connected to the region immediately below the bonding area in the second direction at regular intervals. An opening shape is defined by the connecting portion and the extending portion and the connecting portion, and has an opening that exposes the first main surface of the second semiconductor region and the second main surface of the third semiconductor region, An interlayer insulating film that increases the second width dimension in the second direction of the third semiconductor region under the coupling portion by using the opening compared to the first width dimension in the first direction of the third semiconductor region under the extension portion. And electrically connecting to the first main surface of the second semiconductor region and the second main surface of the third semiconductor region through the opening of the interlayer insulating film. Forming a formed electrode, and forming an external wiring electrically connected to the electrode on the electrode in the bonding area.

  According to the present invention, there are provided a semiconductor device and a method for manufacturing the same that can ensure a bonding strength while ensuring a relatively high breakdown strength and can prevent a breakdown of an interlayer insulating film, an electrode peeling and a breakdown due to bonding. be able to. Furthermore, according to the present invention, it is possible to provide a semiconductor device having good electrical characteristics of a semiconductor element and a method for manufacturing the same. Furthermore, according to the present invention, it is possible to provide a semiconductor device and a manufacturing method thereof that can reduce manufacturing costs.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic and different from actual ones. In addition, there may be a case where the dimensional relationships and ratios are different between the drawings.

  Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is to arrange the components and the like as follows. Not specific. The technical idea of the present invention can be variously modified within the scope of the claims.

(First embodiment)
The first embodiment of the present invention describes an example in which the present invention is applied to a power semiconductor device on which a semiconductor element made of IGBT having a trench structure is mounted and a manufacturing method thereof.

[Device structure of semiconductor element (IGBT)]
As shown in FIGS. 1 to 6, the semiconductor element (semiconductor chip) 1 mounted on the semiconductor device according to the first embodiment includes a first side 101 extending in a first direction (X direction) and A second side 102 opposite to the first side; a third side 103 extending in a second direction (Y direction) intersecting the first direction; and a fourth side 104 opposite to the third side 103. A first semiconductor region (substrate) 111 having a surface exposed and having a first conductivity type (see FIGS. 3 and 6 in particular) and a plurality of semiconductor regions arranged in the first direction on the first semiconductor region 111 A second semiconductor region 112 having a second conductivity type opposite to the first conductivity type, the first main surface being exposed in the second semiconductor region 112. And a third main surface is exposed on the second main surface side of the second semiconductor region 112. A third semiconductor region (emitter region) 113 having the first conductivity type, and another second semiconductor region adjacent to the third semiconductor region 113 in the second semiconductor region 112 in the first direction. 112, the gate electrode (control electrode) 116 disposed between the other third semiconductor regions 113 in the 112, the extending portion 121 covering the gate electrode 116 and extending in the second direction, the first The extending portions 121 adjacent to each other in the direction are connected to each other in the second direction at regular intervals, and the opening shape is defined by the extending portions 121 and the connecting portions 122, and the second main surface of the second semiconductor region 112. The second semiconductor through the interlayer insulating film 12 having the opening 123 exposing the third main surface of the third semiconductor region 113 and the opening 123 provided in the interlayer insulating film 12 from above the interlayer insulating film 12. Second of region 112 And a third main surface electrode electrically connected to (emitter electrode) 13 side and the third semiconductor region 113.

  Then, an opening 123 continues through the third semiconductor region 113 using the interlayer insulating film 12 as a mask. As shown in FIG. 1 and FIG. 2, below the connecting portion 122, compared to the first width dimension 121 W in the first direction of the third semiconductor region 113 below the extending portion 121 or in contact with the extending portion 121. The second width dimension 122W in the second direction of the third semiconductor region 113 that is in contact with the connecting portion 122 is set to be large. As shown in FIG. 1, since etching is performed until the third semiconductor region 113 penetrates, the first width dimension 121 </ b> W of the third semiconductor region 113 is the opening 123 of the extending portion 121 of the interlayer insulating film 12. This is the dimension between the end portion on the side and the gate insulating film 115. Further, the second width dimension 122W of the third semiconductor region 113 corresponds to the width dimension of the main surface side of the connecting portion 122 that contacts the third semiconductor region 113.

  The semiconductor element 1 is an IGBT 11, and the IGBT 11 is composed of an IGBT having a trench gate structure in the first embodiment, as shown in FIGS. 3 and 4. That is, the IGBT 11 includes a p-type fourth semiconductor region 110 (hereinafter referred to as a collector region 110) that is a collector region (or a drain region) and a first n-type semiconductor region that is an n-type base region. Semiconductor region 111 (hereinafter referred to as base region 111), p-type second semiconductor region 112 (hereinafter referred to as base region 112) which is a p-type base region, and n-type third region as an emitter region. Semiconductor region 113 (hereinafter referred to as emitter region 113), hole (trench) 114, gate insulating film 115, gate electrode 116, and collector electrode (first electrode) provided on the entire lower surface of collector region 110. ) And an emitter electrode (second electrode) 13. Here, the “gate electrode” is used in the sense of an electrode capable of controlling the flow of the main current, and if it is an electrode capable of controlling the flow of the main current, silicon polycrystal doped with impurities In addition to the film, at least electrodes such as a semiconductor region, a diffusion region, and a metal film are included.

  As shown in FIG. 6, the base region (substrate) 111 includes a first side 101 and a second side 102 that face each other in the second direction, and a third side 103 and a fourth side that face each other in the first direction. The side 104 is configured by a planar rectangular shape. The base region 111 is a semiconductor chip that is cut out by a dicing process after the IGBT (cell) 11 is manufactured by a silicon single crystal wafer in the manufacturing process of the semiconductor element 1. The planar shape of the base region 111 is not necessarily limited to this planar shape. For example, the base region 111 has the first side 101 and the second side 102 as the long side, the third side 103 and the fourth side. It is comprised by the plane rectangle which makes the edge | side 104 a short side.

  Here, in the first embodiment, the “first direction” is the left-right direction in FIGS. 2, 4, 5, and 6, and is the “X direction”. Further, the “second direction” is the vertical direction in the figure and is the “Y direction”.

  As shown in FIGS. 1 to 6, the planar shape of the interlayer insulating film 12 according to the first embodiment is arranged in the bonding direction of the first electrode 13 and arranged in the first direction at regular intervals. It has a mesh shape having an extending portion 121 provided between the second electrode 13 extending in the direction of the gate electrode 116 and the gate electrode 116, a connecting portion 122 connecting the extending portions 121 adjacent thereto, and an opening 123. . In addition, the planar shape of the interlayer insulating film 12 is a stripe shape in which only the extending portion 121 provided between the second electrode 13 and the gate electrode 116 is formed outside the bonding area of the first electrode 13. .

  The “mesh shape” of the interlayer insulating film 12 is disposed on the gate electrode 116 (hole 114), extends in the same direction as the second direction in which the gate electrode 116 extends, and is similar to the gate electrode 116. Extending portions 121 having a stripe shape in a planar shape, arranged at regular intervals in the first direction, and connecting portions 122 integrally connected to each other between adjacent extending portions 121 in the first direction. And an opening 123 formed in a region surrounded by two extending portions 121 adjacent in the first direction and two connecting portions 122 adjacent in the second direction. Since the connecting portion 122 connects the extending portions 121 adjacent in the first direction at a constant interval in the second direction, the extending portion 121 of the interlayer insulating film 12 and its extension within the bonding area of the second electrode 13. The mechanical strength of the gate electrode 116 immediately below can be improved. In particular, it is possible to prevent the extending portion 121 of the interlayer insulating film 12 and the gate electrode 116 immediately below it from being cracked or peeled off due to stress generated during bonding (for example, ultrasonic vibration energy). On the other hand, the connecting portion 122 of the interlayer insulating film 12 is provided between the extending portions 121 adjacent to each other in the first direction, but the connecting portion 122 is provided at least in the bonding area. Since the mesh-shaped opening 123 is disposed inside, the bonding area is secured while suppressing the reduction of the contact area and the current capacity between the emitter region 113 and the second electrode 13, and the interlayer accompanying the bonding. The insulating film 12 and the gate electrode 116 can be prevented from being broken or peeled off. In addition, these effects can be achieved only by changing the opening pattern of the interlayer insulating film 12, and a manufacturing process is not added, so that the manufacturing is easy and the manufacturing cost does not increase. In the first embodiment, a silicon oxide film or a phosphor glass (PSG) film can be practically used as the interlayer insulating film 12, and the film thickness of the phosphor glass film is, for example, 0.5 μm−3.0. It is set to μm.

  Here, a causal relationship between the opening ratio of the opening 123 of the interlayer insulating film 12 and the defect occurrence rate exists as shown in FIG. In FIG. 7, the horizontal axis represents the opening ratio of the opening 123 of the interlayer insulating film 12, the left vertical axis represents the defect rate (%) due to avalanche breakdown, and the right vertical axis represents the defect rate (%) due to wire bonding damage. Here, since the etching is performed through the third semiconductor region 113 using the opening 123 of the interlayer insulating film 12 as a mask, the opening ratio is the first of the third semiconductor region 113 shown in FIGS. The width dimension in the first direction of the extended portion 121 of the interlayer insulating film 12 corresponding to the width dimension 121W (= first width dimension 121W: the opening 123 at the shortest distance from one end of the gate insulating film 114 of the extended portion 121. This is a value obtained by dividing the dimension to the end by the width dimension in the second direction of the connecting portion 122 (= second width dimension 122W) corresponding to the second width dimension 122W of the third semiconductor region 113.

When the opening ratio of the opening 123 of the interlayer insulating film 12 increases, that is, when the second width 122W of the connecting portion 122 increases with respect to the first width 121W of the extending portion 121, it results from wire bonding damage. The defective rate can be reduced. In the curve A shown in FIG. 7, the aperture ratio is 2.2, and in the curve B, the aperture ratio is 2.0 and the defect rate is effectively zero. That is, the extension portion 121 of the interlayer insulating film 12 and the gate electrode 116 immediately below the extension portion 121 can be prevented from cracking or peeling. The wire bonding conditions of curve A are: bonding load is 1200 g / cm ² , ultrasonic vibration energy (ultrasonic power) is 145 Hz on the first side, 190 Hz on the second side, ultrasonic vibration time is 120 msec on the first side The second side is 170 msec. Also, the wire bonding conditions of curve B are as follows. Bonding load is 1200 g / cm ² , ultrasonic vibration energy (ultrasonic power) is 145 Hz on the first side, 180 Hz on the second side, and ultrasonic vibration time is on the first side. 120 msec, 170 msec on the second side.

  On the other hand, when the opening ratio of the opening 123 of the interlayer insulating film 12 increases, that is, when the second width 122W of the connecting portion 122 increases with respect to the first width 121W of the extending portion 121, the curve C indicates On the other hand, the defect rate due to avalanche destruction increases when the opening ratio is 2.6. This is because the current path from the bonding wire is the shortest on the region where the third semiconductor region 113 is exposed in the opening 123, but the third from the center of the connecting portion 122 (for example, indicated by symbol K in FIG. 2). This is because the current path to the semiconductor region 113 becomes longer, and the current dynamic characteristic time lag increases. In the avalanche resistance, it is important to disperse the applied energy over a wider part to alleviate current concentration and not to turn on the parasitic transistor. Among them, it is effective to reduce the resistance of the second semiconductor region 112 immediately below the third semiconductor region 113. Since the etching is performed until part of the third semiconductor region 113 is penetrated using the interlayer insulating film 12 as a mask, the opening 123 and the resistance of the second semiconductor region 112 immediately below the third semiconductor region 113 are intimate. Have a relationship. That is, based on the causal relationship shown in FIG. 7, the second width dimension 122W of the connecting portion 122 is made larger than the first width dimension 121W of the extending portion 121 of the interlayer insulating film 12 (first width dimension 121W <first width dimension). If the width dimension 122W is set to 2, the defect rate due to wire bonding damage can be reduced. Furthermore, in order to reduce the defect rate due to the avalanche breakdown while reducing the defect rate due to the wire bonding damage, the first width dimension 121W of the extending portion 121 of the interlayer insulating film 12 and the first of the connecting portion 122 are reduced. The second width dimension 122W needs to satisfy the following relational expression.

Second width dimension <2.0 × first width dimension to 2.6 × first width dimension Other dimensions according to the first embodiment of the present invention that satisfy the above formula are, for example, as follows (see FIG. 2).

1. Hole width (a) of hole 114: 0.5 μm
2. Arrangement pitch of holes 114 (b): 2.0 μm
3. The width (121W) of the extending portion 121 of the interlayer insulating film 12: 0.5 μm
4). The width (122W) of the connecting portion 122 of the interlayer insulating film 12: 1.0 μm
5. Arrangement pitch (c) of connecting portions 122 in the first direction: 9.0 μm
6). Length of hole 114 (d): 8.0 μm
7). Impurity density of the second semiconductor region 112: 6.0 × 10 ¹⁷ atoms / cm ²
8). Junction depth of the second semiconductor region 112: 1.4 μm
9. Impurity density of the third semiconductor region 113: 5.0 × 10 ¹⁹ atoms / cm ²
10. Junction depth of the third semiconductor region 113: 0.3 μm
11. Width dimension of the gate electrode 116: 0.5 μm
In the first embodiment, the planar shape of the interlayer insulating film 12 further includes openings 123 arranged at regular intervals in the second direction, as shown in FIG. It is desirable that the adjacent openings 123 be adopted so as to have an offset mesh shape. The offset amount is, for example, a half arrangement pitch.

  Here, the “bonding area of the second electrode 13” in which the planar shape of the interlayer insulating film 12 is set to a mesh shape means that the second electrode (emitter electrode) 13 and the emitter lead (external terminal) are electrically connected. This is the region where the bonding wire (32) to be connected is bonded. A protective film 14 is disposed on the second electrode 13, and an opening 141 for electrically connecting the bonding wire (32) to the second electrode 13 is disposed on the protective film 14 as shown in FIG. 3. The bonding area of the second electrode 13 is in the region of the opening 141 provided in the protective film 14.

  Outside the bonding area of the second electrode 13, the planar shape of the interlayer insulating film 12 is a stripe shape. Specifically, the interlayer insulating film 12 is disposed on the gate electrode 116 (or the hole 114) and extends in the same direction as the second direction in which the gate electrode 116 extends. Similarly, a plurality of arrayed portions 121 arranged in the first direction at constant intervals and sandwiched between the extending portions 121 whose planar shapes are stripe-shaped and adjacent extending portions 121 in the first direction, are spaced at constant intervals in the first direction. And a plurality of openings 124 having a planar stripe shape. Outside the bonding area of the second electrode 13, there is no need to increase the mechanical strength against the stress generated during bonding, so the connecting portion 122 is not disposed between the extending portions 121 adjacent in the first direction. May be. As a result of not providing the connecting portion 122, the opening area of the opening portion 124 can be increased, so that the contact area and the current capacity between the emitter region 113 and the second electrode 13 are ensured, and the electric field concentration is reduced. Can be prevented.

  That is, the second electrode (emitter electrode) 13 is disposed on the interlayer insulating film 12, and the second electrode 13 passes through the opening 123 of the interlayer insulating film 12 in the bonding area of the second electrode 13. It is connected to the IGBT 11. Outside the bonding area of the second electrode 13, the second electrode 13 is connected to the IGBT 11 through the opening 124 of the interlayer insulating film 12. The second electrode 13 is used as an emitter electrode (or source electrode), and an aluminum alloy film can be used for the second electrode 13, for example. The aluminum alloy film is aluminum to which additives such as Si for preventing alloy spikes and Cu for preventing migration are added.

  As shown in FIG. 3, the protective film 14 is disposed on the second electrode 13 in the entire region on the main surface of the substrate 10. As shown in FIGS. 3 to 6, the protective film 14 has an opening 141 in a bonding area on the second electrode 13 in the element region. Further, as shown in FIG. 6, a bonding electrode 13 </ b> G for electrically connecting to the gate electrode 116 of the IGBT 11 is exposed through the opening 142 of the protective film 14 in the protective film 14. The bonding electrode 13 </ b> G of the gate electrode 116 is made of the same conductive material in the same conductive layer as the second electrode 13. As shown in FIG. 6, the opening 141 of the protective film 14 is disposed in the central portion of the base region (substrate) 111, and the opening 142 is disposed in the vicinity of the third side 103 of the base region 111. The planar area of the opening 142 is smaller than the planar area of the opening 141. For the protective film 14, for example, a resin film such as PIF (poly-imide film) or a PSG film can be used practically.

[Assembly structure of semiconductor device]
As shown in FIG. 6, the semiconductor device 201 includes a semiconductor element 1 and a first lead (collector external) having a die bonding region 21 </ b> D on which the semiconductor element 1 is mounted and extending in a first direction (X direction). Terminal) 21, a second lead (gate external terminal) 22 disposed on the left side of the first lead 21 and extending in the second direction, and a second lead disposed on the right side of the first lead 21. A third lead (external emitter terminal) 23 extending in the direction of, a bonding wire 31 for electrically connecting the second lead 22 and the bonding electrode 13G of the semiconductor element 1, and a third lead And a sealing body 4 and a bonding wire 32 that electrically connects the bonding area of the second electrode 13 of the semiconductor element 1 to the bonding area of the second electrode 13 of the semiconductor element 1.

  For the first lead 21, the second lead 22, and the third lead 23, a Cu plate, an Fe—Ni alloy plate, or the like can be used. The surface of the Cu plate may be plated with Ni.

  Although not shown in detail in FIGS. 3 and 6, a conductive adhesive is interposed in the die bonding region 21D of the first lead 21 so that the first electrode on the back surface of the semiconductor element 1 is electrically and mechanically. Connected.

  The bonding wire 31 is electrically connected to the bonding electrode 13G through the opening 142 formed in the protective film 14 of the semiconductor element 1. Similarly, the bonding wire 32 is electrically connected to the electrode 13 through the opening 141 formed in the protective film 14 on the substrate 10. For example, a wire such as Au, Lu, or Al can be practically used as the bonding wires 31 and 32, and this wire is bonded by using ultrasonic bonding together with ultrasonic vibration using a bonding apparatus.

  For example, an epoxy resin is used for the sealing body 4. This epoxy resin is molded by, for example, a molding method. Inside the sealing body 4, the semiconductor element 1, the first lead 21, the second lead 22, the third lead 23, the inner portions (part) of each, and the bonding wires 31 and 32 are hermetically sealed. . Outer portions (parts) of the first lead 21, the second lead 22, and the third lead 23 protrude outside the sealing body 4.

  The assembly procedure of the semiconductor device 201 is as follows. First, the semiconductor element 1 in which the IGBT 11, the interlayer insulating film 12, the second electrode 13, and the protective film 14 are sequentially formed is manufactured. Next, the semiconductor element 1 is mounted on the die bonding region 21 </ b> D of the first lead 21. Next, bonding wires 31 and 32 are bonded. Then, the semiconductor device 201 according to the first embodiment is completed by molding the semiconductor element 1 and the like with the sealing body 4.

[Features of semiconductor devices]
As shown in FIGS. 1 to 6, in the semiconductor device 201 according to the first embodiment, the planar structure of the interlayer insulating film 12 in the bonding area is configured in a mesh shape, and the first of the interlayer insulating film 12 is formed. Since the extending portions 121 adjacent to each other in the direction enhance the mechanical strength by the connecting portion 122, the bonding strength of the interlayer insulating film 12 at the time of bonding is secured, and the breakdown of the interlayer insulating film 12 due to bonding and the electrodes Destruction of the gate electrode 116 or the second electrode 13 can be prevented, for example.

  Furthermore, in the semiconductor device 201 according to the first embodiment, since the connecting portions 122 of the interlayer insulating film 12 are arranged at regular intervals in the second direction, a sufficient planar area of the opening 123 is ensured. can do. Therefore, a sufficient contact area, which is an original characteristic of the IGBT 11 having a stripe structure, can be sufficiently ensured, electric field concentration can be reduced, a sufficient breakdown voltage can be ensured, and the electrical resistance of the semiconductor element 1 can be secured. A semiconductor device 201 with favorable characteristics can be provided.

  Furthermore, in the semiconductor device 201 according to the first embodiment, the connection between the first width dimension 121W of the third semiconductor region 113 under the extension portion 121 (or the extension portion 121) and the third semiconductor region 113 is performed. Since the ratio of the second width dimension 122W under the portion 122 (or the connecting portion 122) is set to an appropriate range, a sufficient breakdown voltage is secured while securing the bonding strength of the interlayer insulating film 12 during bonding. can do.

  Further, in the semiconductor device 201 according to the first embodiment, since the planar shape of the interlayer insulating film 12 outside the bonding area is configured by a stripe shape, the electrical characteristics of the semiconductor element 1 are ensured as described above. can do.

  Further, in the semiconductor device 201 according to the first embodiment, the planar shape of the interlayer insulating film 12 for producing such an effect can be dealt with by simply changing the pattern of the manufacturing mask. In particular, it is not necessary to increase the number of manufacturing steps, and the manufacturing cost can be reduced. Furthermore, the film thickness of the second electrode 13 and the bonding electrode 13G does not need to be increased for bonding, so that the manufacturing cost can be reduced also in this respect.

[Modification]
In the semiconductor device 201 according to the modification of the first embodiment, the planar shape of the interlayer insulating film 12 of the IGBT 11, particularly in the bonding area, is arranged at regular intervals in the second direction as shown in FIG. 8. The opening 123 and the opening 123 adjacent to the first direction side with respect to the opening 123 are configured by a mesh shape formed as needed so as to be on the same straight line. That is, when the connection part 122 is seen in the 1st direction, it forms in a straight line, and when it sees in the 2nd direction, it forms repeatedly at fixed intervals. In the planar shape of the interlayer insulating film 12 according to the modification, the arrangement pitch of the connecting portions 122 and the openings 123 is offset.

  In the semiconductor device 201 according to the modified example configured as described above, the same effect as that obtained by the semiconductor device 201 according to the first embodiment described above can be obtained.

  In the semiconductor device 201 according to the first embodiment, the planar shape of the interlayer insulating film 12 is a mesh shape only in the bonding area of the semiconductor element 1, but the present invention is limited to such a structure. Instead, the planar shape of the interlayer insulating film 12 inside and outside the bonding area may be a mesh shape.

(Second Embodiment)
In the second embodiment of the present invention, an example in which the present invention is applied to a power semiconductor device on which a semiconductor element made of IGBT having a planar structure is mounted and a method for manufacturing the power semiconductor device will be described.

[Device structure of semiconductor element (IGBT)]
As shown in FIG. 9, the semiconductor element 1 mounted on the semiconductor device 201 according to the second embodiment is composed of an IGBT 11 having a planar structure. That is, the IGBT 11 includes a collector region (p-type fourth semiconductor region) 110, an n-type base region (n-type first semiconductor region or substrate) 111, and a p-type base region (p-type second semiconductor region). Semiconductor region) 112, emitter region (n-type third semiconductor region) 113, gate insulating film 115, gate electrode 116, collector electrode (first electrode), emitter electrode (second electrode) 13. The basic cross-sectional structure of the semiconductor element 1 is the same as the cross-sectional structure of the semiconductor element 1 of the semiconductor device 201 according to the first embodiment, but the hole 114 shown in FIGS. 1 and 3 is provided. Absent. That is, in the semiconductor element 1, the gate electrode 116 is disposed in a planar structure on the main surface of the base region 111 with the gate insulating film 115 interposed therebetween, and the base region 112 and the emitter are formed by a double diffusion structure using the gate electrode 116 as a mask. A region 113 is provided.

(Third embodiment)
The third embodiment of the present invention relates to the semiconductor device 201 according to the first embodiment and the second embodiment described above, and includes the semiconductor element 1, the second lead 22, and the third lead 23. An example in which the connection method between them is changed will be described.

  As shown in FIGS. 10 and 11, the semiconductor device 201 according to the third embodiment is electrically connected between the bonding electrode 13G of the semiconductor element 1 and the second lead 22 by a clip lead 22C. The second electrode 13 and the third lead 23 are electrically connected by the clip lead 23C. A solder paste 35 is used for connection between the clip lead 22C and each of the bonding electrode 13G and the second lead 22, and the both are electrically and mechanically connected. Similarly, a solder paste 36 is used for connection between the clip lead 23C and each of the second electrode 13 and the third lead 23, and both are electrically and mechanically connected.

  For the clip leads 22C and 23C, for example, a metal plate such as a Cu plate or an alloy plate such as an Fe-Ni alloy plate can be used. For the solder pastes 35 and 36, for example, Pb-Sn solder or Pb-free solder such as Sn-3 wt% Ag-0.5 wt% Cu can be used. In the connection of the clip lead 22C via the solder paste 35 to the bonding electrode 13G and the connection of the clip lead 22C via the solder paste 35 to the second lead 22, as in the bonding of the bonding wire 31, heat is applied to ultrasonic vibration. It is carried out by a bonding method using pressure bonding together. Similarly, for the connection of the clip lead 23C via the solder paste 36 to the second electrode 13 and the connection of the clip lead 23C via the solder paste 36 to the third lead 23, a heating method using a heater or the like, or a bonding wire Similar to the bonding of 32, a bonding method using ultrasonic vibration in combination with thermocompression bonding is used.

  Further, in order to improve the bondability between the bonding electrode 13G and the solder paste 35, and similarly improve the bondability between the second electrode 13 and the solder paste 36, each of the bonding electrode 13G and the second electrode 13 is provided. A wettability improving film may be formed on the surface. As this wettability improving film, for example, a composite layer in which a Ni layer is laminated on a Ti layer can be used practically.

  The semiconductor device 201 according to the third embodiment configured as described above has the same effect as that obtained by the semiconductor device 201 according to the first embodiment and the second embodiment described above. be able to.

  Furthermore, the resistance component and the inductance component of the metal plates and alloy plates of the clip leads 22C and 23C are characterized by being smaller than that of the wire wiring. On the other hand, although the stress generated at the joint between the metal plate or alloy plate and the bonding area increases, in the third embodiment, the connecting portion 122 is provided in the interlayer insulating film 12 in the bonding area of the second electrode 13. Therefore, the mechanical strength in the bonding area of the second electrode 13 can be increased. Therefore, in the semiconductor device 201, it is possible to prevent the interlayer insulating film 12 and the gate electrode 116 from peeling while reducing the resistance component and the inductance component.

(Other embodiments)
As described above, the present invention has been described with reference to the first embodiment, its modifications, the second embodiment, and the third embodiment. However, the discussion and the drawings that form a part of this disclosure are the present invention. It does not limit. The present invention can be applied to various alternative embodiments, examples, and operational technologies. For example, in the above-described embodiment and the like, the semiconductor device 201 on which the semiconductor element 1 made of the IGBT 11 is mounted has been described as an example. However, the present invention is not limited to the IGBT 11 and is a power transistor (power MOSFET). The present invention can be applied to a semiconductor element comprising the above and a semiconductor device on which the semiconductor element is mounted. Further, the present invention can be applied not only to a trench structure but also to a semiconductor element composed of a power transistor having a planar structure and a semiconductor device having the semiconductor element mounted thereon. Further, the corners of the opening 123 of the interlayer insulating film 12 described above may be rounded.

It is a principal part expansion perspective view of the semiconductor element mounted in the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 2 is an enlarged plan view of a main part of the semiconductor element shown in FIG. 1. FIG. 2 is an enlarged cross-sectional view of a main part when a bonding wire is provided in the semiconductor element shown in FIG. 1. FIG. 4 is an enlarged plan view of a main part of the semiconductor element shown in FIG. 3 (a part of the IGBT excluding the protective film, bonding wire, second electrode, and interlayer insulating film in FIG. 3). FIG. 4 is an enlarged plan view of a main part of an interlayer insulating film in the semiconductor element shown in FIG. 3. 1 is a plan view showing an internal structure of a semiconductor device according to a first embodiment of the present invention. It is a figure which shows the relationship between the opening ratio of the interlayer insulation film which concerns on 1st Embodiment, and a defect rate. It is an enlarged plan view of the principal part of an interlayer insulation film in the semiconductor element concerning the modification of a 1st embodiment. It is a principal part expanded sectional view when a bonding wire is provided in the semiconductor element mounted in the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a top view which shows the internal structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. FIG. 8 is an enlarged cross-sectional view of a main part when a clip lead is provided in the semiconductor element of the semiconductor device shown in FIG. 7.

Explanation of symbols

DESCRIPTION OF SYMBOLS 201 ... Semiconductor device 110 ... Collector area | region or 4th semiconductor region 101 ... 1st edge | side 102 ... 2nd edge | side 103 ... 3rd edge | side 104 ... 4th edge | side 1 ... Semiconductor element 11 ... IGBT
DESCRIPTION OF SYMBOLS 111 ... 1st semiconductor region or board | substrate 112 ... 2nd semiconductor region or base region 113 ... 3rd semiconductor region or emitter region 114 ... Hole 115 ... Gate insulating film 116 ... Gate electrode 12 ... Interlayer insulating film 121 ... Extension part 121W ... first width dimension 122 ... connecting portion 122W ... second width dimension 123, 124 ... opening 13 ... second electrode 13G ... bonding electrode 14 ... protective film 141, 142 ... opening 21 ... first lead 22 ... 2nd lead 23 ... 3rd lead 31, 32 ... Bonding wire 22C, 23C ... Clip lead 35, 36 ... Solder paste 4 ... Sealing body

Claims (6)

A first semiconductor region of a first conductivity type;
A plurality of second semiconductor regions disposed in a first direction, exposing a first main surface, and having a second conductivity type opposite to the first conductivity type;
A plurality of third semiconductor regions disposed in the second direction in the second semiconductor region and having a second main surface exposed in the second semiconductor region and having the first conductivity type When,
Control disposed between the third semiconductor region of the second semiconductor region and the other third semiconductor region of the other second semiconductor region adjacent to the first direction. Electrodes,
An extending portion that covers the control electrode and extends in a second direction intersecting the first direction, and a connecting portion that connects the extending portions adjacent to each other in the first direction at a constant interval. And an opening is defined by the extending portion and the connecting portion, and has an opening that exposes the first main surface of the second semiconductor region and the second main surface of the third semiconductor region. An interlayer insulating film;
Electrically disposed on the interlayer insulating film and electrically through the opening of the interlayer insulating film to the first main surface of the second semiconductor region and the second main surface of the third semiconductor region. Connected electrodes, and
The second width dimension in the second direction of the third semiconductor region under the coupling portion is larger than the first width dimension in the first direction of the third semiconductor region under the extension portion. A semiconductor device.   The semiconductor device according to claim 1, wherein the opening penetrates the third semiconductor region. The first width dimension and the second width dimension are:
3. The semiconductor device according to claim 1, wherein the relational expression of second width dimension <2.0 × first width dimension to 2.6 × first width dimension is satisfied. The second semiconductor region between the third semiconductor region of the second semiconductor region and the other third semiconductor region of the other second semiconductor region adjacent to the first direction. A hole extending through the second semiconductor region from the first main surface to the first semiconductor region side and extending in the second direction;
An insulating film disposed on a side surface of the hole and a bottom surface of the hole, and
The semiconductor device according to claim 1, wherein the control electrode is embedded in the hole with the insulating film interposed therebetween.   5. The semiconductor device according to claim 1, wherein the connecting portion of the interlayer insulating film is disposed in a region immediately below a bonding area of the electrode. A plurality of first semiconductor regions of the first conductivity type and a plurality of semiconductor regions disposed in the first direction, exposing the first main surface, and having a second conductivity type opposite to the first conductivity type. A plurality of second semiconductor regions and a plurality of second semiconductor regions disposed in the first direction in the second semiconductor region, and a second main surface exposed in the second semiconductor region; And a third semiconductor region of the second semiconductor region and another third semiconductor region of the second semiconductor region adjacent to the second semiconductor region in the first direction. Forming a control electrode disposed therebetween;
An extending portion that covers the control electrode and extends in a second direction intersecting the first direction, and the extending portions adjacent to each other in the first direction in a region immediately below the bonding area in the second direction An opening shape is defined by the connecting portion connected at a constant interval, and the extending portion and the connecting portion, and the first main surface of the second semiconductor region and the second main surface of the third semiconductor region. A third semiconductor region under the connecting portion as compared to a first width dimension in the first direction of the third semiconductor region under the extended portion by the opening. Forming an interlayer insulating film for enlarging the second width dimension in the second direction;
Electrically disposed on the interlayer insulating film and electrically through the opening of the interlayer insulating film to the first main surface of the second semiconductor region and the second main surface of the third semiconductor region. Forming a connected electrode;
Forming an external wiring electrically connected to the electrode on the electrode in the bonding area;
A method for manufacturing a semiconductor device, comprising:

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