JP2003188378A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2003188378A
JP2003188378A JP2001381719A JP2001381719A JP2003188378A JP 2003188378 A JP2003188378 A JP 2003188378A JP 2001381719 A JP2001381719 A JP 2001381719A JP 2001381719 A JP2001381719 A JP 2001381719A JP 2003188378 A JP2003188378 A JP 2003188378A
Authority
JP
Japan
Prior art keywords
surface electrode
electrode
semiconductor element
external
central portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001381719A
Other languages
Japanese (ja)
Inventor
Goji Horiguchi
剛司 堀口
Osamu Usui
修 碓井
Takeshi Oi
健史 大井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2001381719A priority Critical patent/JP2003188378A/en
Publication of JP2003188378A publication Critical patent/JP2003188378A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4846Connecting portions with multiple bonds on the same bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48699Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49174Stacked arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which long-term reliability is enhanced by suppressing temperature rise in the central part of surface electrodes where heat dissipation is poor. <P>SOLUTION: The temperature rise at the central part of the surface electrodes 2 where the heat dissipation is poor is suppressed by such a means that the combined electrical resistance from the semiconductor element 1 to an external electrode 3 via the central part of the surface electrodes 2 and metal wires 4 is made larger than the combined electrical resistance from the semiconductor element 1 to the external electrode 3 via peripheral parts of the surface electrodes 2 and the metal wires 4, or the metal wires 4 are bonded only in the peripheral parts of the surface electrodes 2, or the like. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、半導体装置に関
し、特に、半導体素子と、半導体素子の表面に設けら
れ、半導体素子と電気的に接続された表面電極と、半導
体素子の外部に設けられた外部電極と、表面電極と外部
電極とを電気的に接続する外部配線とを備えた半導体装
置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and particularly to a semiconductor element, a surface electrode provided on the surface of the semiconductor element and electrically connected to the semiconductor element, and provided outside the semiconductor element. The present invention relates to a semiconductor device including an external electrode and an external wiring that electrically connects the surface electrode and the external electrode.

【0002】[0002]

【従来の技術】図17は、従来の半導体装置に一例のパ
ワー半導体モジュールを示す断面図である。ここでは、
パワー半導体モジュールとして、パワー半導体素子にI
GBT(Insulated Gate Bipolar Transistor)を用
いたIGBTモジュールを例に説明する。図17に示す
IGBTモジュールは、文献(タイトル:ハイブリッド
IC・パワーモジュール、出典:パワーデバイス・パワ
ーICハンドブック p249−p296)に記載され
ているものである。図17において、ハンダ105を介
して、両面に銅等の金属配線パターン107が設けられ
た絶縁基板106が金属ベース板108上に配設され、
金属配線パターン107の上にハンダ105を介して接
続される半導体素子101と外部電極103とが、外部
配線の一例である金属ワイヤ104により電気的に接続
されている。
2. Description of the Related Art FIG. 17 is a sectional view showing a power semiconductor module as an example of a conventional semiconductor device. here,
As a power semiconductor module, I
An IGBT module using a GBT (Insulated Gate Bipolar Transistor) will be described as an example. The IGBT module shown in FIG. 17 is described in the literature (title: hybrid IC / power module, source: power device / power IC handbook p249-p296). In FIG. 17, an insulating substrate 106 having metal wiring patterns 107 made of copper or the like on both sides is disposed on a metal base plate 108 via a solder 105,
The semiconductor element 101 connected to the metal wiring pattern 107 via the solder 105 and the external electrode 103 are electrically connected by a metal wire 104 which is an example of external wiring.

【0003】図17に示すIGBTモジュールでは、両
面に薄膜上の銅等の金属配線パターン107が接着され
たAl23やAlN等からなる絶縁基板106が、金属
ベース板108上にハンダ等の導電性材料により接着さ
れている。絶縁基板106上面に接着された銅等の金属
パターン107上に実装された半導体素子101が、金
属ワイヤ104を介して外部電極103と接続され、主
回路を構成している。金属ワイヤ104は、CuやAl
といった金属が主に用いられている。なお、金属ワイヤ
の信頼性を向上させるため、Si、Ni、Cu等を混合
したAlワイヤも広く普及している。
[0003] In the IGBT module shown in FIG. 17, Al 2 O 3 and the insulating substrate 106 made of AlN or the like metal wiring pattern 107 of copper or the like on a thin film on both surfaces is adhered is such as solder on the metal base plate 108 It is adhered by a conductive material. The semiconductor element 101 mounted on the metal pattern 107 such as copper adhered to the upper surface of the insulating substrate 106 is connected to the external electrode 103 via the metal wire 104 to form a main circuit. The metal wire 104 is made of Cu or Al.
Such metals are mainly used. In addition, in order to improve the reliability of the metal wire, an Al wire mixed with Si, Ni, Cu or the like is also widely used.

【0004】図18は、従来のパワー半導体モジュール
における、金属ワイヤ104と半導体素子101の表面
電極102との接合方法を説明するための斜視図であ
り、半導体素子101の表面電極102が、複数の部分
表面電極120により構成されている例を示す図であ
る。
FIG. 18 is a perspective view for explaining a bonding method of the metal wire 104 and the surface electrode 102 of the semiconductor element 101 in the conventional power semiconductor module. It is a figure which shows the example comprised by the partial surface electrode 120.

【0005】また、図18に示すように、N本の金属ワ
イヤ104が、半導体素子101のN個の部分表面電極
120それぞれの主表面の中央部分に1箇所で接合され
ている。
Further, as shown in FIG. 18, N metal wires 104 are bonded to the central portion of the main surface of each of the N partial surface electrodes 120 of the semiconductor element 101 at one location.

【0006】半導体素子101の表面側に陰極側電極
が、裏面側に陽極側電極が形成されているものとする
と、電流は半導体素子101の裏面側から表面電極10
2、金属ワイヤ104を介して外部電極103へと流れ
ていく。このとき、N本の金属ワイヤ104が半導体素
子101の表面電極102の中央部に一列に接合されて
いるため、電流は表面電極の中央部に集中し、半導体素
子101の表面の温度分布が、表面電極102の中央部
が最も高温となることは容易に想像がつく。実際、図1
9に示すように、半導体素子101を駆動するために直
流電流を通電した時の表面電極102の表面の温度分布
の解析結果では、表面電極102の長方形状の主表面の
対角線の交点付近が最も高温となっている。
Assuming that the cathode side electrode is formed on the front surface side of the semiconductor element 101 and the anode side electrode is formed on the back surface side, a current flows from the back surface side of the semiconductor element 101 to the front surface electrode 10.
2. It flows to the external electrode 103 through the metal wire 104. At this time, since the N metal wires 104 are joined in a line to the central portion of the surface electrode 102 of the semiconductor element 101, the current concentrates on the central portion of the surface electrode, and the temperature distribution on the surface of the semiconductor element 101 becomes It can be easily imagined that the central portion of the surface electrode 102 has the highest temperature. In fact, Figure 1
As shown in FIG. 9, in the analysis result of the temperature distribution on the surface of the surface electrode 102 when a direct current is applied to drive the semiconductor element 101, the vicinity of the intersection of the diagonal lines of the rectangular main surface of the surface electrode 102 is the most. It is hot.

【0007】なお、図19においては、表面電極102
の表面の温度を示す等高線が1℃刻みで表示されてお
り、また、114、116、118、120、122、
124、126、130、132といった数字により各
等高線における温度が示されている。また、図19で
は、133℃までの温度が等高線で示されており、表面
電極102の長方形状の主表面の対角線の交点付近をピ
ークとする同心円状の温度分布となる。さらに、表面電
極102と金属ワイヤ104との接合部における温度の
最大値は133.9℃であった。
In FIG. 19, the surface electrode 102
Contour lines showing the temperature of the surface of the are displayed in increments of 1 ° C., and 114, 116, 118, 120, 122,
The numbers at 124, 126, 130, 132 indicate the temperature at each contour line. Further, in FIG. 19, the temperature up to 133 ° C. is indicated by contour lines, and the temperature distribution has a concentric circle shape having a peak near the intersection of diagonal lines of the rectangular main surface of the surface electrode 102. Further, the maximum value of the temperature at the joint between the surface electrode 102 and the metal wire 104 was 133.9 ° C.

【0008】[0008]

【発明が解決しようとする課題】表面電極102と外部
電極103とを接続する金属ワイヤ104が、部分表面
電極120の中央部に一列に接合されている従来のパワ
ー半導体モジュールにおいては、表面電極102の表面
における温度分布は図19に示したとおり、表面電極1
02の長方形状の主表面の対角線の交点付近が最も高温
となる。これは、半導体素子101から金属ベース板1
08までの積層構造材料の面積が、半導体素子101よ
りも大きく、表面電極102の主表面における発熱は、
主表面に平行な方向に拡散するため、表面電極102の
中央部ほど放熱性に劣るためである。
In the conventional power semiconductor module in which the metal wire 104 connecting the surface electrode 102 and the external electrode 103 is joined in a line at the central portion of the partial surface electrode 120, the surface electrode 102 is used. As shown in FIG. 19, the temperature distribution on the surface of the
The highest temperature is near the intersection of the diagonal lines of the rectangular main surface of No. 02. This is from the semiconductor element 101 to the metal base plate 1
The area of the laminated structure material up to 08 is larger than that of the semiconductor element 101, and the heat generation on the main surface of the surface electrode 102 is
This is because the heat dissipation is poorer toward the central portion of the surface electrode 102 because it diffuses in the direction parallel to the main surface.

【0009】そのため、高温となる表面電極102の主
表面の対角線の交点付近と金属ワイヤ104との接合部
は、熱疲労により金属ワイヤ104の剥離が発生し易く
なる。仮に、中央部において一本の金属ワイヤ104が
剥離を起こすと、周縁部の他の各金属ワイヤ104に流
れる電流密度が高くなり、その結果、表面電極102と
周縁部の他の金属ワイヤ104との接合部の温度が上昇
し、周縁部の他の金属ワイヤ104の剥離が加速度的に
発生し易くなるため、パワー半導体モジュールの長期的
な信頼性を損なうことになる。
Therefore, the metal wire 104 is liable to be peeled off due to thermal fatigue at the junction between the intersection of the diagonal lines of the main surface of the surface electrode 102 and the metal wire 104, which become hot. If one metal wire 104 is peeled off in the central portion, the current density flowing in each of the other metal wires 104 in the peripheral portion becomes high, and as a result, the surface electrode 102 and the other metal wires 104 in the peripheral portion are separated from each other. Since the temperature of the joining portion of the power source rises and peeling of the other metal wire 104 in the peripheral portion is likely to occur at an accelerated rate, the long-term reliability of the power semiconductor module is impaired.

【0010】本発明は、上記のような問題点を解決する
ためになされたものであり、その目的は、放熱性が劣る
表面電極の中央部の温度上昇を抑制することにより、長
期的な信頼性が向上した半導体装置を提供することであ
る。
The present invention has been made to solve the above problems, and its purpose is to suppress long-term reliability by suppressing a temperature rise in the central portion of a surface electrode having poor heat dissipation. To provide a semiconductor device having improved property.

【0011】[0011]

【課題を解決するための手段】本発明の第1の局面の半
導体装置は、半導体素子と、半導体素子の主表面に沿っ
て設けられ、該半導体素子と電気的に接続された表面電
極と、半導体素子の外部に設けられた外部電極と、表面
電極と外部電極とを電気的に接続する外部配線とを備
え、表面電極を、主表面側から見て、中央部と中央部を
取り囲む周縁部とに区別した場合に、半導体素子の駆動
時に、周縁部の電流密度が、中央部の電流密度よりも高
くなるように構成されている。
A semiconductor device according to a first aspect of the present invention includes a semiconductor element, a surface electrode provided along a main surface of the semiconductor element, and electrically connected to the semiconductor element. The semiconductor device includes an external electrode provided outside the semiconductor element and an external wiring for electrically connecting the surface electrode and the external electrode, and the surface electrode is seen from the main surface side, and a central portion and a peripheral portion surrounding the central portion are provided. When the semiconductor element is driven, the current density in the peripheral portion is higher than the current density in the central portion.

【0012】上記の構成によれば、半導体素子から表面
電極および外部配線を介して外部電極まで流れる電流の
電流密度が、中央部よりも周縁部の方が大きくなるた
め、放熱性が劣る表面電極の中央部の温度上昇を抑制す
ることが可能となることにより、半導体装置の長期的な
信頼性を向上させることができる。
According to the above structure, since the current density of the current flowing from the semiconductor element to the external electrode via the surface electrode and the external wiring is higher in the peripheral portion than in the central portion, the surface electrode having poor heat dissipation performance. Since it is possible to suppress the temperature rise in the central portion of the semiconductor device, it is possible to improve the long-term reliability of the semiconductor device.

【0013】本発明の第2の局面の半導体装置は、半導
体素子と、半導体素子の主表面に沿って設けられ、半導
体素子と電気的に接続された表面電極と、半導体素子の
外部に設けられた外部電極と、表面電極と外部電極とを
電気的に接続する外部配線とを備え、表面電極を、主表
面側から見て、中央部と中央部を取り囲む周縁部とに区
別した場合に、外部配線が周縁部にのみ接合されてい
る。
A semiconductor device according to a second aspect of the present invention is provided with a semiconductor element, a surface electrode provided along the main surface of the semiconductor element and electrically connected to the semiconductor element, and provided outside the semiconductor element. An external electrode, and an external wiring that electrically connects the surface electrode and the external electrode, and when the surface electrode is distinguished from the central portion and the peripheral portion surrounding the central portion when viewed from the main surface side, The external wiring is joined only to the peripheral portion.

【0014】上記の構成によれば、外部配線が周縁部に
のみ接合されているため、放熱性が劣る表面電極の中央
部の温度上昇を抑制することが可能となることにより、
半導体装置の長期的な信頼性を向上させることができ
る。
According to the above structure, since the external wiring is bonded only to the peripheral portion, it is possible to suppress the temperature rise of the central portion of the surface electrode having poor heat dissipation.
The long-term reliability of the semiconductor device can be improved.

【0015】本発明の第3の局面の半導体装置は、半導
体素子と、半導体素子の主表面に沿って設けられ、半導
体素子と電気的に接続された表面電極と、半導体素子の
外部に設けられた外部電極と、表面電極と外部電極とを
電気的に接続する複数の外部配線とを備え、複数の外部
配線が、表面電極を、中央部と中央部を取り囲む周縁部
とに区別した場合に、中央部と外部電極とを電気的に接
続する内側外部配線と、周縁部と外部電極とを電気的に
接続する外側外部配線とを含み、半導体素子から中央部
および内側外部配線を介して外部電極に至るまでの合成
抵抗が、半導体素子から周縁部および外側外部配線を介
して外部電極に至るまでの合成抵抗よりも大きくなるよ
うに構成されている。
A semiconductor device according to a third aspect of the present invention is provided with a semiconductor element, a surface electrode provided along the main surface of the semiconductor element and electrically connected to the semiconductor element, and provided outside the semiconductor element. An external electrode and a plurality of external wirings that electrically connect the surface electrode and the external electrode. When the plurality of external wirings distinguish the surface electrode into a central portion and a peripheral portion surrounding the central portion, An outer external wiring that electrically connects the central portion and the external electrode and an outer external wiring that electrically connects the peripheral portion and the external electrode. The combined resistance up to the electrode is configured to be larger than the combined resistance from the semiconductor element to the external electrode via the peripheral portion and the outer external wiring.

【0016】上記の構成によれば、半導体素子から中央
部および内側外部配線を介して外部電極に至るまでの合
成抵抗が、半導体素子から周縁部および外側外部配線を
介して外部電極に至るまでの合成抵抗よりも大きくなる
ように構成されているため、放熱性が劣る表面電極の中
央部の温度上昇を抑制することが可能となることによ
り、半導体装置の長期的な信頼性を向上させることがで
きる。
According to the above structure, the combined resistance from the semiconductor element to the external electrode via the central portion and the inner external wiring extends from the semiconductor element to the external electrode via the peripheral portion and the outer external wiring. Since it is configured to be larger than the combined resistance, it is possible to suppress the temperature rise in the central portion of the surface electrode, which has poor heat dissipation, thereby improving the long-term reliability of the semiconductor device. it can.

【0017】本発明の第4の局面の半導体装置は、半導
体素子と、半導体素子の主表面に沿って設けられ、半導
体素子と電気的に接続された表面電極と、半導体素子の
外部に設けられた外部電極と、表面電極と外部電極とを
電気的に接続する複数の外部配線とを備え、複数の外部
配線が、表面電極を、主表面側から見て、中央部と中央
部を取り囲む周縁部とに区別した場合に、中央部と外部
電極とを電気的に接続する内側外部配線と、周縁部と外
部電極とを電気的に接続する外側外部配線とを含み、内
側外部配線の抵抗が、外側外部配線の抵抗よりも大き
い。
A semiconductor device according to a fourth aspect of the present invention is provided with a semiconductor element, a surface electrode provided along the main surface of the semiconductor element and electrically connected to the semiconductor element, and provided outside the semiconductor element. An external electrode and a plurality of external wirings for electrically connecting the surface electrode and the external electrode, and the plurality of external wirings surround the central portion and the peripheral portion surrounding the central portion when the surface electrode is viewed from the main surface side. When divided into a portion, the inner external wiring that electrically connects the central portion and the external electrode and the outer external wiring that electrically connects the peripheral portion and the external electrode are included. , Greater than the resistance of the outer wiring.

【0018】上記の構成によれば、内側外部配線の抵抗
が、外側外部配線の抵抗よりも大きいため、放熱性が劣
る表面電極の中央部の温度上昇を抑制することが可能と
なることにより、半導体装置の長期的な信頼性を向上さ
せることができる。
According to the above structure, since the resistance of the inner external wiring is larger than the resistance of the outer external wiring, it is possible to suppress the temperature rise of the central portion of the surface electrode which is inferior in heat dissipation. The long-term reliability of the semiconductor device can be improved.

【0019】本発明の第5の局面の半導体装置は、半導
体素子と、半導体素子の主表面に沿って設けられ、半導
体素子と電気的に接続された表面電極と、半導体素子の
外部に設けられた外部電極と、表面電極と外部電極とを
電気的に接続する複数の外部配線とを備え、複数の外部
配線が、表面電極を、主表面側から見て、中央部と中央
部を取り囲む周縁部とに区別した場合に、中央部と外部
電極とを電気的に接続する内側外部配線と、周縁部と外
部電極とを電気的に接続する外側外部配線とを含み、外
側外部配線と周縁部との接合箇所数が、内側外部配線と
中央部との接合個所数よりも多く設けられている。
A semiconductor device according to a fifth aspect of the present invention is provided with a semiconductor element, a surface electrode provided along the main surface of the semiconductor element and electrically connected to the semiconductor element, and provided outside the semiconductor element. An external electrode and a plurality of external wirings for electrically connecting the surface electrode and the external electrode, and the plurality of external wirings surround the central portion and the peripheral portion surrounding the central portion when the surface electrode is viewed from the main surface side. The outer external wiring and the peripheral portion include the inner external wiring electrically connecting the central portion and the external electrode, and the outer external wiring electrically connecting the peripheral portion and the external electrode. The number of joints between the inner external wiring and the central portion is larger than the number of joints between the inner outer wiring and the central portion.

【0020】上記の構成によれば、外側外部配線と周縁
部との接合箇所数が、内側外部配線と中央部との接合個
所数よりも多く設けられているため、放熱性が劣る表面
電極の中央部の温度上昇を抑制することが可能となるこ
とにより、半導体装置の長期的な信頼性を向上させるこ
とができる。
According to the above construction, the number of joints between the outer outer wiring and the peripheral portion is larger than the number of joints between the inner outer wiring and the central portion. Since it is possible to suppress the temperature rise in the central portion, it is possible to improve the long-term reliability of the semiconductor device.

【0021】本発明の第6の局面の半導体装置は、半導
体素子と、半導体素子の主表面に沿って設けられ、半導
体素子と電気的に接続された表面電極と、半導体素子の
外部に設けられた外部電極と、表面電極と外部電極とを
電気的に接続する複数の外部配線とを備え、複数の外部
配線は、表面電極を、主表面側から見て、中央部と該中
央部を取り囲む周縁部とに区別した場合に、中央部と外
部電極とを電気的に接続する内側外部配線と、周縁部と
外部電極とを電気的に接続する外側外部配線とを含み、
周縁部の表面電極の厚さが、中央部の表面電極の厚さよ
りも大きくなるように構成されている。
A semiconductor device according to a sixth aspect of the present invention is provided with a semiconductor element, a surface electrode provided along the main surface of the semiconductor element and electrically connected to the semiconductor element, and provided outside the semiconductor element. External electrodes and a plurality of external wirings that electrically connect the surface electrodes to the external electrodes. The plurality of external wirings surround the central portion and the central portion when the surface electrodes are viewed from the main surface side. When distinguished into a peripheral portion, including an inner external wiring electrically connecting the central portion and the external electrode, and an outer external wiring electrically connecting the peripheral portion and the external electrode,
The thickness of the surface electrode in the peripheral portion is larger than the thickness of the surface electrode in the central portion.

【0022】上記の構成によれば、周縁部の表面電極の
厚さが、中央部の表面電極の厚さよりも大きくなるよう
に構成されているため、放熱性が劣る表面電極の中央部
の温度上昇を抑制することが可能となることにより、半
導体装置の長期的な信頼性を向上させることができる。
According to the above structure, since the thickness of the surface electrode at the peripheral portion is larger than the thickness of the surface electrode at the central portion, the temperature at the central portion of the surface electrode having poor heat dissipation is poor. Since the rise can be suppressed, the long-term reliability of the semiconductor device can be improved.

【0023】本発明の第7の局面の半導体装置は、半導
体素子と、半導体素子の表面に設けられ、半導体素子と
電気的に接続された表面電極と、半導体素子の外部に設
けられた外部電極と、表面電極と外部電極とを電気的に
接続する外部配線とを備え、表面電極が、密接して形成
されたストライプ状の複数の部分表面電極を含み、複数
の部分表面電極が、表面電極を、中央部と中央部を取り
囲む周縁部とに区別した場合に、中央部および周縁部の
双方を横断する内側部分表面電極と、周縁部のみに位置
する外側部分表面電極とを有し、外部配線と外側部分表
面電極との接合箇所数が、外部配線と内側部分表面電極
との接合個所数よりも多く設けられている。
A semiconductor device according to a seventh aspect of the present invention is a semiconductor element, a surface electrode provided on the surface of the semiconductor element and electrically connected to the semiconductor element, and an external electrode provided outside the semiconductor element. And an external wiring for electrically connecting the surface electrode and the external electrode, the surface electrode includes a plurality of striped partial surface electrodes formed in close contact, and the plurality of partial surface electrodes are the surface electrodes. Is divided into a central portion and a peripheral portion surrounding the central portion, and has an inner partial surface electrode that traverses both the central portion and the peripheral portion, and an outer partial surface electrode that is located only in the peripheral portion. The number of joints between the wiring and the outer partial surface electrode is larger than the number of joints between the outer wiring and the inner partial surface electrode.

【0024】上記の構成によれば、外部配線と外側部分
表面電極との接合箇所数が、外部配線と内側部分表面電
極との接合個所数よりも多く設けられているため、放熱
性が劣る表面電極の中央部の温度上昇を抑制することが
可能となることにより、半導体装置の長期的な信頼性を
向上させることができる。
According to the above structure, the number of joints between the external wiring and the outer surface electrode is larger than the number of joints between the outer wiring and the inner surface electrode. Since it is possible to suppress the temperature rise in the central portion of the electrode, it is possible to improve the long-term reliability of the semiconductor device.

【0025】本発明の第1の局面〜第7の局面の半導体
装置は、表面電極の主表面は長方形であり、周縁部が、
長方形と対角線の交点が共通であるとともに、縦横それ
ぞれの辺の長さが長方形の2/5となる仮想長方形の外
側の部分であれば、以下の実施の形態で示すように、中
央部と周縁部とを区別する位置の臨界的意義が明確にな
る。
In the semiconductor device according to the first aspect to the seventh aspect of the present invention, the main surface of the surface electrode is rectangular, and the peripheral portion is
As long as the intersection of the rectangle and the diagonal line is common and the length of each of the vertical and horizontal sides is 2/5 of the rectangle, it is the outer portion of the virtual rectangle. The critical significance of the position that distinguishes the part becomes clear.

【0026】なお、上記第1の局面から第7の局面まで
の本発明を適宜組み合わせて使用してもよい。このよう
にすることにより、第1の局面から第7の局面までの発
明の効果を足し合わせることができる。
The present inventions of the first aspect to the seventh aspect may be appropriately combined and used. By doing so, the effects of the inventions of the first aspect to the seventh aspect can be added.

【0027】[0027]

【発明の実施の形態】以下、図に基づいて、発明の実施
の形態を説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

【0028】(実施の形態1)図1は、実施の形態1の
パワー半導体モジュールの表面電極2と金属ワイヤ4と
の接合形態を示す斜視図であり、図1には、主表面が長
方形状の半導体素子1と、この半導体素子1の主表面に
接して設けられ、この半導体素子1の主表面と大きさお
よび形状が一致する長方形状の主表面を有する表面電極
2と、半導体素子の外部に設けられた外部電極3と、表
面電極2と外部電極3とを電気的に接続する金属ワイヤ
4とが示されている。また、表面電極2は、複数のスト
ライプ状の部分表面電極20に分割されている。
(Embodiment 1) FIG. 1 is a perspective view showing a bonding form of a surface electrode 2 and a metal wire 4 of a power semiconductor module according to Embodiment 1. In FIG. 1, the main surface has a rectangular shape. Of the semiconductor element 1, a surface electrode 2 provided in contact with the main surface of the semiconductor element 1 and having a rectangular main surface having the same size and shape as the main surface of the semiconductor element 1, and the exterior of the semiconductor element. There is shown an external electrode 3 provided on the surface and a metal wire 4 for electrically connecting the surface electrode 2 and the external electrode 3. The surface electrode 2 is divided into a plurality of stripe-shaped partial surface electrodes 20.

【0029】本実施の形態では、表面電極2の厚みは表
面電極2の主表面の全域にわたって均一であるものとす
る。複数のストライプ状の部分表面電極20は、外側に
位置する部分表面電極20と内側に位置する内側部分表
面電極20とがあり、外側の部分表面電極20には3箇
所で、内側の部分表面電極20には2箇所で、金属ワイ
ヤ4が接合されている。なお、金属ワイヤは同じ種類の
金属ワイヤであるため、長さおよび断面積が同じであれ
ば、同じ抵抗になるものとする。
In the present embodiment, the thickness of front surface electrode 2 is assumed to be uniform over the entire main surface of front surface electrode 2. The plurality of stripe-shaped partial surface electrodes 20 include an outer partial surface electrode 20 and an inner partial surface electrode 20. The outer partial surface electrode 20 has three internal surface electrodes. The metal wire 4 is joined to 20 at two locations. Since the metal wires are the same kind of metal wire, they have the same resistance if they have the same length and cross-sectional area.

【0030】従来の表面電極と金属ワイヤとの接合形態
では、図19に示したように、表面電極2の中央部、す
なわち、表面電極2の長方形状の主表面の対角線の交点
付近の温度が高くなる。そのため、本発明者は、表面電
極2の中央部の電流密度を低減することにより、半導体
素子1の表面電極2の温度分布の均一化を図ることが有
効であることを見出した。そして、それを実現するため
に、表面電極2のピーク温度を低減する、言いかえれ
ば、放熱性に劣る表面電極2の中央部の温度上昇を抑制
する表面電極2と金属ワイヤ4との接合形態を発明し
た。
In the conventional joining mode of the surface electrode and the metal wire, as shown in FIG. 19, the temperature in the central portion of the surface electrode 2, that is, in the vicinity of the intersection of the diagonal lines of the rectangular main surface of the surface electrode 2, is Get higher Therefore, the present inventor has found that it is effective to reduce the current density at the central portion of the surface electrode 2 so as to make the temperature distribution of the surface electrode 2 of the semiconductor element 1 uniform. Then, in order to realize it, the peak temperature of the surface electrode 2 is reduced, in other words, the bonding form between the surface electrode 2 and the metal wire 4 which suppresses the temperature rise of the central portion of the surface electrode 2 having poor heat dissipation. Invented

【0031】また、3次元の電気回路網と熱回路網によ
る連成解析により、その接合形態の妥当性を検証した。
図1に示した接合形態はその一例である。
Further, the validity of the joint form was verified by a coupled analysis using a three-dimensional electric circuit network and a thermal circuit network.
The joining form shown in FIG. 1 is an example thereof.

【0032】本実施の形態では、図1に示すように、外
部電極3と半導体素子1とを電気的に接続するための、
金属ワイヤ4と表面電極2との接合箇所数に関し、外側
に位置する部分表面電極20と金属ワイヤ4との接合箇
所数を、内側の部分表面電極20と金属ワイヤ4との接
合箇所数より多くすることにより、各部分表面電極20
間に電流密度の分布を生じさせ、内側の部分表面電極2
0を流れる電流の密度が、外側の部分表面電極20を流
れる電流の密度よりも小さくなるようにした。
In the present embodiment, as shown in FIG. 1, for electrically connecting the external electrode 3 and the semiconductor element 1,
Regarding the number of joints between the metal wire 4 and the surface electrode 2, the number of joints between the outer partial surface electrode 20 and the metal wire 4 is larger than the number of joints between the inner partial surface electrode 20 and the metal wire 4. By doing so, each partial surface electrode 20
A current density distribution is generated between the two, and the inner partial surface electrode 2
The density of the current flowing through 0 is set to be smaller than the density of the current flowing through the outer partial surface electrode 20.

【0033】また、図1に示す接合形態では、内側の部
分表面電極20と金属ワイヤ4との接合箇所を部分表面
電極20端部の2箇所としているため、内側に位置する
部分表面電極20と金属ワイヤ4との接合個所の温度上
昇を抑制することができる。その結果、放熱性が劣る表
面電極2の中央部の温度上昇を抑制することが可能とな
る。さらに、表面電極2の中央部、すなわち内側に位置
する部分表面電極20の中央部には金属ワイヤ4が接合
されていないため、表面電極2の中央部の電流密度をさ
らに低減することができる。
Further, in the joining form shown in FIG. 1, since the joining portions of the inner partial surface electrode 20 and the metal wire 4 are two places of the end portion of the partial surface electrode 20, the inner partial surface electrode 20 and the inner portion of the partial surface electrode 20 are joined. It is possible to suppress an increase in the temperature at the joint with the metal wire 4. As a result, it becomes possible to suppress the temperature rise in the central portion of the surface electrode 2 which has poor heat dissipation. Furthermore, since the metal wire 4 is not bonded to the central portion of the surface electrode 2, that is, the central portion of the partial surface electrode 20 located inside, the current density in the central portion of the surface electrode 2 can be further reduced.

【0034】なお、パワー半導体モジュールとして、表
面電極2が複数のストライプ状の部分表面電極20より
構成されているIGBTチップを例に、直流電流通電時
におけるIGBTチップ表面上の温度分布を、3次元の
電気回路網と熱回路網による連成解析を行った。
As an example of an IGBT chip in which the surface electrode 2 is composed of a plurality of stripe-shaped partial surface electrodes 20 as a power semiconductor module, the temperature distribution on the surface of the IGBT chip when a direct current is applied is shown three-dimensionally. We conducted a coupled analysis of the electric circuit network and the thermal circuit network.

【0035】今回は、半導体素子としてIGBTを例に
挙げ、また、表面電極2は、10本のストライプ状の部
分表面電極20で構成されているものとした。また、外
側の部分表面電極20と金属ワイヤ4との接合箇所は3
箇所、内側の部分表面電極20と金属ワイヤ4との接合
箇所は2箇所とし、IGBTの表面電極2の厚さは均一
としている。
This time, an IGBT is taken as an example of the semiconductor element, and the surface electrode 2 is composed of 10 striped partial surface electrodes 20. Also, the number of joints between the outer partial surface electrode 20 and the metal wire 4 is 3
The number of joints between the inner surface electrode 20 and the metal wire 4 is two, and the thickness of the surface electrode 2 of the IGBT is uniform.

【0036】また、前述の連成解析の解析結果を等高線
図で示したものが図2である。図2においては、部分表
面電極20と金属ワイヤ4との接合箇所9が示されてい
る。また、図2においては、表面電極2の表面の温度を
示す等高線が1℃刻みで表示されており、また、11
4、116、118、120、122、124といった
数字により各等高線における温度が示されている。即
ち、図2には、125℃までの温度が等高線で示されて
おり、表面電極2と金属ワイヤ4との接合部における温
度の最大値は124.2℃となるという解析結果が得ら
れた。なお、解析条件は表面電極2(部分表面電極2
0)と金属ワイヤ4との接合箇所が違う点を除けば、従
来技術で示したものに対する解析条件と同一である。
FIG. 2 is a contour diagram showing the analysis result of the above-mentioned coupled analysis. In FIG. 2, a joint portion 9 between the partial surface electrode 20 and the metal wire 4 is shown. Further, in FIG. 2, contour lines showing the temperature of the surface of the surface electrode 2 are displayed in steps of 1 ° C., and 11
The numbers at 4, 116, 118, 120, 122, 124 indicate the temperature at each contour line. That is, in FIG. 2, the temperature up to 125 ° C. is indicated by contour lines, and the analysis result that the maximum value of the temperature at the joint between the surface electrode 2 and the metal wire 4 is 124.2 ° C. was obtained. . The analysis conditions are the surface electrode 2 (partial surface electrode 2
0) and the metal wire 4 are joined at different points, except that the analysis conditions are the same as those for the prior art.

【0037】このように、図1に示すような表面電極2
と金属ワイヤ4との接合形態にすることにより、図19
に示した従来例の表面電極102と金属ワイヤ104と
の接合形態よりも、表面電極2の中央部の温度の最大値
を9.7℃低下させることができる。したがって、放熱
性に劣る表面電極2の中央部の温度上昇を抑制する効果
が得られている。
Thus, the surface electrode 2 as shown in FIG.
19 and the metal wire 4 are joined together.
It is possible to lower the maximum value of the temperature of the central portion of the surface electrode 2 by 9.7 ° C. as compared with the conventional bonding example of the surface electrode 102 and the metal wire 104 shown in FIG. Therefore, the effect of suppressing the temperature rise of the central portion of the surface electrode 2 which is inferior in heat dissipation is obtained.

【0038】このように、金属ワイヤ4と表面電極2と
の接合形態において、外側に位置する部分表面電極20
と金属ワイヤ4との接合箇所数を、内側に位置する部分
表面電極20と金属ワイヤ4との接合箇所数より多くす
ることにより、また、表面電極2の中央部には金属ワイ
ヤ4が接合されていないことにより、放熱性が劣る表面
電極2の中央部の電流密度を低減することができる。そ
のため、放熱性が劣る表面電極2の中央部の温度上昇を
抑制することができる。その結果、長期的信頼性の優れ
たパワー半導体モジュールを提供することができる。
As described above, in the bonding mode of the metal wire 4 and the surface electrode 2, the partial surface electrode 20 located outside
By making the number of joints between the metal wire 4 and the metal wire 4 larger than the number of joints between the partial surface electrode 20 and the metal wire 4 located inside, the metal wire 4 is joined to the central portion of the surface electrode 2. By not doing so, it is possible to reduce the current density in the central portion of the surface electrode 2 which is inferior in heat dissipation. Therefore, it is possible to suppress the temperature rise of the central portion of the surface electrode 2 which is inferior in heat dissipation. As a result, a power semiconductor module having excellent long-term reliability can be provided.

【0039】なお、図1に示すパワー半導体モジュール
の表面電極2と金属ワイヤ4との接合形態では、半導体
素子1の外側のストライプ状の部分表面電極20と金属
ワイヤ4との接合箇所を3箇所としているが、金属ワイ
ヤ4と2箇所で接合されている内側の部分表面電極20
より接合箇所数が多ければ、外側の部分表面電極20に
流れる電流密度が高くなり、同様の効果が得られるた
め、外側のストライプ状の部分表面電極20と金属ワイ
ヤ4との接合箇所は3箇所以上であればよい。
In the joining mode of the surface electrode 2 and the metal wire 4 of the power semiconductor module shown in FIG. 1, there are three joining points between the striped partial surface electrode 20 and the metal wire 4 on the outside of the semiconductor element 1. However, the inner partial surface electrode 20 is joined to the metal wire 4 at two points.
If the number of joints is larger, the current density flowing in the outer partial surface electrode 20 becomes higher, and the same effect is obtained. Therefore, there are three joints between the outer striped partial surface electrode 20 and the metal wire 4. The above is sufficient.

【0040】また、図1では、各部分表面電極20と各
金属ワイヤ4とを一箇所のみで接合するとともに、外側
の部分表面電極20に対しては3本の金属ワイヤ4を、
内側の部分表面電極20に対しては2本の金属ワイヤ4
を接合した形態を用いたが、金属ワイヤ4の使用本数や
表面電極2と金属ワイヤ4との接合形態については図1
に示すものに限定されるものではない。たとえば、金属
ワイヤ4の径や長さ、または、半導体素子1を流れる電
流値によって決まる設計基準を満足する限り、図3に示
すように、全ての部分表面電極20に対して1本の金属
ワイヤ4で連続的に接合してもよい。他にも、図4〜図
9に示すような様々なバリエーションが考えられる。
Further, in FIG. 1, each partial surface electrode 20 and each metal wire 4 are joined at only one place, and three metal wires 4 are connected to the outer partial surface electrode 20.
Two metal wires 4 for the inner partial surface electrode 20.
Although the form in which the metal wires 4 are joined is used, the number of used metal wires 4 and the form in which the surface electrodes 2 and the metal wires 4 are joined are shown in FIG.
It is not limited to those shown in. For example, as long as the design criteria determined by the diameter and length of the metal wire 4 or the current value flowing through the semiconductor element 1 is satisfied, one metal wire is provided for all the partial surface electrodes 20 as shown in FIG. You may join continuously at 4. Besides, various variations as shown in FIGS. 4 to 9 are possible.

【0041】例えば、図4に示す接合形態では、外側の
部分表面電極20には1本の金属ワイヤ4が連続的に3
箇所で接合され、内側の部分表面電極20には2本の金
属ワイヤ4が用いられ、それぞれの金属ワイヤ4は、内
側の部分表面電極20端部に1箇所で接合されている。
For example, in the joining form shown in FIG. 4, one metal wire 4 is continuously connected to the outer partial surface electrode 20 by three wires.
Two metal wires 4 are used for the inner partial surface electrode 20 and are joined at one place, and each metal wire 4 is joined to the end of the inner partial surface electrode 20 at one place.

【0042】また、図5、図6に示す接合形態では、全
ての部分表面電極20に2本の金属ワイヤ4が接合され
ており、内側の部分表面電極20にはそれぞれの金属ワ
イヤ4が部分表面電極20端部の1箇所で接合されるの
に対し、外側の部分表面電極20には、一方の金属ワイ
ヤ4が部分表面電極20の一方の端部および中央部の2
箇所で連続的に接合され、他方の金属ワイヤ4は、部分
表面電極20の他方の端部と接合されている。
Further, in the joining modes shown in FIGS. 5 and 6, two metal wires 4 are joined to all the partial surface electrodes 20, and each metal wire 4 is partially joined to the inner partial surface electrode 20. While the surface electrode 20 is bonded at one end, the outer partial surface electrode 20 is provided with one metal wire 4 at one end of the partial surface electrode 20 and at the center.
The metal wires 4 are continuously bonded at the points, and the other metal wire 4 is bonded to the other end of the partial surface electrode 20.

【0043】また、図7に示す接合形態では、外側の部
分表面電極20には、3本の金属ワイヤ4がそれぞれ1
箇所で接合され、内側の部分表面電極20には1本の金
属ワイヤ4が連続的に2箇所で接合されている。
Further, in the joining form shown in FIG. 7, the outer partial surface electrode 20 has three metal wires 4 each.
One metal wire 4 is continuously joined to the inner partial surface electrode 20 at two places.

【0044】また、図8、図9に示す形態では、外側の
部分表面電極20には、2本の金属ワイヤ4を用い、一
方の金属ワイヤ4が部分表面電極20の一方の端部と中
央部の2箇所で連続的に接合され、他方の金属ワイヤ4
が部分表面電極20の他方の端部と接合されるのに対し
て、内側の部分表面電極20には、1本の金属ワイヤ4
が連続的に2箇所で接合されている。
Further, in the embodiment shown in FIGS. 8 and 9, two metal wires 4 are used for the outer partial surface electrode 20, and one metal wire 4 is formed at one end and the center of the partial surface electrode 20. Part of the metal wire 4 which is continuously joined at two points
Is bonded to the other end of the partial surface electrode 20, while one metal wire 4 is attached to the inner partial surface electrode 20.
Are continuously joined at two points.

【0045】さらに、本実施の形態では、半導体素子1
の表面にストライプ状の部分表面電極20が設けられた
IGBTチップを例に説明してきたが、必ずしもストラ
イプ状の部分表面電極20である必要はなく、また、I
GBT以外の他の半導体素子についても同様に、放熱性
に劣る表面電極の中央部の温度上昇を抑制する効果が得
られる。
Furthermore, in the present embodiment, the semiconductor element 1
The IGBT chip in which the striped partial surface electrode 20 is provided on the surface of the above has been described as an example, but the striped partial surface electrode 20 is not necessarily required.
Similarly, with respect to semiconductor elements other than the GBT, the effect of suppressing the temperature rise in the central portion of the surface electrode having poor heat dissipation can be obtained.

【0046】また、本実施の形態においては、図10に
示すように、表面電極2と金属ワイヤ4との接合箇所を
設ける周縁部が、表面電極2の主表面の長方形と対角線
の交点が共通するとともに、縦横それぞれの辺の長さが
長方形の2/5となる長方形Xを仮に想定した場合に、
この仮想の長方形Xよりも外側の部分である。
Further, in the present embodiment, as shown in FIG. 10, the peripheral portion where the joining portion of the surface electrode 2 and the metal wire 4 is provided has a common intersection of the rectangle and the diagonal line of the main surface of the surface electrode 2. In addition, if a rectangle X in which the length of each side is 2/5 of the rectangle is assumed,
It is a portion outside the virtual rectangle X.

【0047】このように仮想長方形Xの外側の周縁部に
表面電極2と金属ワイヤ4との接合箇所を設けることに
より、表面電極2の中央部の温度上昇を抑制する効果を
効率的に得ることができることは、3次元の電気回路網
と熱回路網による連成解析により検証済であり、その検
証結果を図10を用いて説明する。
By thus providing the joint portion between the surface electrode 2 and the metal wire 4 on the outer peripheral edge of the virtual rectangle X, the effect of suppressing the temperature rise of the central portion of the surface electrode 2 can be efficiently obtained. It has been verified by the coupled analysis of the three-dimensional electric circuit network and the thermal circuit network that the above can be achieved, and the verification result will be described with reference to FIG.

【0048】図10は、表面電極2の主表面を構成する
長方形の縦方向の一辺の長さをa、表面電極2の中央部
の金属ワイヤ4を接合しない領域を構成する長方形の縦
方向の一辺の長さを2dとした時の、表面電極2と金属
ワイヤ4との接合部の温度の最大値を、d/aをパラメ
ータとしてプロットしたものであり、d/aを増加させ
ると、表面電極2と金属ワイヤ4との接合部の温度の最
大値は常に低下するが、d/a=0.2以上となると、
表面電極2と金属ワイヤ4との接合部の温度上昇抑制効
果が低減する。この結果より、表面電極2の主表面が構
成する長方形と対角線の交点が共通であるとともに、縦
横それぞれの辺の長さが長方形の2/5となる仮想長方
形Xの外側の周縁部に表面電極2と金属ワイヤ4との接
合箇所を設ければ、表面電極2の中央部の温度上昇を抑
制する効果を効率的に得られることが分かる。
In FIG. 10, the length of one side in the vertical direction of the rectangle forming the main surface of the surface electrode 2 is a, and the length in the vertical direction of the rectangle forming the region where the metal wire 4 in the central portion of the surface electrode 2 is not bonded is shown. The maximum value of the temperature of the joint between the surface electrode 2 and the metal wire 4 when the length of one side is 2d is plotted using d / a as a parameter. Although the maximum value of the temperature at the joint between the electrode 2 and the metal wire 4 is constantly reduced, when d / a = 0.2 or more,
The effect of suppressing the temperature rise at the joint between the surface electrode 2 and the metal wire 4 is reduced. From this result, the rectangle formed by the main surface of the surface electrode 2 and the intersection of the diagonal line are common, and the surface electrode is formed on the outer peripheral edge of the virtual rectangle X in which the length of each side is 2/5 of the rectangle. It is understood that the effect of suppressing the temperature rise in the central portion of the front surface electrode 2 can be efficiently obtained by providing the joint portion between the metal wire 4 and the metal wire 4.

【0049】(実施の形態2)図11は、実施の形態2
のパワー半導体モジュールの表面電極2と金属ワイヤ4
との接合形態を示す斜視図である。図11においては、
表面電極2の中央部の厚さを周縁部の厚さより小さくし
た領域20aを有する表面電極2(ストライプ状の部分
表面電極20の集合)が示されている。また、図11に
は、表面電極2と金属ワイヤ4との接合箇所9が示され
ている。図1に示す接合形態では、表面電極2の厚さを
一定としていたが、表面電極2の厚さは必ずしも均一で
ある必要はない。
(Second Embodiment) FIG. 11 shows a second embodiment.
Power semiconductor module surface electrode 2 and metal wire 4
It is a perspective view which shows the joining form with. In FIG. 11,
The surface electrode 2 (a group of stripe-shaped partial surface electrodes 20) having a region 20a in which the thickness of the central portion of the surface electrode 2 is smaller than the thickness of the peripheral portion is shown. Further, FIG. 11 shows a joint portion 9 between the surface electrode 2 and the metal wire 4. In the bonding form shown in FIG. 1, the thickness of the surface electrode 2 is constant, but the thickness of the surface electrode 2 does not necessarily have to be uniform.

【0050】表面電極2の厚さを場所ごとに変える場
合、表面電極2の厚さを大きくすることにより、表面電
極2の主表面に平行な方向の抵抗を小さくし、かつ、表
面電極2の主表面に垂直方向の抵抗を大きくすることが
できため、半導体素子1から流れてきた電流を表面電極
2の主表面に沿って表面電極2の全体に拡散させること
ができる。なお、本実施の形態においては、表面電極2
を構成する部分表面電極20は同じ種類の金属電極を用
いるため、厚さが同じであれば、同じ抵抗になるものと
する。
When the thickness of the surface electrode 2 is changed from place to place, the resistance in the direction parallel to the main surface of the surface electrode 2 is reduced by increasing the thickness of the surface electrode 2 and Since the resistance in the direction perpendicular to the main surface can be increased, the current flowing from the semiconductor element 1 can be diffused along the main surface of the surface electrode 2 to the entire surface electrode 2. In this embodiment, the surface electrode 2
Since the same kind of metal electrode is used for the partial surface electrodes 20 constituting the above, if the thicknesses are the same, the resistances are the same.

【0051】さらに、表面電極2の周縁部の厚さが小さ
い領域20a以外の領域にのみ金属ワイヤ4を接合して
いる。このように、表面電極2の中央部の厚さを小さく
し、言いかえれば、周縁部の表面電極2の厚さを大きく
し、また、半導体素子1の周縁部の表面電極2の厚さが
小さい領域20a以外の周縁部の領域にのみ金属ワイヤ
4を接合することにより、表面電極2の中央部、すなわ
ち、表面電極2の長方形状の主表面の対角線の交点付近
の電流密度を低減することができるため、放熱性が劣る
表面電極2の中央部の温度上昇を抑制することが可能と
なる。
Further, the metal wire 4 is bonded only to the region other than the region 20a where the peripheral portion of the surface electrode 2 has a small thickness. In this way, the thickness of the central portion of the surface electrode 2 is reduced, in other words, the thickness of the surface electrode 2 at the peripheral portion is increased, and the thickness of the surface electrode 2 at the peripheral portion of the semiconductor element 1 is reduced. By reducing the current density in the central portion of the surface electrode 2, that is, in the vicinity of the intersection of the diagonal lines of the rectangular main surface of the surface electrode 2, by bonding the metal wire 4 only to the peripheral area other than the small area 20a. Therefore, it is possible to suppress the temperature rise of the central portion of the front surface electrode 2 having poor heat dissipation.

【0052】図12は、図11に示すような半導体素子
1に10本のストライプ状の部分表面電極20を設けた
IGBTチップの、半導体素子1に直流電流を通電した
時のIGBTチップの表面電極2の温度分布を、3次元
の電気回路網と熱回路網による連成解析結果を図示した
ものである。
FIG. 12 shows a surface electrode of an IGBT chip in which ten stripe-shaped partial surface electrodes 20 are provided on the semiconductor device 1 as shown in FIG. 11 when a direct current is applied to the semiconductor device 1. 2 shows the temperature distribution of No. 2 as a result of a coupled analysis by a three-dimensional electric circuit network and a thermal circuit network.

【0053】この解析結果を得るために用いたパワー半
導体モジュールは、図11に示したものと同様に、外側
の部分表面電極20と金属ワイヤ4との接合箇所は3箇
所、内側の部分表面電極20と金属ワイヤ4との接合箇
所は2箇所である。また、IGBTの表面電極2の周縁
部の厚さを中央部の厚さよりも大きくしている。
The power semiconductor module used for obtaining this analysis result is similar to the one shown in FIG. 11 in that the outer partial surface electrode 20 and the metal wire 4 are joined at three places and the inner partial surface electrode is joined. There are two bonding points between the metal wire 20 and the metal wire 4. Further, the thickness of the peripheral portion of the surface electrode 2 of the IGBT is made larger than the thickness of the central portion.

【0054】図12においては、表面電極2の中央部の
領域であって、周縁部より厚さを小さくした領域20a
を有する表面電極2が示されている。図2と同様に、表
面電極2の表面の温度を示す等高線は1℃刻みで表示さ
れ、114、116、118、120、122、124
といった数字により各等高線における温度が示されてい
る。図12では、124℃までの温度が等高線で示され
ており、表面電極2の表面の温度は、長方形の主表面の
ほぼ全ての領域にわたって125℃以下となり、表面電
極2と金属ワイヤ4との接合部における温度の最大値は
123.9℃となり、実施の形態1の接合形態よりも、
さらに、放熱性に劣る表面電極の中央部の温度上昇を抑
制することができたことになる。
In FIG. 12, a region 20a which is a central region of the surface electrode 2 and has a smaller thickness than the peripheral region thereof.
The front surface electrode 2 with is shown. Similar to FIG. 2, contour lines showing the temperature of the surface of the surface electrode 2 are displayed in steps of 1 ° C., and 114, 116, 118, 120, 122, 124.
The temperature at each contour line is indicated by a number such as. In FIG. 12, the temperature up to 124 ° C. is indicated by contour lines, and the temperature of the surface of the surface electrode 2 is 125 ° C. or lower over almost the entire area of the rectangular main surface, and the surface electrode 2 and the metal wire 4 are separated from each other. The maximum value of the temperature at the joint is 123.9 ° C., which is higher than that of the first embodiment.
Further, it means that the temperature rise in the central portion of the surface electrode, which is inferior in heat dissipation, can be suppressed.

【0055】このように、表面電極2の周縁部の厚さを
中央部の厚さより大きくし、かつ、表面電極2の周縁部
にのみ金属ワイヤ4を接合することにより、放熱性が劣
る表面電極2の中央部の電流密度を低減することができ
るため、表面電極2の中央部の温度上昇を抑制すること
が可能である。
As described above, by making the thickness of the peripheral portion of the surface electrode 2 larger than the thickness of the central portion and bonding the metal wire 4 only to the peripheral portion of the surface electrode 2, the surface electrode having a poor heat dissipation property. Since the current density in the central portion of 2 can be reduced, it is possible to suppress the temperature rise in the central portion of the surface electrode 2.

【0056】なお、図11に示すパワー半導体モジュー
ルの表面電極2と金属ワイヤ4との接合形態では、外側
の部分表面電極20と金属ワイヤ4との接合箇所を3箇
所としているが、金属ワイヤ4が2箇所で接合されてい
る内側の部分表面電極20より接合箇所が多ければ、外
側の部分表面電極20に流れる電流が大きくなり、同様
の効果が得られるため、外側の部分表面電極20と金属
ワイヤ4との接合箇所は3箇所以上であれば図11に示
す形態には限定されない。
In the joining form of the surface electrode 2 and the metal wire 4 of the power semiconductor module shown in FIG. 11, the outer partial surface electrode 20 and the metal wire 4 are joined at three places. If there are more joints than the inner partial surface electrode 20 that is joined at two locations, the current flowing through the outer partial surface electrode 20 becomes large, and the same effect can be obtained. The number of joints with the wire 4 is not limited to the form shown in FIG. 11 as long as it is three or more.

【0057】また、図11では、各部分表面電極20に
対し各金属ワイヤ4は一箇所のみで接合するとともに、
外側の部分表面電極20に対しては3本の金属ワイヤ4
を、内側の部分表面電極20に対しては2本の金属ワイ
ヤを使用した例を示しているが、金属ワイヤ4の使用本
数や接合形態についてはこの限りではなく、金属ワイヤ
4の径や、半導体素子を流れる電流値によって決まる設
計基準を満足する限り、図3に示すように全ての部分表
面電極20に対して1本の金属ワイヤ4で連続的に接合
してもよい。他にも、図4〜図9に示すような様々なバ
リエーションが考えられる。
Further, in FIG. 11, each metal wire 4 is joined to each partial surface electrode 20 at only one place, and
Three metal wires 4 for the outer partial surface electrode 20.
Although the example in which two metal wires are used for the inner partial surface electrode 20 is shown, the number of metal wires 4 to be used and the bonding form are not limited to this, and the diameter of the metal wire 4 and As long as the design criteria determined by the current value flowing through the semiconductor element is satisfied, one metal wire 4 may be continuously bonded to all the partial surface electrodes 20 as shown in FIG. Besides, various variations as shown in FIGS. 4 to 9 are possible.

【0058】さらに、本実施の形態では、半導体素子1
にストライプ状の部分表面電極20が設けられたIGB
Tチップを例に説明してきたが、必ずしもストライプ状
の部分表面電極20である必要はなく、また、IGBT
以外の他の半導体素子1についても同様に、放熱性に劣
る表面電極2の中央部の温度上昇を抑制する効果が得ら
れる。
Further, in the present embodiment, the semiconductor device 1
IGB in which a striped partial surface electrode 20 is provided on
Although the T-chip has been described as an example, the stripe-shaped partial surface electrode 20 does not necessarily have to be used.
Other semiconductor elements 1 other than the above can similarly obtain the effect of suppressing the temperature rise of the central portion of the surface electrode 2 having poor heat dissipation.

【0059】また、本実施の形態においては、表面電極
2の主表面は長方形であり、表面電極2の厚さが大きい
周縁部が、長方形と対角線の交点を共通するとともに、
縦横それぞれの辺の長さが長方形の2/5となる仮想長
方形Xの外側の部分である。このように仮想長方形Xの
外側の周縁部の厚さを仮想長方形Xの内側の中央部の厚
さよりも大きくすることにより、表面電極2の中央部の
温度上昇を効率的に抑制することができることは、3次
元の電気回路網と熱回路網による連成解析により検証済
であり、その検証結果を図13を用いて説明する。
Further, in the present embodiment, the main surface of the surface electrode 2 is rectangular, and the peripheral portion of the surface electrode 2 having a large thickness has the intersection of the rectangle and the diagonal line in common, and
It is an outer portion of the virtual rectangle X in which the length of each of the vertical and horizontal sides is 2/5 of the rectangle. As described above, by making the thickness of the outer peripheral portion of the virtual rectangle X larger than the thickness of the inner central portion of the virtual rectangle X, it is possible to efficiently suppress the temperature rise of the central portion of the surface electrode 2. Has been verified by a coupled analysis with a three-dimensional electric circuit network and a thermal circuit network, and the verification result will be described with reference to FIG.

【0060】図13は、表面電極2を構成する長方形状
の主表面の縦方向の一辺の長さをa、表面電極2の中央
部の厚さを周縁部より小さくする長方形の領域の縦方向
の一辺を2dとした時の、表面電極2と金属ワイヤ4と
の接合部の温度の最大値を、d/aをパラメータとして
プロットしたものであり、d/aを増加させると、表面
電極2と金属ワイヤ4との接合部の温度の最大値は常に
低下するが、d/a=0.2以上となると、表面電極1
と金属ワイヤ4との接合部の温度上昇を抑制する効果が
低減する。この結果より、表面電極2の主表面が構成す
る長方形と対角線の交点が共通であるとともに、縦横そ
れぞれの辺の長さが長方形の2/5となる仮想長方形X
の外側の周縁部の厚さを大きくすれば、放熱性に劣る表
面電極2の中央部の温度上昇を抑制する効果を効率的に
得ることができることが分かる。
FIG. 13 is a longitudinal direction of a rectangular area in which the length of one side in the vertical direction of the rectangular main surface forming the surface electrode 2 is a and the thickness of the central portion of the surface electrode 2 is smaller than the peripheral portion. The maximum value of the temperature of the joint between the surface electrode 2 and the metal wire 4 when one side is 2d is plotted with d / a as a parameter. When d / a is increased, the surface electrode 2 The maximum value of the temperature at the joint between the metal wire 4 and the metal wire 4 always decreases, but when d / a = 0.2 or more, the surface electrode
The effect of suppressing the temperature rise at the joint between the metal wire 4 and the metal wire 4 is reduced. From this result, a virtual rectangle X in which the rectangle formed by the main surface of the surface electrode 2 has a common intersection of diagonal lines and the lengths of the vertical and horizontal sides are 2/5 of the rectangle.
It can be seen that if the thickness of the outer peripheral portion is increased, the effect of suppressing the temperature rise of the central portion of the surface electrode 2 having poor heat dissipation can be efficiently obtained.

【0061】(実施の形態3)図14は、実施の形態3
のパワー半導体モジュールの表面電極2と金属ワイヤ4
との接合形態を示す斜視図である。本実施の形態では、
複数の部分表面電極20に分割された表面電極2が設け
られており、外側の部分表面電極20に接合される金属
ワイヤ4aの径が、内側の部分表面電極20に接合され
る金属ワイヤ4bの径よりも大きい場合のパワー半導体
モジュールが用いられている。なお、金属ワイヤは同じ
種類の金属ワイヤであるため、長さおよび断面積が同じ
であれば、同じ抵抗になるものとする。
(Third Embodiment) FIG. 14 shows a third embodiment.
Power semiconductor module surface electrode 2 and metal wire 4
It is a perspective view which shows the joining form with. In this embodiment,
The surface electrode 2 divided into a plurality of partial surface electrodes 20 is provided, and the diameter of the metal wire 4a bonded to the outer partial surface electrode 20 is the same as that of the metal wire 4b bonded to the inner partial surface electrode 20. A power semiconductor module having a diameter larger than the diameter is used. Since the metal wires are the same kind of metal wire, they have the same resistance if they have the same length and cross-sectional area.

【0062】このように、外側の部分表面電極20に接
合される金属ワイヤ4aの径を、内側の部分表面電極2
0に接合される金属ワイヤ4bの径よりも大きくするこ
とにより、半導体素子1から表面電極2の中央部を介し
て外部電極3に至るまでの金属ワイヤ4の抵抗を、半導
体素子1から表面電極2の周縁部を介して外部電極3に
至るまでの金属ワイヤ4の抵抗よりも大きくすることが
できる。
As described above, the diameter of the metal wire 4a bonded to the outer partial surface electrode 20 is set to the inner partial surface electrode 2
By making the diameter of the metal wire 4b bonded to 0 larger than the diameter of the metal wire 4b bonded to 0, the resistance of the metal wire 4 from the semiconductor element 1 to the external electrode 3 through the central portion of the surface electrode 2 can be reduced. The resistance of the metal wire 4 up to the external electrode 3 via the peripheral edge of the metal wire 2 can be made larger.

【0063】このようにすることで、表面電極2の中央
部の電流密度を低減することができるとともに、表面電
極2の中央部には金属ワイヤ4が接合されていないた
め、放熱性に劣る表面電極2の中央部の温度上昇を抑制
することができる。その結果、長期的信頼性の優れたパ
ワー半導体モジュールを提供することができる。
By doing so, the current density at the central portion of the front surface electrode 2 can be reduced, and since the metal wire 4 is not bonded to the central portion of the front surface electrode 2, the surface having a poor heat dissipation property can be obtained. It is possible to suppress the temperature rise in the central portion of the electrode 2. As a result, a power semiconductor module having excellent long-term reliability can be provided.

【0064】なお、図14に示すパワー半導体モジュー
ルの表面電極2と金属ワイヤ4との接合形態では、外側
の部分表面電極20と金属ワイヤ4との接合箇所を3箇
所としているが、金属ワイヤ4が2箇所で接合されてい
る内側の部分表面電極20より接合箇所が多ければ、外
側の部分表面電極20に流れる電流が大きくなり、同様
の効果が得られるため、外側の部分表面電極20と金属
ワイヤ4との接合箇所は3箇所以上であればよい。
In the joining form of the surface electrode 2 and the metal wire 4 of the power semiconductor module shown in FIG. 14, the outer partial surface electrode 20 and the metal wire 4 are joined at three places. If there are more joints than the inner partial surface electrode 20 that is joined at two locations, the current flowing through the outer partial surface electrode 20 becomes large, and the same effect can be obtained. The number of joints with the wire 4 may be three or more.

【0065】また、図14では、各部分表面電極20に
対し金属ワイヤ4は一箇所のみで接合されるとともに、
外側の部分表面電極20に対しては3本の金属ワイヤ4
を、内側の部分表面電極20に対しては2本の金属ワイ
ヤ4を使用した形態を示したが、金属ワイヤ4の使用本
数や接合形態についてはこの限りではない。たとえば、
金属ワイヤ4の径や、半導体素子1を流れる電流値によ
って決まる設計基準を満足する限り、図3に示すよう
に、全ての部分表面電極20に対して1本の金属ワイヤ
4で連続的に接合してもよい。他にも、図4〜図9に示
すような様々なバリエーションが考えられる。
Further, in FIG. 14, the metal wire 4 is joined to each partial surface electrode 20 at only one place, and
Three metal wires 4 for the outer partial surface electrode 20.
Although the form in which the two metal wires 4 are used for the inner partial surface electrode 20 is shown, the number of the metal wires 4 used and the bonding form are not limited to this. For example,
As long as the design criteria determined by the diameter of the metal wire 4 and the value of the current flowing through the semiconductor element 1 are satisfied, one metal wire 4 is continuously bonded to all the partial surface electrodes 20 as shown in FIG. You may. Besides, various variations as shown in FIGS. 4 to 9 are possible.

【0066】さらに、本実施の形態では、半導体素子の
表面にストライプ状の部分表面電極20が設けられたI
GBTチップを例に説明してきたが、必ずしもストライ
プ状の部分表面電極20である必要はなく、また、IG
BT以外の他の半導体素子1についても同様に、放熱性
が劣る表面電極の中央部の温度上昇を抑制する効果が得
られる。
Further, in this embodiment, the stripe-shaped partial surface electrode 20 is provided on the surface of the semiconductor element.
Although the GBT chip has been described as an example, the stripe-shaped partial surface electrode 20 is not necessarily required, and the IG
Similarly, for the semiconductor elements 1 other than BT, the effect of suppressing the temperature rise of the central portion of the surface electrode, which has poor heat dissipation, can be obtained.

【0067】(実施の形態4)図15は、実施の形態4
のパワー半導体モジュールの表面電極と金属ワイヤ4と
の接合形態を示す斜視図である。本実施の形態では、複
数の部分表面電極20に分割された表面電極2が設けら
れており、外側の部分表面電極20に接合される金属ワ
イヤ4aの長さが、内側の部分表面電極20に接合され
る金属ワイヤ4bの長さよりも短くなっている。なお、
金属ワイヤは同じ種類の金属ワイヤであるため、長さお
よび断面積が同じであれば、同じ抵抗になるものとす
る。
(Fourth Embodiment) FIG. 15 shows a fourth embodiment.
FIG. 3 is a perspective view showing a bonding form between a surface electrode and a metal wire 4 of the power semiconductor module of FIG. In the present embodiment, the surface electrode 2 divided into a plurality of partial surface electrodes 20 is provided, and the length of the metal wire 4a bonded to the outer partial surface electrode 20 is equal to that of the inner partial surface electrode 20. It is shorter than the length of the metal wire 4b to be joined. In addition,
Since the metal wires are the same kind of metal wire, they have the same resistance if they have the same length and cross-sectional area.

【0068】このように、外側の部分表面電極20に接
合される金属ワイヤ4aの長さを、内側の部分表面電極
20に接合される金属ワイヤ4bの長さよりも短くする
ことにより、半導体素子1から表面電極2の中央部を介
して外部電極3に至るまでの金属ワイヤ4の抵抗を、半
導体素子1から表面電極2の周縁部を介して外部電極3
に至るまでの金属ワイヤ4の抵抗よりも大きくすること
ができる。
As described above, by making the length of the metal wire 4a joined to the outer partial surface electrode 20 shorter than the length of the metal wire 4b joined to the inner partial surface electrode 20, the semiconductor element 1 is obtained. From the semiconductor element 1 through the peripheral portion of the surface electrode 2 to the external electrode 3 through the central portion of the surface electrode 2 to the external electrode 3.
Can be made larger than the resistance of the metal wire 4 up to.

【0069】このようにして、表面電極2の中央部の電
流密度を低減することができるとともに、表面電極2の
中央部には金属ワイヤ4が接合されていないため、放熱
性に劣る表面電極2の中央部の温度上昇を抑制すること
ができる。その結果、長期的信頼性の優れたパワー半導
体モジュールを提供することができる。
In this way, the current density at the central portion of the surface electrode 2 can be reduced, and since the metal wire 4 is not bonded to the central portion of the surface electrode 2, the surface electrode 2 having poor heat dissipation performance. It is possible to suppress the temperature rise in the central part of the. As a result, a power semiconductor module having excellent long-term reliability can be provided.

【0070】なお、図15に示すパワー半導体モジュー
ルの表面電極2と金属ワイヤ4との接合形態では、外側
の部分表面電極20と金属ワイヤ4との接合箇所を3箇
所としているが、金属ワイヤ4が2箇所で接合されてい
る内側の部分表面電極20よりも接合箇所が多ければ、
外側の部分表面電極20に流れる電流が大きくなり、同
様の効果が得られるため、外側の部分表面電極20と金
属ワイヤ4との接合箇所は3箇所以上であればよい。
In the joining form of the surface electrode 2 and the metal wire 4 of the power semiconductor module shown in FIG. 15, the outer partial surface electrode 20 and the metal wire 4 are joined at three places. If there are more bonding points than the inner partial surface electrode 20 bonded at two points,
Since the current flowing through the outer partial surface electrode 20 becomes large and the same effect can be obtained, the number of joints between the outer partial surface electrode 20 and the metal wire 4 may be three or more.

【0071】また、図15では、各部分表面電極20に
対し各金属ワイヤ4は一箇所のみで接合されるととも
に、外側の部分表面電極20に対しては3本の金属ワイ
ヤ4を、内側の部分表面電極20に対しては2本の金属
ワイヤ4を使用した例を示しているが、金属ワイヤ4の
使用本数や接合形態についてはこの限りではない。たと
えば、金属ワイヤ4の径や、半導体素子1を流れる電流
値によって決まる設計基準を満足する限り、図3に示す
ように、全ての部分表面電極20に対して1本の金属ワ
イヤ4で連続的に接合してもよい。他にも、図4〜図9
に示すような様々なバリエーションが考えられる。
In addition, in FIG. 15, each metal wire 4 is joined to each partial surface electrode 20 at only one place, and three metal wires 4 are connected to the outer partial surface electrode 20 and the inner partial surface electrode 20. Although an example in which two metal wires 4 are used for the partial surface electrode 20 is shown, the number of metal wires 4 to be used and the bonding form are not limited to this. For example, as long as the design criteria determined by the diameter of the metal wire 4 and the current value flowing through the semiconductor element 1 are satisfied, one metal wire 4 is continuously connected to all the partial surface electrodes 20 as shown in FIG. May be joined to. In addition, FIGS.
Various variations are possible as shown in.

【0072】さらに、本実施の形態では、半導体素子1
の表面にストライプ状の部分表面電極20が設けられた
IGBTチップを例に説明してきたが、必ずしもストラ
イプ状の部分表面電極20である必要はなく、また、I
GBT以外の他の半導体素子1についても同様に、放熱
性に劣る表面電極の中央部の温度上昇を抑制する効果が
得られる。
Further, in the present embodiment, the semiconductor element 1
The IGBT chip in which the striped partial surface electrode 20 is provided on the surface of the above has been described as an example, but the striped partial surface electrode 20 is not necessarily required.
Similarly, with respect to the semiconductor element 1 other than the GBT, the effect of suppressing the temperature rise of the central portion of the surface electrode having poor heat dissipation can be obtained.

【0073】(実施の形態5)図16は、実施の形態5
のパワー半導体モジュールの表面電極2と金属ワイヤ4
との接合形態を示す斜視図である。本実施の形態では、
複数の部分表面電極20に分割された表面電極2におい
て、外部電極3と金属ワイヤ4との接合位置をずらすこ
とにより、外側の部分表面電極20に接合される金属ワ
イヤ4aの長さを、内側の部分表面電極20に接合され
る金属ワイヤ4bの長さよりも短くしている。なお、金
属ワイヤは同じ種類の金属ワイヤであるため、長さおよ
び断面積が同じであれば、同じ抵抗になるものとする。
(Fifth Embodiment) FIG. 16 shows a fifth embodiment.
Power semiconductor module surface electrode 2 and metal wire 4
It is a perspective view which shows the joining form with. In this embodiment,
In the front surface electrode 2 divided into the plurality of partial front surface electrodes 20, the length of the metal wire 4a bonded to the outer partial surface electrode 20 is changed to the inner side by shifting the bonding position between the external electrode 3 and the metal wire 4. The length is shorter than the length of the metal wire 4b joined to the partial surface electrode 20. Since the metal wires are the same kind of metal wire, they have the same resistance if they have the same length and cross-sectional area.

【0074】このように、外側の部分表面電極20に接
合される金属ワイヤ4aの長さを、内側の部分表面電極
20に接合される金属ワイヤ4bの長さよりも短くする
ことにより、半導体素子1から表面電極2の中央部を介
して外部電極3に至るまでの金属ワイヤ4の抵抗を、半
導体素子1から表面電極2の周縁部を介して外部電極3
に至るまでの金属ワイヤ4の抵抗より大きくすることが
できる。
As described above, by making the length of the metal wire 4a joined to the outer partial surface electrode 20 shorter than the length of the metal wire 4b joined to the inner partial surface electrode 20, the semiconductor element 1 is obtained. From the semiconductor element 1 through the peripheral portion of the surface electrode 2 to the external electrode 3 through the central portion of the surface electrode 2 to the external electrode 3.
Can be made larger than the resistance of the metal wire 4 up to.

【0075】このようにして、表面電極2の中央部の電
流密度を低減することができるとともに、表面電極2の
中央部には金属ワイヤ4が接合されていないため、放熱
性が劣る表面電極2の中央部の温度上昇を抑制すること
ができる。その結果、長期的信頼性の優れたパワー半導
体モジュールを提供することができる。
In this way, the current density at the central portion of the front surface electrode 2 can be reduced, and since the metal wire 4 is not bonded to the central portion of the front surface electrode 2, the front surface electrode 2 having a poor heat dissipation property. It is possible to suppress the temperature rise in the central part of the. As a result, a power semiconductor module having excellent long-term reliability can be provided.

【0076】なお、図16に示すパワー半導体モジュー
ルの表面電極2と金属ワイヤ4との接合形態では、半導
体素子1の外側の部分表面電極20と金属ワイヤ4との
接合箇所を3箇所としているが、金属ワイヤ4が2箇所
で接合されている内側の部分表面電極20より接合箇所
が多ければ、外側の部分表面電極20に流れる電流が大
きくなり、同様の効果が得られるため、外側の部分表面
電極20と金属ワイヤ4との接合箇所は3箇所以上であ
ればよい。
Although the surface electrode 2 and the metal wire 4 of the power semiconductor module shown in FIG. 16 are bonded to each other, there are three bonding points between the metal wire 4 and the partial surface electrode 20 outside the semiconductor element 1. If there are more joining points than the inner partial surface electrode 20 where the metal wire 4 is joined at two points, the current flowing through the outer partial surface electrode 20 becomes large, and the same effect can be obtained. The number of bonding points between the electrode 20 and the metal wire 4 may be three or more.

【0077】また、図16では、各部分表面電極20に
対し各金属ワイヤ4は一箇所のみで接合するとともに、
外側の部分表面電極20に対しては3本の金属ワイヤ4
を、内側の部分表面電極20に対しては2本の金属ワイ
ヤ4を使用した例を示しているが、金属ワイヤ4の使用
本数や接合形態についてはこの限りではない。たとえ
ば、金属ワイヤ4の径や、半導体素子1を流れる電流値
によって決まる設計基準を満足する限り、図3に示すよ
うに全ての部分表面電極20に対して1本の金属ワイヤ
4で連続的に接合してもよい。他にも、図4〜図9に示
すような様々なバリエーションが考えられる。
Further, in FIG. 16, each metal wire 4 is joined to each partial surface electrode 20 at only one location, and
Three metal wires 4 for the outer partial surface electrode 20.
Although the example in which two metal wires 4 are used for the inner partial surface electrode 20 is shown, the number of metal wires 4 to be used and the bonding form are not limited to this. For example, as long as the design criteria determined by the diameter of the metal wire 4 and the current value flowing through the semiconductor element 1 are satisfied, one metal wire 4 is continuously provided for all the partial surface electrodes 20 as shown in FIG. You may join. Besides, various variations as shown in FIGS. 4 to 9 are possible.

【0078】さらに、本実施の形態では、半導体素子1
の表面にストライプ状の部分表面電極20が設けられた
IGBTチップを例に説明してきたが、必ずしもストラ
イプ状の部分表面電極20である必要はなく、また、I
GBT以外の他の半導体素子1についても同様に、放熱
性に劣る表面電極2の中央部の温度上昇を抑制する効果
が得られる。
Further, in the present embodiment, the semiconductor device 1
The IGBT chip in which the striped partial surface electrode 20 is provided on the surface of the above has been described as an example, but the striped partial surface electrode 20 is not necessarily required.
The semiconductor element 1 other than the GBT also has the same effect of suppressing the temperature rise in the central portion of the surface electrode 2 having poor heat dissipation.

【0079】なお、上記実施の形態1〜5に開示された
発明を任意に組合わせることは可能であり、このよう
に、実施の形態1〜5に開示された発明を任意に組合わ
せれば、それぞれの実施の形態で得られる効果を足し合
わせることができる。
It is possible to arbitrarily combine the inventions disclosed in the above first to fifth embodiments. Thus, if the inventions disclosed in the first to fifth embodiments are arbitrarily combined, The effects obtained in the respective embodiments can be added together.

【0080】また、今回開示された実施の形態はすべて
の点で例示であって制限的なものではないと考えられる
べきである。本発明の範囲は上記した説明ではなく特許
請求の範囲によって示され、特許請求の範囲と均等の意
味および範囲内でのすべての変更が含まれることが意図
される。
It should be considered that the embodiments disclosed this time are exemplifications in all points and not restrictive. The scope of the present invention is shown not by the above description but by the scope of the claims, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope.

【0081】[0081]

【発明の効果】本発明によれば、半導体装置の駆動時
に、放熱性に劣る表面電極の中央部の温度上昇を抑制す
ることが可能となることにより、半導体装置の長期的な
信頼性を向上させることができる。
According to the present invention, when the semiconductor device is driven, it is possible to suppress the temperature rise of the central portion of the surface electrode which is inferior in heat dissipation, thereby improving the long-term reliability of the semiconductor device. Can be made.

【図面の簡単な説明】[Brief description of drawings]

【図1】 実施の形態1のパワー半導体モジュールの表
面電極と金属ワイヤとの接合形態を示す斜視図である。
FIG. 1 is a perspective view showing a bonding form of a surface electrode and a metal wire of a power semiconductor module according to a first embodiment.

【図2】 実施の形態1のパワー半導体モジュールの表
面電極と金属ワイヤとの接合形態において、半導体素子
を駆動した際の表面電極の表面温度分布を示す図であ
る。
FIG. 2 is a diagram showing a surface temperature distribution of a surface electrode when a semiconductor element is driven in a bonding mode of a surface electrode and a metal wire of the power semiconductor module of the first embodiment.

【図3】 実施の形態1のパワー半導体モジュールの表
面電極と金属ワイヤとの他の接合形態を示す斜視図であ
る。
FIG. 3 is a perspective view showing another bonding mode of the surface electrode and the metal wire of the power semiconductor module of the first embodiment.

【図4】 実施の形態1の他の例のパワー半導体モジュ
ールの表面電極と金属ワイヤとの接合形態を示す斜視図
である。
FIG. 4 is a perspective view showing a bonding form of a surface electrode and a metal wire of a power semiconductor module of another example of the first embodiment.

【図5】 実施の形態1の他の例のパワー半導体モジュ
ールの表面電極と金属ワイヤとの接合形態を示す斜視図
である。
FIG. 5 is a perspective view showing a bonding form of a surface electrode and a metal wire of a power semiconductor module of another example of the first embodiment.

【図6】 実施の形態1の他の例のパワー半導体モジュ
ールの表面電極と金属ワイヤとの接合形態を示す斜視図
である。
FIG. 6 is a perspective view showing a bonding form of a surface electrode and a metal wire of a power semiconductor module of another example of the first embodiment.

【図7】 実施の形態1の他の例のパワー半導体モジュ
ールの表面電極と金属ワイヤとの接合形態を示す斜視図
である。
FIG. 7 is a perspective view showing a bonding form of a surface electrode and a metal wire of a power semiconductor module of another example of the first embodiment.

【図8】 実施の形態1の他の例のパワー半導体モジュ
ールの表面電極と金属ワイヤとの接合形態を示す斜視図
である。
FIG. 8 is a perspective view showing a bonding form of a surface electrode and a metal wire of a power semiconductor module of another example of the first embodiment.

【図9】 実施の形態1の他の例のパワー半導体モジュ
ールの表面電極と金属ワイヤとの接合形態を示す斜視図
である。
FIG. 9 is a perspective view showing a bonding form of a surface electrode and a metal wire of a power semiconductor module of another example of the first embodiment.

【図10】 半導体素子を駆動した際の表面電極と金属
ワイヤとの接合部の温度と、金属ワイヤを接合しない領
域との関係を示す図である。
FIG. 10 is a diagram showing a relationship between a temperature of a bonding portion between a surface electrode and a metal wire when a semiconductor element is driven and a region where the metal wire is not bonded.

【図11】 実施の形態2のパワー半導体モジュールの
表面電極と金属ワイヤとの接合形態を示す斜視図であ
る。
FIG. 11 is a perspective view showing how the surface electrode and the metal wire of the power semiconductor module of the second embodiment are joined.

【図12】 実施の形態2のパワー半導体モジュールの
表面電極と金属ワイヤとの接合形態において、半導体素
子を駆動した際における表面電極の表面温度分布を示す
図である。
FIG. 12 is a diagram showing a surface temperature distribution of a surface electrode when a semiconductor element is driven in a bonding mode of a surface electrode and a metal wire of a power semiconductor module according to a second embodiment.

【図13】 半導体素子を駆動した際における表面電極
と金属ワイヤとの接合部温度と、表面電極を周縁部より
薄くする領域との関係を示す図である。
FIG. 13 is a diagram showing a relationship between a junction temperature between a surface electrode and a metal wire when a semiconductor element is driven and a region where the surface electrode is thinner than a peripheral edge portion.

【図14】 実施の形態3のパワー半導体モジュールの
表面電極と金属ワイヤとの接合形態を示す斜視図であ
る。
FIG. 14 is a perspective view showing how the surface electrode and the metal wire of the power semiconductor module of the third embodiment are joined.

【図15】 実施の形態4のパワー半導体モジュールの
表面電極と金属ワイヤとの接合形態を示す斜視図であ
る。
FIG. 15 is a perspective view showing how the surface electrode and the metal wire of the power semiconductor module of Embodiment 4 are joined.

【図16】 実施の形態5のパワー半導体モジュールの
表面電極と金属ワイヤとの接合形態を示す斜視図であ
る。
FIG. 16 is a perspective view showing how the surface electrode and the metal wire of the power semiconductor module of the fifth embodiment are joined.

【図17】 従来のパワー半導体モジュールを示す断面
図である。
FIG. 17 is a sectional view showing a conventional power semiconductor module.

【図18】 従来のパワー半導体モジュールにおける、
表面電極と金属ワイヤとの接合形態を示す斜視図であ
る。
FIG. 18 shows a conventional power semiconductor module,
It is a perspective view which shows the joining form of a surface electrode and a metal wire.

【図19】 従来のパワー半導体モジュールの表面電極
と金属ワイヤとの接合形態において、半導体素子を駆動
した際における表面電極の表面温度分布を示す図であ
る。
FIG. 19 is a diagram showing a surface temperature distribution of a surface electrode when a semiconductor element is driven in a bonding mode of a surface electrode of a conventional power semiconductor module and a metal wire.

【符号の説明】[Explanation of symbols]

1 半導体素子、2 表面電極、3 外部電極、4 金
属ワイヤ、4a 周縁部の部分表面電極と接合される金
属ワイヤ、4b 中央部の部分表面電極と接合される金
属ワイヤ、5 ハンダ、6 絶縁板、7 金属パター
ン、8 金属ベース板、9 表面電極と金属ワイヤとの
接合部、20 部分表面電極、20a 周縁部より厚さ
を小さくした表面電極の中央部。
DESCRIPTION OF SYMBOLS 1 semiconductor element, 2 surface electrode, 3 external electrode, 4 metal wire, 4a metal wire joined with partial surface electrode of peripheral part, 4b metal wire joined with partial surface electrode of central part, 5 solder, 6 insulating plate , 7 metal pattern, 8 metal base plate, 9 joining part of surface electrode and metal wire, 20 partial surface electrode, 20a central part of surface electrode having a smaller thickness than the peripheral part.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 大井 健史 東京都千代田区丸の内二丁目2番3号 三 菱電機株式会社内 Fターム(参考) 5F033 HH11 MM21 RR03 RR05 UU07 VV00 VV07 XX22 5F044 AA07 AA18 EE02 JJ05    ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takeshi Oi             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. F term (reference) 5F033 HH11 MM21 RR03 RR05 UU07                       VV00 VV07 XX22                 5F044 AA07 AA18 EE02 JJ05

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子と、 該半導体素子の主表面に沿って設けられ、該半導体素子
と電気的に接続された表面電極と、 該半導体素子の外部に設けられた外部電極と、 前記表面電極と前記外部電極とを電気的に接続する外部
配線とを備え、 前記表面電極を、前記主表面側から見て、中央部と該中
央部を取り囲む周縁部とに区別した場合に、前記半導体
素子の駆動時に、前記周縁部の電流密度が、前記中央部
の電流密度よりも高くなるように構成された、半導体装
置。
1. A semiconductor element, a surface electrode provided along a main surface of the semiconductor element and electrically connected to the semiconductor element, an external electrode provided outside the semiconductor element, and the surface. An external wire that electrically connects the electrode and the external electrode, wherein the front surface electrode, when viewed from the main surface side, is divided into a central portion and a peripheral portion surrounding the central portion, the semiconductor A semiconductor device configured such that a current density of the peripheral portion is higher than a current density of the central portion when the element is driven.
【請求項2】 半導体素子と、 該半導体素子の主表面に沿って設けられ、該半導体素子
と電気的に接続された表面電極と、 該半導体素子の外部に設けられた外部電極と、 前記表面電極と前記外部電極とを電気的に接続する外部
配線とを備え、 前記表面電極を、前記主表面側から見て、中央部と該中
央部を取り囲む周縁部とに区別した場合に、前記外部配
線が前記周縁部にのみ接合された、半導体装置。
2. A semiconductor element, a surface electrode provided along the main surface of the semiconductor element and electrically connected to the semiconductor element, an external electrode provided outside the semiconductor element, and the surface. An external wire for electrically connecting the electrode and the external electrode, wherein when the surface electrode is divided into a central portion and a peripheral portion surrounding the central portion when viewed from the main surface side, the external A semiconductor device in which wiring is joined only to the peripheral portion.
【請求項3】 半導体素子と、 該半導体素子の主表面に沿って設けられ、該半導体素子
と電気的に接続された表面電極と、 該半導体素子の外部に設けられた外部電極と、 前記表面電極と前記外部電極とを電気的に接続する複数
の外部配線とを備え、 該複数の外部配線は、 前記表面電極を、前記主表面側から見て、中央部と該中
央部を取り囲む周縁部とに区別した場合に、 前記中央部と前記外部電極とを電気的に接続する内側外
部配線と、 前記周縁部と前記外部電極とを電気的に接続する外側外
部配線とを含み、 前記半導体素子から前記中央部および前記内側外部配線
を介して前記外部電極に至るまでの合成抵抗が、前記半
導体素子から前記周縁部および前記外側外部配線を介し
て前記外部電極に至るまでの合成抵抗よりも大きくなる
ように構成された、半導体装置。
3. A semiconductor element, a surface electrode provided along the main surface of the semiconductor element and electrically connected to the semiconductor element, an external electrode provided outside the semiconductor element, and the surface. A plurality of external wirings for electrically connecting the electrodes and the external electrodes, wherein the plurality of external wirings include a central portion and a peripheral portion surrounding the central portion when the surface electrode is viewed from the main surface side. And an outer outer wire electrically connecting the peripheral portion and the outer electrode, the semiconductor element including the inner outer wire electrically connecting the central portion and the outer electrode to each other. From the semiconductor element to the external electrode through the central portion and the inner external wiring is greater than the synthetic resistance from the semiconductor element to the external electrode through the peripheral portion and the outer external wiring. To be Configured, the semiconductor device.
【請求項4】 半導体素子と、 該半導体素子の主表面に沿って設けられ、該半導体素子
と電気的に接続された表面電極と、 該半導体素子の外部に設けられた外部電極と、 前記表面電極と前記外部電極とを電気的に接続する複数
の外部配線とを備え、該複数の外部配線は、 前記表面電極を、前記主表面側から見て、中央部と該中
央部を取り囲む周縁部とに区別した場合に、 前記中央部と前記外部電極とを電気的に接続する内側外
部配線と、 前記周縁部と前記外部電極とを電気的に接続する外側外
部配線とを含み、前記内側外部配線の抵抗が、前記外側
外部配線の抵抗よりも大きい、半導体装置。
4. A semiconductor element, a surface electrode provided along the main surface of the semiconductor element and electrically connected to the semiconductor element, an external electrode provided outside the semiconductor element, and the surface. A plurality of external wirings for electrically connecting the electrodes and the external electrodes, wherein the plurality of external wirings include a central portion and a peripheral portion surrounding the central portion when the surface electrode is viewed from the main surface side. And an inner outer wiring that electrically connects the central portion and the outer electrode, and an outer outer wiring that electrically connects the peripheral portion and the outer electrode. A semiconductor device, wherein the resistance of the wiring is larger than the resistance of the outer wiring.
【請求項5】 半導体素子と、 該半導体素子の主表面に沿って設けられ、該半導体素子
と電気的に接続された表面電極と、 該半導体素子の外部に設けられた外部電極と、 前記表面電極と前記外部電極とを電気的に接続する複数
の外部配線とを備え、 該複数の外部配線は、 前記表面電極を、前記主表面側から見て、中央部と該中
央部を取り囲む周縁部とに区別した場合に、 前記中央部と前記外部電極とを電気的に接続する内側外
部配線と、 前記周縁部と前記外部電極とを電気的に接続する外側外
部配線とを含み、 前記外側外部配線と前記周縁部との接合箇所数が、前記
内側外部配線と前記中央部との接合個所数よりも多く設
けられた、半導体装置。
5. A semiconductor element, a surface electrode provided along the main surface of the semiconductor element and electrically connected to the semiconductor element, an external electrode provided outside the semiconductor element, and the surface. A plurality of external wirings for electrically connecting the electrodes and the external electrodes, wherein the plurality of external wirings include a central portion and a peripheral portion surrounding the central portion when the surface electrode is viewed from the main surface side. And an outer outer wire electrically connecting the peripheral portion and the outer electrode, the outer outer wire A semiconductor device, wherein the number of joints between the wiring and the peripheral portion is larger than the number of joints between the inner external wiring and the central portion.
【請求項6】 半導体素子と、 該半導体素子の主表面に沿って設けられ、該半導体素子
と電気的に接続された表面電極と、 該半導体素子の外部に設けられた外部電極と、 前記表面電極と前記外部電極とを電気的に接続する複数
の外部配線とを備え、 該複数の外部配線は、 前記表面電極を、前記主表面側から見て、中央部と該中
央部を取り囲む周縁部とに区別した場合に、 前記中央部と前記外部電極とを電気的に接続する内側外
部配線と、 前記周縁部と前記外部電極とを電気的に接続する外側外
部配線とを含み、 前記周縁部の前記表面電極の厚さが、前記中央部の前記
表面電極の厚さよりも大きくなるように構成された、半
導体装置。
6. A semiconductor element, a surface electrode provided along the main surface of the semiconductor element and electrically connected to the semiconductor element, an external electrode provided outside the semiconductor element, and the surface. A plurality of external wirings for electrically connecting the electrodes and the external electrodes, wherein the plurality of external wirings include a central portion and a peripheral portion surrounding the central portion when the surface electrode is viewed from the main surface side. And an outer external wire electrically connecting the peripheral portion and the external electrode, the peripheral portion including the inner external wiring electrically connecting the central portion and the external electrode, The semiconductor device is configured such that the thickness of the front surface electrode is larger than the thickness of the front surface electrode in the central portion.
【請求項7】 半導体素子と、 該半導体素子の主表面に沿って設けられ、該半導体素子
と電気的に接続された表面電極と、 該半導体素子の外部に設けられた外部電極と、 前記表面電極と前記外部電極とを電気的に接続する外部
配線とを備え、 前記表面電極は、密接して形成されたストライプ状の複
数の部分表面電極を含み、 該複数の部分表面電極は、 前記表面電極を、前記主表面側から見て、中央部と該中
央部を取り囲む周縁部とに区別した場合に、 前記中央部および前記周縁部の双方を横断する内側部分
表面電極と、 前記周縁部のみに位置する外側部分表面電極とを有し、 前記外部配線と前記外側部分表面電極との接合箇所数
が、前記外部配線と前記内側部分表面電極との接合個所
数よりも多く設けられた、半導体装置。
7. A semiconductor element, a surface electrode provided along the main surface of the semiconductor element and electrically connected to the semiconductor element, an external electrode provided outside the semiconductor element, and the surface. An electrode and an external wiring for electrically connecting the external electrode, wherein the surface electrode includes a plurality of striped partial surface electrodes formed in close contact with each other, and the plurality of partial surface electrodes are the surface. When the electrode is divided into a central portion and a peripheral portion surrounding the central portion when viewed from the main surface side, an inner partial surface electrode that traverses both the central portion and the peripheral portion, and only the peripheral portion An outer partial surface electrode located at, the number of joints between the external wiring and the outer partial surface electrode is provided more than the number of joints between the external wiring and the inner partial surface electrode, the semiconductor apparatus.
【請求項8】 前記表面電極の主表面は長方形であり、 前記周縁部が、前記長方形と対角線の交点が共通である
とともに、縦横それぞれの辺の長さが前記長方形の2/
5となる仮想長方形の外側の部分である、請求項1〜請
求項7のいずれかに記載の半導体装置。
8. The main surface of the surface electrode has a rectangular shape, the peripheral portion has a common intersection of the rectangle and a diagonal line, and the length of each of the vertical and horizontal sides is 2 / of the rectangular shape.
The semiconductor device according to any one of claims 1 to 7, which is an outer portion of a virtual rectangle of 5.
JP2001381719A 2001-12-14 2001-12-14 Semiconductor device Withdrawn JP2003188378A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001381719A JP2003188378A (en) 2001-12-14 2001-12-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001381719A JP2003188378A (en) 2001-12-14 2001-12-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2003188378A true JP2003188378A (en) 2003-07-04

Family

ID=27592309

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001381719A Withdrawn JP2003188378A (en) 2001-12-14 2001-12-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2003188378A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006156479A (en) * 2004-11-25 2006-06-15 Toyota Motor Corp Power semiconductor device
JP2008187151A (en) * 2007-01-31 2008-08-14 Toyota Motor Corp Semiconductor device and its manufacturing method
JP2008186957A (en) * 2007-01-29 2008-08-14 Honda Motor Co Ltd Semiconductor device and manufacturing method thereof
JP2010004003A (en) * 2008-05-20 2010-01-07 Mitsubishi Electric Corp Power semiconductor device
JP2013179369A (en) * 2003-05-02 2013-09-09 Orthodyne Electronics Corp Ribbon bonding
JP2014127562A (en) * 2012-12-26 2014-07-07 Sanken Electric Co Ltd Power semiconductor module
US9418916B2 (en) 2013-01-25 2016-08-16 Fuji Electric Co., Ltd. Semiconductor device
JP2019121612A (en) * 2017-12-28 2019-07-22 新電元工業株式会社 Electronic device
CN110100314A (en) * 2017-06-09 2019-08-06 富士电机株式会社 The manufacturing method of semiconductor device and semiconductor device
JP2019135761A (en) * 2018-02-05 2019-08-15 株式会社東芝 Semiconductor module and method for manufacturing the same
DE112021001406T5 (en) 2020-11-25 2022-12-22 Fuji Electric Co., Ltd. SEMICONDUCTOR MODULE

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013179369A (en) * 2003-05-02 2013-09-09 Orthodyne Electronics Corp Ribbon bonding
JP2006156479A (en) * 2004-11-25 2006-06-15 Toyota Motor Corp Power semiconductor device
JP2008186957A (en) * 2007-01-29 2008-08-14 Honda Motor Co Ltd Semiconductor device and manufacturing method thereof
JP2008187151A (en) * 2007-01-31 2008-08-14 Toyota Motor Corp Semiconductor device and its manufacturing method
JP2010004003A (en) * 2008-05-20 2010-01-07 Mitsubishi Electric Corp Power semiconductor device
JP2014127562A (en) * 2012-12-26 2014-07-07 Sanken Electric Co Ltd Power semiconductor module
US9418916B2 (en) 2013-01-25 2016-08-16 Fuji Electric Co., Ltd. Semiconductor device
CN110100314A (en) * 2017-06-09 2019-08-06 富士电机株式会社 The manufacturing method of semiconductor device and semiconductor device
US10672762B2 (en) 2017-06-09 2020-06-02 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
JP2021052208A (en) * 2017-06-09 2021-04-01 富士電機株式会社 Semiconductor device and manufacturing method for semiconductor device
JP7078099B2 (en) 2017-06-09 2022-05-31 富士電機株式会社 Semiconductor devices and methods for manufacturing semiconductor devices
JP2019121612A (en) * 2017-12-28 2019-07-22 新電元工業株式会社 Electronic device
JP7050487B2 (en) 2017-12-28 2022-04-08 新電元工業株式会社 Electronic device
JP2019135761A (en) * 2018-02-05 2019-08-15 株式会社東芝 Semiconductor module and method for manufacturing the same
DE112021001406T5 (en) 2020-11-25 2022-12-22 Fuji Electric Co., Ltd. SEMICONDUCTOR MODULE

Similar Documents

Publication Publication Date Title
US8537550B2 (en) Wiring board and power conversion device
JP5605095B2 (en) Semiconductor device
TWI446493B (en) Semiconductor die package including stacked dice and heat sink structures
JP2015142059A (en) power semiconductor module
JP5776701B2 (en) Semiconductor device and method for manufacturing semiconductor device
JPWO2013118478A1 (en) Semiconductor device
US20050046020A1 (en) Semiconductor device with pipe for passing refrigerant liquid
JP2003188378A (en) Semiconductor device
JP6244272B2 (en) Semiconductor device
JP2001284525A (en) Semiconductor chip and semiconductor device
JP5098630B2 (en) Semiconductor device and manufacturing method thereof
JP6875588B1 (en) Semiconductor device
JP4293272B2 (en) Semiconductor device
JP7419781B2 (en) semiconductor module
JP4797492B2 (en) Semiconductor device
JPWO2020149225A1 (en) Semiconductor device
CN107039408A (en) The manufacture method of semiconductor device and semiconductor device
JP5418654B2 (en) Semiconductor device
JP2010123873A (en) Insulating gate type semiconductor device
JP7298679B2 (en) Silicon carbide semiconductor device
JP7342889B2 (en) semiconductor equipment
WO2020250582A1 (en) Semiconductor device
JP7294403B2 (en) semiconductor equipment
US20230307348A1 (en) Semiconductor apparatus
WO2023203688A1 (en) Semiconductor device and production method for semiconductor device

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20050301