JP5418654B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP5418654B2
JP5418654B2 JP2012224623A JP2012224623A JP5418654B2 JP 5418654 B2 JP5418654 B2 JP 5418654B2 JP 2012224623 A JP2012224623 A JP 2012224623A JP 2012224623 A JP2012224623 A JP 2012224623A JP 5418654 B2 JP5418654 B2 JP 5418654B2
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solder layer
semiconductor device
semiconductor element
lead frame
solder
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JP2013009014A (en
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良成 池田
春隆 谷口
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
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    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
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    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

この発明は、半導体装置に関し、特にＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ：絶縁ゲートバイポーラトランジスタ）などの縦型半導体装置を備えるパワー半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a power semiconductor device including a vertical semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor).

従来、絶縁基板に設けられた回路パターン上に、ＩＧＢＴなどの縦型半導体素子が接合されたパッケージ構造を有するパワーデバイスが提案されている。図１４は、第１従来例の半導体装置の構造について示す断面図である。図１４に示すように、第１従来例の半導体装置は、半導体素子６１と、セラミクス絶縁基板（ＤＣＢ基板）などの絶縁基板６２と、銅（Ｃｕ）ベース６６と、冷却体６７と、を備えている。なお、図１４においては、絶縁基板６２と、半導体素子６１またはＣｕベース６６との接合部分を明確にするために、樹脂ケース、外部端子、ワイヤボンディングなどの図示を省略している。   Conventionally, there has been proposed a power device having a package structure in which a vertical semiconductor element such as an IGBT is bonded on a circuit pattern provided on an insulating substrate. FIG. 14 is a cross-sectional view showing the structure of the semiconductor device of the first conventional example. As shown in FIG. 14, the semiconductor device of the first conventional example includes a semiconductor element 61, an insulating substrate 62 such as a ceramics insulating substrate (DCB substrate), a copper (Cu) base 66, and a cooling body 67. ing. In FIG. 14, the resin case, external terminals, wire bonding, and the like are not shown in order to clarify the bonding portion between the insulating substrate 62 and the semiconductor element 61 or the Cu base 66.

絶縁基板６２は、絶縁層６３のおもて面側に回路パターン６４が設けられ、裏面側に裏銅箔６５が設けられている。半導体素子６１の裏面は、第１半田層７１を介して回路パターン６４と接合している。Ｃｕベース６６のおもて面は、第２半田層７２を介して裏銅箔６５と接合している。また、Ｃｕベース６６の裏面は、サーマルコンパウンド７３を介して冷却体６７と接合している。図示はしないが、冷却体６７の周縁には、外部端子の設けられた樹脂ケースが接着されている。このような半導体装置においては、半導体素子６１のおもて面に設けられた図示省略した電極と回路パターン６４とは図示省略したアルミワイヤなどのワイヤボンディングによって電気的に接続されている。   The insulating substrate 62 is provided with a circuit pattern 64 on the front side of the insulating layer 63 and a back copper foil 65 on the back side. The back surface of the semiconductor element 61 is bonded to the circuit pattern 64 via the first solder layer 71. The front surface of the Cu base 66 is bonded to the back copper foil 65 via the second solder layer 72. Further, the back surface of the Cu base 66 is joined to the cooling body 67 via the thermal compound 73. Although not shown, a resin case provided with external terminals is bonded to the periphery of the cooling body 67. In such a semiconductor device, an electrode (not shown) provided on the front surface of the semiconductor element 61 and the circuit pattern 64 are electrically connected by wire bonding such as an aluminum wire (not shown).

また、第１半田層７１および第２半田層７２は、板半田やクリーム半田などの、半田層の厚さが一定となるような半田である。ここで、近時、環境上の配慮から、鉛を含まない（Ｐｂフリー）半田材料を用いることが要求されている。Ｐｂフリー半田材料としては、例えばＳｎＡｇ系半田（溶融点：約２２０℃）が挙げられる。   Further, the first solder layer 71 and the second solder layer 72 are solders such as plate solder and cream solder that have a constant solder layer thickness. Here, recently, from environmental considerations, it is required to use a lead-free (Pb-free) solder material. Examples of the Pb-free solder material include SnAg solder (melting point: about 220 ° C.).

上述したパッケージ構造の半導体装置に、Ｐｂフリー半田を用いた場合、半導体装置の動作寿命を推定する実機動作試験（パワーサイクル試験）などにおいて、半導体素子６１の中央部が高温になる。このため、半導体素子６１の中央部周辺に接する第１半田層７１が劣化し、縦方向に割れが生じ、半導体装置の機能を喪失させることがある（例えば、下記非特許文献１参照。）。   When Pb-free solder is used for the semiconductor device having the above-described package structure, the central portion of the semiconductor element 61 becomes high in an actual machine operation test (power cycle test) for estimating the operation life of the semiconductor device. For this reason, the 1st solder layer 71 which contact | connects the center part periphery of the semiconductor element 61 deteriorates, a crack arises in the vertical direction, and the function of a semiconductor device may be lost (for example, refer the following nonpatent literature 1).

さらに、半導体パッケージの小型化、半導体素子６１の面積低減化に伴い、電流密度の増加が望まれている。一方、従来のワイヤボンディング技術では、負荷電流レベルの限界にきており、パワーサイクル寿命の点でも、ボンディングワイヤと半導体素子６１の接合部の熱疲労が一層、厳しいものとなっている。これらの対策として、半導体素子６１の表面の電流密度を均一化して温度分布の均一化を図るとともに、半導体素子６１の裏面側に加えて表面側からも熱を逃がす構造として、半導体素子６１の表面電極にリードフレームなどの配線用導体を面接合させてその接合面積を大きくすることが考えられる。   Furthermore, with the miniaturization of the semiconductor package and the reduction in the area of the semiconductor element 61, an increase in current density is desired. On the other hand, the conventional wire bonding technique has reached the limit of the load current level, and the thermal fatigue of the bonding portion between the bonding wire and the semiconductor element 61 is further severe in terms of the power cycle life. As measures against these, the surface of the semiconductor element 61 has a structure in which the current density on the surface of the semiconductor element 61 is made uniform to make the temperature distribution uniform, and heat is released from the surface side in addition to the back side of the semiconductor element 61. It is conceivable to increase the bonding area by surface bonding a wiring conductor such as a lead frame to the electrode.

図１５は、第２従来例の半導体装置の構造について示す断面図である。図１５に示すように、第２従来例の半導体装置において、半導体素子６１のおもて面に設けられた図示省略した電極は、第３半田層７４を介してリードフレーム８１と接合している。さらに、リードフレーム８１は、第４半田層７５を介して絶縁基板６２の図示省略した回路パターンと接合している。このように、半導体素子６１のおもて面の電極は、絶縁基板６２の回路パターンと、ワイヤボンディングではなく接合面積の大きいリードフレーム８１による面接合よって電気的に接続されている（例えば、下記特許文献１参照。）。   FIG. 15 is a cross-sectional view showing the structure of the semiconductor device of the second conventional example. As shown in FIG. 15, in the semiconductor device of the second conventional example, an electrode (not shown) provided on the front surface of the semiconductor element 61 is joined to the lead frame 81 via the third solder layer 74. . Further, the lead frame 81 is bonded to a circuit pattern (not shown) of the insulating substrate 62 via the fourth solder layer 75. As described above, the electrode on the front surface of the semiconductor element 61 is electrically connected to the circuit pattern of the insulating substrate 62 not by wire bonding but by surface bonding using the lead frame 81 having a large bonding area (for example, the following). (See Patent Document 1).

なお、図１５においては、絶縁基板６２の回路パターンの一部が、半導体素子６１のおもて面に設けられた図示省略したゲート電極と、ボンディングワイヤ８５によって電気的に接続されている。また、Ｃｕベース６６の周縁にはエミッタ用端子８３とコレクタ用端子８４などの外部端子が設けられたケース８２が接着されている。絶縁基板６２の回路パターンの一部は、エミッタ用端子８３やコレクタ用端子８４と、ボンディングワイヤ８６によって電気的に接続されている。   In FIG. 15, a part of the circuit pattern of the insulating substrate 62 is electrically connected to a gate electrode (not shown) provided on the front surface of the semiconductor element 61 by a bonding wire 85. Further, a case 82 provided with external terminals such as an emitter terminal 83 and a collector terminal 84 is bonded to the periphery of the Cu base 66. A part of the circuit pattern of the insulating substrate 62 is electrically connected to the emitter terminal 83 and the collector terminal 84 by the bonding wire 86.

また、半導体装置の放熱性をさらによくするため、半導体素子とリードフレームとの接合面積をさらに大きくする方法が提案されている（例えば、下記特許文献２参照。）。特許文献２の技術においては、半導体素子の活性領域の周囲に設けられた、例えばガードリングなどの耐圧構造領域の上にも、半田を介してリードフレームを接合している。   In order to further improve the heat dissipation of the semiconductor device, a method of further increasing the junction area between the semiconductor element and the lead frame has been proposed (for example, see Patent Document 2 below). In the technique of Patent Document 2, a lead frame is also joined via solder on a breakdown voltage structure region such as a guard ring provided around an active region of a semiconductor element.

特開２００５−１１６７０２号公報JP-A-2005-116702 特開２００７−２７３０８号公報JP 2007-27308 A

両角 朗、外２名、「パワー半導体モジュールにおける信頼性設計技術」、富士時報、Ｖｏｌ．７４ Ｎｏ．２ ２００１年、ｐ．１４７（４７）−１４８（４８）Akira Ryokaku and two others, “Reliability Design Technology for Power Semiconductor Modules”, Fuji Jiho, Vol. 74 No. 2 2001, p. 147 (47) -148 (48)

しかしながら、上述した特許文献１の技術では、半導体素子のおもて面の電極に第３半田層を介してリードフレームを接合する際に、電極であるアルミニウム（Ａｌ）膜が損傷し、半導体装置の寿命を極端に短くしてしまうという問題がある。その理由は、半導体素子のおもて面には、一般に半田が接合しにくいＡｌ膜を電極として設けるが、リードフレームなどの導体を半田を介して接合する場合、Ａｌ膜の上にめっき、蒸着またはスパッタなどの処理をおこない、半田との接合性に優れているニッケル（Ｎｉ）膜やＣｕ膜を成膜するためである。このとき、ＮｉやＣｕは、Ａｌよりもヤング率が高いため、何らかの力がかかった場合、Ａｌ膜に応力が集中し、Ａｌ膜にクラックが生じてしまう。また、半導体層の、半導体素子のおもて面のＮｉ膜やＣｕ膜と、半田層との境界近傍にクラックが入る可能性がある。このように、Ａｌ膜にクラックが入ると半導体素子の機能が喪失するため、半導体装置の寿命が短くなるという問題がある。   However, in the technique of Patent Document 1 described above, when the lead frame is bonded to the electrode on the front surface of the semiconductor element via the third solder layer, the aluminum (Al) film as the electrode is damaged, and the semiconductor device There is a problem of extremely shortening the lifetime of the. The reason is that, on the front surface of the semiconductor element, an Al film, which is generally difficult to bond solder, is provided as an electrode. When a conductor such as a lead frame is bonded via solder, plating and vapor deposition are performed on the Al film. Alternatively, a process such as sputtering is performed to form a nickel (Ni) film or a Cu film that is excellent in solderability. At this time, since Ni and Cu have a higher Young's modulus than Al, when some force is applied, stress concentrates on the Al film and cracks are generated in the Al film. In addition, there is a possibility that a crack may occur in the vicinity of the boundary between the Ni film or Cu film on the front surface of the semiconductor element and the solder layer of the semiconductor layer. As described above, when the Al film is cracked, the function of the semiconductor element is lost, so that there is a problem that the life of the semiconductor device is shortened.

また、上述した特許文献２の技術では、半導体素子とリードフレームとを接合する半田の端部が、耐圧構造領域である絶縁層の上を覆うように設けられている。ここで、Ｎｉ膜や半田は、絶縁膜と接合しないため、半導体素子の表面電極であるＡｌ膜の、絶縁膜とＮｉ膜との境界部分に応力が集中する。このため、Ａｌ膜にクラックが生じ、半導体素子が破壊されるという問題が挙げられる。このことは、例えば半導体素子に設けられたトレンチの上に半田の端部が位置する場合も同様である。   Further, in the technique disclosed in Patent Document 2 described above, the end portion of the solder that joins the semiconductor element and the lead frame is provided so as to cover the insulating layer that is the breakdown voltage structure region. Here, since the Ni film and the solder do not join with the insulating film, stress concentrates on the boundary portion between the insulating film and the Ni film of the Al film that is the surface electrode of the semiconductor element. For this reason, there is a problem that a crack occurs in the Al film and the semiconductor element is destroyed. This is the same when, for example, the end portion of the solder is located on the trench provided in the semiconductor element.

この発明は、上述した従来技術による問題点を解消するため、半田により基板に接合された半導体素子の寿命を長くすることができる半導体装置を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of extending the life of a semiconductor element bonded to a substrate with solder in order to eliminate the above-described problems caused by the prior art.

上述した課題を解決し、目的を達成するため、この発明にかかる半導体装置は、半導体素子のおもて面に設けられた表面電極と、リードフレームとが半田層によって接合された半導体装置において、前記半田層が鉛フリー半田からなり、前記半田層の前記リードフレームとの接触面の端部より外側の領域の幅が、前記半田層の厚さの２倍以上であり、かつ、前記半田層の外周にわたってほぼ一定であり、前記リードフレームにかかるせん断応力の集中部が前記半田層と前記リードフレームとの境界近傍であることを特徴とする。 In order to solve the above-described problems and achieve the object, a semiconductor device according to the present invention is a semiconductor device in which a surface electrode provided on a front surface of a semiconductor element and a lead frame are joined by a solder layer. The solder layer is made of lead-free solder, and the width of the area outside the end of the contact surface of the solder layer with the lead frame is at least twice the thickness of the solder layer, and the solder layer wherein the of Ri substantially constant der around the periphery, concentration of the shearing stress applied to the lead frame is in the vicinity of the border of said lead frame with said solder layer.

また、この発明にかかる半導体装置は、上述した発明において、前記半導体素子は、前記表面電極の設けられた活性領域と、前記活性領域の周囲に設けられた耐圧構造領域と、を備え、前記表面電極は、前記活性領域において、前記半導体素子のおもて面上にアルミニウム膜と、ニッケル膜とが順に積層されてなり、前記アルミニウム膜は、前記半導体素子のおもて面上に前記活性領域から前記耐圧構造領域にわたって設けられており、前記ニッケル膜と、前記耐圧構造領域の前記アルミニウム膜上に設けられた絶縁膜との境界を、前記半田層が覆わないことを特徴とする。 The semiconductor device according to the present invention is the above-described invention, wherein the semiconductor element includes an active region provided with the surface electrode and a breakdown voltage structure region provided around the active region, electrode, said in the active region, and an aluminum film on a front surface of the semiconductor element, Ri is a nickel film Na are stacked in this order, wherein the aluminum film is on the front side of the semiconductor element The solder layer is provided from the active region to the breakdown voltage structure region , and the solder layer does not cover a boundary between the nickel film and the insulating film provided on the aluminum film in the breakdown voltage structure region.

また、この発明にかかる半導体装置は、上述した発明において、前記半田層の厚さは、５０μｍ以上５００μｍ以下であることを特徴とする。   In the semiconductor device according to the present invention as set forth in the invention described above, the thickness of the solder layer is 50 μm or more and 500 μm or less.

また、この発明にかかる半導体装置は、上述した発明において、前記半田層の厚さは、好ましくは、１５０μｍ以上２５０μｍ以下であることを特徴とする。   In the semiconductor device according to the present invention as set forth in the invention described above, the thickness of the solder layer is preferably 150 μm or more and 250 μm or less.

また、この発明にかかる半導体装置は、上述した発明において、前記半田層は、端部の形状が直線形状であることを特徴とする。   The semiconductor device according to the present invention is characterized in that, in the above-described invention, the solder layer has a linear shape at an end.

また、この発明にかかる半導体装置は、上述した発明において、前記半田層は、端部の形状が上に凸の形状であることを特徴とする。   The semiconductor device according to the present invention is characterized in that, in the above-described invention, the solder layer has a shape in which an end portion is convex upward.

また、この発明にかかる半導体装置は、上述した発明において、前記半導体素子は、縦型の絶縁ゲートバイポーラトランジスタであることを特徴とする。   In the semiconductor device according to the present invention as set forth in the invention described above, the semiconductor element is a vertical insulated gate bipolar transistor.

上述した各請求項の発明によれば、半導体素子とリードフレームとを接合している半田層にクラックが入る場合、半田層とリードフレームとの境界近傍にクラックが入るため、半導体素子の表面電極にクラックが入ることを抑えることができる。   According to the invention of each claim described above, when a crack is generated in the solder layer joining the semiconductor element and the lead frame, the crack is generated in the vicinity of the boundary between the solder layer and the lead frame. Can prevent cracks from entering.

上述した発明によれば、半導体素子とリードフレームとを接合している半田層が、活性領域と耐圧構造領域との境界を覆わないため、活性領域と耐圧構造領域との境界に応力が集中することを防ぐことができる。このため、この境界から、半導体素子の表面電極に直接クラックが入ることを防ぐことができる。   According to the above-described invention, since the solder layer that joins the semiconductor element and the lead frame does not cover the boundary between the active region and the breakdown voltage structure region, stress is concentrated on the boundary between the active region and the breakdown voltage structure region. Can be prevented. For this reason, it is possible to prevent cracks from directly entering the surface electrode of the semiconductor element from this boundary.

上述した発明によれば、半導体素子の表面電極の濡れ性を調整することで、半田層の半導体素子との接触面の端部の位置を調整することができる。したがって、半田層のリードフレームとの接触面の端部より外側の領域の幅を、所望の幅にすることができる。   According to the above-described invention, the position of the end portion of the contact surface of the solder layer with the semiconductor element can be adjusted by adjusting the wettability of the surface electrode of the semiconductor element. Therefore, the width of the region outside the end of the contact surface of the solder layer with the lead frame can be set to a desired width.

本発明にかかる半導体装置によれば、半田により基板に接合された半導体素子の寿命を長くすることができるという効果を奏する。   According to the semiconductor device of the present invention, there is an effect that the life of the semiconductor element bonded to the substrate by solder can be extended.

実施の形態１にかかる半導体装置の構造について示す要部の断面図である。FIG. 3 is a cross-sectional view of a main portion showing the structure of the semiconductor device according to the first embodiment. 実施の形態１にかかる半導体装置の、活性領域と耐圧構造領域との境界付近の構造について示す要部の断面図である。FIG. 3 is a cross-sectional view of a main portion showing the structure near the boundary between an active region and a breakdown voltage structure region of the semiconductor device according to the first embodiment; アスペクト比と、フィレットにかかる熱応力比と、の関係について示す特性図である。It is a characteristic view shown about the relationship between an aspect ratio and the thermal stress ratio concerning a fillet. アスペクト比が０．５の場合のせん断応力の分布を示す説明図である。It is explanatory drawing which shows distribution of the shear stress in case an aspect ratio is 0.5. アスペクト比が１．０の場合のせん断応力の分布を示す説明図である。It is explanatory drawing which shows distribution of the shear stress in case an aspect ratio is 1.0. アスペクト比が１．５の場合のせん断応力の分布を示す説明図である。It is explanatory drawing which shows distribution of the shear stress in case an aspect ratio is 1.5. アスペクト比が２．０の場合のせん断応力の分布を示す説明図である。It is explanatory drawing which shows distribution of the shear stress in case an aspect ratio is 2.0. アスペクト比が３．０の場合のせん断応力の分布を示す説明図である。It is explanatory drawing which shows distribution of the shear stress in case an aspect ratio is 3.0. アスペクト比が２．０で、フィレットの端部の形状が上に凸の場合のせん断応力の分布を示す説明図である。It is explanatory drawing which shows distribution of the shear stress in case an aspect ratio is 2.0 and the shape of the edge part of a fillet is convex upward. 実施の形態２にかかる半導体装置の製造方法について示す平面図である。FIG. 6 is a plan view showing a method for manufacturing a semiconductor device according to a second embodiment; 実施の形態２にかかる半導体装置の製造方法について示す平面図である。FIG. 6 is a plan view showing a method for manufacturing a semiconductor device according to a second embodiment; 実施の形態２にかかる半導体装置の製造方法について示す平面図である。FIG. 6 is a plan view showing a method for manufacturing a semiconductor device according to a second embodiment; 実施の形態２にかかる半導体装置の製造方法について示す平面図である。FIG. 6 is a plan view showing a method for manufacturing a semiconductor device according to a second embodiment; 第１従来例の半導体装置の構造について示す断面図である。It is sectional drawing shown about the structure of the semiconductor device of a 1st prior art example. 第２従来例の半導体装置の構造について示す断面図である。It is sectional drawing shown about the structure of the semiconductor device of a 2nd prior art example.

以下に添付図面を参照して、この発明にかかる半導体装置の好適な実施の形態を詳細に説明する。なお、以下の実施の形態の説明およびすべての添付図面において、同様の構成には同一の符号を付し、重複する説明を省略する。   Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. Note that, in the following description of the embodiments and all the attached drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

（実施の形態１）
図１は、実施の形態１にかかる半導体装置の構造について示す要部の断面図である。図１においては、パッケージ構造の半導体装置における半導体素子１と、リードフレーム３との接合部分を拡大して示している。図１に示すように、実施の形態１にかかる半導体装置において、半導体素子１は、半田層２を介してリードフレーム３と接合している。なお、半田層２のリードフレーム３との接触面の端部より外側の領域を、フィレット２０とする。 (Embodiment 1)
FIG. 1 is a cross-sectional view of the main part showing the structure of the semiconductor device according to the first embodiment. In FIG. 1, a joint portion between the semiconductor element 1 and the lead frame 3 in the semiconductor device having a package structure is shown enlarged. As shown in FIG. 1, in the semiconductor device according to the first embodiment, the semiconductor element 1 is joined to the lead frame 3 via the solder layer 2. A region outside the end of the contact surface of the solder layer 2 with the lead frame 3 is a fillet 20.

半導体素子１は、例えばおもて面側と裏面側に電極を有する、縦型のＩＧＢＴなどである。半導体素子１のおもて面には、表面電極１１が設けられている。表面電極１１は、例えばＡｌ膜１２の上にＮｉ膜１３が積層された構造となっている。Ａｌ膜１２の上に、Ｎｉ膜１３を積層する理由は、Ａｌ膜１２には、例えばＳｎＡｇ系のＰｂフリー半田を接合することが困難なためである。したがって、Ａｌ膜１２の上にＳｎＡｇ系のＰｂフリー半田が接合可能なＮｉ膜１３を積層する。   The semiconductor element 1 is, for example, a vertical IGBT having electrodes on the front surface side and the back surface side. A surface electrode 11 is provided on the front surface of the semiconductor element 1. The surface electrode 11 has a structure in which a Ni film 13 is laminated on an Al film 12, for example. The reason why the Ni film 13 is laminated on the Al film 12 is that it is difficult to bond, for example, SnAg-based Pb-free solder to the Al film 12. Therefore, the Ni film 13 to which SnAg-based Pb-free solder can be bonded is laminated on the Al film 12.

リードフレーム３は、例えばＣｕで作製されている。ここで、ＣｕとＮｉの濡れ広がりが異なるため、Ｃｕの表面で半田が広がりにくく、Ｎｉの表面で半田が広がりやすくなっている。このため、図１に示すように、半田とＮｉの接触面積が、半田とＣｕとの接触面積よりも大きくなるため、フィレット２０の形状は、リードフレーム３側から半導体素子１側に向かって広がった形状となる。なお、図１においては、フィレット２０の端部の形状を直線形状として記載しているが、例えば上に凸の形状でもよい。   The lead frame 3 is made of, for example, Cu. Here, since wetting and spreading of Cu and Ni are different, the solder hardly spreads on the surface of Cu, and the solder tends to spread on the surface of Ni. For this reason, as shown in FIG. 1, since the contact area between the solder and Ni is larger than the contact area between the solder and Cu, the shape of the fillet 20 expands from the lead frame 3 side toward the semiconductor element 1 side. Shape. In addition, in FIG. 1, although the shape of the edge part of the fillet 20 is described as a linear shape, an upward convex shape may be sufficient, for example.

半田層２の厚さｈは、例えば５０μｍ〜５００μｍ程度であり、１５０μｍ〜２５０μｍが好ましい。また、フィレット２０と半導体素子１（厳密には、Ｎｉ膜１３、以下同様）が接する領域の幅（以下、フィレット幅ｘとする）は、半田層２の厚さｈの２倍以上である。すなわち、フィレット幅ｘは、アスペクト比（フィレット幅ｘ／半田層２の厚さｈ）が２．０以上となるような幅である。その理由は後述する。   The thickness h of the solder layer 2 is, for example, about 50 μm to 500 μm, and preferably 150 μm to 250 μm. Further, the width (hereinafter referred to as fillet width x) of the region where the fillet 20 and the semiconductor element 1 (strictly speaking, the Ni film 13 and so on) are in contact is twice or more the thickness h of the solder layer 2. That is, the fillet width x is a width such that the aspect ratio (fillet width x / thickness h of the solder layer 2) is 2.0 or more. The reason will be described later.

また、図２は、実施の形態１にかかる半導体装置の、活性領域と耐圧構造領域との境界付近の構造について示す要部の断面図である。図２においては、半導体素子１の活性領域５１と、活性領域５１の周囲に設けられたガードリングなどの耐圧構造領域５２と、の境界付近の構造について拡大して示している。図２に示すように、実施の形態１にかかる半導体装置においては、フィレット２０の端部と半導体素子１（Ｎｉ膜１３）との境界点は、ガードリングとなる絶縁膜４とＮｉ膜１３との境界より、活性領域５１側である。すなわち、半田層２の端部が耐圧構造領域５２の絶縁膜４に達していない。   FIG. 2 is a cross-sectional view of the main part showing the structure near the boundary between the active region and the breakdown voltage structure region of the semiconductor device according to the first embodiment. In FIG. 2, the structure in the vicinity of the boundary between the active region 51 of the semiconductor element 1 and the breakdown voltage structure region 52 such as a guard ring provided around the active region 51 is shown in an enlarged manner. As shown in FIG. 2, in the semiconductor device according to the first embodiment, the boundary point between the end of the fillet 20 and the semiconductor element 1 (Ni film 13) is the insulating film 4 serving as a guard ring and the Ni film 13. From the boundary, the active region 51 side. That is, the end of the solder layer 2 does not reach the insulating film 4 in the breakdown voltage structure region 52.

（アスペクト比について）
つぎに、実施の形態１にかかる半導体装置におけるフィレットのアスペクト比について説明する。まず、アスペクト比が異なる場合にフィレットにかかる熱応力の比を、有限要素法（ＦＥＭ）解析によって構造解析した結果を図３に示す。図３は、アスペクト比と、フィレットにかかる熱応力比と、の関係について示す特性図である。なお、図３において、縦軸は、熱応力比であり、横軸は、アスペクト比である。また、ＦＥＭ解析の前提条件として、図１に示した層構成を仮定している。 (About aspect ratio)
Next, the aspect ratio of the fillet in the semiconductor device according to the first embodiment will be described. First, FIG. 3 shows the result of structural analysis of the ratio of thermal stress applied to the fillet when the aspect ratio is different by finite element method (FEM) analysis. FIG. 3 is a characteristic diagram showing the relationship between the aspect ratio and the thermal stress ratio applied to the fillet. In FIG. 3, the vertical axis represents the thermal stress ratio, and the horizontal axis represents the aspect ratio. Moreover, the layer structure shown in FIG. 1 is assumed as a precondition for the FEM analysis.

ここで、実施例においては、パワーサイクル試験を想定し、温度差が１００℃となるように、温度範囲を室温（約２５℃）から１２５℃にしたときの熱応力をＦＥＭ解析によって解析した。また、半田層の厚さｈを、１００μｍとした。なお、熱応力比は、フィレット幅ｘが１００μｍ（アスペクト比：１）のときに生じた熱応力を基準（１）とした比率である。   Here, in the examples, assuming a power cycle test, the thermal stress when the temperature range was changed from room temperature (about 25 ° C.) to 125 ° C. was analyzed by FEM analysis so that the temperature difference would be 100 ° C. Further, the thickness h of the solder layer was set to 100 μm. The thermal stress ratio is a ratio based on the thermal stress generated when the fillet width x is 100 μm (aspect ratio: 1) as a reference (1).

図３に示すように、アスペクト比が２以上になると、アスペクト比が１のときと比べて、表面電極に生じる熱応力が２５％程度低減する。したがって、後述するように、フィレットにかかるせん断応力の集中部がフィレットとリードフレームとの境界近傍となる。   As shown in FIG. 3, when the aspect ratio is 2 or more, the thermal stress generated in the surface electrode is reduced by about 25% compared to when the aspect ratio is 1. Therefore, as will be described later, the concentrated portion of shear stress applied to the fillet is in the vicinity of the boundary between the fillet and the lead frame.

なお、ＦＥＭ解析モデルは実機と同様の構造で、温度負荷に関しても同様としている。実機でもアスペクトを２以上にすることで、フィレットにかかるせん断応力の集中部がフィレットとリードフレームとの境界近傍になることを確認した。   The FEM analysis model has the same structure as the actual machine, and the same applies to the temperature load. In the actual machine, it was confirmed that by setting the aspect to 2 or more, the concentrated portion of the shear stress applied to the fillet is in the vicinity of the boundary between the fillet and the lead frame.

つぎに、ＦＥＭ解析結果のせん断応力分布について示す。図４〜図９においては、アスペクト比を変化させた場合の、フィレットにかかるせん断応力の分布を示している。図４は、アスペクト比が０．５の場合のせん断応力の分布を示す説明図である。また、図５は、アスペクト比が１．０の場合のせん断応力の分布を示す説明図である。図４または図５に示すように、アスペクト比が１．０以下の場合、せん断応力の集中部Ｐ１、Ｐ２がフィレット２１、２２と半導体素子１との境界近傍となる。したがって、半導体素子１の表面電極にクラックが入りやすくなり、半導体素子１の寿命が短くなる。   Next, the shear stress distribution of the FEM analysis result is shown. 4 to 9 show the distribution of shear stress applied to the fillet when the aspect ratio is changed. FIG. 4 is an explanatory diagram showing the distribution of shear stress when the aspect ratio is 0.5. FIG. 5 is an explanatory diagram showing the distribution of shear stress when the aspect ratio is 1.0. As shown in FIG. 4 or 5, when the aspect ratio is 1.0 or less, the shear stress concentration portions P <b> 1 and P <b> 2 are in the vicinity of the boundary between the fillets 21 and 22 and the semiconductor element 1. Therefore, the surface electrode of the semiconductor element 1 is easily cracked, and the life of the semiconductor element 1 is shortened.

図６は、アスペクト比が１．５の場合のせん断応力の分布を示す説明図である。図６に示すように、アスペクト比が１．５の場合、せん断応力の集中部Ｐ３がフィレット２３の端部全体に分布している。このため、フィレット２３の端部の全体にクラックの入る可能性があるため、半導体素子１の表面電極にクラックが入る可能性がある。   FIG. 6 is an explanatory diagram showing the distribution of shear stress when the aspect ratio is 1.5. As shown in FIG. 6, when the aspect ratio is 1.5, the shear stress concentration portion P <b> 3 is distributed over the entire end portion of the fillet 23. For this reason, since there is a possibility that cracks may occur in the entire end portion of the fillet 23, cracks may occur in the surface electrode of the semiconductor element 1.

図７は、アスペクト比が２．０の場合のせん断応力の分布を示す説明図である。また、図８は、アスペクト比が３．０の場合のせん断応力の分布を示す説明図である。図７または図８に示すように、アスペクト比が２．０以上の場合、せん断応力の集中部Ｐ４、Ｐ５がフィレット２４、２５とリードフレーム３との境界近傍となる。このため、半田層２にクラックが入っても、半導体素子１の表面電極からは遠いため、半導体素子１の表面電極にクラックが入りづらくなり、半導体素子１の寿命が長くなる。このように、アスペクト比を２．０以上とすることで、半導体素子１の寿命を長くすることができる。   FIG. 7 is an explanatory diagram showing the distribution of shear stress when the aspect ratio is 2.0. FIG. 8 is an explanatory diagram showing the distribution of shear stress when the aspect ratio is 3.0. As shown in FIG. 7 or FIG. 8, when the aspect ratio is 2.0 or more, the shear stress concentration portions P <b> 4 and P <b> 5 are near the boundaries between the fillets 24 and 25 and the lead frame 3. For this reason, even if a crack occurs in the solder layer 2, it is far from the surface electrode of the semiconductor element 1, so that it is difficult for the surface electrode of the semiconductor element 1 to crack, and the life of the semiconductor element 1 is prolonged. Thus, the lifetime of the semiconductor element 1 can be extended by setting the aspect ratio to 2.0 or more.

さらに、図９は、アスペクト比が２．０で、フィレットの端部の形状が上に凸の場合のせん断応力の分布を示す説明図である。図９に示すように、フィレット２６の端部の形状が上に凸の形状でも、直線形状の場合と同様に、せん断応力の集中部Ｐ６がフィレット２６とリードフレーム３との境界近傍となる。したがって、フィレット２６の端部の形状によらず、アスペクト比が２．０以上の場合は、半導体素子１の寿命が長くなることがわかる。   Further, FIG. 9 is an explanatory diagram showing the distribution of shear stress when the aspect ratio is 2.0 and the shape of the end of the fillet is convex upward. As shown in FIG. 9, even when the shape of the end portion of the fillet 26 is convex upward, the shear stress concentration portion P <b> 6 is near the boundary between the fillet 26 and the lead frame 3, as in the case of the linear shape. Therefore, regardless of the shape of the end of the fillet 26, it can be seen that when the aspect ratio is 2.0 or more, the life of the semiconductor element 1 is extended.

上述した実施の形態１によれば、半導体素子のおもて面側と、リードフレームとに挟まれた半田層の端部において、半田層へのクラックが、半田層とリードフレームとの境界の近傍に生じやすいため、半導体素子の表面電極にクラックが入ることを防ぐことができる。また、活性領域に形成されたＮｉ膜と、耐圧構造領域に形成された絶縁膜との境界に半田層が達していないため、Ｎｉ膜と絶縁膜との境界にせん断応力が集中するのを防ぎ、表面電極のＡｌ膜に直接クラックが入ることを防ぐことができる。   According to the first embodiment described above, cracks in the solder layer occur at the boundary between the solder layer and the lead frame at the end of the solder layer sandwiched between the front surface side of the semiconductor element and the lead frame. Since it is likely to occur in the vicinity, cracks can be prevented from entering the surface electrode of the semiconductor element. In addition, since the solder layer does not reach the boundary between the Ni film formed in the active region and the insulating film formed in the breakdown voltage structure region, shear stress is prevented from concentrating on the boundary between the Ni film and the insulating film. Further, it is possible to prevent cracks from being directly formed in the Al film of the surface electrode.

（実施の形態２）
つぎに、実施の形態２にかかる半導体装置の製造方法について説明する。図１０〜図１３は、実施の形態２にかかる半導体装置の製造方法について順に示す平面図である。まず、図１０に示すように、半導体素子１の活性領域５１の周囲の耐圧構造領域５２において、ガードリングとなる絶縁膜４を形成する。 (Embodiment 2)
Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. 10 to 13 are plan views sequentially illustrating the method for manufacturing the semiconductor device according to the second embodiment. First, as shown in FIG. 10, the insulating film 4 serving as a guard ring is formed in the breakdown voltage structure region 52 around the active region 51 of the semiconductor element 1.

ついで、図１１に示すように、活性領域５１と絶縁膜４の境界部分に、カプトンテープやポリイミドなどの高耐熱有機材料によりマスク５３を形成する。マスク５３の幅は、チップサイズ、チップ上に接合するリードフレームの大きさ、半田層の厚さを考慮して、アスペクト比２となるようにする。具体的には、例えば半田層の厚さを１００μｍ程度にする場合、チップ上に接合するリードフレームより２００μｍほど大きな開口部を設けたマスクを形成する。   Next, as shown in FIG. 11, a mask 53 is formed of a high heat resistant organic material such as Kapton tape or polyimide at the boundary between the active region 51 and the insulating film 4. The width of the mask 53 is set to an aspect ratio of 2 in consideration of the chip size, the size of the lead frame bonded on the chip, and the thickness of the solder layer. Specifically, for example, when the thickness of the solder layer is set to about 100 μm, a mask having an opening that is 200 μm larger than the lead frame to be bonded on the chip is formed.

ついで、図１２に示すように、半田層のフィレットにおけるアスペクト比が２以上になる量の、板半田またはクリーム半田などのＰｂフリー半田２ａを活性領域５１の表面電極の上に設ける。Ｐｂフリー半田としては、例えばＳｎＡｇ系半田が好ましい。ここで、半田２ａを設ける前に、半導体素子１の表面電極の清浄度を高めてもよい。具体的には、半導体素子１の表面電極に例えばＡｕなどのめっきを施す。また、半導体素子１の表面電極の表面の酸化膜を、プラズマ洗浄や水素還元などにより除去する。このようにすることで、半導体素子１の表面電極における半田の濡れ性が向上する。なお、これらの処理は、図１１に示すマスクを施す処理の前におこなってもよい。   Next, as shown in FIG. 12, Pb-free solder 2a such as plate solder or cream solder is provided on the surface electrode of the active region 51 so that the aspect ratio of the fillet of the solder layer is 2 or more. As the Pb-free solder, for example, SnAg solder is preferable. Here, before providing the solder 2a, the cleanliness of the surface electrode of the semiconductor element 1 may be increased. Specifically, the surface electrode of the semiconductor element 1 is plated with, for example, Au. Further, the oxide film on the surface electrode of the semiconductor element 1 is removed by plasma cleaning, hydrogen reduction, or the like. By doing in this way, the wettability of the solder in the surface electrode of the semiconductor element 1 improves. Note that these processes may be performed before the masking process shown in FIG.

ついで、図１３に示すように、Ｐｂフリー半田２ａの上にリードフレーム３を載置し、Ｐｂフリー半田２ａが半導体素子１とリードフレーム３とに挟まれた状態のまま、リフロー炉に投入し加熱する。このようにすることで、半導体素子１とリードフレーム３とを半田２ａを介して接合する。   Next, as shown in FIG. 13, the lead frame 3 is placed on the Pb-free solder 2a, and the Pb-free solder 2a is put in the reflow furnace while being sandwiched between the semiconductor element 1 and the lead frame 3. Heat. By doing in this way, the semiconductor element 1 and the lead frame 3 are joined via the solder 2a.

上述した実施の形態２によれば、実施の形態１と同様の効果を得ることができる。また、半導体素子の表面電極の濡れ性を向上させることで、フィレットの半導体素子との接触面の端部の位置を調整し、フィレットのアスペクト比を調整することができる。   According to the second embodiment described above, the same effect as in the first embodiment can be obtained. Further, by improving the wettability of the surface electrode of the semiconductor element, the position of the end of the contact surface of the fillet with the semiconductor element can be adjusted, and the aspect ratio of the fillet can be adjusted.

以上のように、本発明にかかる半導体装置は、高温で動作するパワーデバイスに有用であり、特に、半導体素子の表面電極に半田を介してリードフレームを接合する半導体装置に適している。   As described above, the semiconductor device according to the present invention is useful for a power device that operates at a high temperature, and is particularly suitable for a semiconductor device in which a lead frame is bonded to a surface electrode of a semiconductor element via solder.

１ 半導体素子
２ 半田層
３ リードフレーム
１１ 表面電極
１２ Ａｌ膜
１３ Ｎｉ膜
２０ フィレット DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Solder layer 3 Lead frame 11 Surface electrode 12 Al film 13 Ni film 20 Fillet

Claims (7)

半導体素子のおもて面に設けられた表面電極と、リードフレームとが半田層によって接合された半導体装置において、
前記半田層が鉛フリー半田からなり、
前記半田層の前記リードフレームとの接触面の端部より外側の領域の幅が、前記半田層の厚さの２倍以上であり、かつ、前記半田層の外周にわたってほぼ一定であり、
前記リードフレームにかかるせん断応力の集中部が前記半田層と前記リードフレームとの境界近傍であることを特徴とする半導体装置。 In a semiconductor device in which a surface electrode provided on the front surface of a semiconductor element and a lead frame are joined by a solder layer,
The solder layer is made of lead-free solder,
Width of the outer region from the end portion of the contact surface between the lead frame of the solder layer, the more than twice the thickness of the solder layer, and, Ri approximately constant der around the periphery of the solder layer,
A semiconductor device, wherein a concentrated portion of shear stress applied to the lead frame is in the vicinity of a boundary between the solder layer and the lead frame . 前記半導体素子は、前記表面電極の設けられた活性領域と、前記活性領域の周囲に設けられた耐圧構造領域と、を備え、
前記表面電極は、前記活性領域において、前記半導体素子のおもて面上にアルミニウム膜と、ニッケル膜とが順に積層されてなり、
前記アルミニウム膜は、前記半導体素子のおもて面上に前記活性領域から前記耐圧構造領域にわたって設けられており、
前記ニッケル膜と、前記耐圧構造領域の前記アルミニウム膜上に設けられた絶縁膜との境界を、前記半田層が覆わないことを特徴とする請求項１に記載の半導体装置。 The semiconductor element includes an active region provided with the surface electrode, and a breakdown voltage structure region provided around the active region,
It said surface electrode, in the active region, and an aluminum film on a front surface of the semiconductor element, Ri is a nickel film Na are stacked in this order,
The aluminum film is provided on the front surface of the semiconductor element from the active region to the breakdown voltage structure region,
2. The semiconductor device according to claim 1, wherein the solder layer does not cover a boundary between the nickel film and an insulating film provided on the aluminum film in the breakdown voltage structure region. 前記半田層の厚さは、５０μｍ以上５００μｍ以下であることを特徴とする請求項１または２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the solder layer has a thickness of 50 μm or more and 500 μm or less. 前記半田層の厚さは、好ましくは、１５０μｍ以上２５０μｍ以下であることを特徴とする請求項３に記載の半導体装置。   The semiconductor device according to claim 3, wherein a thickness of the solder layer is preferably 150 μm or more and 250 μm or less. 前記半田層は、端部の形状が直線形状であることを特徴とする請求項１〜４のいずれか一つに記載の半導体装置。   The semiconductor device according to claim 1, wherein the solder layer has a linear shape at an end portion. 前記半田層は、端部の形状が上に凸の形状であることを特徴とする請求項１〜４のいずれか一つに記載の半導体装置。   The semiconductor device according to claim 1, wherein the solder layer has a shape in which an end portion is convex upward. 前記半導体素子は、縦型の絶縁ゲートバイポーラトランジスタであることを特徴とする請求項１〜６のいずれか一つに記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor element is a vertical insulated gate bipolar transistor.
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