JP6479036B2 - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP6479036B2
JP6479036B2 JP2016556123A JP2016556123A JP6479036B2 JP 6479036 B2 JP6479036 B2 JP 6479036B2 JP 2016556123 A JP2016556123 A JP 2016556123A JP 2016556123 A JP2016556123 A JP 2016556123A JP 6479036 B2 JP6479036 B2 JP 6479036B2
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solder
semiconductor device
electrode
external electrode
film
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洋輔 中田
洋輔 中田
三紀夫 石原
三紀夫 石原
達也 川瀬
達也 川瀬
井本　裕児
裕児 井本
晋助 浅田
晋助 浅田
藤野　純司
純司 藤野
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Mitsubishi Electric Corp
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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/732—Location after the connecting process
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

本発明は、ＩＧＢＴ（Insulated Gate Bipolor Transistor）、ＭＯＳＦＥＴ、あるいはダイオードなどの半導体素子を用いた半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device using a semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor), a MOSFET, or a diode, and a method of manufacturing the same.

従来の電力用の半導体素子を用いた半導体装置において、半導体素子に設けられる素子側電極と外部電極との電気的接続を半田接合材を介挿して行った半導体装置がある。このような半田接合を行う半導体装置では、半田接合材によって素子側電極の一部に応力が集中することにより、素子側電極と外部電極との電気的接続が良好に行えないという技術課題が存在する。   In a conventional semiconductor device using a power semiconductor element, there is a semiconductor device in which an electrical connection between an element side electrode provided on the semiconductor element and an external electrode is performed by inserting a solder bonding material. In a semiconductor device that performs such solder bonding, there is a technical problem that electrical connection between the device side electrode and the external electrode can not be favorably performed because stress is concentrated on a part of the device side electrode by the solder bonding material. Do.

上述した技術課題を解決するための技術的工夫を図った半導体装置として、例えば、特許文献１で開示された半導体装置がある。   A semiconductor device disclosed in Patent Document 1 is, for example, a semiconductor device in which the technical device for solving the above-described technical problems has been devised.

この半導体装置は、素子側電極である表面電極上にメッキ電極を形成し、メッキ電極と外部電極との間に半田接合材を設けて、表面電極，外部電極間の電気的接続を図る際、メッキ電極の外縁部に応力が集中してメッキ電極が剥離することを抑制すべく、メッキ電極の平面形状を外部電極より広くし、外部電極の側面からメッキ電極端の側面にかけて、半田接合材の端面の断面形状に傾きを持たせた端面傾き形状を設けている。   In this semiconductor device, a plated electrode is formed on a surface electrode which is an element side electrode, a solder bonding material is provided between the plated electrode and the external electrode, and electrical connection between the surface electrode and the external electrode is intended. In order to suppress stress concentration on the outer edge of the plating electrode and exfoliation of the plating electrode, the planar shape of the plating electrode is made wider than the external electrode, and the solder bonding material is made from the side surface of the external electrode to the side surface of the plating electrode An end face inclined shape is provided in which the cross-sectional shape of the end face is inclined.

特開２００８−２４４０４５号公報（図２）JP 2008-244045 A (FIG. 2)

しかしながら、特許文献１で開示された半導体装置は、上記端面傾き形状を設けるために、外部電極よりも広い面積でメッキ電極を形成する必要性から、外部電極の接合面積が、メッキ電極、すなわち、半導体素子の表面電極における半田接合面積より必ず小さくなってしまう結果、外部電極，表面電極間の電流密度向上に限界が生じてしまう問題点があった。   However, in the semiconductor device disclosed in Patent Document 1, the bonding area of the external electrode is the plating electrode, that is, because it is necessary to form the plating electrode in a larger area than the external electrode in order to provide the end face inclination shape. As a result of the area necessarily becoming smaller than the solder joint area of the surface electrode of the semiconductor element, there is a problem that the improvement of the current density between the external electrode and the surface electrode is limited.

また、半導体素子としてＳｉＣ半導体素子等、高温対応半導体素子は大面積化が難しいという、別の課題を有しているため、この別の課題が、上記問題点の解消をより困難にしてしまうことになる。   In addition, since other semiconductor devices compatible with high temperature, such as SiC semiconductor devices as semiconductor devices, have another problem that enlargement of area is difficult, this other problem makes it more difficult to solve the above problems. become.

一般に電力用のパワー半導体モジュールと呼ばれる半導体装置では、半導体素子から発熱があり、パワー半導体モジュールの内部に温度サイクルが発生し、電流が流れる部分に大きな熱ストレスが加わる。特に、上述した高温対応半導体素子では、電流密度や使用温度範囲が高くなるため、より大きなストレスが加わることとなる。   In a semiconductor device generally called a power semiconductor module for power, heat is generated from the semiconductor element, a temperature cycle occurs inside the power semiconductor module, and a large thermal stress is applied to a portion through which current flows. In particular, in the above-described high-temperature compatible semiconductor element, the current density and the operating temperature range become high, so that a larger stress is applied.

さらに、半導体素子の大面積化も難しい。このため、特許文献１に開示された半導体装置のように、外部電極側の接合面積を必然的に半導体素子の表面電極より小さく設計することが要求される半導体装置では、外部電極側で接合面積が小さくなり電流密度が高くなるため半田クラック等に対する許容度も少なくなる。   Furthermore, it is difficult to increase the area of the semiconductor element. For this reason, as in the semiconductor device disclosed in Patent Document 1, in the semiconductor device which is required to design the junction area on the external electrode side necessarily smaller than the surface electrode of the semiconductor element, the junction area on the external electrode side As the current density becomes higher, the tolerance to solder cracks and the like also decreases.

加えて、特許文献１で開示された半導体装置は、外部電極側における半田に発生する応力を緩和する構造が採用されていないため半田クラックを誘導しやすいという問題点があるため、良好な通電性を確保するための高電流密度と装置の高信頼性とを両立できていないという問題点があった。   In addition, since the semiconductor device disclosed in Patent Document 1 does not employ a structure for relieving stress generated in the solder on the external electrode side, there is a problem that solder cracks are easily induced. There is a problem that the high current density for securing and the high reliability of the device can not be simultaneously achieved.

本発明では、上記のような問題点を解決し、外部電極との通電性の向上と装置の高信頼性とを共に実現した半田接合構造の半導体装置を提供することを目的とする。   An object of the present invention is to solve the above-mentioned problems and to provide a semiconductor device having a solder joint structure, which realizes both the improvement of the conductivity with the external electrode and the high reliability of the device.

この発明に係る請求項１記載の本願発明の半導体装置は、一方主面及び他方主面を有し、一方主面上に平坦な表面を有する一方電極が設けられる半導体素子と、前記一方電極の上方に設けられた外部電極とを備え、前記外部電極の表面と前記一方電極の表面とが対向し、前記一方電極の表面，前記外部電極の表面間に形成され、前記一方電極，前記外部電極間を電気的に接続する半田形成部をさらに備え、前記一方電極及び前記外部電極が平面視重複する領域の少なくとも一部が、前記一方電極及び前記外部電極それぞれの表面における第１及び第２の半田接合領域として規定され、前記外部電極は、他の領域より前記一方電極の表面側に突出した垂下部を有し、前記垂下部は平面視して前記第２の半田接合領域を含み、前記第１及び第２の半田接合領域の中心位置である半田中心点に向かって、前記外部電極の表面と前記一方電極の表面との垂直距離が短くなる傾斜部を有し、前記半田形成部は、前記一方電極の前記第１の半田接合領域から前記外部電極の前記第２の接合領域にかけて形成され、前記一方電極の表面から上方にかけて前記半田中心点の方向に湾曲した第１の湾曲形状と、前記外部電極の表面から下方にかけて前記半田中心点の方向に湾曲した第２の湾曲形状とを含む端面形状を有し、前記外部電極の表面における前記第２の半田接合領域上に少なくとも設けられ、前記外部電極に比べ半田濡れ性が優る構成材料で形成された被覆膜をさらに備え、前記被覆膜は前記外部電極の表面における前記垂下部上にのみに形成される。

A semiconductor device according to the present invention according to claim 1 of the present invention comprises a semiconductor element having one main surface and the other main surface and provided with one electrode having a flat surface on one main surface, and the above-mentioned one electrode An external electrode provided on the upper side, the surface of the external electrode and the surface of the one electrode face each other, and formed between the surface of the one electrode and the surface of the external electrode, the one electrode, the external electrode The semiconductor device further includes a solder formation portion electrically connecting the first and second electrodes on the surface of each of the one electrode and the external electrode, at least a part of a region where the one electrode and the external electrode overlap in plan view. The external electrode has a drooping portion that protrudes from the other region to the surface side of the one electrode, and the drooping portion includes the second solder bonding region in plan view. First and second The solder forming portion has an inclined portion in which the vertical distance between the surface of the external electrode and the surface of the one electrode is shortened toward the solder center point which is the center position of the junction region, and the solder forming portion A first curved shape formed from a first solder joint area to the second joint area of the external electrode and curved in the direction of the solder center point from the surface of the one electrode to the upper side, and the surface of the external electrode from possess an end surface shape and a second curved shape curved in the direction of the solder center point to bottom, at least provided on the second solder joint region on the surface of the external electrode, compared to the external electrode A coating film formed of a constituent material having excellent solder wettability is further provided, wherein the coating film is formed only on the hanging portion on the surface of the external electrode .

請求項１記載の本願発明の半導体装置における半田形成部は、一方電極の表面からの第１の湾曲形状と外部電極の表面からの第２の湾曲形状とを含む端面形状を有するため、一方電極及び他方電極の第１及び第２の半田接合領域それぞれに発生する応力の低減を図ることにより、半田形成部の信頼性の向上を図ることができる。   The solder forming portion in the semiconductor device of the present invention according to claim 1 has an end face shape including the first curved shape from the surface of the one electrode and the second curved shape from the surface of the external electrode. The reliability of the solder-formed portion can be improved by reducing the stress generated in each of the first and second solder connection regions of the other electrode.

また、請求項１記載の本願発明は、半田形成部が第１及び第２の湾曲形状を含む端面形状を有する態様で、一方電極及び外部電極が平面視重複する領域を全て第１及び第２の半田接合領域に設定することができるため、第１及び第２の半田接合領域の面積の拡大を図ることにより、一方電極及び外部電極間の通電能力の向上を図ることができる。   Further, the present invention according to claim 1 is an aspect in which the solder formation portion has an end face shape including the first and second curved shapes, and all the regions where one electrode and the external electrode overlap in plan view are the first and second Since the area of the first and second solder connection regions can be expanded, the current-carrying capacity between the one electrode and the external electrode can be improved.

この発明の目的、特徴、局面、及び利点は、以下の詳細な説明と添付図面とによって、より明白となる。   The objects, features, aspects and advantages of the present invention will be more apparent from the following detailed description and the accompanying drawings.

この発明の実施の形態１である半導体装置の構造を示す断面図である。FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to Embodiment 1 of the present invention. 図１の半導体装置における着目領域を拡大した要部の断面図である。It is sectional drawing of the principal part which expanded the view area | region in the semiconductor device of FIG. 実施の形態１の上面構造を模式的に示した説明図である。FIG. 2 is an explanatory view schematically showing an upper surface structure of the first embodiment. 実施の形態２の半導体装置の構造を示す断面図である。FIG. 18 is a cross-sectional view showing the structure of the semiconductor device of Embodiment 2; 実施の形態３の半導体装置の特徴部の構造を示す説明図である。FIG. 18 is an explanatory view showing a structure of a characterizing part of the semiconductor device of the embodiment 3; 実施の形態４における第１の態様の半導体装置の特徴部の構造を示す説明図である。FIG. 33 is an explanatory drawing showing the structure of a characterizing part of the semiconductor device of the first aspect in the fourth embodiment. 実施の形態４における第２の態様の半導体装置の特徴部の構造を示す説明図である。FIG. 33 is an explanatory view showing a structure of a characterizing portion of the semiconductor device of the second aspect in the fourth embodiment.

＜実施の形態１＞
（構成）
図１は、この発明の実施の形態１である半導体装置の構造を示す断面図である。図２は、図１で示した半導体装置における着目領域Ｃ１１を拡大した要部の断面図である。図３は実施の形態１の上面構造を模式的に示した説明図である。なお、図３のＡ−Ａ断面が図１で示す構造に対応している。また、図１〜図３にはＸＹＺ直交座標系を示している。Embodiment 1
(Constitution)
FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of an essential part of the region of interest C11 in the semiconductor device shown in FIG. FIG. 3 is an explanatory view schematically showing an upper surface structure of the first embodiment. In addition, the AA cross section of FIG. 3 respond | corresponds to the structure shown in FIG. Further, FIGS. 1 to 3 show an XYZ orthogonal coordinate system.

これらの図に示すように、縦型のＩＧＢＴ等の半導体素子１は表面及び裏面（一方主面及び他方主面）を有し、表面上に平坦な表面を有する表面電極１１（一方電極）が設けられる。   As shown in these figures, a semiconductor element 1 such as a vertical IGBT has a surface electrode 11 (one electrode) having a front surface and a back surface (one main surface and the other main surface) and having a flat surface on the surface. Provided.

そして、表面電極１１の上方に、互いの表面が対向する態様で設けられた外部電極３１が設けられる。なお、本明細書では、説明の都合上、表面電極１１，外部電極３１間で互いに対向する面を表面とする。すなわち、表面電極１１において＋Ｚ方向側の面を表面、外部電極３１において−Ｚ方向側の面を表面として説明する。   Then, an external electrode 31 is provided above the surface electrode 11 in such a manner that the surfaces thereof face each other. In the present specification, for convenience of description, surfaces facing each other between the surface electrode 11 and the external electrode 31 are referred to as the surface. That is, the surface on the + Z direction side of the surface electrode 11 will be described as the surface, and the surface on the −Z direction side of the external electrode 31 will be described as the surface.

そして、半導体素子上半田２１（半田形成部）が、表面電極１１の表面，外部電極３１の表面間に形成されることにより、表面電極１１，外部電極３１間を電気的に接続する。   Then, the on-semiconductor-element solder 21 (solder-formed portion) is formed between the surface of the surface electrode 11 and the surface of the external electrode 31 to electrically connect the surface electrode 11 and the external electrode 31.

表面電極１１と外部電極３１とが平面視重複する全部及び大部分の領域が、表面電極１１及び外部電極３１の表面における半田接合領域Ｒ１１ｈ及びＲ３１ｈ（第１及び第２の半田接合領域）として規定される。実施の形態１では、図１及び図３に示すように、半田接合領域Ｒ１１ｈ及び半田接合領域Ｒ３１ｈが平面視して完全一致している態様を示している。   All and most of areas where the surface electrode 11 and the external electrode 31 overlap in plan view are defined as solder joint areas R11h and R31h (first and second solder joint areas) on the surface of the surface electrode 11 and the external electrode 31 Be done. In the first embodiment, as shown in FIGS. 1 and 3, an aspect is shown in which the solder joint region R11 h and the solder joint region R31 h completely coincide with each other in plan view.

外部電極３１は他の領域より表面電極１１の表面側（−Ｚ側）に突出した垂下部３１ａを有している。垂下部３１ａの平面形状を半田接合領域Ｒ３１ｈと一致させても良い。   The external electrode 31 has a drooping portion 31 a that protrudes to the surface side (−Z side) of the surface electrode 11 from other regions. The planar shape of the hanging portion 31a may be made to coincide with the solder bonding region R31h.

この垂下部３１ａは、半田接合領域Ｒ３１ｈを含む領域に設けられ、半田接合領域Ｒ１１ｈ及びＲ３１ｈの中心位置である半田中心点ＨＣ（図３参照）の方向に向かって、外部電極３１の表面と表面電極１１の表面との垂直距離ＤＡが短くなる傾斜部３１ｓを有している。例えば、図２に示すように、半田中心点ＨＣの方向である＋Ｘ方向側に位置する垂直距離ＤＡ１は、相対的に−Ｘ方向側に位置する垂直距離ＤＡ２より短くなる。なお、半田中心点ＨＣを含む垂下部３１ａの底面部３１ｍは垂直距離ＤＡが一定の平坦構造を呈している。   The drooping portion 31a is provided in a region including the solder joint region R31h, and the surface and the surface of the external electrode 31 in the direction of the solder center point HC (see FIG. 3) which is the central position of the solder joint regions R11h and R31h. There is an inclined portion 31s in which the vertical distance DA with the surface of the electrode 11 is shortened. For example, as shown in FIG. 2, the vertical distance DA1 located on the + X direction side, which is the direction of the solder center point HC, is shorter than the vertical distance DA2 located relatively on the −X direction side. The bottom portion 31m of the hanging portion 31a including the solder center point HC has a flat structure in which the vertical distance DA is constant.

半導体素子上半田２１は、表面電極１１の半田接合領域Ｒ１１ｈから外部電極３１の半田接合領域Ｒ３１ｈにかけて形成される。正確には、表面電極１１上の半田接合領域Ｒ１１ｈに半田接合用金属膜１３が形成され、この半田接合用金属膜１３上に形成された半導体素子上半田２１を介して、表面電極１１，外部電極３１との電気的接続が行われている。   The solder on semiconductor element 21 is formed from the solder joint region R11h of the surface electrode 11 to the solder joint region R31h of the external electrode 31. More precisely, the solder bonding metal film 13 is formed on the solder bonding region R11 h on the surface electrode 11, and the surface electrode 11 is exposed via the solder 21 on the semiconductor element formed on the solder bonding metal film 13. Electrical connection with the electrode 31 is made.

半導体素子上半田２１は、図２に示すように、表面電極１１の表面から上方（＋Ｚ方向）にかけて半田中心点ＨＣの方向（図２では＋Ｘ方向）に湾曲したフィレットＦ１（第１の湾曲形状）と、外部電極３１の表面から下方（−Ｚ方向）にかけて半田中心点ＨＣの方向に湾曲したフィレットＦ２（第２の湾曲形状）とを含む端面形状を有している。以下、図２で示したフィレットＦ１及びＦ２を有する垂下部３１ａの端面形状を「上下フィレット構造」と呼ぶ場合がある。   As shown in FIG. 2, the solder on semiconductor element 21 is a fillet F1 (first curved shape) curved in the direction of the solder center point HC (+ X direction in FIG. 2) from the surface of the surface electrode 11 to the upper side (+ Z direction). And a fillet F2 (second curved shape) curved in the direction of the solder center point HC from the surface of the external electrode 31 to the lower side (−Z direction). Hereinafter, the end face shape of the hanging portion 31a having the fillets F1 and F2 shown in FIG. 2 may be referred to as "upper and lower fillet structure".

このように、半導体素子１は、半田接合領域Ｒ１１ｈ及びＲ３１ｈにおいて、半導体素子上半田２１を介して表面電極１１，外部電極３１間が半田接合されることにより、表面電極１１，外部電極３１間の電気的接続が行われる。   As described above, in the semiconductor element 1, the surface electrode 11 and the external electrode 31 are soldered to each other through the solder 21 on the semiconductor element in the solder bonding regions R11 h and R 31 h, whereby the surface electrode 11 and the external electrode 31 are interposed. Electrical connection is made.

互いに同一の半田接合領域Ｒ１１ｈ及びＲ３１ｈの平面形状として、少なくとも１つ以上の平面視矩形状が考えられる。例えば、図３に示すように、角部が曲率半径ｒ２で丸められた平面視矩形状の２つの半田接合領域Ｒ１１ｈ及びＲ３１ｈが設けられる構造を採用しても良い。また、図３で示す構造では、垂下部３１ａの底面部３１ｍも平面視矩形状で形成され、底面部３１ｍの外周と半田接合領域Ｒ１１ｈ（Ｒ３１ｈ）の外周との平面距離ｒ１が設定されている。図３で示す構造では、垂下部３１ａも２つの半田接合領域Ｒ３１ｈに対応して２つ設けられ、半導体素子上半田２１も半田接合領域Ｒ１１ｈ及びＲ３１ｈに対応して２つ設けられることになる。   At least one or more rectangular shapes in plan view can be considered as planar shapes of the same solder joint regions R11h and R31h. For example, as shown in FIG. 3, a structure may be employed in which two solder joint regions R11h and R31h having a rectangular shape in a plan view and in which the corner portion is rounded at a curvature radius r2 are provided. Further, in the structure shown in FIG. 3, the bottom 31m of the hanging portion 31a is also formed in a rectangular shape in a plan view, and a plane distance r1 between the outer periphery of the bottom 31m and the outer periphery of the solder joint region R11h (R31h) is set. . In the structure shown in FIG. 3, two drooping portions 31a are also provided corresponding to two solder joint regions R31h, and two semiconductor element solders 21 are also provided corresponding to solder joint regions R11h and R31h.

このように、複数の半田接合領域Ｒ１１ｈ及びＲ３１ｈに対応した複数の半導体素子上半田２１を設けることによって表面電極１１及び外部電極３１間の電気的に接続を図ることにより、例えば、ゲート配線形成領域等の半田形成を望まない表面電極１１上の領域を避けることができ、表面電極１１及び外部電極３１間のフレキシブルな電気的接続が可能となる効果を奏する。   Thus, by providing the plurality of on-semiconductor-element solders 21 corresponding to the plurality of solder bonding regions R11h and R31h to electrically connect the surface electrodes 11 and the external electrodes 31, for example, a gate wiring formation region And the like on the surface electrode 11 where the formation of solder is not desired can be avoided, and the flexible electrical connection between the surface electrode 11 and the external electrode 31 can be achieved.

図３に示すように、半田接合領域Ｒ１１ｈ及びＲ３１ｈを平面視矩形状に形成するのは、半導体素子１が一般的にウエハを矩形状（長方形）に切りだして得られるのが一般的であり、半田接合領域Ｒ１１ｈの形状も半導体素子１と同様に矩形状に形成することで、半導体素子１の終端部から一定の距離を確保しつつ、かつ、最大の接合面積を得ることができるためである。   As shown in FIG. 3, the solder bonding regions R11h and R31h are generally formed in a rectangular shape in plan view because the semiconductor element 1 is generally obtained by cutting a wafer into a rectangular shape (rectangular shape). By forming the solder bonding region R11h in a rectangular shape as in the semiconductor element 1, it is possible to obtain a maximum bonding area while securing a constant distance from the terminal end of the semiconductor element 1. is there.

また、図３に示すように、半田接合領域Ｒ１１ｈの角部は曲率半径ｒ２で面取りされていることが望ましい。これは、半導体素子上半田２１が角部へ濡れ広がるときに直角であると半田の表面張力により角度の急な形状には濡れ広がり難いため、曲状に面取りし角部の角度を緩やかにすることで、半田接合領域Ｒ１１ｈ及びＲ３１ｈの全域へ確実に半田を濡れ広げることができるためである。   Further, as shown in FIG. 3, it is desirable that the corner portion of the solder joint region R11 h is chamfered with a curvature radius r2. This is because when the solder on the semiconductor element 21 spreads to the corner, the surface tension of the solder does not easily spread due to the surface tension of the solder if it is perpendicular, so the beveled corner makes the angle of the corner loose. This is because the solder can be surely spread over the entire area of the solder bonding regions R11h and R31h.

前述したように、半田接合領域Ｒ１１ｈ及び半田接合領域Ｒ３１ｈは互いに平面視同一形状で形成されているため、半田接合領域Ｒ３１ｈ及び半田接合領域Ｒ１１ｈそれぞれにおいて、半導体素子上半田２１と接合する半田濡れ角（半田なす角）が等しくなり、双方に共通した半田フィレット形状（フィレットＦ２及びＦ１）を形成することができる。   As described above, since the solder joint region R11h and the solder joint region R31h are formed in the same shape in plan view, the solder wetting angle with the solder on the semiconductor element 21 in each of the solder joint region R31h and the solder joint region R11h (Soldering angles) become equal, and it is possible to form a solder fillet shape (fillets F2 and F1) common to both.

前述したように、外部電極３１の垂下部３１ａは、平坦な底面部３１ｍを有する。半導体装置１０１を上面視したとき、底面部３１ｍの各辺は、半田接合領域Ｒ３１ｈの外周における対応する辺から、一定の平面距離ｒ１をもって内側に位置する。前述した通り、半田接合領域Ｒ３１ｈと半田接合領域Ｒ１１ｈとの平面形状は等しく、矩形状の角部は曲率半径ｒ２で曲状に面取りされているため、半田接合領域Ｒ３１ｈも外周が同一の曲率半径ｒ２で面取りされている。   As described above, the hanging portion 31a of the external electrode 31 has the flat bottom portion 31m. When the semiconductor device 101 is viewed from above, each side of the bottom surface portion 31m is positioned inward from the corresponding side on the outer periphery of the solder bonding region R31h with a certain plane distance r1. As described above, since the planar shapes of the solder joint region R31h and the solder joint region R11h are equal, and the rectangular corner portion is chamfered in a curved shape with the curvature radius r2, the curvature radius of the solder joint region R31h is the same as the outer periphery It is chamfered by r2.

この際、曲率半径ｒ２＝平面距離ｒ１とすることにより、垂下部３１ａの半田接合領域Ｒ３１ｈは編曲点となる角部においてもなだらかな稜線を形成することができ、かつ、稜線を矩形状の角部以外に形成できる結果、半導体素子上半田２１から発生する応力の集中を回避できる。なお、稜線とは垂下部３１ａの半田接合領域Ｒ３１ｈと底面部３１ｍとの間の稜線を意味する。   At this time, by setting the radius of curvature r2 = the plane distance r1, the solder joint region R31h of the drooping portion 31a can form a gentle ridge line also at the corner portion to be a bending point, and the ridge line is a rectangular corner As a result of being formed outside the portion, concentration of stress generated from the solder 21 on the semiconductor element can be avoided. In addition, a ridgeline means the ridgeline between the solder joint region R31h of the drooping portion 31a and the bottom portion 31m.

例えば、半田接合領域Ｒ１１ｈの平面座標に対する変数を前述の垂直距離ＤＡとし、半田接合領域Ｒ１１ｈの面積と垂直距離ＤＡとを乗算して得られる体積を仮想体積Ｖ２としたとき、半導体素子上半田２１の実際の半田体積Ｖ１は、「仮想体積Ｖ２＞半田体積Ｖ１」を満足する。これは、「Ｖ２＞Ｖ１」とすることにより、半導体素子上半田２１は上述した上下フィレット構造を有する端面形状を形成することができるためである。   For example, assuming that the variable with respect to the plane coordinates of the solder joint region R11h is the above-described vertical distance DA, and the volume obtained by multiplying the area of the solder joint region R11h by the vertical distance DA is the virtual volume V2, The actual solder volume V1 of the above satisfies “virtual volume V2> solder volume V1”. This is because by setting “V2> V1”, the solder on semiconductor element 21 can form the end face shape having the above-described upper and lower fillet structure.

また、図１及び図３に示すように、外部電極３１の垂下部３１ａの底面部３１ｍには、半田中心点ＨＣを中心として外部電極３１をＺ方向に沿って貫通する貫通穴３１ｔを設けることが望ましい。   Further, as shown in FIGS. 1 and 3, in the bottom portion 31m of the hanging portion 31a of the external electrode 31, there is provided a through hole 31t which penetrates the external electrode 31 along the Z direction centering on the solder center point HC. Is desirable.

半導体装置１０１の外部電極３１に貫通穴３１ｔを設けることにより、半導体素子上半田２１の形成時に余剰な半田が貫通穴３１ｔへ流れ込むことで余剰半田を吸収し、半導体素子上半田２１が多めに振れたときも、半導体素子上半田２１の側面に上下フィレット構造を確実に形成することができる。   By forming the through holes 31t in the external electrodes 31 of the semiconductor device 101, excess solder flows into the through holes 31t when forming the on-semiconductor-device solder 21 to absorb the excess solder, and the on-semiconductor-device solder 21 swings more. Also in this case, the upper and lower fillet structures can be reliably formed on the side surfaces of the solder 21 on the semiconductor element.

このように、半導体素子上半田２１の端面形状として上下フィレット構造を設けることにより、半導体素子上半田２１と外部電極３１の傾斜部３１ｓとの端部における半田形成の際の断面角度及び半導体素子上半田２１と半田接合用金属膜１３との端部における半田形成の際の断面角度である２つの半田なす角（半田濡れ角）を共に９０度以下に抑えることができる。   Thus, by providing the upper and lower fillet structure as the end face shape of the solder on the semiconductor element 21, the cross-sectional angle and the semiconductor element on forming the solder at the end of the solder on the semiconductor element 21 and the inclined portion 31s of the external electrode 31 Two solder forming angles (solder wetting angles), which are cross-sectional angles at the time of solder formation at the end portions of the solder 21 and the solder bonding metal film 13, can be suppressed to 90 degrees or less.

すなわち、図２に示すように、外部電極３１側の半田なす角θＨ１及び表面電極１１側の半田なす角θＨ２を共に９０度以下に抑えることができる。なお、半田なす角は、小さい方が半田応力を低くすることができるため望ましく、例えば、６０度以下では半田応力が半減する実例がある。   That is, as shown in FIG. 2, it is possible to suppress both the soldering angle θH1 on the external electrode 31 side and the soldering angle θH2 on the front surface electrode 11 side to 90 degrees or less. Note that the smaller the solder angle, the smaller the solder stress can be made, which is desirable. For example, there is an example in which the solder stress is reduced by half at 60 degrees or less.

ＩＧＢＴ等の半導体素子１は、例えば、表面及び裏面（一方主面及び他方主面）上に、表面電極１１及び裏面電極１２を有している。裏面電極１２は半導体素子下半田２２を介して基板電極３８と電気的に接続されつつ接合される。   The semiconductor element 1 such as an IGBT has, for example, a front surface electrode 11 and a back surface electrode 12 on the front surface and the back surface (one main surface and the other main surface). The back surface electrode 12 is joined while being electrically connected to the substrate electrode 38 via the semiconductor element lower solder 22.

表面電極１１は、例えば、Ａｌ（アルミニウム）を９５％以上含む材料からなる金属膜であることが望ましい。Ａｌを９５％以上含む材料を半導体素子１の表面電極１１として採用する理由は、Ｓｉ基板やＳｉＣ（炭化珪素）基板など、各種基板を用いた半導体素子１の電極として、よく知られた既存の方法で容易に形成・加工でき、また表面電極１１と共通の製造プロセスにて制御端子用の電極（後述する部分表面電極１１ｇ）を形成すること一般的であるが、この制御端子用の電極に対して金属ワイヤーを接合（ワイヤーボンド）する際にも、接続信頼性の優れた接合を確保できるためである。   The surface electrode 11 is preferably, for example, a metal film made of a material containing 95% or more of Al (aluminum). The reason why a material containing 95% or more of Al is adopted as the surface electrode 11 of the semiconductor element 1 is because the existing well known as an electrode of the semiconductor element 1 using various substrates such as Si substrate and SiC (silicon carbide) substrate. It is generally possible to easily form and process by a method, and to form an electrode for control terminal (partial surface electrode 11g described later) in a common manufacturing process with the surface electrode 11, but for this control terminal, On the other hand, even when bonding metal wires (wire bonding), bonding with excellent connection reliability can be ensured.

Ａｌを９５％以上含む材料である表面電極１１の表面上に、例えば、ＳｎＡｇＣｕ系のＰｂフリー半田を接合することが困難なため、表面電極１１の上に半田接合用金属膜１３を形成することにより半田との接合性・半田濡れ性を確保している。なお、「半田濡れ性」とは、半田の接合対象との半田づけ難易度を示すなじみやすさ等の半田の特性を意味する。   Since it is difficult to join, for example, SnAgCu-based Pb-free solder on the surface of the surface electrode 11 which is a material containing 95% or more of Al, the metal film 13 for solder bonding is formed on the surface electrode 11 The bondability with the solder and solder wettability are secured by this. The “solder wettability” means the characteristics of the solder such as the ease of fitting that indicates the degree of difficulty of soldering with the solder bonding object.

半田接合用金属膜１３として、例えば、主としてＮｉ（ニッケル）からなる金属膜（半田接合用ニッケル膜）を含み、さらにその上に酸化防止のためのＡｕ（金）からなる金属膜が形成された、積層金属膜で構成することが考えられる。半田接合用金属膜１３用の主たる金属膜としてＮｉを採用する理由は、半田と容易に金属間化合物を形成し、良好で安定な半田接合を得ることができるためである。   As the metal film 13 for solder bonding, for example, a metal film mainly composed of Ni (nickel) (nickel film for solder bonding) is included, and further, a metal film made of Au (gold) for oxidation prevention is formed thereon It is conceivable to construct a laminated metal film. The reason why Ni is adopted as the main metal film for the solder bonding metal film 13 is that an intermetallic compound can be easily formed with the solder and a good and stable solder bonding can be obtained.

このように、半導体素子上半田２１との接合性の優れた構成材料であるＮｉを用いた半田接合用ニッケル膜を含む半田接合用金属膜１３を表面電極１１の半田接合領域Ｒ１１ｈ上に形成することにより、半田接合領域Ｒ１１ｈにおける半田濡れ性の向上を図ることができる。   As described above, the solder bonding metal film 13 including the nickel film for solder bonding using Ni, which is a constituent material having excellent bonding with the solder on the semiconductor element 21, is formed on the solder bonding region R11h of the surface electrode 11. Thereby, the solder wettability in the solder joint region R11h can be improved.

なお、半田接合用金属膜１３を構成するＮｉ及びＡｕは、例えば、スパッタなどに代表される気相堆積法や、Ｐ（燐）を含有する無電解メッキ法を含む湿式メッキ法にて、形成することができる。気相体積法にて半田接合用金属膜１３を形成する方法として、例えば、メタルマスク越しに金属膜をスパッタするマスクスパッタ法や、半田接合領域Ｒ１１ｈ以外をフォトレジストで覆ったあと金属膜をスパッタ処理し、高圧で有機溶剤を吹き付けることでフォトレジストごと半田接合領域Ｒ１１ｈ以外の金属膜を除去するＪＥＴリフトオフ法が、挙げられる。湿式メッキにて半田接合用金属膜１３を形成する方法として、例えば、半田接合領域Ｒ１１ｈの表面電極１１を露出し、それ以外の部分を被覆膜で覆い、ジンケート法を用いた湿式メッキ法にて半田接合用金属膜１３を成長させることで、半田接合領域Ｒ１１ｈに選択的に半田接合用金属膜１３を形成する方法が挙げられる。特に、半導体素子１及び周辺材料が高温に晒される半導体装置では、半田接合用金属膜１３が半導体素子上半田２１中へ拡散しその厚みが徐々に減少し接合信頼性が劣化するため、半田接合用金属膜１３は厚い方が望ましいが、湿式メッキ法で半田接合用金属膜１３を形成する場合は、メッキ液への浸漬時間を延長することで、容易に厚い金属膜を形成することができる。 The Ni and Au constituting the solder bonding metal film 13 are formed by, for example, a wet deposition method including a vapor deposition method represented by sputtering or the like, or an electroless plating method containing P (phosphorus). can do. As a method of forming the metal film 13 for solder bonding by the vapor phase volume method, for example, a mask sputtering method of sputtering a metal film through a metal mask or a metal film is covered after a photoresist other than the solder bonding region R11h is covered. A JET lift-off method may be mentioned, in which the photoresist and the metal film other than the solder bonding region R11h are removed together with the photoresist by processing and spraying an organic solvent at high pressure. As a method of forming a solder bonding metal layer 13 by a wet plating, for example, to expose the surface electrodes 11 of the solder joint area R11h, covered with the covering film other portions, the wet plating method using a zincate method There is a method of selectively forming the solder bonding metal film 13 in the solder bonding region R11 h by growing the solder bonding metal film 13. In particular, in the semiconductor device in which the semiconductor element 1 and the peripheral materials are exposed to high temperatures, the solder bonding metal film 13 diffuses into the solder 21 on the semiconductor element and its thickness gradually decreases to deteriorate the bonding reliability. Although it is desirable that the metal film 13 is thick, when forming the metal film 13 for solder bonding by wet plating, it is possible to easily form a thick metal film by extending the immersion time in the plating solution. .

外部電極３１は、例えば、Ｃｕ（銅）からなる金属板で形成される。外部電極３１にＣｕを用いる理由は、打ち抜き等の加工で任意の形状に容易に加工でき、また、半田と容易に接合することができ、かつ、高い通電能力を実現することができるため、外部電極３１として適しているからである。垂下部３１ａは、例えば、打ち抜き加工後の板状の外部電極構造に垂下部に対応した押し金型を用いることで形成することができる。他に、例えば、垂下部３１ａに対応した金属板を平坦な外部電極主要部に半田付けやろう付けなどで接合することで、外部電極３１を形成することができる。   The outer electrode 31 is formed of, for example, a metal plate made of Cu (copper). The reason why Cu is used for the external electrode 31 is that it can be easily processed into an arbitrary shape by processing such as punching, can be easily joined with solder, and can achieve high current-carrying capacity. It is because it is suitable as the electrode 31. The hanging portion 31a can be formed, for example, by using a pressing die corresponding to the hanging portion in the plate-like external electrode structure after punching. In addition, for example, the external electrode 31 can be formed by joining a metal plate corresponding to the hanging portion 31a to the flat external electrode main portion by soldering or brazing.

外部電極３１をＣｕの単体構造で形成した場合、半導体素子上半田２１と比較的容易に接合でき、通電能力の高い外部電極３１を比較的容易な加工処理によって得ることができる。   When the external electrode 31 is formed of a single-piece structure of Cu, the external electrode 31 can be relatively easily joined to the solder 21 on the semiconductor element, and the external electrode 31 having a high current-carrying capacity can be obtained by relatively easy processing.

図１に示すように、基板電極３８上には外部電極３１とは別の外部電極３５が設けられ、半田接合領域Ｒ１１ｈ以外の部分表面電極１１ｇは半田接合用金属膜１３及び制御配線３７を介して制御電極３６に電気的に接続される。なお、部分表面電極１１ｇはＩＧＢＴのゲート電極等として機能し、通常は、半田接合領域Ｒ１１ｈに形成される表面電極１１と電気的に独立して形成される。   As shown in FIG. 1, an external electrode 35 different from the external electrode 31 is provided on the substrate electrode 38, and the partial surface electrode 11g other than the solder joint region R11h is through the solder joint metal film 13 and the control wiring 37. Thus, the control electrode 36 is electrically connected. The partial surface electrode 11g functions as a gate electrode or the like of the IGBT, and is generally formed electrically independent of the surface electrode 11 formed in the solder bonding region R11h.

このように、半導体装置１０１は、複数の外部電極３１及び外部電極３５並びに制御電極３６が取り付けられたモジュールの形で製品が完成する。   Thus, the semiconductor device 101 completes a product in the form of a module to which the plurality of external electrodes 31, the external electrodes 35, and the control electrode 36 are attached.

そして、図１に示すように、例えば、半導体素子１（表面電極１１（１１ｇ）、裏面電極１２、及び半田接合用金属膜１３を含む）と半導体素子上半田２１と半導体素子下半田２２と外部電極３１、外部電極３５及び制御電極３６の少なくとも一部とは、樹脂４１によって封止される。樹脂４１によって封止することで、半導体素子１及び周辺の接合構造が、外部からの異物や湿気により破損、汚染、ショートされることを防止することができるため、信頼性が向上するだけでなく、半導体装置１０１の取り扱いが容易になり歩留まりも向上する。加えて、半導体装置１０１を通電したとき、外部電極３１が発熱により膨脹することを抑制することもでき、外部電極３１の半田接合領域Ｒ３１ｈの信頼性を向上することができる。   Then, as shown in FIG. 1, for example, the semiconductor element 1 (including the front surface electrode 11 (11 g), the back surface electrode 12, and the solder bonding metal film 13), the semiconductor element solder 21 and the semiconductor element solder 22 and the outside The electrode 31, the external electrode 35, and at least a part of the control electrode 36 are sealed by a resin 41. By sealing with the resin 41, the junction structure of the semiconductor element 1 and the periphery can be prevented from being damaged, contaminated, or shorted by foreign matter and moisture from the outside, so that not only reliability can be improved. The handling of the semiconductor device 101 is facilitated, and the yield is also improved. In addition, when the semiconductor device 101 is energized, expansion of the external electrode 31 due to heat generation can be suppressed, and the reliability of the solder joint region R 31 h of the external electrode 31 can be improved.

このように、樹脂４１によって半導体素子１と半導体素子上半田２１と外部電極３１の少なくとも一部とを封止することにより、樹脂形成後の半導体装置１０１の取り扱いが容易になり歩留まりが向上するとともに、半導体素子１への吸着や異物付着を抑制することにより信頼性の向上を図ることができる。   As described above, by sealing the semiconductor element 1 and at least a part of the semiconductor element solder 21 and the external electrode 31 with the resin 41, the handling of the semiconductor device 101 after resin formation is facilitated and the yield is improved. By suppressing the adsorption to the semiconductor element 1 and the adhesion of foreign matter, the reliability can be improved.

また、樹脂４１、半導体素子１、外部電極３１の線膨脹係数を、それぞれα４、α１、α３としたとき、その関係をα１（第１の線膨張係数）＜α４（第２の線膨張係数）＜α３（第３の線膨張係数）とすることで、外部電極３１と樹脂４１とが剥離することを抑制しながら、半導体素子１に樹脂応力が発生することも抑制することができるため、信頼性を向上することができる。   In addition, when the linear expansion coefficients of the resin 41, the semiconductor element 1 and the external electrode 31 are α4, α1 and α3, respectively, the relationship is α1 (first linear expansion coefficient) <α4 (second linear expansion coefficient) By setting it as <α 3 (third linear expansion coefficient), it is possible to suppress the occurrence of the resin stress in the semiconductor element 1 while suppressing the peeling of the external electrode 31 and the resin 41, so that the reliability It is possible to improve the quality.

樹脂４１を形成する方法として、金型を用い高圧で樹脂４１を封入するトランスファモールド法や、より安価な、樹脂４１を樹脂盛りで形成するポッティング法が、挙げられる。実施の形態１の半導体装置１０１では、隙間が狭くなりやすい外部電極３１と半導体素子１間の半導体素子上半田２１に上下フィレット構造が形成されるため、細部にも樹脂が封入されやすく、安価なポッティング法を用いることに適している。   Examples of a method of forming the resin 41 include a transfer molding method in which the resin 41 is sealed at high pressure using a mold, and a potting method in which the resin 41 is formed with a resin heap which is less expensive. In the semiconductor device 101 according to the first embodiment, the upper and lower fillet structures are formed on the solder 21 on the semiconductor element between the external electrode 31 and the semiconductor element 1 where the gap tends to be narrow. It is suitable to use the potting method.

具体的には、仮固定された半導体素子１、半導体素子上半田２１及び外部電極３１等の樹脂形成対象領域に液状樹脂を吐出して加熱硬化させるポッティング法を用いて樹脂形成処理を実行することにより、半導体素子１と半導体素子上半田２１と外部電極３５の少なくとも一部とを覆うように樹脂４１を形成する。   Specifically, the resin formation process is performed using a potting method in which liquid resin is discharged to a resin formation target area such as the semiconductor element 1 temporarily fixed, the solder on the semiconductor element 21, the external electrode 31, etc. Thus, the resin 41 is formed so as to cover the semiconductor element 1, the solder 21 on the semiconductor element, and at least a part of the external electrode 35.

このように、樹脂４１を形成する工程として比較的安価に行えるポッティング法を用いた樹脂形成処理を実行して半導体装置１０１を製造することにより、半導体素子１と外部電極３１との間に未充填箇所を生じさせることなく、樹脂４１により半導体素子１、半導体素子上半田２１及び外部電極３５等を封止することができる。   As described above, the resin forming process using the potting method, which can be performed relatively inexpensively, as the process of forming the resin 41 is performed to manufacture the semiconductor device 101, so that the space between the semiconductor element 1 and the external electrode 31 is not filled. The semiconductor element 1, the solder on the semiconductor element 21, the external electrode 35, and the like can be sealed with the resin 41 without producing a portion.

半導体素子１に形成されるガードリング等の耐圧保持領域上には、表面電極１１ではなく保護膜１４が形成されている。保護膜１４により、冷熱サイクルなどで発生する樹脂４１からの応力を緩和することができ、ガードリングなどの耐圧保持領域が、応力により破壊されることを防止することができる。   A protective film 14, not the surface electrode 11, is formed on a withstand voltage holding area such as a guard ring formed in the semiconductor element 1. The protective film 14 can relieve the stress from the resin 41 generated in the cooling and heating cycle and the like, and can prevent the withstand voltage holding area such as the guard ring from being broken by the stress.

保護膜１４は、例えば、ポリイミドからなる絶縁膜（ポリイミド膜）で、厚みが２〜２０μｍ程度である。ポリイミド膜は、感光性のポリイミドを用いて、リソグラフィー法で形成する場合や、非感光性のポリイミドを用いて、さらに感光性レジストを併用しこれをリソグラフィー法で所望の形状に加工し、加工後のレジストを用いてポリイミドを加工するという比較的簡単な製造プロセスで、耐圧保持領域を覆う形状の保護膜１４を形成することができる。さらに、ポリイミド膜である保護膜１４によって、半導体素子上半田２１及び樹脂４１を形成する処理を含む半導体素子１を実装時における熱処理に耐えることができる。   The protective film 14 is, for example, an insulating film (polyimide film) made of polyimide and has a thickness of about 2 to 20 μm. The polyimide film is formed by a lithography method using photosensitive polyimide, or a photosensitive resist is further used together with a non-photosensitive polyimide, and this is processed into a desired shape by lithography, and after processing The protective film 14 having a shape covering the withstand voltage holding area can be formed by a relatively simple manufacturing process of processing polyimide using the resist of Furthermore, the protective film 14 which is a polyimide film can withstand the heat treatment at the time of mounting the semiconductor device 1 including the process of forming the on-semiconductor-device solder 21 and the resin 41.

例えば、前述の湿式メッキ法で半田接合用金属膜１３を形成するときの被覆膜として、前述の保護膜１４を用いることができる。 For example, as an object to be covered film when forming the solder bonding metal layer 13 by a wet plating method described above, it is possible to use a protective film 14 described above.

すなわち、実施の形態１の半導体装置１０１の製造方法において、保護膜１４及び半田接合用金属膜１３を形成する以下のステップ(a) ，(b) を実行することができる。   That is, in the method of manufacturing the semiconductor device 101 according to the first embodiment, the following steps (a) and (b) of forming the protective film 14 and the solder bonding metal film 13 can be performed.

ステップ(a)：半導体素子１表面上において表面電極１１が形成されていない耐圧保持領域を含む領域から、表面電極１１の表面における半田接合領域Ｒ１１ｈの外縁部にかけて保護膜１４を形成する（図１参照）。その結果、保護膜１４は耐圧保持領域だけでなく、半田接合領域Ｒ１１ｈ以外の表面電極１１を覆うべく、耐圧保持領域から必要なだけ延展した形状を有する。   Step (a): A protective film 14 is formed from the area including the withstand voltage holding area where the surface electrode 11 is not formed on the surface of the semiconductor element 1 to the outer edge portion of the solder bonding area R11 h on the surface of the surface electrode 11 (FIG. 1) reference). As a result, the protective film 14 has a shape which is extended as necessary from the withstand voltage holding region so as to cover not only the withstand voltage holding region but also the surface electrodes 11 other than the solder bonding region R11 h.

ステップ(b)：保護膜１４をマスクとして湿式メッキ法を用いて、表面電極１１の表面における半田接合領域Ｒ１１ｈ上に半田接合用金属膜１３を形成する。   Step (b): A solder bonding metal film 13 is formed on the solder bonding region R11h on the surface of the surface electrode 11 by wet plating using the protective film 14 as a mask.

上述したステップ(a) ，(b) を含む半導体装置１０１の製造方法を実行することにより、保護膜１４を半田接合用金属膜１３形成用のマスクとして使用することで、湿式メッキ法を用いた場合にも、追加工程なくマスクとなる保護膜１４を形成することができ、半導体装置１０１の製造コストを削減することができる。   By using the protective film 14 as a mask for forming the metal film 13 for solder bonding by executing the manufacturing method of the semiconductor device 101 including the steps (a) and (b) described above, the wet plating method is used. Also in this case, the protective film 14 to be a mask can be formed without an additional step, and the manufacturing cost of the semiconductor device 101 can be reduced.

このように、半導体素子１の表面上において表面電極１１が形成されていない領域を含んで選択的に保護膜１４を設けることにより、樹脂４１の形成工程以前の半導体素子１の扱いが容易になり歩留まりが向上すると同時に、樹脂４１からの応力を受け半導体素子１におけるガードリング等の耐圧保持領域が破壊されることを抑制し信頼性が向上する。   Thus, by selectively providing the protective film 14 on the surface of the semiconductor element 1 including the region where the surface electrode 11 is not formed, handling of the semiconductor element 1 before the step of forming the resin 41 is facilitated. At the same time as the yield is improved, the breakdown of the breakdown voltage holding area such as a guard ring in the semiconductor element 1 due to the stress from the resin 41 is suppressed and the reliability is improved.

半導体素子１と外部電極３１とを、半導体素子上半田２１を用いて半田接合する方法として、例えば、溶融した半田を前述の貫通穴３１ｔから流し込むことで半田接合する溶融半田滴下法や、固相やペースト状の半田を半田接合領域Ｒ１１ｈ上に設置しリフローすることで半田接合するリフロー法が挙げられる。   As a method of soldering the semiconductor element 1 and the external electrode 31 by using the solder 21 on the semiconductor element, for example, a molten solder dropping method in which the molten solder is soldered by pouring the molten solder from the through holes 31t, a solid phase And a reflow method in which solder bonding is performed by setting and reflowing a paste-like solder on the solder bonding region R11h.

リフロー法は、還元雰囲気中において、表面電極１１の表面と外部電極３１の表面との間に配置された固相あるいはペースト状の半田材を溶融することにより、半導体素子上半田２１を得る方法である。   The reflow method is a method of obtaining the solder 21 on the semiconductor element by melting the solid phase or paste solder material disposed between the surface of the surface electrode 11 and the surface of the external electrode 31 in a reducing atmosphere. is there.

実施の形態１の半導体装置１０１において、半導体素子上半田２１の体積を安定させる必要があるため、固相やペースト状の半田を用いて半田量が制御しやすい上述したリフロー法が適している。   In the semiconductor device 101 according to the first embodiment, since it is necessary to stabilize the volume of the solder 21 on the semiconductor element, the above-described reflow method is suitable which can easily control the amount of solder using solid phase or paste solder.

外部電極３１や半導体素子上半田２１の表面が酸化し酸化膜が形成されている場合、半田濡れ性が低下し、半田濡れ不良が発生する。したがって、実施の形態１の半導体装置１０１において、外部電極３１の垂下部３１ａへ半導体素子上半田２１が濡れ広がることが重要であるため、上述したリフロー法により、還元雰囲気で前述の酸化膜を除去して半田濡れ性が良い状況で垂下部３１ａの半田接合領域Ｒ３１ｈに半田を進展させることにより上下フィレット構造を有する半導体素子上半田２１を精度良く得ることができる。   When the surface of the external electrode 31 and the solder 21 on the semiconductor element is oxidized to form an oxide film, the wettability of the solder is lowered and the solder wettability is generated. Therefore, in the semiconductor device 101 of the first embodiment, it is important that the solder on the semiconductor element 21 spreads to the hanging portion 31a of the external electrode 31. Therefore, the aforementioned oxide film is removed in a reducing atmosphere by the above-described reflow method. By advancing the solder to the solder joint region R31h of the drooping portion 31a in a state where the solder wettability is good, the solder 21 on the semiconductor element having the upper and lower fillet structure can be obtained with high accuracy.

また、半導体素子上半田２１用の半田材を溶融して外部電極３１と半導体素子１とを接合する最中に、溶融した半田内部に気泡が発生したときも、垂下部３１ａの存在により、気泡が半田の外側へ排出されやすいため、実装後の半田ボイドを低減することができる。   Also, when bubbles are generated inside the melted solder while the solder material for the solder 21 on the semiconductor element is melted and the external electrode 31 and the semiconductor element 1 are bonded, the air bubbles are generated due to the presence of the drooping portion 31a. Since it is easy to be discharged to the outside of the solder, it is possible to reduce the solder void after mounting.

（動作・作用・効果）
実施の形態１における半導体装置１０１によれば、装置の動作時などに発生する冷熱サイクルにおいて、半導体素子上半田２１の組織が疲労変形を起こし、特に半導体素子上半田２１の端部により発生する応力を、半導体素子上半田２１に設けた上下フィレット構造によって低減することができる。(Operation, action, effect)
According to the semiconductor device 101 of the first embodiment, the structure of the solder 21 on the semiconductor element undergoes fatigue deformation in a thermal cycle which occurs at the time of operation of the device, and in particular, stress generated by the end portion of the solder 21 on the semiconductor element Can be reduced by the upper and lower fillet structure provided in the solder 21 on the semiconductor element.

上下フィレット構造は、半導体素子１側のフィレットＦ１だけでなく、外部電極３１側にもフィレットＦ２を形成した構造であるため、半導体素子１側及び外部電極３１側双方の半田応力を同時に軽減し、信頼性の高い接合構造を得ると同時に、外部電極３１側の半田接合領域Ｒ３１ｈの面積を半導体素子１の半田接合領域Ｒ１１ｈと、同等程度まで拡大することができるため、通電性能も維持することができる。使用温度範囲がより高温で、チップの大面積化が難しい、例えば、ＳｉＣなどの化合物半導体を用いた半導体装置においては、実施の形態１の半導体装置１０１によって得られる効果は特に有効となる。   The upper and lower fillet structure is a structure in which the fillet F2 is formed not only on the fillet F1 on the semiconductor element 1 side but also on the external electrode 31 side, so the solder stress on both the semiconductor element 1 side and the external electrode 31 side is reduced simultaneously At the same time as obtaining a highly reliable junction structure, the area of the solder junction region R31h on the external electrode 31 side can be expanded to the same extent as the solder junction region R11h of the semiconductor element 1, so maintaining the conduction performance it can. The effect obtained by the semiconductor device 101 according to the first embodiment is particularly effective in a semiconductor device using a compound semiconductor such as SiC, which has a high operating temperature range and difficult to increase the chip area.

すなわち、ＳｉＣ（炭化珪素）を構成材料とした半導体素子１は高温に対応しており、より厳しい温度条件で使用される可能性があるが、半導体素子上半田２１の信頼性の向上を図っているため、半導体素子１が高温となり、表面電極１１及び外部電極３１が高温状態になっても装置は安定して動作することができる。   That is, the semiconductor element 1 made of SiC (silicon carbide) corresponds to a high temperature, and may be used under more severe temperature conditions. However, the reliability of the solder 21 on the semiconductor element is improved. Therefore, even if the temperature of the semiconductor element 1 becomes high and the surface electrode 11 and the external electrode 31 become high temperature, the device can operate stably.

外部電極３１に形成された垂下部３１ａ表面に、半導体素子上半田２１が塗れ上がることにより、半導体素子上半田２１の端部形状は半田中心点ＨＣが形成される内側に凹んだ形状である上下フィレット構造を呈するため、半導体素子１側、外部電極３１側、双方にフィレットＦ１及びＦ２を形成することができる。垂下部３１ａは、半導体素子１の半田中心点ＨＣから外側にかけて、徐々に半導体素子１の半田接合用金属膜１３との垂直距離ＤＡが開く構造になっているので、半導体素子１の終端部と外部電極３１の絶縁距離を確保しつつ、実効的な半導体素子上半田２１の厚みを抑えることができるので、半田から発生する応力を低減することができる。   When the solder 21 on the semiconductor element is applied to the surface of the drooping portion 31a formed on the external electrode 31, the end portion of the solder 21 on the semiconductor element has an upper end and a lower end which is a concave shape formed inside the solder center point HC. In order to exhibit a fillet structure, fillets F1 and F2 can be formed on both the semiconductor element 1 side and the external electrode 31 side. The drooping portion 31a has a structure in which the vertical distance DA with the solder bonding metal film 13 of the semiconductor element 1 gradually increases from the solder center point HC of the semiconductor element 1 to the outer side. Since the thickness of the effective solder on semiconductor element 21 can be suppressed while securing the insulation distance of the external electrode 31, the stress generated from the solder can be reduced.

このように、実施の形態１の半導体装置１０１における半導体素子上半田２１（半田形成部）は、表面電極１１（一方電極）の表面からのフィレットＦ１（第１の湾曲形状）と外部電極３１の表面からのフィレットＦ２（第２の湾曲形状）とを含む端面形状を有する。その結果、表面電極１１及び外部電極３１の半田接合領域Ｒ１１ｈ及びＲ３１ｈそれぞれに発生する応力の低減を図ることができるため、半導体素子上半田２１の信頼性の向上を図ることができる。   As described above, the solder 21 on the semiconductor element (solder formation portion) in the semiconductor device 101 of the first embodiment is the fillet F 1 (first curved shape) from the surface of the surface electrode 11 (one electrode) and the external electrode 31. It has an end face shape including the fillet F2 (second curved shape) from the surface. As a result, since it is possible to reduce the stress generated in each of the solder bonding regions R11h and R31h of the surface electrode 11 and the external electrode 31, the reliability of the solder on the semiconductor element 21 can be improved.

また、半導体装置１０１の半導体素子上半田２１がフィレットＦ１及びフィレットＦ２を有する上下フィレット構造を有する態様で、表面電極１１及び外部電極３１が平面視重複する領域を全て半田接合領域Ｒ１１ｈ及びＲ３１ｈに設定することができるため、半田接合領域Ｒ１１ｈ及びＲ３１ｈの面積の拡大を図ることにより、表面電極１１，外部電極３１間の通電能力の向上を図ることができる。   Further, in a mode in which the solder 21 on the semiconductor element of the semiconductor device 101 has an upper and lower fillet structure having the fillet F1 and the fillet F2, all regions where the surface electrodes 11 and the external electrodes 31 overlap in plan view are set as solder bonding regions R11h and R31h. Therefore, by increasing the area of the solder bonding regions R11h and R31h, the current-carrying capacity between the surface electrode 11 and the external electrode 31 can be improved.

その結果、長期使用が可能になるとともに、歩留まりの向上を図った半導体装置１０１を得ることができる。   As a result, long-term use can be achieved, and the semiconductor device 101 with improved yield can be obtained.

加えて、半田接合領域Ｒ１１ｈ及びＲ３１ｈは、平面形状が矩形状となる傾向が高い半導体素子１と相似関係になり得る平面形状である矩形状を呈することにより、設計段階で効率的に半田接合領域Ｒ１１ｈ及びＲ３１ｈの形成面積の拡大を図ることができる。   In addition, the solder joint regions R11h and R31h are efficiently formed in the solder joint region at the design stage by exhibiting a rectangular shape that is a planar shape that can be in a similar relationship with the semiconductor element 1 having a high tendency to be rectangular. The formation area of R11h and R31h can be enlarged.

さらに、半田接合領域Ｒ１１ｈ及びＲ３１ｈは角部が面取りされた面取り矩形状となる平面形状を呈することにより、半導体素子上半田２１における半田接合領域Ｒ１１ｈ及びＲ３１ｈの応力集中を緩和するとともに、角部への半田濡れ広がりを容易にすることができ、半田接合領域Ｒ１１ｈ及びＲ３１ｈの信頼性のさらなる向上と生産性の向上を図ることができる。   Furthermore, the solder joint regions R11h and R31h have a planar shape that is a chamfered rectangular shape with chamfered corner portions, thereby relieving stress concentration in the solder joint regions R11h and R31h in the solder on semiconductor element 21 and The solder wetting and spreading can be facilitated, and the reliability of the solder bonding regions R11h and R31h can be further improved and the productivity can be improved.

また、半田接合領域Ｒ１１ｈと半田接合領域Ｒ３１ｈとを平面視完全重複する同一形状に設定することにより、半導体素子上半田２１にフィレットＦ１及びＦ２をより確実に形成することができる。   Further, by setting the solder joint region R11h and the solder joint region R31h in the same shape so as to completely overlap in plan view, the fillets F1 and F2 can be more reliably formed on the solder on the semiconductor element 21.

＜実施の形態２＞
（構成）
図４は実施の形態２の半導体装置１０２の構造を示す断面図である。以下、図１〜図３で示した実施の形態１の半導体装置１０１と同様な構造部分は同一符号を付し説明を適宜省略し、実施の形態１との相違点を中心に説明する。なお、図４にはＸＹＺ直交座標系を示している。Second Embodiment
(Constitution)
FIG. 4 is a cross-sectional view showing the structure of the semiconductor device 102 of the second embodiment. The same reference numerals as in the semiconductor device 101 of the first embodiment shown in FIGS. 1 to 3 denote the same parts, and a description thereof will be omitted as appropriate, and the differences from the first embodiment will be mainly described. Note that FIG. 4 shows an XYZ orthogonal coordinate system.

実施の形態２の半導体装置１０２では、外部電極３１に替えて外部電極５０を用いた点が実施の形態１と異なる。外部電極５０は、例えば、Ｃｕより線膨脹係数が低い金属材料で構成される金属板５１を母材とし、母材の表面及び裏面にＣｕ金属シート５２を形成した複合金属板構造を呈している。なお、図４で示す垂下部５０ａ、底面部５０ｍ及び着目領域Ｃ１２は、図１〜図３で示した半導体装置１０１の垂下部３１ａ、底面部３１ｍ及び着目領域Ｃ１１に対応する。   The semiconductor device 102 of the second embodiment is different from the first embodiment in that an external electrode 50 is used instead of the external electrode 31. The external electrode 50 has, for example, a composite metal plate structure in which a Cu metal sheet 52 is formed on the front and back surfaces of a base material using a metal plate 51 composed of a metal material having a linear expansion coefficient lower than that of Cu. . The drooping portion 50a, the bottom surface portion 50m and the focus area C12 shown in FIG. 4 correspond to the drooping portion 31a, bottom surface portion 31m and focus area C11 of the semiconductor device 101 shown in FIGS.

例えば、Ｃｕより線膨脹係数が低い金属板５１の表面及び裏面に、Ｃｕ金属シート５２（銅形成層）を貼り合わせることにより、表面及び裏面がＣｕ層となる外部電極５０を得ることができる。他に、例えば、Ｃｕより線膨脹係数が低い金属板５１に、メッキ加工することでＣｕ膜であるＣｕ金属シート５２を形成することができる。メッキ加工は、例えば、無電解メッキ法を用いることもできるが、金属板５１を電極として用いることにより、厚い膜厚のＣｕ金属シート５２を比較的容易に形成することができるため、電界メッキ法を用いる方が望ましい。Ｃｕより線膨脹係数が低い金属板５１として、例えば、Ｆｅ（鉄）を含むＮｉ合金を用いることができる。   For example, by bonding the Cu metal sheet 52 (copper-forming layer) to the front and back surfaces of the metal plate 51 having a linear expansion coefficient lower than that of Cu, the external electrode 50 in which the front and back surfaces are Cu layers can be obtained. In addition, for example, a Cu metal sheet 52 which is a Cu film can be formed by plating on a metal plate 51 having a linear expansion coefficient lower than that of Cu. For example, electroless plating can be used for the plating process, but using the metal plate 51 as an electrode makes it possible to relatively easily form the Cu metal sheet 52 having a large thickness. It is desirable to use As the metal plate 51 having a linear expansion coefficient lower than that of Cu, for example, a Ni alloy containing Fe (iron) can be used.

（動作・効果・作用）
外部電極５０として、Ｃｕより線膨脹係数が低い金属板５１を母材とすることにより、線膨脹係数を半導体素子１に近づけることができるため、半導体装置１０２の動作時などに発生する冷熱サイクルにおいて発生する外部電極５０の変形を抑えることができる。(Operation, effect, action)
By using the metal plate 51 having a linear expansion coefficient lower than that of Cu as the external electrode 50 as a base material, the linear expansion coefficient can be made closer to the semiconductor element 1, so in the cooling and heating cycles generated during the operation of the semiconductor device 102. The deformation of the generated external electrode 50 can be suppressed.

さらに外部電極５０の表面及び裏面にＣｕ金属シート５２層を形成することにより、外部電極５０の表面及び裏面における電気抵抗を低減すると同時に、外部電極５０の半田接合性、及び半導体素子上半田２１との接合界面の信頼性も確保することができるため、より信頼性の高い半導体装置１０２を実現することができる。   Furthermore, by forming a Cu metal sheet 52 layer on the front and back surfaces of the external electrode 50, the electrical resistance on the front and back surfaces of the external electrode 50 is reduced, and at the same time the solderability of the external electrode 50 and the solder 21 on the semiconductor element are obtained. Since the reliability of the bonding interface can be secured, the semiconductor device 102 with higher reliability can be realized.

このように、実施の形態２の半導体装置１０２では、外部電極５０の表面及び裏面に形成される銅形成層であるＣｕ金属シート５２によって通電性能と半導体素子上半田２１との半田濡れ性を確保しながら、外部電極５０の母材となる金属板５１によって線膨脹係数を半導体素子１に近づけることができるため、実施の形態１の効果に加え、通電性及び半田濡れ性と装置の信頼性との両立を図ることができる効果を奏する。   As described above, in the semiconductor device 102 according to the second embodiment, the Cu metal sheet 52, which is a copper formation layer formed on the front and back surfaces of the external electrode 50, secures the conduction performance and the solder wettability with the solder 21 on the semiconductor element. While the coefficient of linear expansion can be made closer to the semiconductor element 1 by the metal plate 51 which is the base material of the external electrode 50, in addition to the effects of the first embodiment, the conductivity, the solder wettability and the reliability of the device The effect of being able to aim at coexistence of is produced.

＜実施の形態３＞
（構成）
図５は実施の形態３の半導体装置１０３の特徴部分の構造を示す説明図である。図５は図１及び図４で示した実施の形態１あるいは実施の形態２の半導体装置１０１あるいは１０２における着目領域Ｃ１１あるいはＣ１２に対応する箇所の構造を示している。Embodiment 3
(Constitution)
FIG. 5 is an explanatory view showing the structure of the characteristic part of the semiconductor device 103 of the third embodiment. FIG. 5 shows the structure of a portion corresponding to the focused region C11 or C12 in the semiconductor device 101 or 102 of the first or second embodiment shown in FIGS.

以下、同一構造部分には同一符号を付して説明を省略しつつ、図５を参照して、実施の形態１及び実施の形態２との相違点を中心に実施の形態３の半導体装置１０３について説明する。   In the following, the same structural parts are given the same reference numerals, and the description thereof is omitted, and with reference to FIG. 5, the semiconductor device 103 of the third embodiment is focused on the differences with the first embodiment and the second embodiment. Will be explained.

外部電極３１（５０）において、半田接合領域Ｒ３１ｈを含む垂下部３１ａ（５０ａ）の表面上に、外部電極３１より半田濡れ性がよい、被覆膜３２が形成されている点が実施の形態１及び実施の形態２と異なる。 In the external electrode 31 (50), on the surface of the suspended portion 31a (50a) comprising a solder joint area R31h, good solder wettability than the external electrodes 31, the embodiment is that the covering film 32 is formed 1 And different from the second embodiment.

被覆膜３２は、例えば、Ｎｉからなる金属膜であるニッケル被覆膜である。被覆膜３２は、例えば、外部電極３１のうち垂下部３１ａ（５０ａ）の表面のみに形成され、それ以外の領域は被覆膜３２が形成されることなく外部電極３１の表面が露出している。被覆膜３２として、Ｎｉを形成する方法としては、例えば、Ｎｉを無電解メッキ法で形成する方法が挙げられる。垂下部３１ａは外部電極３１の他の領域から半導体素子１側に突出しているので、垂下部３１ａのみをメッキ液に浸漬することができ、容易に部分メッキすることができる。例えば、外部電極３１に通電することで電界メッキを用いることもできる。 The covering film 32 is, for example, a nickel coating film is a metal film made of Ni. The covering film 32 is formed, for example, only on the surface of the suspended portion 31a (50a) of the external electrode 31, the other area is exposed surfaces of the external electrodes 31 without the covering film 32 is formed There is. As the covering film 32, as a method for forming a Ni, for example, a method of forming a Ni by electroless plating. Since the drooping portion 31a protrudes from the other region of the external electrode 31 to the semiconductor element 1 side, only the drooping portion 31a can be immersed in the plating solution, and partial plating can be easily performed. For example, electrolytic plating can be used by energizing the external electrode 31.

（動作・効果・作用）
実施の形態３の半導体装置１０３は、外部電極３１あるいは外部電極５０を有する実施の形態１あるいは実施の形態２の効果に加え、以下の効果を奏する。(Operation, effect, action)
The semiconductor device 103 according to the third embodiment has the following effects in addition to the effects of the first or second embodiment having the external electrode 31 or the external electrode 50.

半導体装置１０３は、外部電極３１における半田接合領域Ｒ３１ｈを含む垂下部３１ａの表面に、外部電極３１より半田濡れ性がよい被覆膜３２を形成することにより、垂下部３１ａに対する半導体素子上半田２１の濡れ広がりを促がし、外部電極３１側のフィレットＦ２を、より確実に形成することができる。 The semiconductor device 103, the surface of the hanging portion 31a including the solder joint area R31h in the external electrode 31, by forming the solder wettability is better to be covered film 32 from the outer electrode 31, the semiconductor device for hanging portion 31a solder 21 And the fillet F2 on the external electrode 31 side can be formed more reliably.

加えて、半導体装置１０３は、外部電極３１の表面における垂下部３１ａのみに選択的に被覆膜３２を形成することにより、半導体素子上半田２１の濡れ広がりを、より確実に垂下部３１ａのみに留めておくことができるため、半導体素子上半田２１の形状制御性を向上させる効果を奏する。 In addition, the semiconductor device 103, by forming a selectively be covered film 32 only in the suspended portion 31a on the surface of the external electrode 31, the wetting and spreading of the semiconductor element on the solder 21, only the more reliable hanging part 31a Since it can be held, the effect of improving the shape controllability of the on-semiconductor-element solder 21 can be obtained.

また、被覆膜３２としてＮｉを構成材料としたニッケル被覆膜を用いることにより、比較的容易な方法でＣｕより半田濡れ性のよい被覆膜３２を形成することができ、半田接合領域Ｒ３１ｈの接合信頼性を高めることができる。 Further, by using a nickel target covered film and the constituent materials of Ni as the covering film 32, it is possible to form a covering the good solder wettability of Cu film 32 in a relatively easy way, the solder bonding region R31h Junction reliability can be enhanced.

（変形例）
実施の形態３の変形例として、被覆膜３２として、例えば、Ａｕ（金）を構成材料とした金被覆膜を用いても良い。Ａｕからなる金被覆膜は、Ｎｉからなるニッケル被覆膜と同様、メッキ法にて形成することができる。 (Modification)
As a modification of the third embodiment, as the covering film 32, for example, may be used gold coated film was a constituent material of Au (gold). Gold target covering film made of Au, as well as nickel-be covering film made of Ni, can be formed by a plating method.

被覆膜３２として金被覆膜を用いることにより、半田の主成分であるＳｎ（錫）と反応したときに、Ｓｎ−Ａｕ系金属間化合物が形成されるが、Ｓｎ−Ａｕ系金属間化合物の２元素系の融点上昇は低いため、金被覆膜である被覆膜３２と反応した半田が融点上昇により凝固することを抑えることができる。また、Ａｕは表面が酸化され難く、高い半田濡れ性を実現することができるので、外部電極３１側のフィレットＦ２を、より確実に形成することができる。 The use of gold to be covered film as an object to be covered film 32, when reacted with Sn (tin) is a solder composed mainly, but Sn-Au-based intermetallic compound is formed, Sn-Au intermetallic compound low melting point elevation of 2-element for, solder react with a covering film 32 which is a gold target covered film can be prevented from being solidified by a melting point rises. In addition, Au is unlikely to be oxidized on the surface, and high solder wettability can be realized, so that the fillet F2 on the external electrode 31 side can be formed more reliably.

＜実施の形態４＞
（第１の態様：構成）
図６はこの発明の実施の形態４における第１の態様の半導体装置１０４Ａの特徴部の構造を示す説明図である。図６は図１あるいは図４で示した実施の形態１あるいは実施の形態２の半導体装置１０１あるいは１０２における着目領域Ｃ１１あるいはＣ１２に対応する箇所の構造を示している。Fourth Preferred Embodiment
(First aspect: configuration)
FIG. 6 is an explanatory drawing showing the structure of the characterizing part of the semiconductor device 104A of the first aspect in the fourth embodiment of the present invention. FIG. 6 shows the structure of a portion corresponding to the focused region C11 or C12 in the semiconductor device 101 or 102 of the first or second embodiment shown in FIG. 1 or FIG.

以下、同一構造部分には同一符号を付して説明を省略しつつ、図６を参照して、実施の形態１及び実施の形態２との相違点を中心に実施の形態４の第１の態様である半導体装置１０４について説明する。   Hereinafter, the same reference numerals are given to the same structural portions, and the description thereof is omitted. Referring to FIG. 6, the first embodiment of the fourth embodiment will be described focusing on the differences with the first embodiment and the second embodiment. The semiconductor device 104 which is an aspect will be described.

図６に示すように、半導体装置１０４Ａは、外部電極３１（５０）の表面側において、半田接合領域Ｒ３１ｈより外周側に位置する垂下部外周部３１ｂ上に被覆膜３３（半田形成防止膜）を形成したことを特徴としている。なお、図６では、外部電極３１における垂下部３１ａ（５０ａ）より外周側の領域を垂下部外周部３１ｂとしている。 As shown in FIG. 6, the semiconductor device 104A, in the surface side of the external electrode 31 (50), the solder joint hanging part outer peripheral portion 31b on the covering film 33 which is located radially outward of the region R31h (solder formed preventing film) It is characterized by having formed. In FIG. 6, a region on the outer peripheral side of the hanging portion 31a (50a) of the external electrode 31 is a hanging outer peripheral portion 31b.

被覆膜３３は、半田の進展を阻害する構造である半田形成防止構造として寄与する。被覆膜３３は、例えば、外部電極３１より半田濡れ性が低い構成材料を用いて形成されている。被覆膜３３として、例えば、ソルダーレジストを構成材料とした被覆膜が考えられる。この場合、外部電極３１にソルダーレジストを印刷し、加熱乾燥し、マスク露光し、現像し、加熱硬化することで、垂下部３１ａの半田接合領域Ｒ３１ｈを露出させつつ、ソルダーレジストを構成材料とした被覆膜３３を垂下部外周部３１ｂのみに選択的に形成することができる。 The covered film 33 contributes as the solder forming prevention structure is a structure to inhibit the development of the solder. The covered film 33 is, for example, formed by using the constituent materials less solder wettability than the external electrodes 31. As the covering layer 33, for example, it is covered film is considered that the solder resist and the material. In this case, the solder resist is printed on the external electrode 31, heat-dried, mask-exposed, developed, and heat-cured to form the solder resist as a constituent material while exposing the solder joint region R31h of the hanging portion 31a. it can be selectively formed to be covered film 33 only on the hanging part outer peripheral portion 31b.

（動作・作用）
外部電極３１において半田接合領域Ｒ３１ｈより外側の垂下部外周部３１ｂに、半田形成防止構造である被覆膜３３を形成することにより、半導体素子上半田２１の濡れ広がりを、より確実に半田接合領域Ｒ３１ｈのみに留めておくことができるため、半導体素子上半田２１の形状制御性がより一層向上する。この際、半田形成阻害構造として、外部電極３１より半田濡れ性が低い被覆膜３３を採用することにより、垂下部３１ａより外側へ半田が濡れ広がることをより確実に防止することができる。 (Operation / action)
In the external electrode 31 on the outside of the hanging part outer peripheral portion 31b of solder bonding region R31h, by forming a target covering film 33 which is a solder forming prevention structure, the spreading of the semiconductor element on the solder 21, more reliably solder bonding region Since only R 31 h can be held, the shape controllability of the solder on semiconductor element 21 is further improved. In this case, as the solder-inhibiting structure, by employing the solder wettability is low to be covered film 33 from the external electrode 31, it is possible to more reliably prevent solder that wets and spreads outward from the hanging part 31a.

被覆膜３３の構成材料としてソルダーレジストを用いることで、半田が濡れ広がることを確実に防止することができると同時に、樹脂４１との密着性の向上を図ることができる。 By using a solder resist as the material of the covering layer 33, and at the same time it is possible to reliably prevent the solder spreads, it is possible to improve the adhesion with the resin 41.

（第２の態様：構成）
図７はこの発明の実施の形態４における第２の態様の半導体装置１０４Ｂの特徴部の構造を示す説明図である。図７は図１あるいは図４で示した実施の形態１あるいは実施の形態２の半導体装置１０１あるいは１０２における着目領域Ｃ１１あるいはＣ１２に対応する箇所の構造を示している。(Second aspect: Configuration)
FIG. 7 is an explanatory drawing showing the structure of the characterizing part of the semiconductor device 104B of the second aspect in the fourth embodiment of the present invention. FIG. 7 shows the structure of a portion corresponding to the focused area C11 or C12 in the semiconductor device 101 or 102 of the first or second embodiment shown in FIG. 1 or FIG.

以下、同一構造部分には同一符号を付して説明を省略しつつ、図７を参照して、実施の形態１及び実施の形態２との相違点を中心に実施の形態４の第２の態様である半導体装置１０４Ｂについて説明する。   Hereinafter, the same reference numerals are given to the same structural portions, and the description thereof is omitted. Referring to FIG. 7, a second embodiment of the fourth embodiment will be described focusing on the differences with the first embodiment and the second embodiment. The semiconductor device 104B which is an aspect will be described.

同図に示すように、外部電極３１の表面側において、半田接合領域Ｒ３１ｈ及び垂下部３１ａより外側の領域である垂下部外周部３１ｂに、半田形成防止構造として凹凸加工部３４（凹凸構造）が形成されている。凹凸加工部３４は、例えば、外部電極３１に凹凸加工部３４形状に対応した金型を押しつけることにより製造される。他に、例えば、外部電極３１の垂下部外周部３１ｂの表面に、凹凸加工部３４の凹部に対応した部分のみ露出した形状のレジストを形成し、レジスト越しにエッチングし、このレジストを除去することにより、凹凸加工部３４を形成しても良い。   As shown in the figure, on the surface side of the external electrode 31, a concavo-convex processed portion 34 (concave and convex structure) is provided as a solder formation preventing structure in the drooping outer peripheral portion 31b outside the solder joint region R31h and the drooping portion 31a. It is formed. The uneven portion 34 is manufactured, for example, by pressing a die corresponding to the shape of the uneven portion 34 to the external electrode 31. In addition, for example, on the surface of the hanging outer peripheral portion 31b of the external electrode 31, a resist having a shape in which only a portion corresponding to the concave portion of the concavo-convex processed portion 34 is exposed is etched over the resist to remove this resist. The uneven portion 34 may be formed by this.

このように、実施の形態４の第２の態様である半導体装置１０４Ｂは、外部電極３１の垂下部外周部３１ｂに凹凸加工部３４を形成することにより、垂下部３１ａより外側へ半田が濡れ広がることをより確実に防止することができると同時に、樹脂４１との密着性を向上することができる。   As described above, in the semiconductor device 104B according to the second aspect of the fourth embodiment, the solder wets and spreads to the outer side than the hanging portion 31a by forming the concavo-convex processed portion 34 in the hanging outer peripheral portion 31b of the external electrode 31. At the same time, the adhesion to the resin 41 can be improved.

（効果）
実施の形態４の半導体装置１０４（１０４Ａ及び１０４Ｂ）は、外部電極３１あるいは外部電極５０を有する実施の形態１あるいは実施の形態２の効果に加え、以下の効果を奏する。(effect)
The semiconductor device 104 (104A and 104B) of the fourth embodiment has the following effects in addition to the effects of the first or second embodiment having the external electrode 31 or the external electrode 50.

このように、実施の形態４の半導体装置１０４は、外部電極３１の半田接合領域Ｒ３１ｈの領域である垂下部外周部３１ｂに、被覆膜３３あるいは凹凸加工部３４である半田形成防止構造を設けることにより、垂下部外周部３１ｂへの半田形成を防止することにより、半導体素子上半田２１におけるフィレットＦ２を安定性良く形成することができる。 Thus, the semiconductor device 104 of the fourth embodiment, the hanging portion outer peripheral portion 31b which is a region of the solder joint area R31h external electrode 31 is provided with a solder forming prevention structure which is an object to be covered film 33 or the roughened portion 34 Thus, by preventing the formation of the solder on the hanging outer peripheral portion 31b, the fillet F2 of the on-semiconductor-element solder 21 can be stably formed.

第１の態様である半導体装置１０４Ａは、半田形成防止膜である被覆膜３３によって垂下部外周部３１ｂへの半田形成を確実に防止して、半田形状制御性を高めることにより、装置の歩留まり及び信頼性の向上を図ることができる。 The semiconductor device 104A which is a first aspect is to reliably prevent solder formation on the hanging portion outer peripheral portion 31b by the covering film 33 which is a solder formation preventing film, by increasing the solder shape controllability, device yield And the reliability can be improved.

第２の態様である半導体装置１０４Ｂは、凹凸加工部３４（凹凸構造）によって垂下部外周部３１ｂへの半田形成を確実に防止して、半田形状制御性を高めることにより、装置の歩留まり及び信頼性の向上を図ることができる。さらに、樹脂４１を設ける際、凹凸加工部３４の凹部に樹脂４１が入り込むことにより樹脂４１との密着性を高め、半導体装置１０４Ｂの信頼性のさらなる向上を図ることができる。   The semiconductor device 104B according to the second aspect reliably prevents the solder formation on the hanging outer peripheral portion 31b by the concavo-convex processed portion 34 (concave and convex structure), and improves the solder shape controllability, thereby improving the yield and reliability of the device. It is possible to improve the quality. Furthermore, when the resin 41 is provided, the resin 41 intrudes into the concave portion of the concavo-convex processed portion 34, so that the adhesiveness with the resin 41 can be enhanced, and the reliability of the semiconductor device 104B can be further improved.

＜その他＞
実施の形態１〜実施の形態４の半導体装置１０１〜１０４（１０４Ａ，１０４Ｂ）では。半導体素子１としてＩＧＢＴを例に挙げたが、他にパワーＭＯＳＦＥＴ、整流ダイオードなどの他のデバイスを半導体素子１として構成しても良い。いずれの場合も外部電極３１（５０）に垂下部３１ａ（５０ａ）が形成され、垂下部３１ａと半導体素子１とを半田接合し、半田フィレット（フィレットＦ１及びＦ２）を形成することができれば、実施の形態１〜実施の形態４の効果である装置の通電能力及び信頼性の向上を図るという効果を達成すことができる。<Others>
In the semiconductor devices 101 to 104 (104A, 104B) of the first to fourth embodiments. Although the IGBT has been exemplified as the semiconductor element 1, other devices such as a power MOSFET and a rectifier diode may be configured as the semiconductor element 1. In any case, if the drooping portion 31a (50a) is formed on the external electrode 31 (50), and the drooping portion 31a and the semiconductor element 1 can be soldered to form the solder fillets (fillets F1 and F2), It is possible to achieve the effect of improving the energization capability and the reliability of the device, which is the effect of the first to fourth embodiments.

さらに、本発明は半導体素子１として特にパワーデバイスに限定すべき理由もなく半導体デバイス一般に応用できる。その他、本発明の特徴を失わない範囲でさまざまな形態をなし得る。   Furthermore, the present invention can be applied to semiconductor devices in general without a reason to be particularly limited to the power device as the semiconductor device 1. Besides, various forms can be made without losing the features of the present invention.

この発明は詳細に説明されたが、上記した説明は、全ての局面において、例示であって、この発明がそれに限定されるものではない。例示されていない無数の変形例が、この発明の範囲から外れることなく想定され得るものと解される。   Although the present invention has been described in detail, the above description is an exemplification in all aspects, and the present invention is not limited thereto. It is understood that countless variations not illustrated are conceivable without departing from the scope of the present invention.

すなわち、本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略したりすることが可能である。   That is, in the present invention, within the scope of the invention, each embodiment can be freely combined, or each embodiment can be appropriately modified or omitted.

１ 半導体素子、１１ 表面電極、１２ 裏面電極、１３ 半田接合用金属膜、１４ 保護膜、２１ 半導体素子上半田、２２ 半導体素子下半田、３１，３５，５０ 外部電極、３１ａ，５０ａ 垂下部、３２，３３ 被覆膜、３４ 凹凸加工部、３６ 制御電極、４１ 樹脂、５１ 金属板、５２ Ｃｕ金属シート、１０１〜１０３，１０４Ａ，１０４Ｂ 半導体装置。


DESCRIPTION OF SYMBOLS 1 semiconductor element, 11 surface electrode, 12 back surface electrode, 13 metal film for solder joining, 14 protective film, 21 solder on semiconductor element, 22 solder on semiconductor element, 31, 35, 50 external electrode, 31a, 50a hanging portion, 32 , 33 to be covered film, 34 roughened portion, 36 a control electrode, 41 resin, 51 a metal plate, 52 Cu metal sheet, 101～103,104A, 104B semiconductor device.


Claims (26)

一方主面及び他方主面を有し、一方主面上に平坦な表面を有する一方電極（１１）が設けられる半導体素子（１）と、
前記一方電極の上方に設けられた外部電極（３１，５０）とを備え、前記外部電極の表面と前記一方電極の表面とが対向し、
前記一方電極の表面，前記外部電極の表面間に形成され、前記一方電極，前記外部電極間を電気的に接続する半田形成部（２１）をさらに備え、
前記一方電極及び前記外部電極が平面視重複する領域の少なくとも一部が、前記一方電極及び前記外部電極それぞれの表面における第１及び第２の半田接合領域（Ｒ１１ｈ及びＲ３１ｈ）として規定され、
前記外部電極は、他の領域より前記一方電極の表面側に突出した垂下部（３１ａ）を有し、前記垂下部は平面視して前記第２の半田接合領域を含み、前記第１及び第２の半田接合領域の中心位置である半田中心点（ＨＣ）に向かって、前記外部電極の表面と前記一方電極の表面との垂直距離が短くなる傾斜部（３１ｓ）を有し、
前記半田形成部は、前記一方電極の前記第１の半田接合領域から前記外部電極の前記第２の接合領域にかけて形成され、前記一方電極の表面から上方にかけて前記半田中心点の方向に湾曲した第１の湾曲形状（Ｆ１）と、前記外部電極の表面から下方にかけて前記半田中心点の方向に湾曲した第２の湾曲形状（Ｆ２）とを含む端面形状を有し、
前記外部電極の表面における前記第２の半田接合領域上に少なくとも設けられ、前記外部電極に比べ半田濡れ性が優る構成材料で形成された被覆膜（３２）をさらに備え、
前記被覆膜は前記外部電極の表面における前記垂下部上にのみに形成される、
半導体装置。 A semiconductor element (1) having a first main surface and a second main surface and having a first electrode (11) having a flat surface on the first main surface;
And an external electrode (31, 50) provided above the one electrode, wherein the surface of the external electrode and the surface of the one electrode face each other,
It further comprises a solder forming portion (21) formed between the surface of the one electrode and the surface of the external electrode to electrically connect the one electrode and the external electrode.
At least a part of a region where the one electrode and the external electrode overlap in plan view is defined as first and second solder joint regions (R11h and R31h) on the surface of the one electrode and the external electrode,
The external electrode has a drooping portion (31a) which protrudes to the surface side of the one electrode from the other region, and the drooping portion includes the second solder joint region in plan view and includes the first and the second A slant portion (31s) in which the vertical distance between the surface of the external electrode and the surface of the one electrode is shortened toward the solder center point (HC) which is the center position of the solder joint region 2;
The solder formation portion is formed from the first solder joint region of the one electrode to the second joint region of the external electrode, and is curved in the direction of the solder center point from the surface of the one electrode to the upper side a first curved shape (F1), the end surface shape including a second curved shape (F2) and curved in the direction of the solder center point to bottom from the surface of the external electrodes possess,
It further comprises a covering film (32) provided at least on the second solder joint region on the surface of the external electrode, and formed of a constituent material superior in solder wettability to the external electrode.
The coating film is formed only on the hanging portion on the surface of the external electrode,
Semiconductor device. 請求項１記載の半導体装置であって、
第１及び第２の半田接合領域の平面形状は矩形状を呈する、
半導体装置。 The semiconductor device according to claim 1, wherein
The planar shape of the first and second solder joint regions is rectangular.
Semiconductor device. 請求項２記載の半導体装置であって、
前記第１及び第２の半田接合領域の平面形状である矩形状は、角部が面取りされた面取り矩形状を呈する、
半導体装置。 The semiconductor device according to claim 2,
The rectangular shape, which is the planar shape of the first and second solder joint regions, exhibits a chamfered rectangular shape with chamfered corners.
Semiconductor device. 請求項３記載の半導体装置であって、
前記第１及び第２の半田接合領域は平面視完全重複する同一形状を呈する、
半導体装置。 The semiconductor device according to claim 3, wherein
The first and second solder joint regions have the same shape completely overlapping in plan view,
Semiconductor device. 請求項３記載の半導体装置であって、
前記垂下部は前記半田中心点を含んで前記一方電極の表面からの距離が一定となる平坦な底面部（３１ｍ）を有し、
前記第２の半田接合領域の外周からの前記底面の外周への平面距離（ｒ１）と、前記面取り矩形状における角部の曲率半径（ｒ２）とを等しくしたことを特徴とする、
半導体装置。 The semiconductor device according to claim 3, wherein
The hanging portion has a flat bottom portion (31 m) including the solder center point and having a constant distance from the surface of the one electrode,
The flat distance (r1) from the outer periphery of the second solder joint region to the outer periphery of the bottom surface is made equal to the curvature radius (r2) of the corner in the chamfered rectangular shape.
Semiconductor device. 請求項５記載の半導体装置であって、
前記外部電極は前記底面部を含む前記垂下部において、表面から裏面を貫通する貫通穴（３１ｔ）を有する、
半導体装置。 A semiconductor device 請 Motomeko 5, wherein,
The external electrode has a through hole (31t) penetrating from the front surface to the back surface in the hanging portion including the bottom surface portion.
Semiconductor device. 請求項１から請求項６のうち、いずれか１項に記載の半導体装置であって、
前記外部電極（３１）は銅を構成材料とした単体構造である、
半導体装置。 7. The semiconductor device according to any one of claims 1 to 6, wherein
The external electrode (31) is a single-piece structure using copper as a constituent material,
Semiconductor device. 請求項１から請求項６のうち、いずれか１項に記載の半導体装置であって、
前記外部電極（５０）は、
銅より線膨張係数が低い金属材料により構成した金属板（５１）と、
前記金属板の表面上に少なくとも形成され、銅を構成材料とした銅形成層（５２）とを含む、
半導体装置。 7. The semiconductor device according to any one of claims 1 to 6, wherein
The external electrode (50) is
A metal plate (51) made of a metal material having a linear expansion coefficient lower than that of copper;
And at least a copper forming layer (52) formed on the surface of the metal plate and made of copper.
Semiconductor device. 請求項１記載の半導体装置であって、
前記被覆膜はニッケルを構成材料としたニッケル被覆膜である、
半導体装置。 The semiconductor device according to claim 1 , wherein
The coating film is a nickel coating film composed of nickel,
Semiconductor device. 請求項１記載の半導体装置であって、
前記被覆膜は金を構成材料とした金被覆膜である、
半導体装置。 The semiconductor device according to claim 1 , wherein
The coating film is a gold coating film made of gold,
Semiconductor device. 請求項１から請求項１０のうち、いずれか１項に記載の半導体装置であって、
前記外部電極は前記第２の半田接合領域より外周側に位置する垂下部外周部（３１ｂ）を有し、
前記垂下部外周部は前記半田形成部の形成時に半田の形成を防止する半田形成防止構造（３３，３４）を有することを特徴とする、
半導体装置。 A semiconductor device according to any one of claims 1 to 10 , wherein
The external electrode has a hanging portion outer peripheral portion (31b) positioned on the outer peripheral side of the second solder bonding region,
The drooping outer peripheral portion has a solder formation preventing structure (33, 34) for preventing formation of solder when forming the solder formation portion,
Semiconductor device. 請求項１１記載の半導体装置であって、
前記外部電極の表面側における前記垂下部外周部上に形成された半田形成防止膜（３３）をさらに備え、
前記半田形成防止膜は前記外部電極の表面を形成する材料に比べ、半田濡れ性が低い材料で構成され、前記半田形成防止構造は前記半田形成防止膜を含む、
半導体装置。 The semiconductor device according to claim 11 , wherein
It further comprises a solder formation preventing film (33) formed on the drooping outer peripheral portion on the surface side of the external electrode,
The solder formation preventing film is made of a material having lower solder wettability than the material forming the surface of the external electrode, and the solder formation preventing structure includes the solder formation preventing film.
Semiconductor device. 請求項１２記載の半導体装置であって、
前記半田形成防止膜はソルダーレジストを構成材料とする、
半導体装置。 13. The semiconductor device according to claim 12 , wherein
The solder formation preventing film comprises a solder resist as a constituent material.
Semiconductor device. 請求項１２記載の半導体装置であって、
前記外部電極の表面側における前記垂下部外周部に形成された凹凸構造（３４）をさらに備え、
前記半田形成防止構造は前記凹凸構造を含む、
半導体装置。 13. The semiconductor device according to claim 12 , wherein
It further comprises a concavo-convex structure (34) formed on the drooping outer peripheral portion on the surface side of the external electrode,
The solder formation preventing structure includes the uneven structure.
Semiconductor device. 請求項１から請求項１４のうち、いずれか１項に記載の半導体装置であって、
前記第１及び第２の半田接合領域は複数の第１及び第２の半田接合領域を含み、
前記垂下部は前記複数の第２の半田接合領域に対応した複数の垂下部を含み、
前記半田形成部は前記複数の第１及び第２の半田接合領域に対応した複数の半田形成部を含む、
半導体装置。 The semiconductor device according to any one of claims 1 to 14 ,
The first and second solder joint areas include a plurality of first and second solder joint areas,
The drooping includes a plurality of drooping corresponding to the plurality of second solder joint areas,
The solder formation portion includes a plurality of solder formation portions corresponding to the plurality of first and second solder joint regions,
Semiconductor device. 請求項１から請求項１５のうち、いずれか１項に記載の半導体装置であって、
前記半導体素子と前記半田形成部と前記外部電極の少なくとも一部とを覆って封止する樹脂（４１）をさらに備える、
半導体装置。 A semiconductor device according to any one of claims 1 to 15 ,
And a resin (41) which covers and seals the semiconductor element, the solder formation portion, and at least a part of the external electrode.
Semiconductor device. 請求項１６記載の半導体装置であって、
前記半導体素子は第１の線膨張係数を有し、
前記樹脂は前記第１の線膨張係数より高い第２の線膨張係数を有し、
前記外部電極は前記第２の線膨張係数より高い第３の線膨張係数を有する、
半導体装置。 The semiconductor device according to claim 16 , wherein
The semiconductor device has a first linear expansion coefficient,
The resin has a second linear expansion coefficient higher than the first linear expansion coefficient,
The outer electrode has a third linear expansion coefficient higher than the second linear expansion coefficient,
Semiconductor device. 請求項１６または請求項１７に記載の半導体装置であって、
前記一方電極の表面において、少なくとも前記第１の半田接合領域上に形成される半田接合用金属膜（１３）をさらに備え、
前記半田形成部は前記半田接合用金属膜を介して前記一方電極の表面上に形成される、
半導体装置。 The semiconductor device according to claim 16 or 17 , wherein
The semiconductor device further comprises a solder bonding metal film (13) formed on at least the first solder bonding region on the surface of the one electrode.
The solder formation portion is formed on the surface of the one electrode via the solder bonding metal film.
Semiconductor device. 請求項１８記載の半導体装置であって、
前記半田接合用金属膜は、ニッケルを構成材料とした半田接合用ニッケル膜を含む、
半導体装置。 The semiconductor device according to claim 18 , wherein
The solder bonding metal film includes a solder bonding nickel film containing nickel as a constituent material.
Semiconductor device. 請求項１８または請求項１９記載の半導体装置であって、
前記半導体素子は一方主面上において、前記一方電極が形成されていない領域に少なくとも形成される保護膜（１４）をさらに有する、
半導体装置。 21. A semiconductor device according to claim 18 or 19 , wherein
The semiconductor device further includes a protective film (14) formed at least in a region where the one electrode is not formed on one main surface.
Semiconductor device. 請求項２０記載の半導体装置であって、
前記保護膜は厚みが２〜２０μｍのポリイミド膜である、
半導体装置。 21. The semiconductor device according to claim 20 , wherein
The protective film is a polyimide film having a thickness of 2 to 20 μm.
Semiconductor device. 請求項１から請求項２１のうち、いずれか１項に記載の半導体装置であって、
前記半導体素子は炭化珪素を構成材料とした半導体素子である、
半導体装置。 A semiconductor device according to any one of claims 1 to 21 ,
The semiconductor device is a semiconductor device using silicon carbide as a constituent material.
Semiconductor device. 請求項１から請求項２２のうち、いずれか１項の記載の半導体装置であって、
前記一方電極はアルミを９５％以上含む材料から構成される、
半導体装置。 A semiconductor device according to any one of claims 1 to 22 ,
The one electrode is made of a material containing 95% or more of aluminum,
Semiconductor device. 請求項１６から請求項２１のうちいずれか１項に記載の半導体装置の製造方法であって、
前記樹脂を形成する工程として、
仮固定された前記半導体素子、前記半田形成部及び前記外部電極に対し、液状樹脂を吐出して加熱硬化させることにより、前記半導体素子と前記半田形成部と前記外部電極の少なくとも一部とを覆って前記樹脂を形成するステップを有する、
半導体装置の製造方法。 A method of manufacturing a semiconductor device according to any one of claims 16 to 21 ,
As a process of forming the said resin,
A liquid resin is discharged onto the temporarily fixed semiconductor element, the solder formation portion, and the external electrode, and heat curing is performed to cover the semiconductor element, the solder formation portion, and at least a part of the external electrode. Forming the resin.
Semiconductor device manufacturing method. 請求項２０または請求項２１記載の半導体装置の製造方法であって、
前記保護膜及び前記半田接合用金属膜を形成する工程として、
(a) 前記半導体素子の一方主面上において前記一方電極が形成されていない領域から、前記一方電極の表面における前記第１の半田接合領域の外縁領域にかけて前記保護膜を形成するステップと、
(b) 前記保護膜をマスクとして湿式メッキ法を用いて、前記一方電極の表面における前記第１の半田接合領域上に前記半田接合用金属膜を形成するステップとを含む、
半導体装置の製造方法。 22. A method of manufacturing a semiconductor device according to claim 20 or 21 ,
As a process of forming the protective film and the metal film for solder bonding,
(a) forming the protective film from a region where the one electrode is not formed on one main surface of the semiconductor element to an outer edge region of the first solder joint region on the surface of the one electrode;
(b) forming the metal film for solder bonding on the first solder bonding region on the surface of the one electrode using a wet plating method using the protective film as a mask;
Semiconductor device manufacturing method. 請求項１から請求項２３のうち、いずれか１項に記載の半導体装置の製造方法であって、
前記半田形成部を形成する工程として、
還元雰囲気中において、前記一方電極の表面と前記外部電極の表面との間に配置された、固相あるいはペースト状の半田材を溶融することにより、前記半田形成部を得るステップを含む、
半導体装置の製造方法。 A method of manufacturing a semiconductor device according to any one of claims 1 to 23 ,
As a process of forming the said solder formation part,
Obtaining the solder-formed portion by melting a solid-phase or paste-like solder material disposed between the surface of the one electrode and the surface of the external electrode in a reducing atmosphere;
Semiconductor device manufacturing method.
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