JP4815905B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device in which electrodes are respectively provided on a front surface and a back surface of a semiconductor substrate on which a semiconductor element is formed, and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, a semiconductor device in which a metal thin film electrode is formed not only on the surface of a semiconductor substrate on which a semiconductor element is formed but also on the back surface is known. In such a semiconductor device, first, an electrode made of a metal thin film is formed on either one of the front and back surfaces of the semiconductor substrate on which the semiconductor element is formed, and then the electrode is similarly formed on the other surface. It has become.

  In recent years, semiconductor substrates have become thinner and larger in diameter. Accordingly, when one electrode is formed on each of the front and back surfaces of the semiconductor substrate on which the semiconductor element is formed, the electrode is formed on the electrode of the metal thin film when the electrode is formed on one of the front and back surfaces. A problem arises in that stress is generated and the semiconductor substrate is warped.

Therefore, Patent Document 1 proposes a method for solving such a problem. Specifically, Patent Document 1 proposes a method of canceling the film stress on both surfaces of the substrate by simultaneously forming metal thin films as electrodes on the front and back surfaces of the semiconductor substrate.
JP-A-9-186235

  However, the method disclosed in Patent Document 1 does not consider the influence of the difference in the shape and material of the base on the front and back surfaces of the semiconductor substrate. For this reason, a difference occurs in the film stress generated in each metal thin film formed on each of the front and back surfaces of the semiconductor substrate, and the adhesion strength of each metal thin film on the front and back surfaces of the semiconductor substrate differs.

  Specifically, in the semiconductor substrate, the state of the shape such as a pattern or the state by the pretreatment is different between the front and back surfaces. For this reason, even if a metal thin film having the same stress is simultaneously formed on the front and back surfaces of the semiconductor substrate, a difference occurs in the stress of each metal thin film, and the semiconductor substrate may be warped. This warpage of the semiconductor substrate may reduce the crystallinity of the semiconductor substrate and reduce the reliability of the semiconductor element.

  Moreover, since the state of the front and back surfaces of the semiconductor substrate is different, the adhesion strength of the metal thin film to the semiconductor substrate is biased to one of the front and back surfaces. For this reason, for example, when assembling such as soldering through a metal thin film as an electrode formed on a semiconductor substrate, the metal thin film with weak adhesion may be peeled off from the semiconductor substrate. May be reduced.

  In view of the above points, the present invention suppresses the warpage of the semiconductor substrate due to the film stress of the electrode, and reduces the difference in adhesion between each electrode formed on the front and back surfaces of the semiconductor substrate including the semiconductor element. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same.

In order to achieve the above object, according to the present invention, the surface of the first back electrode (31) formed on the back surface of the semiconductor substrate (10) is uneven and the first surface formed on the surface of the semiconductor substrate. electrode (18) recess interlayer insulating film on the surface (17) corresponding to the shape of the opened contact holes (17a) of (18a) that is plurality, of the surface area of the first surface electrode first back electrode are the surface area is the same, a second surface electrode formed on the first surface electrode (25) and the first second back electrodes (32) formed on the back electrode, the first surface electrode and the It is characterized by being formed simultaneously on each surface of one back electrode.

  Thus, the surfaces of the first front electrode and the first back electrode are bumpy surfaces, respectively. Thereby, the junction area of the 2nd surface electrode with respect to the 1st surface electrode can be increased by a plurality of crevices, and the adhesion nature of the 1st surface electrode and the 2nd surface electrode can be improved. Similarly, the bonding area of the second back electrode with respect to the first back electrode can be increased by a bumpy shape, and the adhesion between the first back electrode and the second back electrode can be improved. Therefore, when the semiconductor substrate is mounted, peeling or destruction of each electrode can be prevented.

  Further, the second surface electrode and the second back electrode made of the same material are simultaneously formed on the respective surfaces of the first surface electrode and the first back electrode. Thereby, the film | membrane stress which arises in each of the 2nd surface electrode and 2nd back surface electrode formed in the front and back of a semiconductor substrate can be offset, and the curvature of a semiconductor substrate can be suppressed by extension. Thus, since the curvature of a semiconductor substrate can be suppressed, the crystal defect of a semiconductor substrate can be suppressed, and in addition to ensuring the reliability of a semiconductor element, the crack notch | chip in conveyance in a process can be prevented.

  Further, since the difference between the surface area of the first surface electrode and the surface area of the first back electrode is reduced, the adhesion of the second surface electrode to the first surface electrode and the second back electrode to the first back electrode The difference between the adhesive force and the adhesive force can be reduced. Therefore, the force applied to each electrode on the front and back surfaces of the semiconductor substrate becomes equal, and one electrode can be prevented from peeling off due to the difference in adhesion.

  In the present invention, the second front electrode and the second back electrode are formed simultaneously by a wet plating method, respectively.

  As a result, the second front electrode and the second back electrode can be simultaneously formed on the front and back surfaces of the semiconductor substrate, and the film stress generated in each electrode can be offset together with the electrode formation.

In the present invention, a semiconductor substrate (10) on which a semiconductor element is formed is prepared, and an interlayer insulating film (17) provided with a plurality of contact holes (17a) partly exposed on the surface of the semiconductor substrate is formed. Then, a metal film (40) is formed so as to cover the interlayer insulating film and the contact hole, and this metal film is patterned to form the first surface electrode (18). Subsequently, the first surface electrode is heat-treated to form a plurality of recesses (18a) corresponding to the shape of the contact hole on the surface. Thereafter, a first back electrode (31) is formed on the back surface of the semiconductor substrate, and wet etching is performed simultaneously on the heat-densified first surface electrode and the non-densified first back electrode. the bumpy first surface electrode without violently, so that the first surface electrode and the surface area that is bumpy by the recess are the same, is formed on the bumpy by melting the surface of the first back electrode, the first surface The second surface electrode (25) is formed on the surface of the electrode, and the second back electrode (32) made of the same material as the second surface electrode is formed on the surface of the first back electrode simultaneously.

  Thus, the 2nd surface electrode and the 2nd back electrode are formed simultaneously. Thereby, the film stress which arises in each of the 2nd surface electrode and the 2nd back electrode at the time of forming each electrode can be canceled. Therefore, the warp of the semiconductor substrate due to the film stress of the electrode can be suppressed. Thus, since the curvature of a semiconductor substrate can be suppressed, the crystal defect of a semiconductor substrate can be suppressed and the reliability of a semiconductor element can be ensured.

  Further, the surface of the first surface electrode is formed in a shape (including a recess) corresponding to the contact hole, and the surface of the first back electrode is formed on a rough surface by etching. Thereby, the surface area of the first surface electrode can be increased by the plurality of recesses, and the adhesion of the second surface electrode to the first surface electrode can be improved. Similarly, the surface area of the first back electrode can be increased by the uneven surface, and the adhesion of the second back electrode to the first back electrode can be improved. Therefore, when the semiconductor substrate is mounted, peeling or destruction of each electrode can be prevented.

  Further, the surface of the first back electrode is formed to be uneven by etching so that the difference from the surface area of the first surface electrode that is uneven due to the concave portion is reduced. That is, the etching of the first back electrode is adjusted so that the difference between the surface area of the first front electrode and the surface area of the first back electrode is small. As a result, the difference between the adhesion of the second surface electrode to the first surface electrode and the adhesion of the second back electrode to the first back electrode can be reduced, and a thermal cycle or the like can be performed when the semiconductor substrate is mounted. Even if stress is applied, it is possible to prevent one electrode from peeling off due to the difference in adhesion.

  In the present invention, in the step of simultaneously forming the second front electrode and the second back electrode, the second front electrode and the second back electrode are simultaneously formed by a wet plating method.

  Thus, by simultaneously forming the second front electrode and the second back electrode by the wet plating method, each electrode can be easily formed, and the film stress generated in each electrode can be offset at the time of electrode formation. it can.

  In the present invention, in the step of etching the surface of the first back electrode, the surface of the first surface electrode is also etched simultaneously with the first back electrode.

  In this way, the first surface electrode and the first back electrode are simultaneously etched on both sides. As a result, the surface of the first back electrode can be formed unevenly, and the roughness of the surface of the first surface electrode can be adjusted. Therefore, the state of each surface of the first front electrode and the first back electrode can be adjusted simultaneously.

  In the present invention, in the step of preparing a semiconductor substrate, an FZ crystal grown by the FZ method is prepared as a semiconductor substrate.

  Since the FZ crystal is grown as a single crystal, it has few crystal defects and can be used as a high-quality semiconductor substrate.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic cross-sectional view showing a semiconductor package using a semiconductor chip as a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a semiconductor chip according to an embodiment of the present invention. In the present embodiment, the semiconductor device includes an FS type IGBT (abbreviation for an insulated gate bipolar transistor) having a trench gate structure.

  First, as shown in FIG. 1, the semiconductor package 100 has a structure in which the heat sinks 2 and 3 and the lead terminals 4 are sealed with the resin 5 together with the semiconductor chip 1. One side and the end of the lead terminal 4 are exposed from the resin part 5. In the semiconductor chip 1, the gate electrode pad of the IGBT and the lead terminal 4 are connected via the gate wire 6.

  Each of the heat sinks 2 and 3 functions as a heat radiating plate and an electrode plate for radiating heat generated from the semiconductor chip 1, and therefore has good thermal conductivity and low electrical resistance such as Cu (copper) or Al (aluminum). Composed.

  Further, a solder 7 such as a lead-free solder is installed between the heat sinks 2 and 3 and the semiconductor chip 1. Therefore, the semiconductor chip 1 and the heat sinks 2 and 3 can be electrically connected to the outside via the heat sinks 2 and 3 and the lead terminals 4.

  In FIG. 2, the semiconductor chip 1 is formed using an N− type silicon substrate 10 (hereinafter also referred to as an N− type drift layer 10). The semiconductor chip 1 includes a cell portion and a cell portion. The outer periphery pressure | voltage resistant part formed in the outer periphery is comprised. In the present embodiment, an FZ crystal wafer grown by the FZ (floating zone) method is used as the silicon substrate 10.

  A number of IGBTs are formed in the cell portion. In the semiconductor chip 1, a P-type first base layer 11 is formed on the surface layer portion of the N − -type drift layer 10, and the concentration of the surface layer portion of the P-type first base layer 11 is higher than that of the P-type first base layer 11. A high P-type second base layer 12 is formed. An N + type source layer 13 is formed on the surface layer portion of the P type second base layer 12. A trench 14 is formed so as to penetrate the N + type source layer 13 and the P type first and second base layers 11 and 12 to reach the N− type drift layer 10, and gate insulation is formed on the inner wall surface of the trench 14. A film 15 and a gate layer 16 are sequentially formed, and a trench gate structure including the trench 14, the gate insulating film 15, and the gate layer 16 is configured.

  In the present embodiment, as shown in FIG. 2, the regions where the P-type second base layer 12 and the N + -type source layer 13 are formed and regions where they are not formed are alternately arranged between the trenches 14. It has become. Further, a part of the N + type source layer 13 and the trench gate structure are covered with an interlayer insulating film 17. This interlayer insulating film 17 is also covered by a region where only the P-type first base layer 11 is formed between the trenches 14. Therefore, as shown in FIG. 2, a part of the P-type second base layer 12 and the N + type source layer 13 is exposed from the pattern shape of the interlayer insulating film 17. In the present embodiment, this portion is called a contact hole 17a.

  A first surface electrode 18 is formed on the surface of the silicon substrate 10 so as to be in contact with the P-type second base layer 12 and the N + -type source layer 13 so as to straddle the plurality of trench gate structures. Are connected in common. A concave portion 18a corresponding to the shape of the contact hole 17a is formed on the surface of the first surface electrode 18 as described above.

  The first surface electrode 18 is made of a metal material made of an Al alloy mainly composed of Al, such as Al—Si—Cu, and is formed by sputtering, for example. In this embodiment, AlSi is adopted and the thickness is, for example, 5 μm or more.

  In the present embodiment, although not shown in FIG. 2, a barrier metal layer such as TiTiN is formed between the IGBT and the first surface electrode 18. This barrier metal layer is for preventing alloy spikes generated by heat treatment or the like when the first surface electrode 18 is formed.

  On the other hand, in the peripheral breakdown voltage portion, a P-type layer 19 formed on the surface layer portion of the N − -type drift layer 10, and a field formed on the P-type layer 19 via the LOCOS oxide film 20 and the interlayer insulating film 17. And a first inner peripheral withstand voltage electrode 21 as a plate. Further, an N + type layer 22 formed on the surface layer portion of the N − type drift layer 10 and an outer peripheral breakdown voltage electrode 23 as an outermost peripheral ring formed so as to be in contact with the N + type layer 22 are provided. These first inner peripheral withstand voltage electrode 21 and outer peripheral withstand voltage electrode 23 ensure a static element withstand voltage and reduce the electric field concentration generated inside the IGBT when a surge is applied to the semiconductor chip 1, thereby reducing the electric field strength. It can be lowered. For example, AlSi is used for the first inner peripheral breakdown voltage electrode 21 and the outer peripheral breakdown voltage electrode 23 as in the first surface electrode 18.

  Then, a protective film 24 covering the first surface electrode 18, the first inner peripheral breakdown voltage electrode 21, and the outer peripheral breakdown voltage electrode 23 is formed in the cell portion and the outer peripheral breakdown voltage portion, and the surfaces of the cell portion and the outer peripheral breakdown voltage portion are protected. Yes. As shown in FIG. 2, the protective film 24 is patterned so that a part of the first surface electrode 18 and the first inner peripheral breakdown voltage electrode 21 is exposed. In the present embodiment, for example, polyimide is used for the protective film 24.

  A portion of the protective film 24 where the first surface electrode 18 is exposed is formed with a second surface electrode 25, and a plating layer 26 is formed on the surface of the second surface electrode 25. Therefore, the first and second surface electrodes 18 and 25 and the plating layer 26 constitute an IGBT emitter electrode. Similarly, a second inner peripheral breakdown voltage electrode 27 is formed on a portion of the protective film 24 where the first inner peripheral breakdown voltage electrode 21 is exposed, and a plating layer 28 is formed on the surface of the second inner peripheral breakdown voltage electrode 27. Has been.

  In the present embodiment, the second surface electrode 25, the second inner peripheral withstand voltage electrode 27, and the plating layers 26 and 28 are each formed by a wet plating method. For example, Ni (nickel) is used for the second surface electrode 25 and the second inner peripheral breakdown voltage electrode 27, and Au (gold) is used for the plating layers 26 and 28, for example.

  The back surface structure of the semiconductor chip 1 is common to the cell portion and the outer peripheral pressure resistant portion, and an N + type layer 29 and a P + type layer 30 are sequentially formed on the back surface of the silicon substrate 10. The N + type layer 29 and the P + type layer 30 serve as a collector layer in which the IGBT functions as an FS (Field stop) type. With the N + type layer 29 and the P + type layer 30, the thickness of the silicon substrate 10 can be reduced, and characteristics such as on-voltage and breakdown voltage of the IGBT can be ensured.

  A first back electrode 31 is formed on the surface of the P + type layer 30 by sputtering, and a second back electrode 32 is formed on the surface of the first back electrode 31.

  The boundary between the first and second back electrodes 31 and 32 is bumpy as shown in FIG. This is because the heat treatment of the formed first back electrode 31 is not performed and the crystallinity is not densified. Therefore, when the first back electrode 31 is wet-etched, the surface of the first back electrode 31 is melted and removed. This is because irregularities were formed. Thus, the second back electrode 32 is formed on the surface of the first back electrode 31 whose surface is roughened by wet plating. As described above, since the surface of the first back electrode 31 has an uneven shape, the adhesion area of the second back electrode 32 to the first back electrode 31 can be increased and the adhesion can be improved.

  A plating layer 33 is formed on the surface of the second back electrode 32. The first and second back electrodes 31 and 32 and the plating layer 33 function as a collector electrode of the IGBT.

  In the present embodiment, AlSi is employed for the first back electrode 31. The second back electrode 32 and the plating layer 33 are formed by a wet plating method. For example, Ni is used for the second back electrode 32 and Au is used for the plating layer 33.

  The above is the configuration of the semiconductor chip 1 according to the present embodiment and the semiconductor package 100 using the same.

  Next, a method for manufacturing the semiconductor chip 1 described above will be described with reference to the process diagrams shown in FIGS. FIG. 3 is a diagram showing a flow of manufacturing steps for manufacturing the semiconductor chip 1. FIG. 4 is a diagram showing a manufacturing process. 4 is an enlarged view of the cell portion of the semiconductor chip 1 shown in FIG. In FIG. 4, the IGBT element is omitted.

  First, a wafer (N-type silicon substrate 10) grown by the FZ method is prepared, and a number of IGBTs are formed in the wafer. Although not shown in the manufacturing process diagram, the P-type first and second base layers 11 and 12 and the N + type source layer 13 are formed on the surface layer portion of the N− type drift layer 10. Then, a trench 14 is formed so as to penetrate the N + type source layer 13 and the P type first and second base layers 11 and 12 to reach the N − type drift layer 10, and gate insulation is formed on the inner wall surface of the trench 14. A film 15 and a gate layer 16 are formed. At this time, regions where the P-type second base layer 12 and the N + -type source layer 13 are formed and regions where they are not formed are alternately arranged between the trenches 14.

  Further, a part of the N + type source layer 13, the trench gate structure, and a region where only the P type first base layer 11 is formed between the trenches 14 are covered with an interlayer insulating film 17. The thickness of the wafer on which many such IGBTs are formed is about 650 μm. Each IGBT is partitioned by, for example, a scribe line.

  Hereinafter, it demonstrates along the flow of the manufacturing process shown by FIG.

  First, in the barrier metal layer forming step, a barrier metal layer such as TiTiN is formed on the entire surface of the wafer on which a number of IGBTs are formed. With this barrier metal layer, it is possible to prevent the occurrence of alloy spikes due to the heat treatment performed in the subsequent process.

  Next, in the metal film forming step, a metal film 40 is formed on the surface of the barrier metal layer by sputtering (see FIG. 4A). The metal film 40 becomes the first surface electrode 18, the first inner peripheral breakdown voltage electrode 21, and the outer peripheral breakdown voltage electrode 23. In the present embodiment, AlSi having a small film stress is deposited on the barrier metal layer as the metal film 40. When the metal film 40 is formed on the surface of the barrier metal layer in this manner, as shown in FIG. 4A, the surface of the metal film 40 has irregularities 30a corresponding to the shape of the base. That is, many irregularities 30 a corresponding to the shape of the contact hole 17 a made of the interlayer insulating film 17 are formed on the surface of the metal film 40. The sputtering of the metal film 40 is performed at a high temperature of about 300 to 500 ° C. Thereby, the unevenness | corrugation 30a can be made into the state relaxed comparatively rather than the recessed part shape of the contact hole 17a.

  Then, in the patterning step, the metal film 40 is patterned to form the first surface electrode 18, the first inner peripheral breakdown voltage electrode 21, and the outer peripheral breakdown voltage electrode 23. Specifically, a photoresist is applied to the surface of the metal film 40, and the photoresist is exposed and patterned so that the first surface electrode 18, the first inner peripheral breakdown voltage electrode 21, and the outer peripheral breakdown voltage electrode 23 are opened. . Then, the metal film 40 in the portion where the photoresist is opened is removed by etching, and the photoresist is removed. In the present embodiment, the first surface electrode 18 has a thickness of at least 5 μm.

  After patterning, heat treatment (sintering) is performed at about 200 to 500 ° C. in a heat treatment step. By performing this heat treatment, the surface of the first surface electrode 18 is planarized to make the recesses 18a relatively flat, and the first surface electrode 18 is densified, that is, the crystallinity of the first surface electrode 18 is improved. Let Note that the unevenness 30a does not become completely flat but remains as the recess 18a by this heat treatment, but this is not a problem. The role of the remaining recess 18a will be described in detail later.

  Subsequently, the wafer is thinned in a back surface back etch process. Specifically, a back grind tape or a support base is attached to the front surface of the wafer where the first surface electrode 18 or the like is formed, the wafer is turned over, and the back surface of the wafer is ground to a desired thickness by back grinding or etching. To do. In this embodiment, the wafer is shaved to a thickness of about 180 μm with an abrasive and further shaved to a thickness of about 150 μm with a chemical solution.

  Thereafter, an N + type layer 29 and a P + type layer 30 are formed on the back surface side of the wafer in a back surface ion implantation process. That is, for example, phosphorus that is an N-type impurity is ion-implanted, and boron that is a P-type impurity is ion-implanted, for example. Then, the back grind tape attached to the front side of the wafer is removed, and the wafer is annealed at 300 to 500 ° C. in order to activate it in the heat treatment step. In this way, the N + type layer 29 and the P + type layer 30 are formed.

  Next, the protective film 24 is formed in the protective film forming step. Specifically, the front and back of the wafer are reversed, a resin film is formed on the entire surface side of the wafer, and a photoresist is applied to the surface of the resin film. Then, the photoresist is exposed and patterned so that portions of the resin film where the second surface electrode 25 and the second inner peripheral breakdown voltage electrode 27 are formed are opened. Then, the resin film in the portion where the photoresist is opened is removed by etching, and the photoresist is removed. In the present embodiment, polyimide is used for the protective film 24 and the thickness thereof is 5 to 10 μm.

  Then, in the first back electrode forming step, the first back electrode 31 is formed on the back side of the wafer (see FIG. 4B). First, the front and back sides of the wafer are reversed again, and the first back electrode 31 is deposited on the surface of the P + type layer 30 on the back side of the wafer by sputtering. In the present embodiment, no heat treatment is performed on the first back electrode 31. This is because the surface of the first back electrode 31 formed as shown in FIG. 4B is flat because the back side of the wafer before the first back electrode 31 is formed is flat. This is because it is not necessary to perform planarization.

  Further, since the surface of the first back electrode 31 is dissolved and removed by the subsequent wet etching, a margin is given to the thickness of the first back electrode 31. In the present embodiment, the first back electrode 31 is formed with a thickness of 6 μm. Since the first back electrode 31 is made of AlSi having a low film stress like the first surface electrode 18, the first inner peripheral breakdown voltage electrode 21, and the outer peripheral breakdown voltage electrode 23, the wafer caused by the AlSi film stress is used. Can suppress warping.

  Subsequently, the front and back surfaces of the wafer are simultaneously wet etched in a double-sided wet etching process (see FIG. 4C). Thus, since the first surface electrode 18 is heat-treated and densified on the front surface side of the wafer, the surface unevenness does not become severe without being dissolved and removed by etching. On the other hand, since the heat treatment is not performed on the back surface side of the wafer after the first back electrode 31 is formed, unevenness is generated by melting and removing the surface of the first back electrode 31 by etching. In this way, unevenness is left on the surfaces of the electrodes 18 and 31 on the front and back surfaces of the wafer to ensure the surface area.

  As described above, the unevenness on the surface of the first surface electrode 18 on the wafer surface side and the unevenness on the surface of the first back electrode 31 on the wafer backside can be formed equally. That is, by adjusting the difference in the shape of the base on the front and back surfaces of the wafer by individual formation conditions such as heat treatment, the surface irregularities of the first front surface electrode 18 on the wafer front side and the first back surface electrode 31 on the rear surface side of the wafer are adjusted. The difference, that is, the surface area difference can be reduced.

  Thereafter, wet plating is simultaneously performed on the front and back surfaces of the wafer in a double-sided wet plating process (see FIG. 4D). Specifically, for example, Ni is plated on the front and back surfaces of the wafer at the same time. As a result, the second surface electrode 25 and the second inner peripheral breakdown voltage electrode 27 are formed on the wafer surface side, and the second back electrode 32 is formed on the wafer back surface side. Ni is a substance having a large film stress, but by simultaneously plating the front and back surfaces of the wafer, the film stress generated on the electrodes 25 and 32 on the front and back surfaces of the wafer can be offset, and the warpage of the wafer can be suppressed. Can do. In the present embodiment, the second surface electrode 25 and the second back electrode 32 are formed to have a thickness of 5 μm.

  Further, since the concave portion 18a is left on the surface of the first surface electrode 18 on the wafer surface side, the adhesion of the second surface electrode 25 to the first surface electrode 18 can be ensured. Similarly, since the unevenness is formed on the first back electrode 31 by etching on the back surface side of the wafer, the adhesion of the second back electrode 32 to the first back electrode 31 can be secured. In the present embodiment, as described above, since the surface area of the first surface electrode 18 and the first back electrode 31 is substantially the same, the adhesion of the second surface electrode 25 to the first surface electrode 18 and the first back electrode It can be said that the adhesion of the second back electrode 32 to the electrode 31 is equivalent to each other.

  Then, wet plating is simultaneously performed on the front and back surfaces of the wafer to form plated layers 26, 28, and 33. That is, for example, Au plating layers 26, 28, and 33 are formed on the surface of the second surface electrode 25, the second inner peripheral breakdown voltage electrode 27, and the surface of the second back electrode 32, respectively. Thus, by simultaneously forming the plating layers 26, 28, and 33 on the front and back surfaces of the wafer, the film stresses generated on the plating layers 26, 28, and 33 can be offset on the front and back surfaces of the wafer, and the warpage of the wafer is eventually achieved. Can be suppressed.

  Thereafter, the wafer is diced along a scribe line and divided into individual semiconductor chips 1. Then, the heat sinks 2 and 3 are joined to the front and back surfaces of the semiconductor chip 1 via the solder 7, the gate electrode pad of the semiconductor chip 1 and the lead terminal 4 are connected by the gate wire 6 and molded with the resin 5, The semiconductor package 100 shown in FIG. 1 is completed.

  As shown in FIG. 1, when the semiconductor chip 1 is assembled as a semiconductor package 100, heat sinks 2 and 3 are soldered to the front and back surfaces of the semiconductor chip 1. Even if a stress such as a thermal cycle is applied to the semiconductor package 100 in such a state, as described above, the second surface electrode 25 and the second back electrode 32 in the semiconductor chip 1 have the same adhesion and the first surface, respectively. Adhesion strength is high because it is bonded to the electrode 18 and the first back electrode 31, and the peeling of the second surface electrode 25 or the second back electrode 32 and the destruction of the silicon substrate 10 due to the difference in adhesion are prevented. Can do.

  Further, since the warpage of the wafer is suppressed during the manufacturing process, crystal defects of the silicon substrate 10 can be suppressed, and the reliability of the IGBT element can be ensured.

  As described above, the present embodiment is characterized in that the surfaces of the first front surface electrode 18 and the first back surface electrode 31 are each uneven. Thereby, the contact | adherence area of the 2nd surface electrode 25 with respect to the 1st surface electrode 18 can be increased by several recessed part, and the contact | adhesion power of the 1st surface electrode 18 and the 2nd surface electrode 25 can be improved. Similarly, the contact area of the second back electrode 32 with respect to the first back electrode 31 can be increased by a bumpy shape, and the adhesion between the first back electrode 31 and the second back electrode 32 can be improved.

  Further, the second surface electrode 25 and the second back electrode 32 made of the same material are simultaneously formed on the respective surfaces of the first surface electrode 18 and the first back electrode 31 by a wet plating method. Thereby, the film stress generated when the second surface electrode 25 and the second back electrode 32 are formed on the front and back surfaces of the semiconductor substrate 10 can be offset when the electrodes 25 and 32 are formed. Therefore, warpage of the semiconductor substrate 10 can be suppressed.

  Thus, since the 2nd surface electrode 25 and the 2nd back electrode 32 are formed simultaneously by the method of wet plating, compared with the case where each electrode is formed using a resist, manufacturing process and manufacturing cost are reduced. Can do.

  Further, the difference in surface area between the first surface electrode 18 and the first back electrode 31 is reduced. Thereby, the difference between the adhesion of the second surface electrode 25 to the first surface electrode 18 and the adhesion of the second back electrode 32 to the first back electrode 31 can be reduced. Accordingly, the forces applied to the electrodes 25 and 32 on the front and back surfaces of the semiconductor substrate 10 are equalized, and it is possible to prevent one electrode from being peeled off due to the difference in adhesion.

  In this embodiment, the etching of the first surface electrode 18 and the first back electrode 31 and the film formation of the second surface electrode 25 and the second back electrode 32 are continuously performed by a wet process. Thereby, the adhesion reliability of each of the interfaces of the first and second surface electrodes 18 and 25 and the interfaces of the first and second back electrodes 31 and 32 can be increased, and the plating layers 26, 28, and 33 are formed. It can be carried out continuously by wet processing. That is, these series of processes can be performed with the same equipment. Further, since the front and back surfaces of the wafer can be simultaneously processed in batch mode, the semiconductor chip 1 can be manufactured efficiently and at low cost.

(Other embodiments)
In the above embodiment, an FS type IGBT having a trench gate structure is described as an example of a semiconductor element. However, any semiconductor element having a metal film (electrode) on the front and back surfaces can be applied, and a power MOS can be used as the semiconductor element. A vertical power element such as the above may be adopted. Further, the gate structure of the semiconductor element may be any structure such as a planar structure, a concave structure, a T gate structure, an I gate structure, etc. in addition to the trench gate structure shown in the above embodiment.

  The thickness of the semiconductor chip 1 is not limited to the example of the above embodiment, and can be freely designed within a range of, for example, 50 to 200 μm. In such a case, the wafer can be thinned by etching the wafer or polishing with an abrasive as in the above embodiment.

  In the above-described embodiment, the silicon substrate 10 is used as the semiconductor substrate, but other substrates may be used as long as they can form semiconductor elements.

  In the above embodiment, the first back electrode 31 is deposited and then wet etching is performed. However, the first back electrode 31 may be subjected to heat treatment. In such a case, the heat treatment as much as the front surface side of the wafer is not performed, and the crystallinity of the first back electrode 31 is not improved. Thereby, unevenness | corrugation can be formed in the surface of the 1st back surface electrode 31 by wet etching.

  In the above embodiment, the example in which the semiconductor chip 1 is sandwiched between the heat sinks 2 and 3 and molded with the resin 5 has been described. However, this is an example, and other mounting forms may be used. That is, the heat sink may be connected to only one surface of the semiconductor chip 1.

  The mounting form of the semiconductor chip 1 is not limited to the double-sided soldering mold, but is mounted on a lead frame, a heat sink, a printed board, a ceramic board, etc. by soldering, wire bonding, solder bumps, etc. on the front and back surfaces. It can be applied to the structure.

  5 and 6 are schematic sectional views showing examples of the mounting form of the semiconductor chip 1. In addition, the same code | symbol is attached | subjected in the figure to the part which is mutually the same or equivalent to what was used for the said embodiment.

  5A, the semiconductor chip 1 is mounted on the substrate 50 via the solder 7, and the semiconductor chip 1 and the circuit in the substrate 50 are connected by a wire 60 (which may be a ribbon or a tape). It is.

  5B, the back surface side of the semiconductor chip 1 and the substrate 50 are connected by the solder 7, and the heat sink 3 is joined to the front surface side of the semiconductor chip 1 via the solder 7. 1 and a circuit in the substrate 50 are connected by a wire 60.

  5C, the back surface side of the semiconductor chip 1 and the substrate 50 are connected by the solder 7, and the front surface side of the semiconductor chip 1 and the lead frame 70 are connected by the solder 7. The semiconductor chip 1 is covered at 70. The end of the lead frame 70 is electrically connected to the circuit in the substrate 50 as shown in FIG.

  5D, the back surface side of the semiconductor chip 1 and the substrate 50 are connected by the solder 7, and the front surface side of the semiconductor chip 1 and one end side of the lead frame 71 are connected by the solder 7. In the mounting form shown in FIG. The other end side of the lead frame 71 is electrically connected to the circuit in the substrate 50, and the semiconductor chip 1 and the circuit in the substrate 50 are connected by the wire 60.

  6A, the back surface side of the semiconductor chip 1 and the substrate 50 are connected by solder bumps 80, and the front surface side of the semiconductor chip 1 and the heat sink 3 are connected by solder 7. Further, the mounting form shown in FIG. 6B is obtained by connecting the back surface side of the semiconductor chip 1 and the substrate 50 with solder bumps 80 in the example shown in FIG. 5C.

  6C is obtained by connecting the back surface side of the semiconductor chip 1 and the substrate 50 with solder bumps 80 in the example shown in FIG. 5D. Further, in the mounting form shown in FIG. 6D, the back surface side of the semiconductor chip 1 and the substrate 5 are connected by solder bumps 80, and the front surface side of the semiconductor chip 1 and another substrate 51 (or the heat sink 3, REIT) Frame 71 or the like) may be connected by solder bumps 80.

  The mounting form described above is an example, and each of the examples shown in FIGS. 5 and 6 may be molded with resin.

  In each example shown in FIGS. 5 and 6 also, the adhesion of the second surface electrode 25 to the first surface electrode 18 on the front surface side of the semiconductor chip 1 and the second back surface to the first back electrode 31 on the back surface side. Since the adhesion strength of the electrode 32 is equivalent, the solder 7 and the solder bump 80 are unlikely to peel off on the front and back surfaces of the semiconductor chip 1 during mounting.

  Further, since there is almost no warping of the semiconductor chip 1, it is possible to reduce the influence of distortion and the like caused by the substrates 50 and 51 and the lead frames 70 and 71 connected via the solder 7.

It is a schematic sectional drawing which shows the semiconductor package using the semiconductor chip as a semiconductor device concerning one Embodiment of this invention. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It is the figure which showed the flow of the manufacturing process for manufacturing a semiconductor chip. It is the figure which showed the manufacturing process. In other embodiment, it is the figure which showed the example of the mounting form of the semiconductor chip in the cross section. FIG. 6 is a cross-sectional view showing an example of a mounting form of a semiconductor chip in another embodiment, similarly to FIG. 5.

Explanation of symbols

100 ... Semiconductor package, 1 ... Semiconductor chip, 2, 3 ... Heat sink,
4 ... Lead terminal, 5 ... Resin, 6 ... Gate wire, 7 ... Solder,
10 ... Silicon substrate (N-type drift layer), 17 ... Interlayer insulating film,
17a ... contact hole, 18 ... first surface electrode, 18a ... concave,
25 ... 2nd surface electrode, 26, 28, 33 ... Plating layer, 31 ... 1st back surface electrode,
32: Second back electrode.

Claims (6)

A semiconductor substrate (10) on which a semiconductor element is formed;
An interlayer insulating film (17) formed on the surface of the semiconductor substrate and provided with a plurality of contact holes (17a) partially opened;
A first surface electrode (18) formed so as to cover the interlayer insulating film and the contact hole, and a second surface electrode (25) formed on the surface of the first surface electrode;
A first back electrode (31) formed on the back surface of the semiconductor substrate; and a second back electrode (32) formed on the surface of the first back electrode and made of the same material as the second surface electrode. ,
The surface of the first back electrode is bumpy, and the surface of the first surface electrode is provided with a plurality of recesses (18a) corresponding to the shape of the contact hole, thereby reducing the surface area of the first surface electrode. surface area of the first back electrode are the same,
The semiconductor device, wherein the second surface electrode and the second back electrode are formed simultaneously on the surfaces of the first surface electrode and the first back electrode, respectively. 2. The semiconductor device according to claim 1, wherein the second front electrode and the second back electrode are simultaneously formed by a wet plating method. A semiconductor substrate (10) on which a semiconductor element is formed;
An interlayer insulating film (17) formed on the surface of the semiconductor substrate and provided with a plurality of contact holes (17a) so that a part of the semiconductor substrate is exposed;
A first surface electrode (18) formed so as to cover the interlayer insulating film and the contact hole, and a second surface electrode (25) formed on the surface of the first surface electrode;
A first back electrode (31) formed on the back surface of the semiconductor substrate, and a second back electrode (32) formed on the surface of the first back electrode and made of the same material as the second surface electrode. A device manufacturing method comprising:
Preparing a semiconductor substrate on which a semiconductor element is formed, and forming the interlayer insulating film including a plurality of the contact holes in which a part of the surface of the semiconductor substrate is exposed on the surface of the semiconductor substrate;
Forming a metal film (40) so as to cover the interlayer insulating film and the contact hole;
Patterning the metal film to form a first surface electrode (18);
Heat-treating the first surface electrode to form a plurality of recesses (18a) corresponding to the shape of the contact hole on the surface of the first surface electrode;
Forming a first back electrode (31) on the back surface of the semiconductor substrate;
The first surface electrode that has been heat-treated and densified and the first back electrode that has not been densified are wet-etched at the same time, so that the bumps of the first surface electrode are bumped by the recesses without increasing the bumps. a step going on the first surface electrode and the surface area is to form the uneven by melting manner, the surface of the first back electrode is the same,
Simultaneously forming a second surface electrode (25) on the surface of the first surface electrode and a second back electrode (32) of the same material as the second surface electrode on the surface of the first back electrode; A method for manufacturing a semiconductor device, comprising: 4. The semiconductor according to claim 3, wherein in the step of simultaneously forming the second surface electrode and the second back electrode, the second surface electrode and the second back electrode are simultaneously formed by a wet plating method. 5. Device manufacturing method. 5. The method of manufacturing a semiconductor device according to claim 3, wherein in the step of etching the surface of the first back electrode, the surface of the first surface electrode is also etched simultaneously with the first back electrode. 6. The method of manufacturing a semiconductor device according to claim 3, wherein in the step of preparing the semiconductor substrate, an FZ crystal grown by an FZ method is prepared as a semiconductor substrate.

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