JP2021007182A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

To obtain a semiconductor device and a manufacturing method thereof that can improve the yield during assembly and the uniformity of thermal resistance after assembly.SOLUTION: A semiconductor substrate (1) has a front surface and a back surface facing each other. A gate wiring (2) and first and second surface electrodes (3, 4) are formed on the surface of the semiconductor substrate (1). The first and second surface electrodes (3, 4) are separated from each other by the gate wiring (2). An insulating film (7) covers the gate wiring (2). An electrode layer (8) that is not divided by wiring is formed on the insulating film (7) and the first and second surface electrodes (3, 4) across the gate wiring (2). A back electrode (9) is formed on the back surface of the semiconductor substrate (1). A first plated electrode (10) that is not divided by wiring is formed on the electrode layer (8). A second plated electrode (11) is formed on the back electrode (9).SELECTED DRAWING: Figure 2

Description

The present invention relates to a semiconductor device and a method for manufacturing the same.

A method for manufacturing a semiconductor device in which electrodes are simultaneously formed on both surfaces of a semiconductor substrate by a plating method is disclosed (see, for example, Patent Document 1). Further, in order to realize uniform operation, the electrodes on the surface of the semiconductor substrate are divided on the comb teeth by the gate wiring (see, for example, Patent Document 2). On the other hand, the electrodes on the back surface of the semiconductor substrate generally have the same shape as the semiconductor substrate.

JP-A-2007-5368 JP-A-2003-92406

In the conventional semiconductor device, the shape of the electrode is different between the front surface and the back surface of the semiconductor substrate. Therefore, when the same quality plating electrodes are formed on both sides of the semiconductor substrate by the wet plating method, the film stress of the plating electrodes differs between the front surface and the back surface. As a result, there are problems that the semiconductor substrate is warped convexly toward the surface side, the yield at the time of assembling the semiconductor device is lowered, and the thermal resistance after the assembly becomes non-uniform.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device capable of improving the yield during assembly and the uniformity of thermal resistance after assembly and a method for manufacturing the same. Is.

The semiconductor device according to the present invention is formed on a semiconductor substrate having a front surface and a back surface facing each other, a gate wiring formed on the front surface of the semiconductor substrate, and the front surface of the semiconductor substrate, and is divided into each other by the gate wiring. It is formed on the first and second surface electrodes, the insulating film covering the gate wiring, the insulating film and the first and second surface electrodes straddling the gate wiring, and is divided by the wiring. An electrode layer that is not formed, a back electrode formed on the back surface of the semiconductor substrate, a first plated electrode formed on the electrode layer and not divided by wiring, and a back surface electrode formed on the back surface electrode. It is characterized by including a second plating electrode.

In the present invention, an electrode layer is formed on the first and second surface electrodes separated from each other by the gate wiring, and the first and second plated electrodes are formed on the electrode layer and the back surface electrode, respectively. .. As a result, the electrode shapes on both sides of the semiconductor substrate come close to each other, so that the film stress difference between the electrodes on both sides is reduced, and the warp of the semiconductor substrate is reduced. As a result, it is possible to improve the yield at the time of assembling the semiconductor device and the uniformity of the thermal resistance after the assembly.

It is a top view which shows the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which follows I-II of FIG. It is a top view which shows the semiconductor package which used the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which follows I-II of FIG. It is a top view which shows the semiconductor device which concerns on a comparative example. FIG. 5 is a cross-sectional view taken along the line I-II of FIG. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 2 of this invention.

The semiconductor device and the manufacturing method thereof according to the embodiment of the present invention will be described with reference to the drawings. The same or corresponding components may be designated by the same reference numerals and the description may be omitted.

Embodiment 1.
FIG. 1 is a plan view showing a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line I-II of FIG. This semiconductor device is a power semiconductor device such as an IGBT or MOSFET.

The semiconductor substrate 1 has a front surface and a back surface facing each other. The gate wiring 2 and the surface electrodes 3 and 4 are formed on the surface of the semiconductor substrate 1. In order to operate the semiconductor device uniformly, the surface electrodes 3 and 4 are separated from each other by the gate wiring 2 and partially connected to each other. The gate wiring 2 has a pad 5 for striking a control wire.

A plurality of terminal structure wirings 6 are formed in the terminal region of the semiconductor substrate 1 in order to maintain the withstand voltage of the semiconductor device. The terminal structure wiring 6 has a withstand voltage holding structure such as a guard ring, and is composed of a plurality of wirings. The gate wiring 2, the surface electrodes 3 and 4, and the terminal structure wiring 6 are formed uniformly by, for example, a vapor phase deposition method such as a sputtering method using aluminum as the main material, and are separated and desired by a photoengraving process and an etching process, respectively. It is patterned in the shape of.

The insulating film 7 covers the gate wiring 2. The insulating film 7 can be formed, for example, using a silicon nitride film as a main material. The insulating film 7 is patterned into a desired shape by, for example, depositing a silicon nitride film and then undergoing a photoplate making step and an etching step. The electrode layer 8 straddles the gate wiring 2 and is formed on the insulating film 7 and the surface electrodes 3 and 4.

The back surface electrode 9 is formed on the back surface of the semiconductor substrate 1. The back electrode 9 has the same size as the outer shape of the semiconductor substrate 1. The plating electrode 10 is formed on the electrode layer 8, and the plating electrode 11 is formed on the back surface electrode 9. The thickness and material of the plating electrodes 10 and 11 are the same.

FIG. 3 is a plan view showing a semiconductor package using the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view taken along the line I-II of FIG. The lead frame 12 is bonded to the plating electrode 10 by a bonding material 13 and is electrically and mechanically connected. The conductor substrate 14 is bonded to the plating electrode 11 by the bonding material 15 and is electrically and mechanically connected. The joining materials 13 and 15 are, for example, solders mainly made of tin, which can be easily joined. The pad 5 and the external signal terminal are connected by, for example, a wire made of aluminum as a main material.

The joining material 13 is formed in a region avoiding the gate wiring 2. Therefore, it is possible to prevent the gate wiring 2 from being damaged and short-circuited with the peripheral electrodes due to the stress from the bonding material 13 being applied to the gate wiring 2 during the cooling / heating cycle. On the other hand, the bonding material 15 on the back surface of the semiconductor substrate 1 is formed in the same shape as the semiconductor substrate 1 in order to make it as large as possible. As a result, the heat generated from the semiconductor device can be efficiently dissipated to the conductor substrate 14.

The coating film 16 covers the outer periphery of the solder joint region of the plating electrode 10. Therefore, it is possible to prevent the solder from spreading more than expected on the upper surface of the plating electrode 10. As a result, it is possible to prevent a short circuit with other members and improve the yield and reliability. If the coating film 16 is a material containing polyimide, solder wetting can be reliably prevented. The coating film 16 can be formed by drawing and applying a polyimide precursor solution to a desired shape on the plating electrode 10 and then curing the coating film 16.

The sealing material 17 covers at least a part of the semiconductor substrate 1, the bonding materials 13, 15, the lead frame 12, the conductor substrate 14, and the like. As a result, electrical loss can be reduced and a highly reliable semiconductor device can be realized. The sealing material 17 is, for example, a potting resin or a transfer mold resin.

Subsequently, a method of manufacturing the semiconductor device according to the present embodiment will be described. A gate wiring 2 and surface electrodes 3 and 4 separated from each other by the gate wiring 2 are formed on the surface of the semiconductor substrate 1. An insulating film 7 that covers the gate wiring 2 is formed. An electrode layer 8 is formed on the insulating film 7 and the surface electrodes 3 and 4 so as to straddle the gate wiring 2. The back surface electrode 9 is formed on the back surface of the semiconductor substrate 1.

A plating electrode 10 is formed on the electrode layer 8, a pad 5 is formed on the opened portion of the gate wiring 2, and a plating electrode 11 is formed on the back surface electrode 9 by a wet plating method. By forming these at the same time, the process cost of the plating process can be suppressed. Further, since they are formed at the same time, the thickness and material of the plating electrodes 10 and 11 and the pad 5 are the same.

The plating electrodes 10 and 11 and the pad 5 are made of, for example, nickel as the main material, and can be formed by a process using a zincate treatment. Since it is desirable that the plating electrodes 10 and 11 remain even after solder bonding, it is desirable that the thickness of the plating electrodes 10 and 11 is 1 μm or more. The thickness of the plating electrodes 10 and 11 is preferably 10 μm or less in order to suppress an increase in the process cost of the plating process and secure the yield of the dicing process.

The electrode layer 8 can be formed of, for example, aluminum as the main material. When the gate wiring 2 and the electrode layer 8 are formed of the same material such as aluminum, the electrode layer 8 may be patterned by a process other than the process of etching aluminum in order to prevent the pad 5 of the gate wiring 2 from being etched. desirable. For example, the electrode layer 8 is vaporly deposited through an organic resist film having an opening in the electrode layer forming region by a sputtering method or the like, and then a stripping solution for dissolving the organic resist is sprayed to the electrode layer 8 on the organic resist. The electrode layer 8 is patterned by a lift-off method that selectively removes only. Alternatively, the electrode layer 8 may be patterned by vapor-phase depositing the electrode layer 8 through a mask having an opening in the electrode layer forming region by a sputtering method or the like. As a result, patterning can be easily performed and damage to the surface electrodes 3 and 4 can be reduced.

Further, a pattern is formed by ejecting and drawing a polyimide precursor solution on the plating electrode 10, and a coating film 16 is formed by curing. Thereby, the coating film 16 can be easily patterned without photoengraving.

Subsequently, the effects of the present embodiment will be described in comparison with the comparative examples. FIG. 5 is a plan view showing a semiconductor device according to a comparative example. FIG. 6 is a cross-sectional view taken along the line I-II of FIG. In the comparative example, the shapes of the plating electrodes 10a and 10b on the front surface of the semiconductor substrate 1 and the plating electrodes 11 on the back surface are different. Therefore, there are problems that the semiconductor substrate 1 is warped convexly toward the surface side, the yield at the time of assembling the semiconductor device is lowered, and the thermal resistance after the assembly becomes non-uniform.

On the other hand, in the present embodiment, the electrode layer 8 is formed on the front surface electrodes 3 and 4 separated from each other by the gate wiring 2, and the plated electrodes 10 and 11 are formed on the electrode layer 8 and the back surface electrode 9, respectively. ing. As a result, the electrode shapes on both sides of the semiconductor substrate 1 come close to each other, so that the film stress difference between the electrodes on both sides is reduced, and the warpage of the semiconductor substrate is reduced. As a result, it is possible to improve the yield at the time of assembling the semiconductor device and the uniformity of the thermal resistance after the assembly.

The terminal structure wiring 6 has the same thickness as the surface electrodes 3 and 4 because it is formed by the same process as the surface electrodes 3 and 4 and is patterned by a processing process such as etching. Therefore, when the surface electrodes 3 and 4 are thickened, the terminal structure wiring 6 is also thickened. When the end structure wiring 6 becomes thick, the stress received from the sealing material or the like increases, so that the reliability decreases. Therefore, by not forming the electrode layer 8 in the terminal region, it is possible to prevent the terminal structure wiring 6 from being thickened more than necessary.

Further, since the terminal structure wiring 6 bears the electric field sharing and does not carry a large current, it is not necessary to thicken the film and lower the resistance value. On the other hand, it is desirable to make the surface electrodes 3 and 4 as thick as possible in order to cope with the energization of a large current and to alleviate the stress generated by the expansion and contraction of the solder. According to this embodiment, the thickness of the electrode can be increased while suppressing the thickness of the terminal structure wiring 6, so that a more reliable semiconductor device can be formed. For example, the thickness of the surface electrodes 3 and 4 and the terminal structure wiring 6 is designed to be 1.5 μm or less, and the total thickness of the surface electrodes 3 and 4 and the electrode layer 8 is designed to be 3 μm or more.

The insulating film 7 is also provided between the surface electrodes 3 and 4 and the electrode layer 8. Therefore, even when the semiconductor device receives stress from the outside, it is possible to prevent damage such as wiring cracks from reaching the surface electrodes 3 and 4.

A plurality of through holes are provided in the insulating film 7, and the surface electrodes 3 and 4 and the electrode layer 8 are mechanically and electrically connected through the plurality of through holes. On the other hand, an opening is provided in the insulating film 7 on the pad 5 of the gate wiring 2. The other portion of the gate wiring 2 is covered with the insulating film 7, and the insulating property between the gate wiring 2 and the surface electrodes 3 and 4 is ensured.

The insulating film 7 covers the plurality of terminal structure wirings 6 to equalize the electric field distribution among the plurality of terminal structure wirings 6. That is, the insulating film 7 is a protective film that protects the terminal region and extends to the operating cell region. By sharing the insulating film 7 and the protective film in this way, the insulating film 7 can be formed without an additional processing process.

The thickness of the surface electrodes 3 and 4 and the terminal structure wiring 6 is thinner than the thickness of the electrode layer 8. As a result, it is possible to secure the electrode thickness on the operating cell that contributes to the solder bondability and the wire bondability while ensuring the reliability of the terminal structure, and it is possible to improve the reliability and productivity.

The front electrode 3 and 4 and the back electrode 9 are made of a material containing aluminum. Therefore, it can be easily formed and processed as an electrode of a semiconductor device, has low electrical resistance when energized, and can form a mechanically stable bonding interface.

The electrode layer 8 is made of a material containing aluminum. Therefore, the plating electrode 10 can be easily formed, the electrical resistance when energized is low, and a mechanically stable bonding interface with the surface electrodes 3 and 4 made of a material containing aluminum can be obtained. Further, since the material is the same as that of the back surface electrode 9, the plating electrodes 10 and 11 can be easily formed by a wet plating method. Further, the insulating film 7 contains silicon nitride. Since silicon nitride functions as a protective film and is compatible with the aluminum of the surface electrodes 3 and 4, it is possible to obtain an electrically and mechanically stable structure.

Since the plating electrodes 10 and 11 contain nickel or copper, they can be easily bonded to the solder to form an electrically and mechanically stable bonding interface. Further, it is desirable that a material containing gold is formed on the outermost surfaces of the plating electrodes 10 and 11. As a result, it is possible to prevent the underlying solder bonding electrode from being oxidized and the solder wettability from being lowered before the solder is bonded.

Further, the conductor substrate 14 may be bonded to the plating electrode 11 by sintering fine particles using Ag as a main material. However, when fine particles composed of Ag as a main material are sintered and bonded, it is common to pressurize the semiconductor substrate 1 for bonding. However, the semiconductor substrate 1 may be damaged due to the stress generated when the semiconductor substrate 1 is bent by the external pressure or the friction with the external jig. On the other hand, in the present embodiment, since the warping of the semiconductor substrate 1 can be eliminated, the damage generated in the semiconductor substrate 1 at the time of pressurization can be reduced.

Embodiment 2.
FIG. 7 is a cross-sectional view showing a semiconductor device according to the second embodiment of the present invention. An organic film 18 is formed on the insulating film 7. As a result, it is possible to prevent the gate wiring 2 from short-circuiting with the surface electrodes 3 and 4 or the electrode layer 8 due to stress during the thermal cycle.

It is desirable that the organic film 18 has the same shape as the insulating film 7 and overlaps the insulating film 7. It is desirable to secure an overlap amount of 10 μm or more in consideration of halation and overlay accuracy during photoengraving. If the organic film 18 contains polyimide, it can be easily formed and processed as an insulating film of a semiconductor device.

The semiconductor substrate 1 is not limited to the one formed of silicon, and may be formed of a wide bandgap semiconductor having a larger bandgap than silicon. The wide bandgap semiconductor is, for example, silicon carbide, gallium nitride based material, or diamond. A semiconductor device formed of such a wide bandgap semiconductor substrate can be miniaturized because of its high withstand voltage resistance and high allowable current density. By using this miniaturized element, the semiconductor module incorporating this device can also be miniaturized. Further, since the heat resistance of the device is high, the heat radiation fins of the heat sink can be miniaturized, so that the semiconductor module can be further miniaturized. Further, since the power loss of the element is low and the efficiency is high, the efficiency of the semiconductor module can be improved.

1 Semiconductor substrate, 2 gate wiring, 3, 4 front electrode, 5 pad, 6 terminal structure wiring, 7 insulating film, 8 electrode layer, 9 back electrode, 10, 11 plated electrode, 12 lead frame, 13, 15 bonding material, 14 Conductor substrate, 16 Coating film, 17 Encapsulant, 18 Organic film

Claims (25)

A semiconductor substrate having front and back surfaces facing each other,
With the gate wiring formed on the surface of the semiconductor substrate,
The first and second surface electrodes formed on the surface of the semiconductor substrate and separated from each other by the gate wiring,
The insulating film covering the gate wiring and
An electrode layer formed on the insulating film and the first and second surface electrodes straddling the gate wiring and not divided by the wiring.
A back electrode formed on the back surface of the semiconductor substrate and
A first plated electrode formed on the electrode layer and not divided by wiring,
A semiconductor device including a second plating electrode formed on the back surface electrode. The semiconductor device according to claim 1, wherein the thickness and material of the first and second plating electrodes are the same as each other. The semiconductor device according to claim 1 or 2, wherein the thickness of the first and second plating electrodes is 1 μm or more and 10 μm or less. The insulating film is also provided between the first and second surface electrodes and the electrode layer.
The insulating film is provided with a plurality of through holes.
The semiconductor according to any one of claims 1 to 3, wherein the first and second surface electrodes and the electrode layer are mechanically and electrically connected through the plurality of through holes. apparatus. The semiconductor device according to any one of claims 1 to 4, wherein the insulating film is a protective film that protects a terminal region and extends to an operating cell region. A terminal structure wiring formed on the surface of the semiconductor substrate in the terminal region and having the same thickness as the first and second surface electrodes is provided.
The semiconductor device according to any one of claims 1 to 5, wherein the electrode layer is not formed in the terminal region. The semiconductor device according to claim 6, wherein the thickness of the first and second surface electrodes and the terminal structure wiring is thinner than the thickness of the electrode layer. A lead frame bonded to the first plating electrode by a first bonding material, and
A conductor substrate bonded to the second plating electrode by a second bonding material,
The semiconductor device according to any one of claims 1 to 7, further comprising the semiconductor substrate, the lead frame, and a sealing material that covers at least a part of the conductor substrate. The semiconductor device according to claim 8, wherein the first bonding material is formed in a region avoiding the gate wiring. The semiconductor device according to claim 8 or 9, wherein the first and second bonding materials contain tin. The semiconductor device according to any one of claims 1 to 10, further comprising a coating film that covers the outer periphery of the solder joint region of the first plating electrode. The semiconductor device according to claim 11, wherein the coating film contains polyimide. The semiconductor device according to any one of claims 1 to 12, further comprising an organic film formed on the insulating film. The semiconductor device according to claim 13, wherein the organic film contains polyimide. The semiconductor device according to any one of claims 1 to 14, wherein the first and second front electrode and the back electrode are made of a material containing aluminum. The semiconductor device according to any one of claims 1 to 15, wherein the electrode layer is made of a material containing aluminum. The semiconductor device according to any one of claims 1 to 16, wherein the insulating film contains silicon nitride. The semiconductor device according to any one of claims 1 to 17, wherein the first and second plated electrodes contain nickel or copper. The semiconductor device according to any one of claims 1 to 18, wherein a material containing gold is formed on the outermost surfaces of the first and second plating electrodes. The semiconductor device according to any one of claims 1 to 19, wherein the semiconductor substrate is formed of a wide bandgap semiconductor. A step of forming a gate wiring and first and second surface electrodes separated from each other by the gate wiring on the surface of the semiconductor substrate.
The process of forming an insulating film covering the gate wiring and
A step of forming an electrode layer that is not divided by wiring on the insulating film and the first and second surface electrodes across the gate wiring, and
The process of forming the back electrode on the back surface of the semiconductor substrate and
Manufacture of a semiconductor device comprising a step of simultaneously forming a first plating electrode which is not divided by wiring on the electrode layer and a second plating electrode on the back surface electrode by a plating method. Method. The method for manufacturing a semiconductor device according to claim 21, wherein the electrode layer is patterned by a lift-off method. The method for manufacturing a semiconductor device according to claim 21, wherein the electrode layer is patterned by depositing the electrode layer through a mask having an opening in the electrode layer forming region. The method for manufacturing a semiconductor device according to any one of claims 21 to 23, wherein the conductor substrate is bonded to the second plating electrode by sintering fine particles composed of a main material of Ag. A pattern is formed by ejecting and drawing the polyimide precursor solution on the first plating electrode, and by curing, a coating film covering the outer periphery of the solder joint region of the first plating electrode is formed. The method for manufacturing a semiconductor device according to any one of claims 21 to 24.

Images