JP2011249438A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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JP2011249438A
JP2011249438A JP2010118970A JP2010118970A JP2011249438A JP 2011249438 A JP2011249438 A JP 2011249438A JP 2010118970 A JP2010118970 A JP 2010118970A JP 2010118970 A JP2010118970 A JP 2010118970A JP 2011249438 A JP2011249438 A JP 2011249438A
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layer
etching
emitter
forming
aluminum layer
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JP5548519B2 (en
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Keisuke Shiba
敬祐 芝
Shinnosuke Sato
進之介 佐藤
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Honda Motor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Die Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which an emitter and a gate finger electrode having a desired thickness can be formed without requiring exact control of etching thickness in the etching of a pressure-contact IGBT having an emitter and a gate finger electrode consisting of an extremely thin metal film.SOLUTION: The method for manufacturing a semiconductor device used in a pressure-contact semiconductor includes: a step for forming a first Al layer on an Si substrate; a step for etching a part of the first Al layer so that an emitter electrode and a gate finger electrode having a desired shape can be obtained; a step for forming an underlying layer consisting of a metal other than Al on the first Al layer; a step for forming a second Al layer on the underlying layer; a step for coating a part of the second Al layer corresponding to the emitter electrode with resist; a step for etching the second Al layer other than the part coated with resist; a step for etching the underlying layer other than the part coated with resist; and a step for removing the resist.

Description

本発明は、圧接型の半導体装置の製造方法に係り、特に、半導体素子の主電極に対して安定した加圧接触ができる領域と、加圧接触しない領域との間の段差を形成する方法に関する。   The present invention relates to a method of manufacturing a pressure contact type semiconductor device, and more particularly, to a method of forming a step between a region where stable pressure contact can be made with respect to a main electrode of a semiconductor element and a region where pressure contact is not performed. .

半導体素子の一種である絶縁ゲートバイポーラトランジスタ（以下、ＩＧＢＴと略称する）は、主に電力制御の用途に使用されており、装置の電流容量を増加させるために、ＩＧＢＴ素子を多数積層することが要求されているが、ＩＧＢＴモジュールを導線によって接続する場合、多数のＩＧＢＴを接続することが煩雑であったり、導線の持つインダクタンス成分の問題があった。   An insulated gate bipolar transistor (hereinafter abbreviated as IGBT), which is a kind of semiconductor element, is mainly used for power control, and a large number of IGBT elements may be stacked in order to increase the current capacity of the device. Although required, when connecting an IGBT module with a conducting wire, it is complicated to connect many IGBTs, and there is a problem of an inductance component of the conducting wire.

そこで、ＩＧＢＴをチップ状に形成し、ＩＧＢＴチップの両面をＤＣＢ基板等の外部電極で挟み込むことにより、直接接触によって外部電極とＩＧＢＴチップの端子との接続を行う、圧接型ＩＧＢＴが用いられている。   Therefore, a pressure contact IGBT is used in which the IGBT is formed in a chip shape, and the both sides of the IGBT chip are sandwiched between external electrodes such as a DCB substrate, thereby connecting the external electrode and the terminal of the IGBT chip by direct contact. .

圧接型ＩＧＢＴチップにおいては、一方の面にはエミッタ電極が露出し、他方の面にはコレクタ電極が露出しており、ＩＧＢＴチップの両面を挟み込むことでこれら電極と外部との接続を行っているが、チップのエミッタ電極側には、エミッタ電極とは絶縁体によって絶縁されたゲートフィンガー電極が存在しており、このゲートフィンガー電極は、外部電極との接触がなされないように、エミッタ電極の露出する高さよりも低く形成される必要がある。   In the pressure contact type IGBT chip, the emitter electrode is exposed on one surface and the collector electrode is exposed on the other surface, and the electrodes are connected to the outside by sandwiching both surfaces of the IGBT chip. However, on the emitter electrode side of the chip, there is a gate finger electrode that is insulated from the emitter electrode by an insulator, and this gate finger electrode is exposed to the emitter electrode so as not to contact the external electrode. It is necessary to be formed lower than the height.

このようにエミッタ電極よりもゲートフィンガー電極が低くなるように電極を形成する技術として、シリコン基板上にゲート酸化膜、ゲートフィンガー電極、酸化膜、層間絶縁膜を形成した後、第１成膜層を厚く（１０μｍ以上）成膜し、第２成膜層を薄く（５μｍ程度）成膜した後、第１成膜層の中間までエッチングをする技術が開示されている（例えば、特許文献１参照）。   As a technique for forming the electrode so that the gate finger electrode is lower than the emitter electrode in this way, after forming a gate oxide film, a gate finger electrode, an oxide film, and an interlayer insulating film on the silicon substrate, the first film formation layer is formed. Has been disclosed (see, for example, Patent Document 1). After the film is formed thick (10 μm or more), the second film layer is thin (about 5 μm), and then the film is etched to the middle of the first film layer. ).

この技術では、エッチング後に適切な電極の厚さを残すために、第２成膜層の厚さを第１成膜層の厚さの半分にする必要がある。   In this technique, in order to leave an appropriate electrode thickness after etching, the thickness of the second film-forming layer needs to be half the thickness of the first film-forming layer.

特開平４−３６１５３２号公報JP-A-4-361532

しかしながら、エッチングは、溶解時間や周囲の温度等の条件によって、溶解の進行が面内においてばらつきが大きい方法である。また、各電極の形成厚さは、数μｍ程度と薄いため、エッチングの進行をこの薄さの中で所望の位置に制御することは極めて困難である。   However, etching is a method in which the progress of dissolution varies greatly in the plane depending on conditions such as dissolution time and ambient temperature. Further, since the formation thickness of each electrode is as thin as about several μm, it is extremely difficult to control the progress of etching to a desired position within this thinness.

特許文献１に記載の技術では、エッチングを第１成膜層の中間位置で厳密に制御する必要があり、その際、エッチング量が少な過ぎると第２成膜層がゲート・エミッタ間に残存してゲート・エミッタ短絡が生じ、逆にエッチング量が多過ぎると第１成膜層の非加圧接触部の配線が薄くなることで断線が生じ易くなり、歩留まりを大幅に低下させてしまうという問題があった。   In the technique described in Patent Document 1, it is necessary to strictly control etching at an intermediate position of the first film formation layer. At this time, if the etching amount is too small, the second film formation layer remains between the gate and the emitter. As a result, the gate-emitter short circuit occurs, and conversely, if the etching amount is too large, the wiring of the non-pressurized contact portion of the first film formation layer becomes thin, and disconnection is likely to occur, resulting in a significant decrease in yield. was there.

また、第１成膜層と第２成膜層の界面に形成される自然酸化膜層によって第１成膜層と第２成膜層間に密着性が低下し、冷熱サイクル時に膜剥がれが発生するなど、耐久信頼性が低下するという問題もあった。   In addition, the natural oxide film layer formed at the interface between the first film-forming layer and the second film-forming layer reduces the adhesion between the first film-forming layer and the second film-forming layer, and film peeling occurs during the cooling / heating cycle. There was also a problem that durability reliability decreased.

本願発明は、上記状況に鑑みてなされたものであり、極めて薄い金属膜からなるエミッタ電極およびゲートフィンガー電極を有する圧接型ＩＧＢＴにおけるエッチングにおいて、エッチング厚さの厳密な制御を必要とすることなく、かつ所望の厚さを有するエミッタ電極およびゲートフィンガー電極を形成することができ、さらに、成膜層どうしの密着性にも問題のない半導体装置の製造方法を提供することを目的としている。   The present invention has been made in view of the above situation, and in etching in a pressure contact type IGBT having an emitter electrode and a gate finger electrode made of an extremely thin metal film, without requiring precise control of the etching thickness, In addition, an object of the present invention is to provide a method for manufacturing a semiconductor device in which an emitter electrode and a gate finger electrode having a desired thickness can be formed, and there is no problem in adhesion between film formation layers.

本願発明は、圧接型半導体に用いる半導体装置の製造方法であって、シリコン基板上に第１アルミニウム層を形成する工程と、所望のエミッタ電極およびゲートフィンガー電極形状となるよう第１アルミニウム層の一部をエッチングする工程と、第１アルミニウム層上にアルミニウム以外の金属からなる下地層を形成する工程と、下地層上に第２アルミニウム層を形成する工程と、第２アルミニウム層のうちエミッタ電極に相当する部分にレジストを塗布する工程と、レジストを塗布した部分以外の第２アルミニウム層をエッチングする工程と、レジストを塗布した部分以外の下地層をエッチングする工程と、レジストを除去する工程とを有することを特徴としている。   The present invention relates to a method of manufacturing a semiconductor device used for a pressure-contact type semiconductor, comprising a step of forming a first aluminum layer on a silicon substrate, and a step of forming a first aluminum layer so as to have a desired emitter electrode and gate finger electrode shape. Etching a portion, forming a base layer made of a metal other than aluminum on the first aluminum layer, forming a second aluminum layer on the base layer, and forming an emitter electrode in the second aluminum layer A step of applying a resist to the corresponding portion, a step of etching the second aluminum layer other than the portion where the resist is applied, a step of etching a base layer other than the portion where the resist is applied, and a step of removing the resist It is characterized by having.

本願発明においては、下地層を形成するアルミニウム以外の金属は、チタンまたはＭｏＳｉから選択される金属であることを好ましい態様としている。   In this invention, it is set as the preferable aspect that metals other than aluminum which form a base layer are metals selected from titanium or MoSi.

本願発明によれば、第１アルミニウム層、下地層、第２アルミニウム層の順に成膜されているので、ゲートフィンガー電極部分では、最上層の第２アルミニウム層をエッチングする際にアルミニウムエッチング用薬液ではアルミニウムのみがエッチングされて、下地層を構成するアルミニウム以外の金属はエッチングされない。したがって、エッチング時間を十分に長く取っても、最下層の第１アルミニウム層は下地層に保護されるので、エッチングは第２アルミニウム層のみに制限することができる。   According to the present invention, since the first aluminum layer, the base layer, and the second aluminum layer are formed in this order, when the uppermost second aluminum layer is etched in the gate finger electrode portion, Only aluminum is etched, and metals other than aluminum constituting the underlayer are not etched. Therefore, even if the etching time is sufficiently long, the lowermost first aluminum layer is protected by the underlayer, so that the etching can be limited only to the second aluminum layer.

結果として、エミッタ電極は第１アルミニウム層＋下地層＋第２アルミニウム層の合計高さとし、ゲートフィンガー電極は第１アルミニウム層の高さと規定することができるので、エッチング条件に左右されずに所望の高さの電極を得ることができるという効果を奏する。また、従来技術のように、第１アルミニウム層が断線することもなく、高い歩留まりを実現することができる。   As a result, the emitter electrode can be defined as the total height of the first aluminum layer + the underlayer + the second aluminum layer, and the gate finger electrode can be defined as the height of the first aluminum layer. There exists an effect that the electrode of height can be obtained. In addition, unlike the prior art, the first aluminum layer is not broken, and a high yield can be realized.

本発明を適用することができる圧接型ＩＧＢＴチップの一例を示す平面図である。It is a top view which shows an example of the press-contact type IGBT chip | tip which can apply this invention. 図１の平面図におけるＡ−Ａ線断面図である。It is the sectional view on the AA line in the top view of FIG. 図２における破線部（半導体装置の周縁部）の拡大図である。FIG. 3 is an enlarged view of a broken line portion (peripheral portion of a semiconductor device) in FIG. 2. 本発明の半導体装置の製造工程を示す模式断面図である。It is a schematic cross section which shows the manufacturing process of the semiconductor device of this invention.

以下、本願発明の実施形態について更に詳細に説明する。
図１は、本発明を適用することができる圧接型ＩＧＢＴチップの一例を示す平面図であり、図２は、図１のＡ−Ａ線断面図である。ＩＧＢＴチップ１は、図に示すようにシリコン基板１０の両面に電極が形成されており、上面と下面に、図示しない外部電極を有する基板を挟み込んで、半導体装置として使用される。具体的には、ＩＧＢＴチップ１の上面にはエミッタ電極のセル１２が多数直列接続されて露出しており、下面にはコレクタ電極が露出している。 Hereinafter, embodiments of the present invention will be described in more detail.
FIG. 1 is a plan view showing an example of a pressure contact type IGBT chip to which the present invention can be applied, and FIG. 2 is a cross-sectional view taken along line AA of FIG. The IGBT chip 1 has electrodes formed on both sides of a silicon substrate 10 as shown in the figure, and is used as a semiconductor device by sandwiching a substrate having an external electrode (not shown) between an upper surface and a lower surface. Specifically, a large number of emitter electrode cells 12 are connected in series on the upper surface of the IGBT chip 1 and exposed, and a collector electrode is exposed on the lower surface.

また、多数のセル１２の周囲には、ガードリング１１が設けられている。図３は、図２における破線部分の拡大図であるが、ガードリング１１は、加圧接続の際の支障とならないよう、エミッタ電極よりも低く形成されている。   A guard ring 11 is provided around the large number of cells 12. FIG. 3 is an enlarged view of the broken line portion in FIG. 2, but the guard ring 11 is formed lower than the emitter electrode so as not to hinder the pressure connection.

図４は、本発明の半導体装置の製造工程を示す模式図である。
まず、（ａ）に示すシリコン基板２０に対して、熱酸化工程およびエッチング工程により、酸化膜層を、続いてゲート酸化膜層を形成する。次に、ポリシリコン成膜工程およびこの膜のエッチング工程により、ゲートフィンガー電極を形成する。また、ＣＶＤ成膜工程およびこの膜のエッチング工程により、層間絶縁膜を形成する。以上の工程は公知の技術であるため、図示を省略している。 FIG. 4 is a schematic view showing the manufacturing process of the semiconductor device of the present invention.
First, an oxide film layer and then a gate oxide film layer are formed on the silicon substrate 20 shown in FIG. Next, a gate finger electrode is formed by a polysilicon film forming process and an etching process of this film. Further, an interlayer insulating film is formed by a CVD film forming process and an etching process of this film. Since the above process is a well-known technique, illustration is abbreviate | omitted.

続いて、上記の各工程を経た基板２０上に、スパッタリング等の方法によって第１アルミニウム層２１を形成する。この第１アルミニウム層２１が所望のエミッタ部およびゲート部の形状となるように、フォトリソグラフィー法等によってレジストを塗布してマスキングを行い、続いてエッチングを行い、（ｂ）に示すような基板２０上にエミッタ部２１ａおよびゲート部２１ｂが形成された状態となる。   Then, the 1st aluminum layer 21 is formed on the board | substrate 20 which passed through each said process by methods, such as sputtering. The first aluminum layer 21 is masked by applying a resist by a photolithography method or the like so that the first aluminum layer 21 has the desired emitter and gate shapes, followed by etching, and a substrate 20 as shown in FIG. The emitter portion 21a and the gate portion 21b are formed thereon.

次に、（ｂ）の状態の基板２０、エミッタ部２１ａおよびゲート部２１ｂの全体に、アルミニウム以外の金属からなる下地層２２を同じくスパッタリング等の方法によって成膜して、（ｃ）の状態を得、第１アルミニウム層と同様の方法で第２アルミニウム層２３を下地層２２上に成膜して、（ｄ）の状態を得る。   Next, a base layer 22 made of a metal other than aluminum is formed on the entire substrate 20, emitter 21a and gate 21b in the state (b) by the same method such as sputtering, and the state (c) is obtained. Then, the second aluminum layer 23 is formed on the base layer 22 by the same method as that for the first aluminum layer to obtain the state (d).

ここで、図示は省略されているが、エミッタ部２３ａの上にのみ選択的にレジストを塗布してマスキングを行う。さらに、アルミニウムのみを溶解させ下地層２２の構成金属を溶解させないエッチング薬液を使用してエッチングを行うことによって、（ｄ）における第２アルミニウム層２３のうち除去部２３ｂを除去し、マスキングされている残存部２３ａのみを残存させて、（ｅ）の状態を得る。   Although not shown, masking is performed by selectively applying a resist only on the emitter portion 23a. Further, by performing etching using an etching chemical solution that dissolves only aluminum and does not dissolve the constituent metal of the underlayer 22, the removal portion 23b of the second aluminum layer 23 in (d) is removed and masked. Only the remaining portion 23a is left to obtain the state (e).

次に、下地層２２の構成金属のみを溶解させアルミニウムを溶解させないエッチング薬液を使用してエッチングを行うことによって、エミッタ部に含まれる下地層以外の露出している下地層２２を全て除去して、（ｆ）に示すような、エミッタ部がゲート部よりも高く形成され、外部電極によって加圧接続される際にエミッタ部のみが圧接されるようなＩＧＢＴチップの構造を得ることができる。最後に、ポリイミド層２４等によってエミッタ部を露出させた以外の部分は絶縁被覆を行い、さらに基板２０の裏面に裏面電極層（コレクタ）２５を形成する。   Next, etching is performed using an etching chemical solution that dissolves only the constituent metal of the base layer 22 and does not dissolve aluminum, thereby removing all the exposed base layer 22 other than the base layer included in the emitter portion. As shown in (f), the structure of the IGBT chip can be obtained in which the emitter part is formed higher than the gate part and only the emitter part is pressure-contacted when pressure-connected by the external electrode. Finally, a portion other than the emitter portion exposed by the polyimide layer 24 or the like is covered with an insulating coating, and a back electrode layer (collector) 25 is formed on the back surface of the substrate 20.

上記工程からなる本発明では、図４（ｇ）に示すように、最終的にはエミッタ部の高さは第１アルミニウム層２１ａ、下地層２２および第２アルミニウム層２３ａの合計厚さから決定され、ゲート部の高さは第１アルミニウム層２１ｂのみの厚さから決定される。したがって、スパッタリング等によるこれらの形成厚さを決定すれば、各層の厚さは、その後のエッチング工程の条件には左右されない。すなわち、従来技術のように層の形成厚さをエッチングによって制御するのは極めて困難であるが、スパッタリングはエッチングに比較して制御が容易であるので、エミッタ部およびゲート部を所望の厚さに制御することが可能である。   In the present invention comprising the above steps, as shown in FIG. 4G, the height of the emitter is finally determined from the total thickness of the first aluminum layer 21a, the underlayer 22 and the second aluminum layer 23a. The height of the gate portion is determined from the thickness of only the first aluminum layer 21b. Therefore, if these formation thicknesses by sputtering etc. are determined, the thickness of each layer is not influenced by the conditions of the subsequent etching process. That is, it is extremely difficult to control the formation thickness of the layer by etching as in the prior art, but since sputtering is easier to control than etching, the emitter portion and the gate portion are set to desired thicknesses. It is possible to control.

なお、図３に示すガードリング１１部分も圧接の支障とならないようエミッタ部の高さを越えないように形成する必要があるが、本発明の上記工程を適用することによって、容易に実現することができる。   Note that the guard ring 11 shown in FIG. 3 also needs to be formed so as not to exceed the height of the emitter so as not to interfere with the press contact, but can be easily realized by applying the above-described process of the present invention. Can do.

本発明の下地層２２を構成する金属としては、アルミニウムエッチング用薬液で溶解しない金属であれば適用が可能であり、第１アルミニウム層および第２アルミニウム層との膜剥がれを考慮すると、具体的には、チタンまたはＭｏＳｉが好ましく、特に、チタンが好ましい。チタンは電気伝導性は勿論のこと、第１アルミニウム層と第２アルミニウム層との密着性が高く、耐久信頼性が向上する。   As the metal constituting the underlayer 22 of the present invention, any metal that does not dissolve in the chemical solution for aluminum etching can be applied. In consideration of film peeling between the first aluminum layer and the second aluminum layer, specifically, Is preferably titanium or MoSi, and particularly preferably titanium. Titanium has not only electrical conductivity, but also high adhesion between the first aluminum layer and the second aluminum layer, and durability reliability is improved.

本発明の成膜工程は、ＩＧＢＴだけではなく、加圧接触する用途であればダイオード、ＭＯＳＦＥＴ等のパワー半導体全般に適用することが可能である。   The film forming process of the present invention can be applied not only to IGBTs but also to power semiconductors such as diodes and MOSFETs as long as they are used for pressure contact.

高電流容量用途の圧接型ＩＧＢＴの製造に有望である。   It is promising for the manufacture of pressure contact IGBTs for high current capacity applications.

１…半導体装置（ＩＧＢＴチップ）、
１０…基板、
１１…ガードリング、
１２…セル、
２０…基板、
２１…第１アルミニウム層、
２１ａ…第１アルミニウム層（エミッタ部）、
２１ｂ…第１アルミニウム層（ゲート部）、
２２…下地層、
２３…第２アルミニウム層、
２３ａ…第２アルミニウム層（残存部、エミッタ部）、
２３ｂ…第２アルミニウム層（除去部）、
２４…ポリイミド層、
２５…裏面電極層（コレクタ）。
1 ... Semiconductor device (IGBT chip),
10 ... substrate,
11 ... Guard ring,
12 ... cell,
20 ... substrate,
21 ... 1st aluminum layer,
21a ... 1st aluminum layer (emitter part),
21b ... 1st aluminum layer (gate part),
22: Underlayer,
23. Second aluminum layer,
23a ... second aluminum layer (remaining part, emitter part),
23b ... 2nd aluminum layer (removal part),
24 ... polyimide layer,
25: Back electrode layer (collector).

Claims (2)

圧接型半導体に用いる半導体装置の製造方法であって、
シリコン基板上に第１アルミニウム層を形成する工程と、
所望のエミッタ電極およびゲートフィンガー電極形状となるよう前記第１アルミニウム層の一部をエッチングする工程と、
前記第１アルミニウム層上にアルミニウム以外の金属からなる下地層を形成する工程と、
前記下地層上に第２アルミニウム層を形成する工程と、
前記第２アルミニウム層のうちエミッタ電極に相当する部分にレジストを塗布する工程と、
前記レジストを塗布した部分以外の第２アルミニウム層をエッチングする工程と、
前記レジストを塗布した部分以外の下地層をエッチングする工程と、
前記レジストを除去する工程と
を有することを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device for use in a pressure contact type semiconductor,
Forming a first aluminum layer on a silicon substrate;
Etching a portion of the first aluminum layer to have a desired emitter electrode and gate finger electrode shape;
Forming a base layer made of a metal other than aluminum on the first aluminum layer;
Forming a second aluminum layer on the underlayer;
Applying a resist to a portion corresponding to the emitter electrode in the second aluminum layer;
Etching the second aluminum layer other than the portion coated with the resist;
Etching the base layer other than the portion coated with the resist;
And a step of removing the resist. 前記下地層を形成するアルミニウム以外の金属は、チタンまたはＭｏＳｉから選択される金属であることを特徴とする請求項１に記載の半導体装置の製造方法。

The method for manufacturing a semiconductor device according to claim 1, wherein the metal other than aluminum forming the base layer is a metal selected from titanium and MoSi.

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