CN103165543A - Semiconductor element and manufacture method thereof and sealing structure thereof - Google Patents
Semiconductor element and manufacture method thereof and sealing structure thereof Download PDFInfo
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- CN103165543A CN103165543A CN2013100502817A CN201310050281A CN103165543A CN 103165543 A CN103165543 A CN 103165543A CN 2013100502817 A CN2013100502817 A CN 2013100502817A CN 201310050281 A CN201310050281 A CN 201310050281A CN 103165543 A CN103165543 A CN 103165543A
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- conductive pole
- semiconductor substrate
- semiconductor
- semiconductor element
- metal level
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a semiconductor element and a manufacture method thereof and a sealing structure thereof. The semiconductor element comprises a semiconductor base material, a circuit layer, a metal layer and a passivation layer. The semiconductor base material is provided with a first surface, a second surface and a plurality of conduction posts. The second surface is arranged opposite to the first surface. Each conduction post penetrates through the semiconductor base material and protrudes out of the second surface. The circuit layer is arranged on the first surface of the semiconductor base material and electrically connected with the conduction posts. The metal layer is formed on an exposed top face of each conduction post. The passivation layer is formed on the second surface of the semiconductor base material. The passivation layer is positive pole oxide of the metal layer. The passivation layer is thin in thickness and low in manufacture cost and a semiconductor element warping problem can not occur easily.
Description
Technical field
The present invention relates to a kind of semiconductor element, particularly relevant for a kind of semiconductor element and manufacture method and packaging structure.
Background technology
In existing semiconductor package fabrication, decide according to product demand, the silicon substrate inside of wafer, chip or intermediary layer (interposer) can be equipped with conductive pole and (claim again to wear silicon through hole or the perforation of straight-through silicon wafer, through silicon via), described conductive pole can protrude from a first surface of the inverter circuit layer of silicon substrate, to be electrically connected with other semiconductor constructions (for example upper strata chip).The first surface of described silicon substrate can be provided with passivation layer so that protection to be provided, and the exposed end face of aforementioned conductive pole projection can arrange the substrate layer, to connect conductive pole and scolding tin metal.
In the prior art, can or be coated with non-conductive type high-molecular organic material by the long-pending silicon dioxide in chemical vapor deposition method Shen and form above-mentioned passivation layer.Yet, need to expend higher cost in the mode of the long-pending silicon dioxide in chemical vapor deposition method Shen, and need other treatment process to remove silicon dioxide on conductive pole, entirely also will not increase conductive pole open circuit risk therefore if remove.With non-conductive type high-molecular organic material (pi for example, Polyimide) mode that forms above-mentioned passivation layer also may have residual macromolecular material on conductive pole because removing complete, and then the open circuit risk of increase conductive pole, moreover, thermal coefficient of expansion between high-molecular organic material and silicon substrate does not mate, will cause both to produce stress when temperature change and pull, thereby produce the problem of semiconductor element warpage.
Therefore, be necessary to provide a kind of semiconductor element and manufacture method thereof and packaging structure, to solve the existing problem of prior art.
Summary of the invention
Main purpose of the present invention is to provide a kind of semiconductor element, the conductive pole end face of its semiconductor substrate surface exposure is provided with metal level, and the semiconductor substrate surface is provided with passivation layer, described passivation layer is made of the anodic oxide of described metal level, has advantages of that cost of manufacture is lower and is difficult for causing the semiconductor element warpage issues to occur.
For reaching aforementioned purpose, one embodiment of the invention provides a kind of semiconductor element, described semiconductor element comprises: semiconductor base material, a circuit layer, a metal level and a passivation layer, wherein said semiconductor substrate has a first surface, a second surface and several conductive poles, the relatively described first surface of described second surface, described conductive pole run through described semiconductor substrate and part is protruded described second surface and had an end face that exposes; Described circuit layer is located at the first surface of described semiconductor substrate, and is electrically connected described conductive pole; Described metal level forms in exposing on end face of described conductive pole; Described passivation layer forms in the second surface of described semiconductor substrate, and described passivation layer is the anodic oxide of described metal level.
Another object of the present invention is to provide a kind of semiconductor device manufacturing method, described semiconductor device manufacturing method comprises step: the semiconductor base material is provided, wherein said have a first surface, a second surface and several conductive poles, the relatively described first surface of described second surface, described conductive pole runs through described semiconductor substrate; Second surface to described semiconductor substrate carries out the thinning processing, makes an end face of the exposed described conductive pole of described second surface; Second surface to described semiconductor substrate carries out etching, makes described conductive pole partly protrude from described second surface; Be shaped a metal level in the second surface of described semiconductor substrate and the exposed end face of described conductive pole; Metal level on the second surface of described semiconductor substrate is carried out anode oxidation process, with as a passivation layer; And the projection lower metal layer that forms the part of a described second surface of the described conductive pole protrusion of coating.
Another object of the present invention is to provide a kind of semiconductor component packing structure, a base plate for packaging, semiconductor element, a chip and packaging adhesive material, the circuit layer of wherein said semiconductor element are electrically connected on a surface of described base plate for packaging; Described chip is electrically connected the described conductive pole of the second surface that protrudes described semiconductor element; Described packaging adhesive material is located on the surface of described base plate for packaging and is coated described chip and described semiconductor element.
Because the present invention is disposable semiconductor substrate surface in the exposed side of conductive pole and conductive pole end face form metal layer, by anode oxidation process, the metal level on semiconductor substrate surface is oxidized to passivation layer (being the oxide layer of same metal) again, and the metal level of conductive pole end face remains unchanged, compared to existing silica depositing operation, can reduce the step of the silica that removes the conductive pole end face, cost of manufacture is lower and be difficult for causing the semiconductor element warpage issues to occur.
Description of drawings
Fig. 1 is the generalized section of the semiconductor element of one embodiment of the invention.
Fig. 2 is the generalized section of the semiconductor component packing structure of one embodiment of the invention.
Fig. 3 A ~ 3E is the structural representation of the semiconductor element of construction drawing 1 embodiment.
Embodiment
For allowing above-mentioned purpose of the present invention, feature and advantage become apparent, preferred embodiment of the present invention cited below particularly, and cooperation accompanying drawing are described in detail below.Moreover, the direction term that the present invention mentions, such as " on ", D score, 'fornt', 'back', " left side ", " right side ", " interior ", " outward ", " side " etc., be only the direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the present invention, but not in order to limit the present invention.
Please refer to shown in Figure 1ly, Fig. 1 is the structural plan schematic diagram of the semiconductor element of one embodiment of the invention.Disclosed semiconductor element comprises semiconductor base material 10, a circuit layer 20, a metal level 16 and a passivation layer 18.
The material of described semiconductor substrate 10 can be silicon, GaAs, sapphire substrate or other semi-conducting materials.Described semiconductor substrate 10 has a first surface (lower surface in Fig. 1), a second surface (upper surface in Fig. 1) and several conductive poles 12.The relatively described first surface of described second surface.In one embodiment, the first surface of described semiconductor substrate 10 (lower surface in Fig. 1) can be provided with at least one active element (active component) (for example transistor).Described conductive pole 12 can be to form by wearing the silicon through hole manufacture craft, and it runs through described semiconductor substrate 10 and part is protruded described second surface and had an end face that exposes.In one embodiment, described conductive pole 12 can be for example copper, nickel, and the sidewall of described conductive pole 12 is coated by an insulating barrier 14, and described insulating barrier 14 can be for example silicon dioxide.In one embodiment, the part that described conductive pole 12 protrudes described second surface also is coated with a projection lower metal layer 19, and described projection lower metal layer 19 can be nickel/golden composite bed and/or soldering tin material.
Described circuit layer 20 is located at the first surface of described semiconductor substrate 10, and is electrically connected described conductive pole 12.When described semiconductor substrate 10 did not arrange active element, described circuit layer 20 was the layers (redistribution layer) that reroute.When described semiconductor substrate 10 arranged active element, described circuit layer 20 was electrically connected described conductive pole 12 and active element.
Described metal level 16 forms in exposing on end face of described conductive pole 12.In one embodiment, described metal level 16 can be for example tantalum or aluminium, and its thickness can be between 50 nanometers～600 nanometers.
Described passivation layer 18 forms in the second surface of described semiconductor substrate 10, and described passivation layer 18 is the anodic oxide of the same metal material of described metal level 16, therefore the thickness of described passivation layer 18 can be the thickness that is equal to or slightly greater than described metal level 16.In one embodiment, when aforementioned metal level was tantalum (Ta), described metal level 16 was tantalum pentoxide (Ta
2O
5).
Further with reference to shown in Figure 2, Fig. 2 is the generalized section of the semiconductor component packing structure of one embodiment of the invention.Described semiconductor component packing structure also comprises a base plate for packaging 40, a chip 30 and packaging adhesive material 34 except comprising above-mentioned semiconductor element.
Described base plate for packaging 40 can be for example can first consist of its insulating barrier by glass fibre and epoxy resin, then replaces stacking forming by insulating barrier and circuit layer.The upper surface of described base plate for packaging 40 is provided with several electrical junctions 22, copper bump for example, and its lower surface is provided with the tin ball.The circuit layer 20 of described semiconductor element is electrically connected several electrical junctions 22 of the upper surface of described base plate for packaging 40.
30 of described chips are electrically connected the conductive poles 12 of described semiconductor elements, for example are connected to projection lower metal layer 19 on described conductive pole 12 by the metal coupling 32 that is arranged on chip 30 bottom surfaces, consist of to be electrically connected.
Described packaging adhesive material 34 can be epoxy resin for example, and it is located on the surface of described base plate for packaging 40 and coats described chip 30 and described semiconductor element.
Please refer to shown in Fig. 3 A ~ 3E, it is the structural representation of the semiconductor element of summary announcement construction drawing 1 embodiment respectively.
Please refer to shown in Fig. 3 A, at first semiconductor base material (for example wafer) 10A is provided, for example between 150 microns～250 microns, the first surface of described semiconductor crystal wafer 10A is provided with described circuit layer 20 to thickness, and described conductive pole 12.
Then, please refer to Fig. 3 B, second surface to described semiconductor substrate 10 carries out the thinning processing, for example pass through grinding technics, and then remove the part of described semiconductor substrate 10 and the part of described conductive pole 12 and insulating barrier 14, make the second surface of described semiconductor substrate 10 be able to an end face of exposed described conductive pole 12 and insulating barrier 14 surfaces of a ring-type.Thickness after described semiconductor substrate 10 thinnings for example between 80 microns～120 microns, is for example 100 microns;
Subsequently, please refer to Fig. 3 C, use plasma (plasma) further to carry out dry ecthing to the second surface of described semiconductor substrate 10, with the further described semiconductor substrate 10 of thinning again, make described conductive pole part protrude from (comprising insulating barrier 14) second surface of described semiconductor substrate 10;
then, please refer to Fig. 3 D, be shaped a metal level 16 in the second surface of described semiconductor substrate 10 and the exposed end face of described conductive pole 12, for example with the incidence angle perpendicular to described second surface, metallic is deposited on the second surface of described semiconductor substrate 10 and the exposed end face of described conductive pole 12 by sputter (sputtering) technique, it should be noted that, owing to being that an incidence angle with perpendicular to described second surface is carried out sputtering process, insulating barrier 14 on described conductive pole 12 sidewalls parallel with the metallic incident direction will can synchronously not generate described metal level 16, and then with isolated the opening of metal level 16 on the second surface of the metal level 16 on described conductive pole 12 end faces and described semiconductor substrate 10,
Afterwards, please refer to Fig. 3 E, metal level 16 on the second surface of described semiconductor substrate 10 is positioned in the environment that an electrolysis aqueous vapor forms hydrogen and oxygen, and make described metal level 16 connect an electrode, so that described metal level 16 is carried out anode oxidation process, make metal level 16 oxidations on the second surface of described semiconductor substrate 10, and then as a passivation layer 18;
At last, please refer to Fig. 1, then form the projection lower metal layer 19 (UBM) of the part that coats the described conductive pole 12 described second surfaces of protrusion, semiconductor element of the present invention namely completes.
With tantalum pentoxide (Ta
2O
5) be example, the thermal coefficient of expansion of the silicon dioxide base material that the circuit layer 20 of described passivation layer 18 and semiconductor substrate 10 opposite sides (being first surface) (as reroute layer or active circuit layer) comprises is comparatively approaching, therefore compared to the prior art of coating high-molecular organic material as passivation layer, semiconductor element of the present invention is difficult for occuring warpage issues on the whole.moreover, relation due to vertical sputter, make metal level 16 on the second surface of metal level 16 and described semiconductor substrate 10 on described conductive pole 12 end faces be insulated that layer 14 is isolated to be opened, therefore when selectivity is carried out anodized to the metal level 16 on the second surface of described semiconductor substrate 10, metal level 16 on described conductive pole 12 end faces is unlikely Simultaneous Oxidation, also therefore, the present invention needn't have more the step of the insulating material of removing together the conductive pole end face compared to prior art, the cost that helps to simplify manufacture craft and reduce manufacture craft, with relative raising make efficiency.Moreover, coordinate the mode of anodized also can accurately control the thickness of passivation layer with sputtering way.
In sum, have the semiconductor element of conductive pole and many disappearances of manufacture craft thereof compared to having now, the present invention is in semiconductor substrate surface and the disposable form metal layer of conductive pole end face of the exposed side of conductive pole, by the anode oxidation process selectivity, the metal level on semiconductor substrate surface is oxidized into passivation layer again, and the metal level of conductive pole end face remains unchanged, can relatively reduce the step of the insulating material that removes the conductive pole end face, cost of manufacture is lower and be difficult for causing warpage issues to occur.
The present invention is described by above-mentioned related embodiment, yet above-described embodiment is only for implementing example of the present invention.Must be pointed out that, published embodiment does not limit the scope of the invention.On the contrary, being contained in the spirit of claims and modification and impartial setting of scope is included in scope of the present invention.
Claims (10)
1. semiconductor element, it is characterized in that: it comprises:
The semiconductor base material has a first surface, a second surface and several conductive poles, and the relatively described first surface of described second surface, described conductive pole run through described semiconductor substrate and part is protruded described second surface and had an end face that exposes;
One circuit layer is located at the first surface of described semiconductor substrate, and is electrically connected described conductive pole;
One metal level forms in exposing on end face of described conductive pole; And
One passivation layer forms in the second surface of described semiconductor substrate, and described passivation layer is the anodic oxide of described metal level.
2. semiconductor element as claimed in claim 1, it is characterized in that: described semiconductor substrate is a silicon substrate, described circuit layer is the layer that reroutes.
3. semiconductor element as claimed in claim 1, it is characterized in that: described semiconductor substrate is provided with at least one active element.
4. semiconductor element as claimed in claim 1, it is characterized in that: described metal level is tantalum, described passivation layer is tantalum pentoxide.
5. semiconductor element as claimed in claim 1, it is characterized in that: the sidewall of described conductive pole is coated by an insulating barrier.
6. semiconductor element as claimed in claim 1 is characterized in that: the part that described conductive pole protrudes described second surface is coated with a projection lower metal layer.
7. semiconductor device manufacturing method, it is characterized in that: it comprises the following step:
The semiconductor wafer is provided, wherein said semiconductor crystal wafer comprises semiconductor base material and several conductive poles, described semiconductor substrate has a first surface, a second surface, the relatively described first surface of described second surface, and described conductive pole runs through described semiconductor substrate;
Second surface to described semiconductor substrate carries out the thinning processing, makes an end face of the exposed described conductive pole of described second surface;
Second surface to described semiconductor substrate carries out etching, makes described conductive pole partly protrude from described second surface;
Be shaped a metal level in the second surface of described semiconductor substrate and the exposed end face of described conductive pole;
Metal level on the second surface of described semiconductor substrate is carried out anode oxidation process, with as a passivation layer; And
Form one and coat the projection lower metal layer that described conductive pole protrudes the part of described second surface.
8. semiconductor device manufacturing method as claimed in claim 7, it is characterized in that: described metal level is with the incidence angle perpendicular to described second surface, metallic to be deposited on the second surface of described semiconductor substrate and the exposed end face of described conductive pole by sputtering process.
9. semiconductor device manufacturing method as claimed in claim 7, it is characterized in that: the first surface of described semiconductor substrate is provided with a circuit layer, and described circuit layer is electrically connected described conductive pole; The sidewall of described conductive pole is coated by an insulating barrier; Described metal level is tantalum, and described passivation layer is tantalum pentoxide.
10. a semiconductor component packing is constructed, and it is characterized in that: it comprises:
One base plate for packaging;
Just like the described semiconductor element of claim 1 to 6 any one, the circuit layer of described semiconductor element is electrically connected on a surface of described base plate for packaging;
One chip, the described conductive pole of the second surface of described semiconductor element is protruded in electric connection; And
One packaging adhesive material is located on the surface of described base plate for packaging and coats described chip and described semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310050281.7A CN103165543B (en) | 2013-02-08 | 2013-02-08 | Semiconductor element and manufacture method thereof and packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310050281.7A CN103165543B (en) | 2013-02-08 | 2013-02-08 | Semiconductor element and manufacture method thereof and packaging structure |
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| Publication Number | Publication Date |
|---|---|
| CN103165543A true CN103165543A (en) | 2013-06-19 |
| CN103165543B CN103165543B (en) | 2015-11-18 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109216213A (en) * | 2017-06-30 | 2019-01-15 | 台湾积体电路制造股份有限公司 | Packaging part and forming method thereof |
| CN110391142A (en) * | 2018-04-20 | 2019-10-29 | 台湾积体电路制造股份有限公司 | The method for forming semiconductor devices |
| US11756802B2 (en) | 2017-06-30 | 2023-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermally conductive material in the recess of an encapsulant and sidewall of an integrated circuit device |
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| TW201216425A (en) * | 2010-10-12 | 2012-04-16 | Advanced Semiconductor Eng | Semiconductor device and semiconductor package having the same |
| US20120313247A1 (en) * | 2011-06-09 | 2012-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through Silicon Via Structure and Method |
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| JP2004297045A (en) * | 2003-03-25 | 2004-10-21 | Samsung Electronics Co Ltd | Wafer level package, multi-stacked package, and method of manufacturing same |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109216213A (en) * | 2017-06-30 | 2019-01-15 | 台湾积体电路制造股份有限公司 | Packaging part and forming method thereof |
| CN109216213B (en) * | 2017-06-30 | 2020-06-12 | 台湾积体电路制造股份有限公司 | Package and method of forming the same |
| US10763132B2 (en) | 2017-06-30 | 2020-09-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Release film as isolation film in package |
| US11488843B2 (en) | 2017-06-30 | 2022-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Underfill between a first package and a second package |
| US11756802B2 (en) | 2017-06-30 | 2023-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermally conductive material in the recess of an encapsulant and sidewall of an integrated circuit device |
| CN110391142A (en) * | 2018-04-20 | 2019-10-29 | 台湾积体电路制造股份有限公司 | The method for forming semiconductor devices |
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|---|---|
| CN103165543B (en) | 2015-11-18 |
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