US9392705B2 - Wiring board with through wiring - Google Patents

Wiring board with through wiring Download PDF

Info

Publication number
US9392705B2
US9392705B2 US14/471,209 US201414471209A US9392705B2 US 9392705 B2 US9392705 B2 US 9392705B2 US 201414471209 A US201414471209 A US 201414471209A US 9392705 B2 US9392705 B2 US 9392705B2
Authority
US
United States
Prior art keywords
layer
wiring
hole
metal layer
substrate body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US14/471,209
Other versions
US20150083469A1 (en
Inventor
Masahiro Sunohara
Yuichiro Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Assigned to SHINKO ELECTRIC INDUSTRIES CO., LTD. reassignment SHINKO ELECTRIC INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHIMIZU, YUICHIRO, SUNOHARA, MASAHIRO
Publication of US20150083469A1 publication Critical patent/US20150083469A1/en
Application granted granted Critical
Publication of US9392705B2 publication Critical patent/US9392705B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides

Definitions

  • the present invention relates to a wiring board.
  • a bottom-up plating process using a conductive layer as an electrode has been used, for example. Specifically, first, a film conductive layer is formed at a lower side of the silicon substrate. Then, copper (Cu) is deposited in a through hole provided in the silicon substrate by electrolytic plating process using the conductive layer as a seed layer (see Patent Document 1, for example).
  • the copper (Cu) deposited in the through hole just contacts an inner side surface of the through hole but does not adhere to the inner side surface.
  • pumping phenomenon of copper expansion and contraction due to temperature variation
  • copper is removed from the inner side surface of the through hole to cause a conductive failure of the through wiring.
  • a method of forming a through wiring in which an insulating layer is formed on a surface of a silicon substrate including an inner side surface of a through hole, a seed layer whose adhesion to the insulating layer is good is formed on the surface of the silicon substrate including the inner side surface of the through hole, and then the through wiring is formed in the through hole by filling plating.
  • the pumping phenomenon of the copper may be suppressed and the likelihood that the copper is removed from the inner side surface of the through hole to cause the conductive failure of the through wiring can be reduced.
  • the likelihood of generation of a defect such as a seam, a void, or the like, in the through wiring is increased. The likelihood of such generation of the defect becomes high when the aspect ratio of the through hole becomes high.
  • Patent Document 1 Japanese Laid-open Patent Publication No. 2005-11987
  • the present invention is made in light of the above problems, and provides a wiring board or the like in which conductive failure of a through wiring is suppressed and generation of defect such as a seam, a void or the like in the through wiring is also suppressed.
  • a wiring board including a substrate body provided with a through hole penetrating the substrate body from one surface to another surface of the substrate body; and a through wiring formed in the through hole and including a first metal layer that is formed on a part of an inner side surface of the through hole at the one surface side, a first wiring layer that covers the first metal layer to fill a part of the through hole at the one surface side, a second metal layer that is continuously formed on the rest part of the inner side surface of the through hole at the other surface side and on an end portion of the first wiring layer at the other surface side, and a second wiring layer that covers the second metal layer to fill a part of the through hole at the other surface side, the first wiring layer and the second wiring layer being electrically connected in the through hole via the second metal layer.
  • FIG. 1 is a cross-sectional view illustrating an example of a wiring board of a first embodiment
  • FIG. 2A to FIG. 2C are views illustrating an example of manufacturing steps of the wiring board of the first embodiment
  • FIG. 3A to FIG. 3C are views illustrating an example of manufacturing steps of the wiring board of the first embodiment
  • FIG. 4A to FIG. 4C are views illustrating an example of manufacturing steps of the wiring board of the first embodiment
  • FIG. 5 is a view illustrating an example of a manufacturing step of the wiring board of the first embodiment
  • FIG. 6 is a cross-sectional view illustrating an example of a wiring board of a second embodiment.
  • FIG. 1 is a cross-sectional view illustrating an example of the wiring board 1 of the first embodiment.
  • the wiring board 1 includes a substrate body 11 , an insulating layer 12 , a first adhesion layer 13 , a first metal layer 14 , a first wiring layer 15 , a second adhesion layer 23 , a second metal layer 24 and a second wiring layer 25 .
  • a first wiring layer 15 side is referred to as an upper side or one side
  • a second wiring layer 25 side is referred to as a lower side or the other side
  • a surface of each components at the first wiring layer 15 side is referred to as an upper surface or one surface
  • a surface at the second wiring layer 25 side is referred to as a lower surface or the other surface.
  • the wiring board 1 may be used in an opposite direction or may be used at an arbitrarily angle.
  • a plan view means that an object is seen in a direction that is normal to one surface 11 a of the substrate body 11
  • a “plan shape” means a shape of an object seen in the direction that is normal to the one surface 11 a of the substrate body 11 .
  • the substrate body 11 is a base portion for forming the first wiring layer 15 and the like in the wiring board 1 and the substrate body 11 is provided with through holes 11 x .
  • the thickness of the substrate body 11 may be about 100 to 200 ⁇ m, for example.
  • silicon, glass, resin or the like may be used for the material of the substrate body 11 .
  • semiconductor chips include a silicon substrate, for the material of the substrate body 11 , silicon, or borosilicate glass whose coefficient of thermal expansion is close to that of silicon may be used, in viewpoint of conforming coefficients of thermal expansion.
  • the borosilicate glass is a glass containing boric acid (B 2 O 3 ) and silic acid (SiO 2 ) as a main constituent and having a coefficient of thermal expansion about 3 ppm/° C. Further, in viewpoint of processability, silicon may be used for the material of the substrate body 11 .
  • the reason for conforming the coefficient of thermal expansion of the substrate body 11 with the coefficient of thermal expansion of the semiconductor chip is to reduce thermal stress generated at a contacting portion of the wiring board 1 and the semiconductor chip in both high temperature environment and low temperature environment.
  • the material for the substrate body 11 is silicon is explained.
  • Each of the through holes 11 x is a so-called through silicon via (TSV) that is provided to penetrate the one surface 11 a to the other surface 11 b of the substrate body 11 .
  • TSV through silicon via
  • Each of the through holes 11 x has a substantially circular shape in a plan view, for example.
  • the diameter of the through hole 11 x may be about 20 to 40 ⁇ m, for example.
  • two through holes 11 x are illustrated in FIG. 1 , the number of through holes 11 x provided in the substrate body 11 may be arbitrarily determined.
  • the insulating layer 12 is formed to continuously cover the one surface 11 a and the other surface 11 b of the substrate body 11 and the inner side surfaces of the through holes 11 x .
  • the insulating layer 12 is provided to electrically insulate the substrate body 11 from the first adhesion layer 13 , the first metal layer 14 , the first wiring layer 15 , the second adhesion layer 23 , the second metal layer 24 and the second wiring layer 25 .
  • silicon oxide film SiO 2 film
  • the thickness of the silicon oxide film may be about 1 to 2 ⁇ m, for example.
  • the first adhesion layer 13 is formed on the one surface 11 a of the substrate body 11 at a position around each of the through holes 11 x and further extends on the inner side surface of each of the through holes 11 x , via the insulating layer 12 .
  • the first adhesion layer 13 is stacked on the inner side surface of the through hole 11 x at about a half portion of the inner side surface at the one surface 11 a side, via the insulating layer 12 .
  • the first adhesion layer 13 is made of a material whose adhesion to the insulating layer 12 is better than that of the first metal layer 14 .
  • the thickness of the first adhesion layer 13 that is formed on the one surface 11 a of the substrate body 11 is about 0.2 to 5 ⁇ m, for example.
  • the thickness of the first adhesion layer 13 that is formed on the inner side surface of each of the through holes 11 x may become thinner as it approaches a deeper portion of the through hole 11 x from the one surface 11 a side of the substrate body 11 .
  • the first metal layer 14 is stacked on the first adhesion layer 13 .
  • the first adhesion layer 13 is formed between the substrate body 11 and the first metal layer 14 .
  • a front end portion of the first metal layer 14 may be directly formed on the insulating layer 12 , without interposing the first adhesion layer 13 , in the vicinity of the center portion of the inner side surface of the through hole 11 x.
  • the material of the first metal layer 14 may be copper (Cu), for example.
  • the thickness of the first metal layer 14 that is stacked on the first adhesion layer 13 on the one surface 11 a of the substrate body 11 may be about 0.2 to 5 ⁇ m, for example.
  • the thickness of the first metal layer 14 that is formed at the inner side surface of the through hole 11 x may become thinner as it approaches a deeper portion in the through hole 11 x from the one surface 11 a side of the substrate body 11 .
  • the material for the first adhesion layer 13 may be titanium (Ti), tantalum (Ta), chromium (Cr), titanium tungsten (TiW) or the like, whose adhesion to the silicon oxide film is better than that of copper, for example.
  • the material for the substrate body 11 is silicon
  • the insulating layer 12 is a silicon oxide film and the material for the first metal layer 14 is copper (Cu)
  • adhesion between the silicon oxide film and copper is not good.
  • the silicon oxide and copper can be appropriately adhered with each other via the first adhesion layer 13 .
  • the first wiring layer 15 has a stacked structure of a second conductive layer 15 b and a first conductive layer 15 a at the one surface 11 a side of the substrate body 11 .
  • the first wiring layer 15 includes a pad portion having a plan shape of a substantially circular shape formed on and around each of the through holes 11 x on the one surface 11 a of the substrate body 11 , for example.
  • the first wiring layer 15 may include a pattern portion that is patterned into a predetermined shape on the one surface 11 a of the substrate body 11 in addition to the pad portions.
  • the first wiring layer 15 formed in each of the through holes 11 x covers the first metal layer 14 to fill the one surface 11 a side of the through hole 11 x.
  • the first conductive layer 15 a is formed on the first metal layer 14 at the one surface 11 a side of the substrate body 11 to fill one end side (the one surface 11 a side) of the through hole 11 x .
  • the first conductive layer 15 a is provided with a concave portion 15 x .
  • copper (Cu) or the like may be used, for example.
  • the thickness of the first conductive layer 15 a that is formed on the one surface 11 a of the substrate body 11 may be about 5 to 30 ⁇ m, for example.
  • the second conductive layer 15 b is formed on the first metal layer 14 at the inner side surface of the through hole 11 x such that to fill about a half portion of the through hole 11 x at the upper side.
  • the second conductive layer 15 b contacts a lower end surface of the first conductive layer 15 a and is formed to fill about a half portion of the through hole 11 x at the one surface 11 a .
  • the second conductive layer 15 b is provided with a concave portion 15 y at an end portion at the other surface 11 b side open to the other surface 11 b side.
  • copper (Cu) or the like may be used, for example.
  • a front end portion of the second conductive layer 15 b may be directly formed on the insulating layer 12 without interposing the first adhesion layer 13 and the first metal layer 14 in the vicinity of the center portion of the inner side surface of the through hole 11 x.
  • the second adhesion layer 23 is formed on the other surface 11 b at a position around each of the through holes 11 x and further extends on the inner side surface of each of the through holes 11 x , via the insulating layer 12 .
  • the second adhesion layer 23 is stacked on the inner side surface of the through hole 11 x at about a half portion at the lower side via the insulating layer 12 .
  • the second adhesion layer 23 further extends to stack on a lower end surface of the second conductive layer 15 b including the inner side surface and the inner bottom surface of the concave portion 15 y .
  • the second adhesion layer 23 is made of a material whose adhesion to the insulating layer 12 is better than that of the second metal layer 24 .
  • the thickness of the second adhesion layer 23 that is formed on the other surface 11 b of the substrate body 11 may be about 0.2 to 5 ⁇ m, for example.
  • the thickness of the second adhesion layer 23 that is formed on the inner side surface of the through hole 11 x may become thinner as it approaches a deeper portion of the through hole 11 x from the other surface 11 b side of the substrate body 11 .
  • the second adhesion layer 23 and the first adhesion layer 13 are not directly connected (not in contact with each other).
  • the second metal layer 24 is stacked on the second adhesion layer 23 .
  • the second adhesion layer 23 is formed between the substrate body 11 and the second metal layer 24 , and between an end portion of the first wiring layer 15 at the other surface 11 b side and the second metal layer 24 .
  • a front end portion of the second metal layer 24 may be directly formed on the insulating layer 12 , without intervening the second adhesion layer 23 , in the vicinity of the center portion of the inner side surface of the through hole 11 x.
  • the material of the second metal layer 24 may be copper (Cu), for example.
  • the thickness of the second metal layer 24 that is stacked on the second adhesion layer 23 on the other surface 11 b of the substrate body 11 may be about 0.2 to 5 ⁇ m, for example.
  • the thickness of the second metal layer 24 formed at the inner side surface of the through hole 11 x may become thinner as it approaches a deeper portion of the through hole 11 x from the other surface 11 b side of the substrate body 11 .
  • the material for the second adhesion layer 23 may be titanium (Ti), tantalum (Ta), chromium (Cr), titanium tungsten (TiW) or the like, whose adhesion to the silicon oxide film is better than that of copper, for example.
  • the material for the substrate body 11 is silicon
  • the insulating layer 12 is a silicon oxide film and the material for the second metal layer 24 is copper (Cu)
  • adhesion between the silicon oxide film and copper is not good.
  • the second adhesion layer 23 made of the above described material the silicon oxide film and copper can be appropriately adhered with each other via the second adhesion layer 23 .
  • the second wiring layer 25 is formed on the other surface 11 b side of the substrate body 11 .
  • the second wiring layer 25 includes a pad portion having a plan shape of a substantially circular shape formed on and around each of the through holes 11 x on the other surface 11 b of the substrate body 11 , for example.
  • the second wiring layer 25 may include a pattern portion that is patterned into a predetermined shape on the other surface 11 b of the substrate body 11 in addition to the pad portions.
  • the second wiring layer 25 formed in the through hole 11 x covers the second metal layer 24 to fill other surface 11 b side of the through hole 11 x.
  • the second wiring layer 25 is formed on the second metal layer 24 and extends in the through hole 11 x from the other surface 11 b of the substrate body 11 to fill about a half portion of the through hole 11 x at the lower side.
  • the material of the second wiring layer 25 copper (Cu) or the like may be used, for example.
  • the thickness of the second wiring layer 25 formed on the other surface 11 b of the substrate body 11 may be about 5 to 30 ⁇ m, for example.
  • the second wiring layer 25 is electrically connected to the first wiring layer 15 via the second adhesion layer 23 and the second metal layer 24 in each of the through holes 11 x .
  • the first wiring layer 15 and the second wiring layer 25 provided in each of the through holes 11 x is referred to as a through wiring.
  • the second wiring layer 25 is provided with a protruding portion 25 x at an end portion at the one surface 11 a side (at the first wiring layer 15 side) protruding toward the one surface 11 a side.
  • the protruding portion 25 x fits in the concave portion 15 y .
  • the protruding portion 25 x fits in the concave portion 15 y to form a caulking status in each of the through holes 11 x , and contacting area between the first wiring layer 15 and the second wiring layer 25 in each of the through holes 11 x via the second adhesion layer 23 and the second metal layer 24 becomes large, the first wiring layer 15 and the second wiring layer 25 are bonded with a high intensity.
  • FIG. 2A to FIG. 5 are views illustrating an example of manufacturing steps of the wiring board 1 of the first embodiment.
  • a peripheral portion of the wiring board 1 around one of the through holes 11 x is exemplified in an enlarged manner.
  • the substrate body 11 is prepared. Then, the through holes 11 x each penetrating the one surface 11 a to the other surface 11 b of the substrate body 11 are formed. Thereafter, the insulating layer 12 is formed on the entire surface of the substrate body 11 including the inner side surfaces of the through holes 11 x .
  • a silicon wafer having a size of 6 inches (about 150 mm), 8 inches (about 200 mm), 12 inches (about 300 mm) or the like may be used, for example.
  • the thickness of the silicon wafer may be 0.625 mm (for 6 inches size), 0.725 mm (for 8 inches size), 0.775 mm (for 12 inches size) or the like.
  • the substrate body 11 may be made thinner (100 to 200 ⁇ m, for example) by a backside grinder or the like.
  • the through holes 11 x may be formed by forming a resist layer (not illustrated in the drawings) provided with openings corresponding to the through holes 11 x , and etching the substrate body 11 using the resist layer (not illustrated in the drawings) as a mask.
  • anisotropic etching such as Deep Reactive Ion Etching (DRIE) using SF 6 (sulfur hexafluoride), for example, may be used.
  • the plan shape of the through hole 11 x may be a circular shape having a diameter of about 20 to 40 ⁇ m, for example. When the diameter of the through hole 11 x is 20 ⁇ m and the thickness of the substrate body 11 is 200 ⁇ m, the aspect ratio (ratio of the depth with respect to the diameter) of the through hole 11 x is 10, for example.
  • a silicon oxide film (SiO 2 film) may be used, for example.
  • the silicon oxide film may be formed by thermally oxidizing the surface of the substrate body 11 by a wet thermal oxidation method in which the surface of the substrate body 11 is heated to more than or equal to 1000° C., for example.
  • the thickness of the silicon oxide film may be about 1 to 2 ⁇ m, for example.
  • the first adhesion layer 13 and the first metal layer 14 are formed in this order from the one surface 11 a side of the substrate body 11 by sputtering or the like, for example.
  • the first adhesion layer 13 and the first metal layer 14 are stacked on the one surface 11 a of the substrate body 11 and further extend on the inner side surface of each of the through holes 11 x , via the insulating layer 12 .
  • the first adhesion layer 13 and the first metal layer 14 are formed such that the first adhesion layer 13 and the first metal layer 14 exist at about a half portion of the through hole 11 x at the upper side on the inner side surface of the through hole 11 x via the insulating layer 12 . Further, a front end portion of the first metal layer 14 may be directly formed on the insulating layer 12 , without intervening the first adhesion layer 13 , at an area A that is in the vicinity of the center portion of the inner side surface of the through hole 11 x.
  • the insulating layer 12 is silicon oxide film and the material of the first metal layer 14 is copper (Cu), for the material of the first adhesion layer 13 , titanium (Ti), tantalum (Ta), chromium (Cr), titanium tungsten (TiW) or the like may be used, for example.
  • the thickness of the first adhesion layer 13 that is formed on the one surface 11 a of the substrate body 11 may be about 0.2 to 5 ⁇ m, for example.
  • the thickness of the first metal layer 14 that is stacked on the first adhesion layer 13 on the one surface 11 a of the substrate body 11 may be about 0.2 to 5 ⁇ m, for example.
  • the insulating layer 12 is silicon oxide film and the material of the first metal layer 14 is copper (Cu)
  • adhesion between the silicon oxide film and copper is not good.
  • the first adhesion layer 13 by forming the first adhesion layer 13 by titanium (Ti) or the like, the silicon oxide film and copper can be appropriately adhered via the first adhesion layer 13 .
  • a protection film 100 is laminated on the one surface 11 a of the substrate body 11 via the first adhesion layer 13 and the first metal layer 14 so as to block an end portion of each of the through holes 11 x at the one surface 11 a side.
  • a resin film or the like may be used, for example. Further, a part of the protection film 100 may protrude in each of the through holes 11 x.
  • liquid resin or the like is coated on the other surface 11 b of the substrate body 11 and in the through holes 11 x by a spin coat method, a spray coat method or the like, for example. Then the liquid resin or the like is cured by heating at a predetermined temperature. With this operation, a resist layer 110 is formed that continuously covers the inner side surface of each of the through holes 11 x at the other surface 11 b side, the first metal layer 14 and a portion of the protection film 100 that is exposed in the through hole 11 x . Alternatively, the resist layer 110 may be formed to fill the through holes 11 x.
  • the protection film 100 is removed to expose a portion of the resist layer 110 from an end portion of each of the through holes 11 x at the one surface 11 a side.
  • the protection film 100 may be removed by dissolving with organic solvent that can selectively dissolve the protection film 100 and does not dissolve the resist layer 110 , for example.
  • the protection film 100 may be mechanically peeled or the like, for example.
  • the first conductive layer 15 a that is a part of the first wiring layer 15 , is formed on the first metal layer 14 and the portion of the resist layer 110 that is exposed from the end portion of each of the through holes 11 x at the one surface 11 a .
  • the first conductive layer 15 a may be formed by electrolytic plating in which plating solution is supplied from the one surface 11 a side of the substrate body 11 and using the first metal layer 14 as a power supply layer, for example.
  • copper (Cu) or the like may be used, for example.
  • the thickness of the first conductive layer 15 a that is formed on the one surface 11 a of the substrate body 11 may be about 5 to 30 ⁇ m, for example.
  • the first conductive layer 15 a isotropically grows from the first metal layer 14 by conformal plating, the first conductive layer 15 a is provided with the concave portion 15 x at an upper portion of an area overlapping each of the through holes 11 x , in a plan view.
  • the resist layer 110 is removed.
  • the resist layer 110 may be removed by dissolving with organic solvent, for example.
  • the second conductive layer 15 b that is also a part of the first conductive layer 15 a , is formed on the first conductive layer 15 a at the other surface 11 b side such that to fill the one surface 11 a of each of the through holes 11 x .
  • the second conductive layer 15 b may be formed by electrolytic plating in which plating solution is supplied from the other surface 11 b side of the substrate body 11 and using the first metal layer 14 as a power supply layer.
  • copper (Cu) or the like may be used, for example.
  • the second conductive layer 15 b is formed to fill about a half portion of each of the through holes 11 x at the upper side.
  • the second conductive layer 15 b isotropically grows from the first metal layer 14 by conformal plating, in each of the through holes 11 x , the second conductive layer 15 b is provided with a concave portion 15 y at an end portion at the other surface 11 b side open to the other surface 11 b side. Further, a front end portion of the second conductive layer 15 b may be directly formed on the insulating layer 12 without intervening the first adhesion layer 13 and the first metal layer 14 in the vicinity of the center portion of the inner side surface of the through hole 11 x . With this step, the first wiring layer 15 that covers the first metal layer 14 and fills the one surface 11 a side of each of the through holes 11 x is formed.
  • the second adhesion layer 23 and the second metal layer 24 are formed in this order from the other surface 11 b side of the substrate body 11 by sputtering or the like, for example.
  • the second adhesion layer 23 and the second metal layer 24 are stacked on the other surface 11 b of the substrate body 11 and further extend on the inner side surface of each of the through holes 11 x , via the insulating layer 12 .
  • the second adhesion layer 23 and the second metal layer 24 are formed such that the second adhesion layer 23 and the second metal layer 24 exist at about a half portion of the through hole 11 x at the lower side on the insulating layer 12 .
  • the second adhesion layer 23 and the second metal layer 24 further extend to be continuously stacked on the lower end surface of the second conductive layer 15 b including the inner side surface and the inner bottom surface of the concave portion 15 y formed at the end portion of the first wiring layer 15 at the other surface 11 b side.
  • the second adhesion layer 23 and the first adhesion layer 13 do not directly connected (not in contact with each other).
  • the materials, the thicknesses and the like of the second adhesion layer 23 and the second metal layer 24 may be the same as those of the first adhesion layer 13 and the first metal layer 14 , for example.
  • the insulating layer 12 is a silicon oxide film and the material of the second metal layer 24 is copper (Cu)
  • adhesion between the silicon oxide film and copper is not good.
  • the second adhesion layer 23 made of titanium (Ti) or the like, the silicon oxide film and copper can be appropriately adhered with each other via the second adhesion layer 23 .
  • the second wiring layer 25 is formed on a lower side of the second conductive layer 15 b by electrolytic plating in which plating solution is supplied from the other surface 11 b side of the substrate body 11 and using the second metal layer 24 as a power supply layer, for example.
  • the second wiring layer 25 is formed to cover the second adhesion layer 23 and the second metal layer 24 and fill the other surface 11 b side of each of the through holes 11 x (about a half portion of the through hole 11 x at the lower side).
  • the second wiring layer 25 is electrically connected to the first wiring layer 15 via the second adhesion layer 23 and the second metal layer 24 .
  • the second wiring layer 25 is provided with a protruding portion 25 x at an end portion at the one surface 11 a side protruding toward the one surface 11 a side.
  • the protruding portion 25 x fits in the concave portion 15 y .
  • the first wiring layer 15 and the second wiring layer 25 are patterned into predetermined plan shapes by a subtractive process or the like, and the silicon wafer (the substrate body 11 ) is divided into chips to obtain the wiring board 1 as illustrated in FIG. 1 .
  • the first metal layer 14 made of copper is adhered to the inner side surface of the through hole 11 x via the first adhesion layer 13 .
  • the second metal layer 24 made of copper is adhered to the inner side surface of the through hole 11 x via the second adhesion layer 23 .
  • the protruding portion 25 x of the second wiring layer 25 fits in the concave portion 15 y of the first wiring layer 15 to form a caulking status in each of the through holes 11 x , and contacting area between the first wiring layer 15 and the second wiring layer 25 in each of the through holes 11 x via the second adhesion layer 23 and the second metal layer 24 becomes large, the first wiring layer 15 and the second wiring layer 25 are bonded with a high intensity.
  • the likelihood that the metal layers 14 and 24 are removed from the inner side surface of the through hole 11 x to cause the conductive failure of the through wiring can be reduced.
  • the first adhesion layer 13 and the first metal layer 14 are formed at the one surface 11 a of the substrate body 11 via an insulating layer such as polyimide or the like.
  • an insulating layer such as polyimide or the like.
  • a crack is generated at a portion of the insulating layer such as polyimide or the like that contacts copper (Cu) due to the pumping phenomenon of copper.
  • the likelihood of the generation of the crack at the portion of the insulating layer such as polyimide or the like that contacts copper (Cu) can be reduced. This is the same for the case when forming the second adhesion layer 23 and the second metal layer 24 on the other surface 11 b of the substrate body 11 via an insulating layer such as polyimide or the like.
  • the first wiring layer 15 and the second wiring layer 25 which are formed in different plating steps, compose the through wiring formed in the through hole 31 x .
  • the through wiring that is necessarily formed by a single plating step is about a half of the depth of the through hole 11 x .
  • a high aspect ratio through hole whose aspect ratio is 10, for example
  • FIG. 6 is a cross-sectional view illustrating an example of a wiring board 2 of the second embodiment.
  • the wiring board 2 is different from the wiring board 1 (see FIG. 1 ) in that the substrate body 11 is substituted by a substrate body 31 .
  • the substrate body 31 is a base member obtained by impregnating a glass cloth base member in epoxy resin, for example.
  • the thickness of the substrate body 31 may be about 0.2 to 1.6 mm, for example.
  • the substrate body 31 is an insulating material, the insulating layer 12 is not formed on surfaces of the substrate body 31 .
  • first adhesion layer 13 is not provided and the first metal layer 14 made of copper is directly formed on one surface 31 a of the substrate body 31 and on an inner wall surface of each through hole 31 x .
  • second adhesion layer 23 is not provided, and the second metal layer 24 made of copper is directly formed on another surface 31 b of the substrate body 31 and on an inner wall surface of each of the through holes 31 x .
  • the metal layers 14 and 24 made of copper adhere relatively well to the substrate body 31 that is the base member including the resin as a main constituent, the first adhesion layer 13 and the second adhesion layer 23 are not provided.
  • a base member including resin as a main constituent is prepared as the substrate body 31 .
  • the through holes 31 x are formed in the substrate body 31 by drilling, laser processing or the like.
  • steps similar to those explained with reference to FIG. 2B to FIG. 5 in the first embodiment are performed.
  • the steps of forming the insulating layer 12 , the first adhesion layer 13 and the second adhesion layer 23 are unnecessary in this embodiment.
  • the base member including resin as a main constituent may be used as the substrate body instead of silicon.
  • the metal layers 14 and 24 made of copper and the substrate body 31 that is the base member including resin as a main constituent adhere relatively well with each other.
  • the pumping phenomenon of copper can be suppressed to a certain extent.
  • the structure providing the protruding portion 25 x and the concave portion 15 y the pumping phenomenon of copper can be further suppressed.
  • the first wiring layer 15 and the second wiring layer 25 which are formed in different plating steps, compose the through wiring formed in the through hole 31 x .
  • the through wiring that is necessarily formed by a single plating step is about a half of the depth of the through hole 11 x .
  • a high aspect ratio through hole whose aspect ratio is 10, for example
  • a wiring board or the like can be provided in which conductive failure of a through wiring is suppressed and generation of defect such as a seam, a void or the like in the through wiring is also suppressed.
  • glass may be used instead of silicon, for example.
  • the glass is an insulating material, it is unnecessary to form the insulating layer 12 .
  • the pumping phenomenon of copper can be suppressed by the first and second embodiments.
  • a metal other than copper is used for the seed layer and the wiring layer
  • the pumping phenomenon of such a metal can be suppressed.
  • copper alloy is used for the seed layer and the wiring layer
  • the pumping phenomenon of copper alloy can be suppressed.
  • a method of manufacturing a wiring board comprising:
  • the forming the first wiring layer includes,
  • the second conductive layer of the first wiring layer in the through hole is provided with a concave portion that is open toward the other surface side at an end portion at the other surface side by conformal plating, and
  • the second wiring layer in the through hole is provided with a protruding portion that protrudes toward the one surface side at an end portion at the one surface side, the protruding portion fitting in the concave portion.
  • first metal layer and the second metal layer are formed by sputtering.

Abstract

A wiring board includes a substrate body provided with a through hole penetrating the substrate body from one surface to another surface; and a through wiring formed in the through hole and including a first metal layer formed on a part of an inner side surface of the through hole at the one surface side, a first wiring layer that covers the first metal layer to fill a part of the through hole at the one surface side, a second metal layer continuously formed on the rest part of the inner side surface of the through hole at the other surface side and on an end portion of the first wiring layer at the other surface side, and a second wiring layer that covers the second metal layer to fill a part of the through hole at the other surface side.

Description

CROSS-REFERENCE TO RELATED APPLICATION
The present application is based on and claims the benefit of priority of Japanese Priority Application No. 2013-200631 filed on Sep. 26, 2013, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wiring board.
2. Description of the Related Art
Conventionally, in order to form a through wiring in a silicon substrate, a bottom-up plating process using a conductive layer as an electrode has been used, for example. Specifically, first, a film conductive layer is formed at a lower side of the silicon substrate. Then, copper (Cu) is deposited in a through hole provided in the silicon substrate by electrolytic plating process using the conductive layer as a seed layer (see Patent Document 1, for example).
However, in such a method, the copper (Cu) deposited in the through hole just contacts an inner side surface of the through hole but does not adhere to the inner side surface. Thus, when the silicon substrate is repeatedly used in high temperature environment or low temperature environment, pumping phenomenon of copper (expansion and contraction due to temperature variation) is generated due to the difference between coefficients of thermal expansion of silicon and copper. Then, copper is removed from the inner side surface of the through hole to cause a conductive failure of the through wiring.
In order to solve such a problem, a method of forming a through wiring is known in which an insulating layer is formed on a surface of a silicon substrate including an inner side surface of a through hole, a seed layer whose adhesion to the insulating layer is good is formed on the surface of the silicon substrate including the inner side surface of the through hole, and then the through wiring is formed in the through hole by filling plating. With this method, the pumping phenomenon of the copper may be suppressed and the likelihood that the copper is removed from the inner side surface of the through hole to cause the conductive failure of the through wiring can be reduced. However, there is a problem in that the likelihood of generation of a defect such as a seam, a void, or the like, in the through wiring is increased. The likelihood of such generation of the defect becomes high when the aspect ratio of the through hole becomes high.
PATENT DOCUMENT
[Patent Document 1] Japanese Laid-open Patent Publication No. 2005-11987
SUMMARY OF THE INVENTION
The present invention is made in light of the above problems, and provides a wiring board or the like in which conductive failure of a through wiring is suppressed and generation of defect such as a seam, a void or the like in the through wiring is also suppressed.
According to an embodiment, there is provided a wiring board including a substrate body provided with a through hole penetrating the substrate body from one surface to another surface of the substrate body; and a through wiring formed in the through hole and including a first metal layer that is formed on a part of an inner side surface of the through hole at the one surface side, a first wiring layer that covers the first metal layer to fill a part of the through hole at the one surface side, a second metal layer that is continuously formed on the rest part of the inner side surface of the through hole at the other surface side and on an end portion of the first wiring layer at the other surface side, and a second wiring layer that covers the second metal layer to fill a part of the through hole at the other surface side, the first wiring layer and the second wiring layer being electrically connected in the through hole via the second metal layer.
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.
FIG. 1 is a cross-sectional view illustrating an example of a wiring board of a first embodiment;
FIG. 2A to FIG. 2C are views illustrating an example of manufacturing steps of the wiring board of the first embodiment;
FIG. 3A to FIG. 3C are views illustrating an example of manufacturing steps of the wiring board of the first embodiment;
FIG. 4A to FIG. 4C are views illustrating an example of manufacturing steps of the wiring board of the first embodiment;
FIG. 5 is a view illustrating an example of a manufacturing step of the wiring board of the first embodiment;
FIG. 6 is a cross-sectional view illustrating an example of a wiring board of a second embodiment.
 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The invention will be described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.
It is to be noted that, in the explanation of the drawings, the same components are given the same reference numerals, and explanations are not repeated.
First Embodiment Structure of Wiring Board of First Embodiment
First, a structure of a wiring board 1 of the first embodiment is explained. FIG. 1 is a cross-sectional view illustrating an example of the wiring board 1 of the first embodiment. With reference to FIG. 1, the wiring board 1 includes a substrate body 11, an insulating layer 12, a first adhesion layer 13, a first metal layer 14, a first wiring layer 15, a second adhesion layer 23, a second metal layer 24 and a second wiring layer 25.
In this embodiment, a first wiring layer 15 side is referred to as an upper side or one side, and a second wiring layer 25 side is referred to as a lower side or the other side. Further, a surface of each components at the first wiring layer 15 side is referred to as an upper surface or one surface, and a surface at the second wiring layer 25 side is referred to as a lower surface or the other surface. However, the wiring board 1 may be used in an opposite direction or may be used at an arbitrarily angle. Further, in this embodiment, “in a plan view” means that an object is seen in a direction that is normal to one surface 11 a of the substrate body 11, and a “plan shape” means a shape of an object seen in the direction that is normal to the one surface 11 a of the substrate body 11.
The substrate body 11 is a base portion for forming the first wiring layer 15 and the like in the wiring board 1 and the substrate body 11 is provided with through holes 11 x. The thickness of the substrate body 11 may be about 100 to 200 μm, for example. For the material of the substrate body 11, silicon, glass, resin or the like may be used.
By mounting a semiconductor chip on the wiring board 1, a semiconductor package can be obtained. In such a case, as many of semiconductor chips include a silicon substrate, for the material of the substrate body 11, silicon, or borosilicate glass whose coefficient of thermal expansion is close to that of silicon may be used, in viewpoint of conforming coefficients of thermal expansion. The borosilicate glass is a glass containing boric acid (B2O3) and silic acid (SiO2) as a main constituent and having a coefficient of thermal expansion about 3 ppm/° C. Further, in viewpoint of processability, silicon may be used for the material of the substrate body 11.
The reason for conforming the coefficient of thermal expansion of the substrate body 11 with the coefficient of thermal expansion of the semiconductor chip is to reduce thermal stress generated at a contacting portion of the wiring board 1 and the semiconductor chip in both high temperature environment and low temperature environment. Hereinafter, in this embodiment, an example in which the material for the substrate body 11 is silicon is explained.
Each of the through holes 11 x is a so-called through silicon via (TSV) that is provided to penetrate the one surface 11 a to the other surface 11 b of the substrate body 11. Each of the through holes 11 x has a substantially circular shape in a plan view, for example. The diameter of the through hole 11 x may be about 20 to 40 μm, for example. Although two through holes 11 x are illustrated in FIG. 1, the number of through holes 11 x provided in the substrate body 11 may be arbitrarily determined.
The insulating layer 12 is formed to continuously cover the one surface 11 a and the other surface 11 b of the substrate body 11 and the inner side surfaces of the through holes 11 x. The insulating layer 12 is provided to electrically insulate the substrate body 11 from the first adhesion layer 13, the first metal layer 14, the first wiring layer 15, the second adhesion layer 23, the second metal layer 24 and the second wiring layer 25. For the insulating layer 12, silicon oxide film (SiO2 film) may be used, for example. The thickness of the silicon oxide film may be about 1 to 2 μm, for example.
The first adhesion layer 13 is formed on the one surface 11 a of the substrate body 11 at a position around each of the through holes 11 x and further extends on the inner side surface of each of the through holes 11 x, via the insulating layer 12. In each of the through holes 11 x, the first adhesion layer 13 is stacked on the inner side surface of the through hole 11 x at about a half portion of the inner side surface at the one surface 11 a side, via the insulating layer 12. The first adhesion layer 13 is made of a material whose adhesion to the insulating layer 12 is better than that of the first metal layer 14. The thickness of the first adhesion layer 13 that is formed on the one surface 11 a of the substrate body 11 is about 0.2 to 5 μm, for example. The thickness of the first adhesion layer 13 that is formed on the inner side surface of each of the through holes 11 x may become thinner as it approaches a deeper portion of the through hole 11 x from the one surface 11 a side of the substrate body 11.
The first metal layer 14 is stacked on the first adhesion layer 13. In other words, the first adhesion layer 13 is formed between the substrate body 11 and the first metal layer 14. A front end portion of the first metal layer 14 may be directly formed on the insulating layer 12, without interposing the first adhesion layer 13, in the vicinity of the center portion of the inner side surface of the through hole 11 x.
The material of the first metal layer 14 may be copper (Cu), for example. The thickness of the first metal layer 14 that is stacked on the first adhesion layer 13 on the one surface 11 a of the substrate body 11 may be about 0.2 to 5 μm, for example. The thickness of the first metal layer 14 that is formed at the inner side surface of the through hole 11 x may become thinner as it approaches a deeper portion in the through hole 11 x from the one surface 11 a side of the substrate body 11.
The material for the first adhesion layer 13 may be titanium (Ti), tantalum (Ta), chromium (Cr), titanium tungsten (TiW) or the like, whose adhesion to the silicon oxide film is better than that of copper, for example. When the material for the substrate body 11 is silicon, the insulating layer 12 is a silicon oxide film and the material for the first metal layer 14 is copper (Cu), adhesion between the silicon oxide film and copper is not good. However, by providing the first adhesion layer 13 made of the above described material, the silicon oxide and copper can be appropriately adhered with each other via the first adhesion layer 13.
The first wiring layer 15 has a stacked structure of a second conductive layer 15 b and a first conductive layer 15 a at the one surface 11 a side of the substrate body 11. The first wiring layer 15 includes a pad portion having a plan shape of a substantially circular shape formed on and around each of the through holes 11 x on the one surface 11 a of the substrate body 11, for example. The first wiring layer 15 may include a pattern portion that is patterned into a predetermined shape on the one surface 11 a of the substrate body 11 in addition to the pad portions. The first wiring layer 15 formed in each of the through holes 11 x covers the first metal layer 14 to fill the one surface 11 a side of the through hole 11 x.
The first conductive layer 15 a is formed on the first metal layer 14 at the one surface 11 a side of the substrate body 11 to fill one end side (the one surface 11 a side) of the through hole 11 x. The first conductive layer 15 a is provided with a concave portion 15 x. For the material of the first conductive layer 15 a, copper (Cu) or the like may be used, for example. The thickness of the first conductive layer 15 a that is formed on the one surface 11 a of the substrate body 11 may be about 5 to 30 μm, for example.
The second conductive layer 15 b is formed on the first metal layer 14 at the inner side surface of the through hole 11 x such that to fill about a half portion of the through hole 11 x at the upper side. In other words, the second conductive layer 15 b contacts a lower end surface of the first conductive layer 15 a and is formed to fill about a half portion of the through hole 11 x at the one surface 11 a. The second conductive layer 15 b is provided with a concave portion 15 y at an end portion at the other surface 11 b side open to the other surface 11 b side. For the material of the second conductive layer 15 b, copper (Cu) or the like may be used, for example. Further, a front end portion of the second conductive layer 15 b may be directly formed on the insulating layer 12 without interposing the first adhesion layer 13 and the first metal layer 14 in the vicinity of the center portion of the inner side surface of the through hole 11 x.
The second adhesion layer 23 is formed on the other surface 11 b at a position around each of the through holes 11 x and further extends on the inner side surface of each of the through holes 11 x, via the insulating layer 12. In each of the through holes 11 x, the second adhesion layer 23 is stacked on the inner side surface of the through hole 11 x at about a half portion at the lower side via the insulating layer 12. The second adhesion layer 23 further extends to stack on a lower end surface of the second conductive layer 15 b including the inner side surface and the inner bottom surface of the concave portion 15 y. The second adhesion layer 23 is made of a material whose adhesion to the insulating layer 12 is better than that of the second metal layer 24. The thickness of the second adhesion layer 23 that is formed on the other surface 11 b of the substrate body 11 may be about 0.2 to 5 μm, for example. The thickness of the second adhesion layer 23 that is formed on the inner side surface of the through hole 11 x may become thinner as it approaches a deeper portion of the through hole 11 x from the other surface 11 b side of the substrate body 11. The second adhesion layer 23 and the first adhesion layer 13 are not directly connected (not in contact with each other).
The second metal layer 24 is stacked on the second adhesion layer 23. In other words, the second adhesion layer 23 is formed between the substrate body 11 and the second metal layer 24, and between an end portion of the first wiring layer 15 at the other surface 11 b side and the second metal layer 24. A front end portion of the second metal layer 24 may be directly formed on the insulating layer 12, without intervening the second adhesion layer 23, in the vicinity of the center portion of the inner side surface of the through hole 11 x.
The material of the second metal layer 24 may be copper (Cu), for example. The thickness of the second metal layer 24 that is stacked on the second adhesion layer 23 on the other surface 11 b of the substrate body 11 may be about 0.2 to 5 μm, for example. The thickness of the second metal layer 24 formed at the inner side surface of the through hole 11 x may become thinner as it approaches a deeper portion of the through hole 11 x from the other surface 11 b side of the substrate body 11.
The material for the second adhesion layer 23 may be titanium (Ti), tantalum (Ta), chromium (Cr), titanium tungsten (TiW) or the like, whose adhesion to the silicon oxide film is better than that of copper, for example. When the material for the substrate body 11 is silicon, the insulating layer 12 is a silicon oxide film and the material for the second metal layer 24 is copper (Cu), adhesion between the silicon oxide film and copper is not good. However, by providing the second adhesion layer 23 made of the above described material, the silicon oxide film and copper can be appropriately adhered with each other via the second adhesion layer 23.
The second wiring layer 25 is formed on the other surface 11 b side of the substrate body 11. The second wiring layer 25 includes a pad portion having a plan shape of a substantially circular shape formed on and around each of the through holes 11 x on the other surface 11 b of the substrate body 11, for example. The second wiring layer 25 may include a pattern portion that is patterned into a predetermined shape on the other surface 11 b of the substrate body 11 in addition to the pad portions. The second wiring layer 25 formed in the through hole 11 x covers the second metal layer 24 to fill other surface 11 b side of the through hole 11 x.
Specifically, the second wiring layer 25 is formed on the second metal layer 24 and extends in the through hole 11 x from the other surface 11 b of the substrate body 11 to fill about a half portion of the through hole 11 x at the lower side. For the material of the second wiring layer 25, copper (Cu) or the like may be used, for example. The thickness of the second wiring layer 25 formed on the other surface 11 b of the substrate body 11 may be about 5 to 30 μm, for example.
The second wiring layer 25 is electrically connected to the first wiring layer 15 via the second adhesion layer 23 and the second metal layer 24 in each of the through holes 11 x. Here, the first wiring layer 15 and the second wiring layer 25 provided in each of the through holes 11 x is referred to as a through wiring. The second wiring layer 25 is provided with a protruding portion 25 x at an end portion at the one surface 11 a side (at the first wiring layer 15 side) protruding toward the one surface 11 a side. The protruding portion 25 x fits in the concave portion 15 y. As the protruding portion 25 x fits in the concave portion 15 y to form a caulking status in each of the through holes 11 x, and contacting area between the first wiring layer 15 and the second wiring layer 25 in each of the through holes 11 x via the second adhesion layer 23 and the second metal layer 24 becomes large, the first wiring layer 15 and the second wiring layer 25 are bonded with a high intensity.
(Method of Manufacturing Wiring Board of First Embodiment)
Next, a method of manufacturing the wiring board 1 of the first embodiment is explained. FIG. 2A to FIG. 5 are views illustrating an example of manufacturing steps of the wiring board 1 of the first embodiment. In FIG. 2A to FIG. 5, a peripheral portion of the wiring board 1 around one of the through holes 11 x is exemplified in an enlarged manner.
First, in a step illustrated in FIG. 2A, the substrate body 11 is prepared. Then, the through holes 11 x each penetrating the one surface 11 a to the other surface 11 b of the substrate body 11 are formed. Thereafter, the insulating layer 12 is formed on the entire surface of the substrate body 11 including the inner side surfaces of the through holes 11 x. For the substrate body 11, a silicon wafer having a size of 6 inches (about 150 mm), 8 inches (about 200 mm), 12 inches (about 300 mm) or the like may be used, for example. The thickness of the silicon wafer may be 0.625 mm (for 6 inches size), 0.725 mm (for 8 inches size), 0.775 mm (for 12 inches size) or the like. However, the substrate body 11 may be made thinner (100 to 200 μm, for example) by a backside grinder or the like.
The through holes 11 x may be formed by forming a resist layer (not illustrated in the drawings) provided with openings corresponding to the through holes 11 x, and etching the substrate body 11 using the resist layer (not illustrated in the drawings) as a mask. For the etching, anisotropic etching such as Deep Reactive Ion Etching (DRIE) using SF6 (sulfur hexafluoride), for example, may be used. The plan shape of the through hole 11 x may be a circular shape having a diameter of about 20 to 40 μm, for example. When the diameter of the through hole 11 x is 20 μm and the thickness of the substrate body 11 is 200 μm, the aspect ratio (ratio of the depth with respect to the diameter) of the through hole 11 x is 10, for example.
For the insulating layer 12, a silicon oxide film (SiO2 film) may be used, for example. The silicon oxide film may be formed by thermally oxidizing the surface of the substrate body 11 by a wet thermal oxidation method in which the surface of the substrate body 11 is heated to more than or equal to 1000° C., for example. The thickness of the silicon oxide film may be about 1 to 2 μm, for example.
Next, in a step illustrated in FIG. 2B, the first adhesion layer 13 and the first metal layer 14 are formed in this order from the one surface 11 a side of the substrate body 11 by sputtering or the like, for example. The first adhesion layer 13 and the first metal layer 14 are stacked on the one surface 11 a of the substrate body 11 and further extend on the inner side surface of each of the through holes 11 x, via the insulating layer 12. In each of the through holes 11 x, the first adhesion layer 13 and the first metal layer 14 are formed such that the first adhesion layer 13 and the first metal layer 14 exist at about a half portion of the through hole 11 x at the upper side on the inner side surface of the through hole 11 x via the insulating layer 12. Further, a front end portion of the first metal layer 14 may be directly formed on the insulating layer 12, without intervening the first adhesion layer 13, at an area A that is in the vicinity of the center portion of the inner side surface of the through hole 11 x.
When the insulating layer 12 is silicon oxide film and the material of the first metal layer 14 is copper (Cu), for the material of the first adhesion layer 13, titanium (Ti), tantalum (Ta), chromium (Cr), titanium tungsten (TiW) or the like may be used, for example. The thickness of the first adhesion layer 13 that is formed on the one surface 11 a of the substrate body 11 may be about 0.2 to 5 μm, for example. The thickness of the first metal layer 14 that is stacked on the first adhesion layer 13 on the one surface 11 a of the substrate body 11 may be about 0.2 to 5 μm, for example. When the insulating layer 12 is silicon oxide film and the material of the first metal layer 14 is copper (Cu), adhesion between the silicon oxide film and copper is not good. However, by forming the first adhesion layer 13 by titanium (Ti) or the like, the silicon oxide film and copper can be appropriately adhered via the first adhesion layer 13.
Next, in a step illustrated in FIG. 2C, a protection film 100 is laminated on the one surface 11 a of the substrate body 11 via the first adhesion layer 13 and the first metal layer 14 so as to block an end portion of each of the through holes 11 x at the one surface 11 a side. For the protection film 100, a resin film or the like may be used, for example. Further, a part of the protection film 100 may protrude in each of the through holes 11 x.
Next, in a step illustrated in FIG. 3A, from the other surface 11 b side of the substrate body 11, liquid resin or the like is coated on the other surface 11 b of the substrate body 11 and in the through holes 11 x by a spin coat method, a spray coat method or the like, for example. Then the liquid resin or the like is cured by heating at a predetermined temperature. With this operation, a resist layer 110 is formed that continuously covers the inner side surface of each of the through holes 11 x at the other surface 11 b side, the first metal layer 14 and a portion of the protection film 100 that is exposed in the through hole 11 x. Alternatively, the resist layer 110 may be formed to fill the through holes 11 x.
Next, in a step illustrated in FIG. 3B, the protection film 100 is removed to expose a portion of the resist layer 110 from an end portion of each of the through holes 11 x at the one surface 11 a side. The protection film 100 may be removed by dissolving with organic solvent that can selectively dissolve the protection film 100 and does not dissolve the resist layer 110, for example. Alternatively, the protection film 100 may be mechanically peeled or the like, for example.
Next, in a step illustrated in FIG. 3C, the first conductive layer 15 a, that is a part of the first wiring layer 15, is formed on the first metal layer 14 and the portion of the resist layer 110 that is exposed from the end portion of each of the through holes 11 x at the one surface 11 a. The first conductive layer 15 a may be formed by electrolytic plating in which plating solution is supplied from the one surface 11 a side of the substrate body 11 and using the first metal layer 14 as a power supply layer, for example. For the material of the first conductive layer 15 a, copper (Cu) or the like may be used, for example. The thickness of the first conductive layer 15 a that is formed on the one surface 11 a of the substrate body 11 may be about 5 to 30 μm, for example. As the first conductive layer 15 a isotropically grows from the first metal layer 14 by conformal plating, the first conductive layer 15 a is provided with the concave portion 15 x at an upper portion of an area overlapping each of the through holes 11 x, in a plan view.
Next, in a step illustrated in FIG. 4A, the resist layer 110 is removed. The resist layer 110 may be removed by dissolving with organic solvent, for example.
Next, in a step illustrated in FIG. 4B, the second conductive layer 15 b, that is also a part of the first conductive layer 15 a, is formed on the first conductive layer 15 a at the other surface 11 b side such that to fill the one surface 11 a of each of the through holes 11 x. The second conductive layer 15 b may be formed by electrolytic plating in which plating solution is supplied from the other surface 11 b side of the substrate body 11 and using the first metal layer 14 as a power supply layer. For the material of the second conductive layer 15 b, copper (Cu) or the like may be used, for example. The second conductive layer 15 b is formed to fill about a half portion of each of the through holes 11 x at the upper side. As the second conductive layer 15 b isotropically grows from the first metal layer 14 by conformal plating, in each of the through holes 11 x, the second conductive layer 15 b is provided with a concave portion 15 y at an end portion at the other surface 11 b side open to the other surface 11 b side. Further, a front end portion of the second conductive layer 15 b may be directly formed on the insulating layer 12 without intervening the first adhesion layer 13 and the first metal layer 14 in the vicinity of the center portion of the inner side surface of the through hole 11 x. With this step, the first wiring layer 15 that covers the first metal layer 14 and fills the one surface 11 a side of each of the through holes 11 x is formed.
Next, in a step illustrated in FIG. 4C, the second adhesion layer 23 and the second metal layer 24 are formed in this order from the other surface 11 b side of the substrate body 11 by sputtering or the like, for example. The second adhesion layer 23 and the second metal layer 24 are stacked on the other surface 11 b of the substrate body 11 and further extend on the inner side surface of each of the through holes 11 x, via the insulating layer 12. In each of the through holes 11 x, the second adhesion layer 23 and the second metal layer 24 are formed such that the second adhesion layer 23 and the second metal layer 24 exist at about a half portion of the through hole 11 x at the lower side on the insulating layer 12. Further, the second adhesion layer 23 and the second metal layer 24 further extend to be continuously stacked on the lower end surface of the second conductive layer 15 b including the inner side surface and the inner bottom surface of the concave portion 15 y formed at the end portion of the first wiring layer 15 at the other surface 11 b side. The second adhesion layer 23 and the first adhesion layer 13 do not directly connected (not in contact with each other).
The materials, the thicknesses and the like of the second adhesion layer 23 and the second metal layer 24 may be the same as those of the first adhesion layer 13 and the first metal layer 14, for example. When the insulating layer 12 is a silicon oxide film and the material of the second metal layer 24 is copper (Cu), adhesion between the silicon oxide film and copper is not good. Thus, by providing the second adhesion layer 23 made of titanium (Ti) or the like, the silicon oxide film and copper can be appropriately adhered with each other via the second adhesion layer 23.
Next, in a step illustrated in FIG. 5, the second wiring layer 25 is formed on a lower side of the second conductive layer 15 b by electrolytic plating in which plating solution is supplied from the other surface 11 b side of the substrate body 11 and using the second metal layer 24 as a power supply layer, for example. The second wiring layer 25 is formed to cover the second adhesion layer 23 and the second metal layer 24 and fill the other surface 11 b side of each of the through holes 11 x (about a half portion of the through hole 11 x at the lower side). The second wiring layer 25 is electrically connected to the first wiring layer 15 via the second adhesion layer 23 and the second metal layer 24. Here, in each of the through holes 11 x, the second wiring layer 25 is provided with a protruding portion 25 x at an end portion at the one surface 11 a side protruding toward the one surface 11 a side. The protruding portion 25 x fits in the concave portion 15 y. Thereafter, the first wiring layer 15 and the second wiring layer 25 are patterned into predetermined plan shapes by a subtractive process or the like, and the silicon wafer (the substrate body 11) is divided into chips to obtain the wiring board 1 as illustrated in FIG. 1.
As such, according to the wiring board 1 of the first embodiment, the first metal layer 14 made of copper, for example, is adhered to the inner side surface of the through hole 11 x via the first adhesion layer 13. Further, the second metal layer 24 made of copper, for example, is adhered to the inner side surface of the through hole 11 x via the second adhesion layer 23. Thus, even when the wiring board 1 is repeatedly used in high temperature environment or low temperature environment, pumping phenomenon (expansion and contraction due to temperature variation) of copper can be suppressed compared with the conventional structure. Thus, the likelihood that the metal layers 14 and 24 are removed from the inner side surface of the through hole 11 x to cause the conductive failure of the through wiring can be reduced.
Further, as the protruding portion 25 x of the second wiring layer 25 fits in the concave portion 15 y of the first wiring layer 15 to form a caulking status in each of the through holes 11 x, and contacting area between the first wiring layer 15 and the second wiring layer 25 in each of the through holes 11 x via the second adhesion layer 23 and the second metal layer 24 becomes large, the first wiring layer 15 and the second wiring layer 25 are bonded with a high intensity. Thus, even when the pumping phenomenon of the copper slightly occurs, the likelihood that the metal layers 14 and 24 are removed from the inner side surface of the through hole 11 x to cause the conductive failure of the through wiring can be reduced.
Further, there may be a case in which the first adhesion layer 13 and the first metal layer 14 are formed at the one surface 11 a of the substrate body 11 via an insulating layer such as polyimide or the like. In such a case, there is a problem that a crack is generated at a portion of the insulating layer such as polyimide or the like that contacts copper (Cu) due to the pumping phenomenon of copper. However, in this embodiment, as the pumping phenomenon of copper can be suppressed, the likelihood of the generation of the crack at the portion of the insulating layer such as polyimide or the like that contacts copper (Cu) can be reduced. This is the same for the case when forming the second adhesion layer 23 and the second metal layer 24 on the other surface 11 b of the substrate body 11 via an insulating layer such as polyimide or the like.
Further, the first wiring layer 15 and the second wiring layer 25, which are formed in different plating steps, compose the through wiring formed in the through hole 31 x. In other words, the through wiring that is necessarily formed by a single plating step is about a half of the depth of the through hole 11 x. Thus, it is easy to fill plating metal in a through hole 11 x with a high aspect ratio (through hole whose aspect ratio is 10, for example) to form a through wiring without defect such as a seam, a void or the like. This means that the actual aspect ratio can be made half according to the method of manufacturing the through wiring of the embodiment.
Second Embodiment
In the second embodiment, an example is explained in which a base member including resin as a main constituent is used as the substrate body. It is to be noted that, in the explanation of the drawings, the same components are given the same reference numerals, and explanations are not repeated.
FIG. 6 is a cross-sectional view illustrating an example of a wiring board 2 of the second embodiment. With reference to FIG. 6, the wiring board 2 is different from the wiring board 1 (see FIG. 1) in that the substrate body 11 is substituted by a substrate body 31.
The substrate body 31 is a base member obtained by impregnating a glass cloth base member in epoxy resin, for example. The thickness of the substrate body 31 may be about 0.2 to 1.6 mm, for example. As the substrate body 31 is an insulating material, the insulating layer 12 is not formed on surfaces of the substrate body 31.
Further, the first adhesion layer 13 is not provided and the first metal layer 14 made of copper is directly formed on one surface 31 a of the substrate body 31 and on an inner wall surface of each through hole 31 x. Further, the second adhesion layer 23 is not provided, and the second metal layer 24 made of copper is directly formed on another surface 31 b of the substrate body 31 and on an inner wall surface of each of the through holes 31 x. As the metal layers 14 and 24 made of copper adhere relatively well to the substrate body 31 that is the base member including the resin as a main constituent, the first adhesion layer 13 and the second adhesion layer 23 are not provided.
In order to manufacture the wiring board 2, first, a base member including resin as a main constituent is prepared as the substrate body 31. Then, the through holes 31 x are formed in the substrate body 31 by drilling, laser processing or the like. Thereafter, steps similar to those explained with reference to FIG. 2B to FIG. 5 in the first embodiment are performed. Here, the steps of forming the insulating layer 12, the first adhesion layer 13 and the second adhesion layer 23 are unnecessary in this embodiment.
As such, the base member including resin as a main constituent may be used as the substrate body instead of silicon. In this case, the metal layers 14 and 24 made of copper and the substrate body 31 that is the base member including resin as a main constituent adhere relatively well with each other. Thus, the pumping phenomenon of copper can be suppressed to a certain extent. However, by the structure providing the protruding portion 25 x and the concave portion 15 y, the pumping phenomenon of copper can be further suppressed. This means that as the protruding portion 25 x of the second wiring layer 25 fits in the concave portion 15 y of the first wiring layer 15 to form a caulking status in each of the through holes 11 x, and contacting area between the first wiring layer 15 and the second wiring layer 25 in each of the through holes 11 x via the second metal layer 24 becomes large, the first wiring layer 15 and the second wiring layer 25 are bonded with a high intensity. Thus, even when the pumping phenomenon of the copper slightly occurs, the likelihood that the metal layers 14 and 24 are removed from the inner side surface of the through hole 11 x to cause the conductive failure of the through wiring can be reduced.
Further, the first wiring layer 15 and the second wiring layer 25, which are formed in different plating steps, compose the through wiring formed in the through hole 31 x. In other words, the through wiring that is necessarily formed by a single plating step is about a half of the depth of the through hole 11 x. Thus, it is easy to fill plating metal in a through hole 11 x with a high aspect ratio (through hole whose aspect ratio is 10, for example) to form a through wiring without defect such as a seam, a void or the like. This means that the actual aspect ratio can be made half according to the method of manufacturing the through wiring of the embodiment.
According to the embodiments, a wiring board or the like can be provided in which conductive failure of a through wiring is suppressed and generation of defect such as a seam, a void or the like in the through wiring is also suppressed.
Although a preferred embodiment of the wiring board and the method of manufacturing the wiring board has been specifically illustrated and described, it is to be understood that minor modifications may be made therein without departing from the spirit and scope of the invention as defined by the claims.
The present invention is not limited to the specifically disclosed embodiments, and numerous variations and modifications and modifications may be made without departing from the spirit and scope of the present invention.
In the first embodiment, for the material of the substrate body 11, glass may be used instead of silicon, for example. In this case, as the glass is an insulating material, it is unnecessary to form the insulating layer 12.
Further, as explained above, the pumping phenomenon of copper can be suppressed by the first and second embodiments. However, when a metal other than copper is used for the seed layer and the wiring layer, the pumping phenomenon of such a metal can be suppressed. For example, when copper alloy is used for the seed layer and the wiring layer, the pumping phenomenon of copper alloy can be suppressed.
Various aspects of the subject-matter described herein are set out non-exhaustively in the following numbered clauses:
1. A method of manufacturing a wiring board, comprising:
forming a through hole that penetrates one surface to another surface of a substrate body in the substrate body; and
forming a through wiring in the through hole, including
    • forming a first metal layer on an inner side surface of the through hole at the one surface side,
    • forming a first wiring layer on the first metal layer, which fills the one surface side of the through hole by electrolytic plating using the first metal layer as a power supply layer,
    • forming a second metal layer on an inner side surface of the through hole at the other surface side and on an end portion of the first wiring layer at the other surface side in a continuous manner, and
    • forming a second wiring layer on the second metal layer, which fills the other surface side of the through hole by electrolytic plating using the second metal layer as a power supply layer, the first wiring layer and the second wiring layer being electrically connected with each other via the second metal layer in the through hole.
2. The method of manufacturing the wiring board according to clause 1,
wherein the forming the first wiring layer includes,
    • forming a protection film at the one surface side of the substrate body that blocks the through hole at the one surface side,
    • forming a resist layer, from the other surface side, that continuously covers the inner side surface of the through hole, the first metal layer and a portion of the protection film that is exposed in the through hole,
    • removing the protection film to expose the resist layer from an end portion of the through hole at the one surface side,
    • forming a first conductive layer, from the one surface side, as a part of the first wiring layer on the resist layer exposed at the end portion of the through hole at the one surface side by electrolytic plating using the first metal layer as a power supply layer,
    • removing the resist layer to expose the first conductive layer in the through hole, and
    • forming a second conductive layer, from the other surface side, as another part of the first wiring layer on the first conductive layer such that to fill the one surface side of the through hole by electrolytic plating using the first metal layer as a power supply layer.
3. The method of manufacturing the wiring board according to clause 2,
wherein in the forming the first wiring layer, the second conductive layer of the first wiring layer in the through hole is provided with a concave portion that is open toward the other surface side at an end portion at the other surface side by conformal plating, and
wherein in the forming the second wiring layer, the second wiring layer in the through hole is provided with a protruding portion that protrudes toward the one surface side at an end portion at the one surface side, the protruding portion fitting in the concave portion.
4. The wiring board according to clause 1,
wherein the first metal layer and the second metal layer are formed by sputtering.

Claims (6)

What is claimed is:
1. A wiring board comprising:
a substrate body provided with a through hole penetrating the substrate body from one surface to another surface of the substrate body; and
a through wiring formed in the through hole and including
a first metal layer that is formed on a part of an inner side surface of the through hole at the one surface side,
a first wiring layer that covers the first metal layer to fill a part of the through hole at the one surface side,
a second metal layer that is continuously formed on the rest part of the inner side surface of the through hole at the other surface side and on an end portion of the first wiring layer at the other surface side, and
a second wiring layer that covers the second metal layer to fill a part of the through hole at the other surface side,
the second metal layer being interposed between the first wiring layer and the second wiring layer to isolate the first wiring layer and the second wiring layer, and the first wiring layer and the second wiring layer being electrically connected in the through hole via the second metal layer.
2. The wiring board according to claim 1,
wherein the first wiring layer is provided with a concave portion that is open toward the other surface side at the end portion of the first wiring layer at the other surface side in the through hole, and
wherein the second wiring layer is provided with a protruding portion that protrudes toward the one surface side at an end portion of the second wiring layer at the one surface side in the through hole, the protruding portion fitting in the concave portion.
3. The wiring board according to claim 1,
wherein the through wiring further includes
a first adhesion layer provided between the substrate body and the first metal layer, and
a second adhesion layer provided between the substrate body and the second metal layer, and between the end portion of the first wiring layer at the other surface side and the second metal layer, the first wiring layer and the second wiring layer being electrically connected with each other via the second adhesion layer and the second metal layer in the through hole.
4. The wiring board according to claim 3,
wherein the material of the substrate body is silicon, and an inner side surface of the through hole is covered by a silicon oxide film,
wherein the first adhesion layer is made of material whose adhesion to the silicon oxide film is better than the adhesion of the first metal layer to the silicon oxide film, and
wherein the second adhesion layer is made of material whose adhesion to the silicon oxide film is better than the adhesion of the second metal layer to the silicon oxide film.
5. The wiring board according to claim 1,
wherein the first wiring layer has a structure in which a plurality of conductive layers are stacked on an end portion of the second wiring layer at the one surface side.
6. The wiring board according to claim 1,
wherein the thickness of the first metal layer formed on an inner side surface of the through hole is formed to become thinner as it approaches a deeper portion of the through hole from the one surface side, and
wherein the thickness of the second metal layer formed on an inner side surface of the through hole is formed to become thinner as it approaches a deeper portion of the through hole from the other surface.
US14/471,209 2013-09-26 2014-08-28 Wiring board with through wiring Active 2034-11-05 US9392705B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013200631A JP6286169B2 (en) 2013-09-26 2013-09-26 Wiring board and manufacturing method thereof
JP2013-200631 2013-09-26

Publications (2)

Publication Number Publication Date
US20150083469A1 US20150083469A1 (en) 2015-03-26
US9392705B2 true US9392705B2 (en) 2016-07-12

Family

ID=52689960

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/471,209 Active 2034-11-05 US9392705B2 (en) 2013-09-26 2014-08-28 Wiring board with through wiring

Country Status (2)

Country Link
US (1) US9392705B2 (en)
JP (1) JP6286169B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11546990B2 (en) * 2019-01-31 2023-01-03 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with bridge structure in through hole fulfilling minimum distance design rule

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102382054B1 (en) 2014-11-05 2022-04-01 코닝 인코포레이티드 Bottom-up electrolytic via plating method
KR101898404B1 (en) * 2014-12-17 2018-09-12 미쓰이 가가쿠 가부시키가이샤 Substrate intermediary body, through-hole via electrode substrate, and through-hole via electrode formation method
JP6307167B2 (en) * 2015-05-31 2018-04-04 清川メッキ工業株式会社 Wiring substrate manufacturing method
JP6563317B2 (en) * 2015-11-25 2019-08-21 新光電気工業株式会社 Probe guide plate, manufacturing method thereof, and probe apparatus
US10700035B2 (en) * 2016-11-04 2020-06-30 General Electric Company Stacked electronics package and method of manufacturing thereof
US10312194B2 (en) 2016-11-04 2019-06-04 General Electric Company Stacked electronics package and method of manufacturing thereof
US9966371B1 (en) 2016-11-04 2018-05-08 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US9966361B1 (en) 2016-11-04 2018-05-08 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US10917966B2 (en) * 2018-01-29 2021-02-09 Corning Incorporated Articles including metallized vias
US11152294B2 (en) 2018-04-09 2021-10-19 Corning Incorporated Hermetic metallized via with improved reliability
KR20210127188A (en) 2019-02-21 2021-10-21 코닝 인코포레이티드 Glass or glass ceramic article having copper-metalized through holes and process for making same
IT201900006736A1 (en) 2019-05-10 2020-11-10 Applied Materials Inc PACKAGE MANUFACTURING PROCEDURES
IT201900006740A1 (en) 2019-05-10 2020-11-10 Applied Materials Inc SUBSTRATE STRUCTURING PROCEDURES
US11851321B2 (en) * 2021-03-01 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Micro-electro mechanical system and manufacturing method thereof
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
CN114899197B (en) * 2022-06-20 2023-07-18 业成科技（成都）有限公司 Display panel, display panel manufacturing method and display device

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6016012A (en) * 1996-11-05 2000-01-18 Cypress Semiconductor Corporation Thin liner layer providing reduced via resistance
US20040016114A1 (en) * 2002-07-25 2004-01-29 International Business Machines Corporation Land grid array structures and methods for engineering change
US6716737B2 (en) * 2002-07-29 2004-04-06 Hewlett-Packard Development Company, L.P. Method of forming a through-substrate interconnect
JP2005011987A (en) 2003-06-19 2005-01-13 Shinko Electric Ind Co Ltd Method for manufacturing semiconductor package
US6844241B2 (en) * 2001-02-22 2005-01-18 Tru-Si Technologies, Inc. Fabrication of semiconductor structures having multiple conductive layers in an opening
US20060144618A1 (en) * 2004-12-30 2006-07-06 Samsung Electro-Mechanics Co., Ltd. Fill plated structure of inner via hole and manufacturing method thereof
US20060289968A1 (en) * 2005-06-28 2006-12-28 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US20070032061A1 (en) * 2005-08-05 2007-02-08 Farnworth Warren M Methods of forming through-wafer interconnects and structures resulting therefrom
US20070199736A1 (en) * 2006-02-27 2007-08-30 Advanced Semiconductor Engineering, Inc. Substrate with multilayer plated through hole and method for forming the multilayer plated through hole
US20080149977A1 (en) * 2005-09-01 2008-06-26 Fujitsu Limited Semiconductor device and method for manufacturing the same
US7749899B2 (en) * 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
US20110120762A1 (en) * 2009-11-20 2011-05-26 Ibiden Co., Ltd. Printed wiring board and method for manufacturing printed wiring board
US20110155439A1 (en) * 2009-12-24 2011-06-30 Shinko Electric Industries Co., Ltd. Multilayer wiring substrate and method of manufacturing the same
US20120168220A1 (en) * 2010-12-30 2012-07-05 Samsung Electro-Mechanics Co., Ltd. Multi-layer printed circuit board and method of manufacturing the same
US8729407B2 (en) * 2011-05-27 2014-05-20 Shinko Electric Industries Co., Ltd. Wiring substrate and method for manufacturing wiring substrate

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4634735B2 (en) * 2004-04-20 2011-02-16 大日本印刷株式会社 Manufacturing method of multilayer wiring board
JP4298601B2 (en) * 2004-07-06 2009-07-22 東京エレクトロン株式会社 Interposer and manufacturing method of interposer
JP2007005404A (en) * 2005-06-21 2007-01-11 Matsushita Electric Works Ltd Method of forming through interconnection line in semiconductor substrate
JP2013077807A (en) * 2011-09-13 2013-04-25 Hoya Corp Method for manufacturing substrate and method for manufacturing wiring board

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6016012A (en) * 1996-11-05 2000-01-18 Cypress Semiconductor Corporation Thin liner layer providing reduced via resistance
US6844241B2 (en) * 2001-02-22 2005-01-18 Tru-Si Technologies, Inc. Fabrication of semiconductor structures having multiple conductive layers in an opening
US20040016114A1 (en) * 2002-07-25 2004-01-29 International Business Machines Corporation Land grid array structures and methods for engineering change
US6716737B2 (en) * 2002-07-29 2004-04-06 Hewlett-Packard Development Company, L.P. Method of forming a through-substrate interconnect
JP2005011987A (en) 2003-06-19 2005-01-13 Shinko Electric Ind Co Ltd Method for manufacturing semiconductor package
US7067353B2 (en) 2003-06-19 2006-06-27 Shinko Electric Industries Co., Ltd. Method for manufacturing semiconductor package having electrodes penetrating through semiconductor wafer
US20060144618A1 (en) * 2004-12-30 2006-07-06 Samsung Electro-Mechanics Co., Ltd. Fill plated structure of inner via hole and manufacturing method thereof
US20060289968A1 (en) * 2005-06-28 2006-12-28 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US20070032061A1 (en) * 2005-08-05 2007-02-08 Farnworth Warren M Methods of forming through-wafer interconnects and structures resulting therefrom
US20080149977A1 (en) * 2005-09-01 2008-06-26 Fujitsu Limited Semiconductor device and method for manufacturing the same
US20070199736A1 (en) * 2006-02-27 2007-08-30 Advanced Semiconductor Engineering, Inc. Substrate with multilayer plated through hole and method for forming the multilayer plated through hole
US7749899B2 (en) * 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
US20110120762A1 (en) * 2009-11-20 2011-05-26 Ibiden Co., Ltd. Printed wiring board and method for manufacturing printed wiring board
US20110155439A1 (en) * 2009-12-24 2011-06-30 Shinko Electric Industries Co., Ltd. Multilayer wiring substrate and method of manufacturing the same
US20120168220A1 (en) * 2010-12-30 2012-07-05 Samsung Electro-Mechanics Co., Ltd. Multi-layer printed circuit board and method of manufacturing the same
US8729407B2 (en) * 2011-05-27 2014-05-20 Shinko Electric Industries Co., Ltd. Wiring substrate and method for manufacturing wiring substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11546990B2 (en) * 2019-01-31 2023-01-03 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with bridge structure in through hole fulfilling minimum distance design rule

Also Published As

Publication number Publication date
JP2015070007A (en) 2015-04-13
US20150083469A1 (en) 2015-03-26
JP6286169B2 (en) 2018-02-28

Similar Documents

Publication Publication Date Title
US9392705B2 (en) Wiring board with through wiring
JP4937842B2 (en) Semiconductor device and manufacturing method thereof
JP4694305B2 (en) Manufacturing method of semiconductor wafer
US9247644B2 (en) Wiring board and method for manufacturing the same
US9318351B2 (en) Wiring substrate
US9338886B2 (en) Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device
JP5608605B2 (en) Wiring board manufacturing method
JP4601686B2 (en) Semiconductor device and manufacturing method of semiconductor device
KR20140005107A (en) Substrate, method of manufacturing substrate, semiconductor device, and electronic apparatus
JP5775747B2 (en) Wiring board and manufacturing method thereof
US20090095974A1 (en) Semiconductor package and manufacturing method thereof
JP2019149507A (en) Semiconductor device and manufacturing method thereof
JP4900508B2 (en) Through electrode substrate and manufacturing method thereof
JP2008135553A (en) Substrate laminating method and semiconductor device in which substrates are laminated
JP5565272B2 (en) Through electrode substrate
JP6712136B2 (en) Electronic component manufacturing method
JP5836751B2 (en) Thin film wiring board
TW201611695A (en) Coreless package substrate and method for manufacturing the same
JP2018147947A (en) Through electrode substrate and manufacturing method thereof
JP2011238742A (en) Method for manufacturing a wiring substrate and the wiring substrate
KR20080058207A (en) Manufacturing method of electronic component
JP2012134526A (en) Semiconductor device
CN116889107A (en) Multilayer wiring board
JP2021145142A (en) Through electrode
JP2017054978A (en) Method for manufacturing electronic component

Legal Events

Date Code Title Description
AS Assignment

Owner name: SHINKO ELECTRIC INDUSTRIES CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUNOHARA, MASAHIRO;SHIMIZU, YUICHIRO;REEL/FRAME:033630/0450

Effective date: 20140818

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8