CN207038515U - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN207038515U CN207038515U CN201490001567.4U CN201490001567U CN207038515U CN 207038515 U CN207038515 U CN 207038515U CN 201490001567 U CN201490001567 U CN 201490001567U CN 207038515 U CN207038515 U CN 207038515U
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- China
- Prior art keywords
- scolding tin
- engaging zones
- semiconductor device
- outer electrode
- dip
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 277
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 479
- 238000005452 bending Methods 0.000 claims abstract description 3
- 229910052751 metal Inorganic materials 0.000 claims description 54
- 239000002184 metal Substances 0.000 claims description 54
- 239000011347 resin Substances 0.000 claims description 41
- 229920005989 resin Polymers 0.000 claims description 41
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 35
- 239000000463 material Substances 0.000 claims description 32
- 230000002093 peripheral effect Effects 0.000 claims description 26
- 239000010949 copper Substances 0.000 claims description 25
- 239000000470 constituent Substances 0.000 claims description 19
- 229910052759 nickel Inorganic materials 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 10
- 229920001721 polyimide Polymers 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 238000007665 sagging Methods 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 239000000178 monomer Substances 0.000 claims description 2
- 239000007772 electrode material Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 43
- 238000012545 processing Methods 0.000 description 21
- 230000000694 effects Effects 0.000 description 20
- 230000035882 stress Effects 0.000 description 17
- 230000008595 infiltration Effects 0.000 description 10
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- 150000002739 metals Chemical class 0.000 description 7
- 238000005476 soldering Methods 0.000 description 7
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- 238000009713 electroplating Methods 0.000 description 6
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- 239000004642 Polyimide Substances 0.000 description 5
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- 238000004544 sputter deposition Methods 0.000 description 5
- 230000005611 electricity Effects 0.000 description 4
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- 239000000758 substrate Substances 0.000 description 4
- 230000001351 cycling effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910000765 intermetallic Inorganic materials 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000007790 solid phase Substances 0.000 description 3
- 229910018731 Sn—Au Inorganic materials 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
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- 235000013399 edible fruits Nutrition 0.000 description 2
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- 238000001259 photo etching Methods 0.000 description 2
- 238000004382 potting Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- NWONKYPBYAMBJT-UHFFFAOYSA-L zinc sulfate Chemical compound [Zn+2].[O-]S([O-])(=O)=O NWONKYPBYAMBJT-UHFFFAOYSA-L 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
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- 229910052742 iron Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model provides a kind of semiconductor device of scolding tin connected structure, can realize the high reliability with the raising and can realization device of the powered of outer electrode.Moreover, in the utility model, scolding tin (21) is formed from the scolding tin engaging zones (R11h) of surface electrode (11) to the scolding tin engaging zones (R31h) of outer electrode (31) on semiconductor element.Outer electrode (31) has the dip portion (31a) more prominent to the face side of surface electrode (11) than other regions.Scolding tin (21) has the end surface shape for including rounding (F1) and rounding (F2) on semiconductor element, wherein, direction bending of the rounding (F1) from surface to the top of surface electrode (11) towards scolding tin central point；Rounding (F2) is bent from the surface of outer electrode (31) to the direction underneath towards scolding tin central point.
Description
Technical field
It the utility model is related to one kind and use IGBT (Insulated Gate Bipolor Transistor), MOSFET
Or the semiconductor device of the semiconductor element such as diode (diode).
Background technology
In the semiconductor device using electric power semiconductor element in the prior art, there is such a semiconductor device：
By be arranged between the element lateral electrode of semiconductor element and outer electrode insert scolding tin grafting material come to the two progress
Electrical connection.In the semiconductor device of this progress scolding tin engagement, following technical problem be present：Because scolding tin grafting material causes
Stress concentration can not carry out the electrical connection of element lateral electrode and outer electrode well in the part of element lateral electrode.
As realizing for solving the semiconductor device of the technical cue of above-mentioned technical problem, such as there is patent document 1
Disclosed semiconductor device.
The semiconductor device forms electroplated electrode (plating in the surface electrode as element lateral electrode
Electrode), between electroplated electrode and outer electrode set scolding tin grafting material, in order to suppress realize surface electrode and
Stress concentration causes electroplated electrode to be peeled off in the outer edge of electroplated electrode during electrical connection between outer electrode, makes electroplated electrode
Flat shape is very bigger than external electrical, and from the side of outer electrode to the side at electroplated electrode end be provided with make scolding tin grafting material
The cross sectional shape of end face has the end slope shape of gradient.
Prior art literature
Patent document
Patent document 1：Japanese invention Patent Publication No No. 2008-244045 (Fig. 2)
Utility model technical problems to be solved
However, semiconductor device disclosed in patent document 1 is in order to set above-mentioned end slope shape, it is necessary to than outside
Electric greatly area forms electroplated electrode, therefore the bonding area of outer electrode will necessarily be than electroplated electrode, i.e. semiconductor element
Solder bonding faces product on the surface electrode of part is small, as a result, carrying for the current density between outer electrode and surface electrode be present
Height can produce limit the problem of point.
It is difficult to large area in addition, having as the high temperature resistant such as semiconductor element, SiC semiconductor element semiconductor element
Other technologies problem, therefore, the other technologies problem make it that the elimination of above-described problem is more difficult.
Typically filled in the semiconductor for being referred to as electric power semiconductor module (power semiconductor module)
In putting, semiconductor element can generate heat, and temperature cycles occur in the inside of power semiconductor modular, the part that electric current flows through is applied in
Big thermal stress.Especially, in above-mentioned high temperature resistant semiconductor element, because current density and use temperature range increase, because
This can be applied in bigger stress.
Also, there is also difficulty for the large area of semiconductor element.Therefore, in semiconductor as disclosed in Patent Document 1
Device is such, it is desirable to which the bonding area of outer electrode side is designed as to the semiconductor of the surface electrode certainly less than semiconductor element
In device, diminish in outer electrode side engagement area and current density increases, therefore scolding tin cracking (crack) etc. is allowed
Degree also diminishes.
In addition, the semiconductor device disclosed in patent document 1 uses the weldering relaxed in outer electrode side due to no
The structure of caused stress on tin, and exist and easily induce scolding tin cracking the problem of point, accordingly, there exist can not realize to be used for simultaneously
Ensure the high current density of good powered and high reliability the problem of point of device.
Utility model content
The purpose of this utility model is, solves the above problems a little, there is provided a kind of to realize and the energization performance of outer electrode
Raising and the scolding tin connected structure (solder bonding structure) of the high reliability of realization device semiconductor
Device.
For solving the scheme of technical problem
The semiconductor device of the application utility model described in technical scheme 1 involved by the utility model has semiconductor
Element (semiconductor element) and outer electrode (external electrode), wherein, the semiconductor element
Part has side interarea and opposite side interarea, and the lateral electrode with flat surfaces is provided with the interarea of side；The outside
Electrode is arranged at the top of a lateral electrode, and the surface of the surface of the outer electrode and a lateral electrode is opposite, institute
Stating semiconductor device also has scolding tin forming portion, and the scolding tin forming portion is formed the surface of a lateral electrode and the external electrical
Between the surface of pole, make to electrically connect between a lateral electrode and the outer electrode, a lateral electrode and the external electrical
At least a portion of pole in the overlapping region of plane apparent time is defined as a lateral electrode and the respective table of the outer electrode
The 1st scolding tin engaging zones in face and the 2nd scolding tin engaging zones, the outer electrode have than other regions to a lateral electrode
The dip portion (downwardly extending portion) that protrudes of face side, the dip portion is arranged at comprising described
The region of 2nd scolding tin engaging zones, and with scolding tin central point is close to making the surface and described one of the outer electrode
The rake that vertical range between the surface of lateral electrode shortens, wherein the scolding tin central point is the 1st scolding tin bonding land
Domain and the center of the 2nd scolding tin engaging zones, to institute since the 1st scolding tin engaging zones of a lateral electrode
The 2nd scolding tin engaging zones for stating outer electrode are curved with including the 1st formed with the scolding tin forming portion, the scolding tin forming portion
The end surface shape of curved shape and the 2nd curved shape, wherein, the 1st curved shape is from surface to the top of a lateral electrode
Bent towards the direction of the scolding tin central point, the 2nd curved shape is from the surface of the outer electrode to underneath towards institute
State the direction bending of scolding tin central point.
Utility model effect
Scolding tin forming portion in the semiconductor device of the application utility model described in technical scheme 1 has end surface shape,
The end surface shape includes the 1st curved shape from the surface of a lateral electrode and the 2nd Curved on the surface from outer electrode
Shape, a lateral electrode and the 1st scolding tin engaging zones of another lateral electrode and the engagement of the 2nd scolding tin are resulted from respectively therefore, it is possible to realize
The reduction of the stress in region, hereby it is possible to realize the raising of the reliability of scolding tin forming portion.
In addition, the application utility model described in technical scheme 1 can have with scolding tin forming portion includes the 1st curved shape
With the form of the end surface shape of the 2nd curved shape, a lateral electrode and outer electrode are all set in the overlapping region of plane apparent time
It is set to the 1st scolding tin engaging zones and the 2nd scolding tin engaging zones, therefore, it is possible to by realizing the 1st scolding tin engaging zones and the 2nd weldering
The expansion of the area of tin engaging zones, to realize the raising of the energization ability between a lateral electrode and outer electrode.
In the following detailed description and accompanying drawing, the purpose of this utility model, feature, aspect and advantage are definitely.
Brief description of the drawings
Fig. 1 is the sectional view of the structure for the semiconductor device for being denoted as the utility model embodiment 1.
Fig. 2 is the sectional view of the major part for gazing at region amplification in the semiconductor device by Fig. 1.
Fig. 3 is the explanation figure for the plan structure for schematically showing embodiment 1.
Fig. 4 is the sectional view of the structure for the semiconductor device for representing embodiment 2.
Fig. 5 is the explanation figure of the structure of the features for the semiconductor device for representing embodiment 3.
Fig. 6 is the explanation figure for representing the structure of the features of the semiconductor device of the 1st form in embodiment 4.
Fig. 7 is the explanation figure for representing the structure of the features of the semiconductor device of the 2nd form in embodiment 4.
Embodiment
<Embodiment 1>
(structure)
Fig. 1 is the sectional view of the structure for the semiconductor device for being denoted as the utility model embodiment 1.Fig. 2 is by Fig. 1
The sectional view of the major part for gazing at region C11 amplifications in shown semiconductor device.Fig. 3 is to schematically show embodiment party
The explanation figure of the plan structure of formula 1.In addition, Fig. 3 Section A-A corresponds to the structure shown in Fig. 1.In addition, show in Fig. 1~Fig. 3
Go out XYZ rectangular coordinate systems.
As shown in these figures, the semiconductor element such as longitudinal type IGBT 1 has surface and the back side (side interarea and opposite side master
Face), and surface electrode 11 (lateral electrode) is provided with the surface, the surface electrode 11 has flat surface.
Moreover, the outer electrode 31 set in a manner of mutual surface is opposite is provided with the top of surface electrode 11.Separately
Outside, in this manual, for convenience of description, using the face between surface electrode 11 and outer electrode 31 toward each other as surface.
That is, using the face of +Z direction side as surface in surface electrode 11, using the face of -Z direction side as surface in outer electrode 31
To illustrate.
Moreover, scolding tin 21 (scolding tin forming portion) is formed on surface and the outer electrode of surface electrode 11 on semiconductor element
Between 31 surface, make to electrically connect between surface electrode 11 and outer electrode 31 accordingly.
Surface electrode 11 is defined as surface electricity with outer electrode 31 in the overlapping whole of plane apparent time and most of region
Scolding tin engaging zones R11h and R31h (the 1st scolding tin engaging zones and the engagement of the 2nd scolding tin on pole 11 and the surface of outer electrode 31
Region).In embodiment 1, as shown in figures 1 and 3, show that scolding tin engaging zones R11h and scolding tin engaging zones R31h exist
The completely the same form of plane apparent time.
Outer electrode 31 has the dip portion 31a more prominent to the face side (- Z sides) of surface electrode 11 than other regions.
Dip portion 31a flat shape can be made consistent with scolding tin engaging zones R31h.
Dip portion 31a is arranged at the region for including scolding tin engaging zones R31h, and with being close to scolding tin center
Point HC (reference picture 3) directions and shorten the vertical range DA between the surface of outer electrode 31 and the surface of surface electrode 11
Rake 31s, wherein scolding tin central point HC is scolding tin engaging zones R11h and R31h center.For example, such as Fig. 2 institutes
Show, the vertical range DA1 positioned at the +X direction side as scolding tin central point HC directions is than positioned at the vertical of relative -X direction side
Distance DA2 shortens.In addition, certain flat of the perpendicular distance DA of the bottom surface sections 31m of the dip portion 31a including scolding tin central point HC
Structure.
Scolding tin 21 forms the weldering to outer electrode 31 from the scolding tin engaging zones R11h of surface electrode 11 on semiconductor element
Tin engaging zones R31h.For accurate, the scolding tin engaging zones R11h on surface electrode 11 is formed with scolding tin engagement metal
Film 13, surface electrode 11 and outer is carried out by being formed at the scolding tin engagement with scolding tin 21 on the semiconductor element on metal film 13
The electrical connection of portion's electrode 31.
As shown in Fig. 2 on semiconductor element scolding tin 21 have include rounding (fillet) F1 (the 1st curved shape) and
Rounding F2 (the 2nd curved shape) end surface shape, wherein, rounding F1 is from the surface of surface electrode 11 to top (+Z direction)
Bent to scolding tin central point HC direction (being +X direction in Fig. 2), rounding F2 is from the surface of outer electrode 31 to lower section (- Z sides
To) to scolding tin central point HC direction bend.Below, sometimes by the dip portion 31a's with rounding F1 and F2 shown in Fig. 2
End surface shape is referred to as " upper and lower rounding corner structure ".
In this way, lead between the surface electrode 11 and outer electrode 31 of semiconductor element 1 in scolding tin engaging zones R11h and R31h
Cross scolding tin 21 on semiconductor element to be engaged by scolding tin, accordingly, carry out the electrical connection between surface electrode 11 and outer electrode 31.
As mutually the same scolding tin engaging zones R11h and R31h flat shape, the plane of at least more than one is considered
Apparent time is rectangular shape.Such as can also be as shown in Fig. 3, using following structure：Provided with corner by with radius of curvature r2 roundings
Plane apparent time be rectangular shape 2 scolding tin engaging zones R11h and R31h.In addition, in the structure shown in Fig. 3, dip portion
31a bottom surface sections 31m is also formed using plane apparent time as rectangular shape, and sets bottom surface sections 31m periphery and scolding tin connects
Close the plan range r1 between region R11h (R31h) periphery.In the structure shown in Fig. 3, dip portion 31a also corresponds to 2
Individual scolding tin engaging zones R31h is provided with 2, and scolding tin 21 also corresponds to scolding tin engaging zones R11h and R31h and set on semiconductor element
There are 2.
In this way, by setting scolding tin on multiple semiconductor elements corresponding to multiple scolding tin engaging zones R11h and R31h
21 realize the electrical connection between surface electrode 11 and outer electrode 31, accordingly, such as can avoid the grid on surface electrode 11
(gate) distribution forming region etc. is not intended to be formed the region of scolding tin, obtains to realize between surface electrode 11 and outer electrode 31
The effect that electrically connects of flexibility (flexible) ground.
It is as shown in figure 3, scolding tin engaging zones R11h and R31h are formed as into the reasons why plane apparent time is rectangular shape,
In general, semiconductor element 1 is usually obtained from wafer is cut into rectangular shape (rectangle), by by scolding tin bonding land
Domain R11h shape is again formed as rectangular shape in the same manner as semiconductor element 1, it can be ensured that the terminal with semiconductor element 1
There is a certain distance between portion, and the bonding area of maximum can be obtained.
In addition, as shown in figure 3, it is preferred that scolding tin engaging zones R11h corner is by with radius of curvature r2 chamferings.Its reason exists
In, scolding tin on semiconductor element 21 to corner infiltrate extend when, then can be difficult due to the surface tension of scolding tin if right angle
Extended with the infiltration in shape stuck up suddenly in angle, therefore, chamfering makes the angle in corner ease up into curved, hereby it is possible to make scolding tin
Reliably extension is infiltrated to scolding tin engaging zones R11h and R31h whole region.
As described above, it is phase each other that scolding tin engaging zones R11h and scolding tin engaging zones R31h, which are formed plane apparent time,
Similar shape, therefore, it is possible in scolding tin engaging zones R31h and scolding tin engaging zones R11h, make respectively with being welded on semiconductor element
Scolding tin infiltration angle (scolding tin angle) that tin 21 engages is equal, formed the common scolding tin rounding angular shape of both sides (rounding F2 and
F1)。
As described above, the dip portion 31a of outer electrode 31 has flat bottom surface sections 31m.Overlook semiconductor device 101
When, bottom surface sections 31m each side is located at the inner side of the corresponding sides of scolding tin engaging zones R31h periphery, and has one with the corresponding sides
Fixed plan range r1.As described above, scolding tin engaging zones R31h is identical with scolding tin engaging zones R11h flat shape, rectangle
The corner of shape is by with radius of curvature r2 chamferings, into curved, therefore, scolding tin engaging zones R31h periphery is also by with same curvature
Radius r2 chamferings.
Now, make radius of curvature r2=plan range r1, accordingly, dip portion 31a scolding tin engaging zones R31h even in
Gentle crest line can be also formed as the corner of flex point, and crest line can be formed at beyond the corner of rectangular shape, it is tied
Fruit, the stress concentration caused by scolding tin 21 from semiconductor element can be avoided.In addition, crest line refers to：Dip portion 31a scolding tin
Crest line between engaging zones R31h and bottom surface sections 31m.
For example, when using the scolding tin engaging zones R11h variable relative to plane coordinates as above-mentioned vertical range DA,
When the volume for being multiplied to obtain using scolding tin engaging zones R11h area with vertical range DA is as volume V2 is contemplated, semiconductor element
The actual scolding tin volume V1 of upper scolding tin 21 meets " to contemplate volume V2 ＞ scolding tin volumes V1 ".The reason for this is that by making " V2
＞ V1 ", scolding tin 21 can form the end surface shape with above-mentioned rounding corner structure up and down on semiconductor element.
In addition, as shown in figures 1 and 3, preferably outer electrode 31 dip portion 31a bottom surface sections 31m, with scolding tin center
The through hole 31t for penetrating outer electrode 31 along the Z direction is set centered on point HC.
By setting through hole 31t on the outer electrode 31 of semiconductor device 101, the scolding tin 21 on semiconductor element is formed
Shi Duoyu scolding tin flows into through hole 31t, thus absorbs unnecessary scolding tin, therefore, scolding tin 21 is slightly more on semiconductor element
When, also can reliably the side of scolding tin 21 forms rounding corner structure up and down on semiconductor element.
In this way, the end surface shape as scolding tin on semiconductor element 21, sets rounding corner structure up and down, hereby it is possible to will
Section angle when scolding tin on semiconductor element 21 and the rake 31s of outer electrode 31 end form scolding tin and half
Section angle, 2 scolding tin angles when scolding tin 21 and scolding tin engagement form scolding tin with the end of metal film 13 on conductor element
(scolding tin infiltration angle) is controlled below 90 degree.
That is, as shown in Fig. 2 can be by the scolding tin angle theta H1 of the side of outer electrode 31 and the scolding tin angle of the side of surface electrode 11
θ H2 are controlled below 90 degree.Further, since small scolding tin angle can reduce scolding tin stress, therefore preferably small scolding tin folder
Angle, such as the example that scolding tin stress halves when having scolding tin angle below 60 degree.
The semiconductor elements such as IGBT 1 for example have surface electrode on surface and the back side (side interarea and opposite side interarea)
11 and backplate 12.Backplate 12 is electrically connected and engaged with electrode of substrate 38 by scolding tin under semiconductor element 22.
Surface electrode 11 is preferably the metal film being for example made up of the material containing more than 95% Al (aluminium).As partly leading
The surface electrode 11 of volume elements part 1 is using the reasons why material containing more than 95% Al, as having used Si substrates or SiC
The electrode of the semiconductor element 1 of the various substrates such as (carborundum) substrate, it can be readily formed by known existing method
And processing, in addition, typically by forming the electrode of control terminal (office described later with the common manufacturing process of surface electrode 11
Portion surface electrode 11g), also can when by metal wire bonding (wire bonding (wire bond)) in the control terminal electrode
Ensure the excellent engagement of connection reliability.
Due to being difficult to the surface electrode that the material containing more than 95% Al is engaged in without Pb scolding tin of such as SnAgCu systems
On 11 surfaces, therefore ensure the zygosity with scolding tin with metal film 13 by forming scolding tin engagement on surface electrode 11
With scolding tin wellability.In addition, " scolding tin wellability " refers to：The combination difficulty of the welding difficulty of expression and scolding tin coalesced object
Deng soldering property.
As scolding tin engagement metal film 13, such as consider to be made up of laminated metal membrane, the laminated metal membrane includes master
Will be by the metal film (scolding tin engagement nickel film) that Ni (nickel) is formed, and be formed on for anti-oxidation by Au (gold) structure
Into metal film.It is that it is possible to easily as the reasons why using Ni with the major metal film of metal film 13 for scolding tin engagement
Intermetallic compound is formed with scolding tin, obtains good and stable scolding tin engagement.
In this way, the scolding tin engagement metal film 13 including scolding tin engagement nickel film is formed to the scolding tin in surface electrode 11
On engaging zones R11h, wherein, scolding tin engagement has been used as excellent with the zygosity of scolding tin on semiconductor element 21 by the use of nickel film
Constituent material Ni, hereby it is possible to realize the raising in scolding tin engaging zones R11h scolding tin wellability.
In addition, form the Ni and Au of scolding tin engagement metal film 13 such as can by sputter (sputtering) be
The vapour deposition process of representative or wet type galvanoplastic including the non-electrolytic plating method containing P (phosphorus) are formed.As passing through gas phase
Sedimentation forms the method for scolding tin engagement metal film 13, such as can enumerate the mask for carrying out sputtering metal membrane across metal mask
(mask sputtering) method of sputtering and JET peel off (lift-off) method, wherein, JET stripping methods are：With photoresist
(photoresist) splash-proofing sputtering metal film process is carried out after covering beyond scolding tin engaging zones R11h, by having been blowed with high pressure
Solvent to remove the metal film beyond scolding tin engaging zones R11h according to photoresist.As by wet type galvanoplastic come shape
Method into scolding tin engagement with metal film 13, such as method can be listed below：By scolding tin engaging zones R11h surface electrode 11
Expose, part in addition is covered with cover layer, make weldering by using the wet type galvanoplastic of zincate (zincate) method
Tin engagement metal film 13 grows, to be formed selectively scolding tin engagement metal film 13 in scolding tin engaging zones R11h.Especially
Be, in the semiconductor device that semiconductor element 1 and periphery material are exposed under high temperature, due to scolding tin engagement with metal film 13 to
Spread on semiconductor element in scolding tin 21, its thickness is gradually reduced so that joint reliability deteriorates, therefore preferred thick scolding tin connects
Metal film 13 is shared, in the case where forming scolding tin engagement metal film 13 with wet type galvanoplastic, can electroplated by extending
Dip time in liquid, to be readily formed the metal film of thickness.
Outer electrode 31 is for example formed with the metallic plate being made up of Cu (copper).The reasons why Cu is used in outer electrode 31 exists
In, arbitrary shape can be easily processed into by processing such as punching presses, in addition, easily can be engaged with scolding tin, and can
High pass electric energy power is realized, therefore is adapted as outer electrode 31.Dip portion 31a for example can be by the plate after punch process
Shape outer electrode structure is formed using the extrusion die corresponding with dip portion.In addition, for example can will be with dip portion 31a phases
Corresponding metallic plate soldering or soldering (brazing) etc. are engaged in the main portion of flat outer electrode, to form outer electrode
31。
, can be relatively easily with being welded on semiconductor element in the case where forming outer electrode 31 with Cu monomer structures
Tin 21 engages, and can obtain the high outer electrode 31 of energization ability by being relatively easy to working process.
As shown in figure 1, underlayer electrode 38 is provided with the outer electrode 35 different from outer electrode 31, scolding tin engaging zones
Local surfaces electrode 11g beyond R11h is electrically connected by scolding tin engagement with metal film 13 and control distribution 37 with coordination electrode 36
Connect.In addition, the gate electrodes of local surfaces electrode 11g as IGBT etc. and play function, generally, local surfaces electrode 11g quilts
Be formed as not electrically connecting with being formed on scolding tin engaging zones R11h surface electrode 11.
In this way, the product of semiconductor device 101 is to be provided with multiple outer electrodes 31 and outer electrode 35 and coordination electrode 36
Modular form complete.
Moreover, as shown in figure 1, for example, semiconductor element 1 (including surface electrode 11 (11g), backplate 12 and scolding tin
Metal film 13 is used in engagement), scolding tin 22 under scolding tin 21, semiconductor element on semiconductor element, outer electrode 31 at least a portion,
At least a portion of outer electrode 35, at least a portion of coordination electrode 36 are sealed by resin 41.By being sealed by resin 41, energy
Semiconductor element 1 and the connected structure on periphery breakage, pollution, short circuit due to the foreign matter from outside or moisture are enough prevented, because
This, not only reliability improves, moreover, the processing of semiconductor device 101 becomes easy, yield rate also improves.In addition, moreover it is possible to
Enough when semiconductor device 101 is powered, suppress outer electrode 31 and expanded due to heating, it is possible to increase the weldering of outer electrode 31
Tin engaging zones R31h reliability.
It so, it is possible by by least a portion of the sealed external electrode 31 of resin 41, semiconductor element 1 and semiconductor element
Scolding tin 21 on part, become easy come the processing of the semiconductor device 101 after forming resin, yield rate improves, further, it is possible to logical
The absorption and foreign matter attachment suppressed to semiconductor element 1 is crossed, to realize the raising of reliability.
In addition, when set resin 41, semiconductor element 1, outer electrode 31 linear expansion coefficient be respectively α 4, α 1, α 3 when, make
Its relation is α 1 (the 1st linear expansion coefficient) ＜ α 4 (the 2nd linear expansion coefficient) ＜ α 3 (the 3rd linear expansion coefficient), hereby it is possible to press down
Outer electrode 31 and resin 41 processed are peeled off, and can also suppress that resin stress occurs to semiconductor element 1, therefore can be improved
Reliability.
As the method for forming resin 41, the Transfer molding by high pressure resin by injection 41 using mould can be enumerated
(transfer molding) method and more low price, the embedding of resin 41 (potting) method formed by potting resin.In reality
In the semiconductor device 101 for applying mode 1, due to partly leading between the outer electrode 31 and semiconductor element 1 that easily narrow in gap
Scolding tin 21 forms rounding corner structure, therefore thin portion is also easily injected into resin up and down on volume elements part, is adapted to the embedding using low price
Method.
Specifically, using to temporarily by scolding tin 21 and outer electrode 31 on fixed semiconductor element 1, semiconductor element
Deng resin formed subject area discharge liquid resin and heat make its harden embedding method, come implement resin formation processing, according to
This, forms tree in a manner of scolding tin 21 at least a portion, semiconductor element 1 and the semiconductor element that cover outer electrode 35
Fat 41.
In this way, as the process for forming resin 41, execution has used the resin shape of the embedding method of comparable qurer progress
Into processing, to manufacture semiconductor device 101, hereby it is possible to by scolding tin on the sealing semiconductor element 1 of resin 41, semiconductor element
21 and outer electrode 35 etc., position is not filled by without making to produce between semiconductor element 1 and outer electrode 31.
It is formed in the pressure-resistant holding areas such as the protection ring (guard ring) of semiconductor element 1, does not form surface electricity
Pole 11 and formed with diaphragm 14.By diaphragm 14, can relax due to cold cycling etc. and caused from resin 41
Stress, the pressure-resistant holding area such as protection ring can be prevented by stress rupture.
Diaphragm 14 is, for example, the dielectric film (polyimide film) that is made up of polyimides (polyimide), thickness for 2~
20 μm or so.Photosensitive polyimide is used in polyimide film, in the case of being formed by photoetching process (lithography),
Or using non-photosensitive polyimides and and with photonasty resist, the photonasty resist is processed into institute by photoetching process
Shape desired, such fairly simple manufacturing process is processed to polyimides by using the resist after processing,
The diaphragm 14 for the shape for covering pressure-resistant holding area can be formed.Further, it is possible to the diaphragm by being used as polyimide film
14, come at the heat that is resistant to during including forming scolding tin 21 and the processing of resin 41, actual load semiconductor element 1 on semiconductor element
Reason.
For example, it can be used as using above-mentioned diaphragm 14 by above-mentioned wet type galvanoplastic to form scolding tin engagement gold
Belong to cover layer during film 13.
That is, can implement to form diaphragm 14 and scolding tin in the manufacture method of the semiconductor device 101 of embodiment 1
The step of engagement is with below metal film 13 (a), (b).
Step (a)：On the surface of semiconductor element 1, from including the pressure-resistant holding area for not forming surface electrode 11
Region forms diaphragm 14 (reference picture 1) to the scolding tin engaging zones R11h on the surface of surface electrode 11 outer edge.It is tied
Fruit, diaphragm 14 has the shape for the required scope that only extends from pressure-resistant holding area, not only to cover pressure-resistant holding area,
Also cover the surface electrode 11 beyond scolding tin engaging zones R11h.
Step (b)：It is mask with diaphragm 14, using wet type galvanoplastic, the scolding tin on the surface of surface electrode 11 engages
Scolding tin engagement metal film 13 is formed on the R11h of region.
By implement include above-mentioned steps (a), (b) semiconductor device 101 manufacture method, using diaphragm 14 as
Use for forming scolding tin engagement with the mask of metal film 13, accordingly, in the case of using wet type galvanoplastic, also can not
Increase process and form the diaphragm 14 as mask, the manufacturing cost of semiconductor device 101 can be cut down.
In this way, on the surface of semiconductor element 1, including the region of surface electrode 11 is not formed optionally to set
Diaphragm 14, accordingly, the processing of the semiconductor element 1 before the formation process of resin 41 become easy, and yield rate improves, together
When, due to being caused the pressure-resistant holding area such as the protection ring in semiconductor element 1 destroyed by the stress from resin 41
Situation is inhibited, and reliability improves.
As using scolding tin on semiconductor element 21 come the method that engages semiconductor element 1 and the scolding tin of outer electrode 31,
Such as melting scolding tin can be enumerated and dripped method and backflow welding method, wherein, the melting scolding tin method of dripping is by making the scolding tin of melting from upper
The through hole 31t stated is flowed into carry out the method for scolding tin engagement, and backflow welding method is by the way that the scolding tin of solid phase or cream (paste) shape is set
Put and Reflow Soldering (reflow) is carried out on scolding tin engaging zones R11h to carry out the method for scolding tin engagement.
The welding method that flows back is by making configuration in reducing atmosphere on the surface of surface electrode 11 and the surface of outer electrode 31
Between solid phase or paste soldering tin material melting, to obtain the method for scolding tin 21 on semiconductor element.
In the semiconductor device 101 of embodiment 1, due to needing to make the volume stability of scolding tin 21 on semiconductor element,
Therefore using the scolding tin of solid phase or paste and the above-mentioned backflow welding method of easily controllable soldering tin amount is suitable method.
On outer electrode 31 and semiconductor element scolding tin 21 surface occur oxidation and formed with oxide-film in the case of,
Scolding tin wellability reduces, therefore scolding tin non-wetting occurs.Therefore, in the semiconductor device 101 of embodiment 1, semiconductor
Dip portion 31a infiltration extension of the scolding tin 21 to outer electrode 31 is critically important on element, therefore, by above-mentioned backflow welding method,
Above-mentioned oxide-film is removed under reducing atmosphere, connects the downward lappet 31a of scolding tin scolding tin under the good situation of scolding tin wellability
Region R31h extensions are closed, hereby it is possible to obtain scolding tin on the semiconductor element with upper and lower rounding corner structure with good precision
21。
In addition, the soldering tin material of scolding tin on semiconductor element 21 is being melted to engage outer electrode 31 and semiconductor element
During part 1, even if the scolding tin producing bubbles inside of melting, also due to dip portion 31a presence, and be easy to by bubble to
Discharged on the outside of scolding tin, therefore, it is possible to reduce the cavity of the scolding tin after actual load.
(action, effect and effect)
Semiconductor device 101 in embodiment 1, can by be arranged at scolding tin 21 on semiconductor element up and down
Rounding corner structure, come reduce in device action etc. the tissue of scolding tin 21 on semiconductor element in the cold cycling of generation occur it is tired
Labor deforms, stress caused by the end of scolding tin 21 especially on semiconductor element.
Because upper and lower rounding corner structure is not to be simply formed with the rounding F1 of the side of semiconductor element 1 and in outer electrode 31
Side is also formed with rounding F2 structure, therefore, it is possible to reduce the weldering of the side of semiconductor element 1 and the side both sides of outer electrode 31 simultaneously
Tin stress, the high connected structure of reliability is obtained, simultaneously as can be by the scolding tin engaging zones R31h's of the side of outer electrode 31
Area is expanded to the scolding tin engaging zones R11h equal extents with semiconductor element 1, thus, it is also possible to maintain energization performance.
Use temperature range is at higher temperature and be difficult to by chip large area, the compound semiconductor such as using SiC semiconductor
In device, the effect obtained by the semiconductor device 101 of embodiment 1 is particularly effective.
That is, high temperature is corresponded to the semiconductor element 1 that SiC (carborundum) is constituent material, may be in harsher temperature
Under the conditions of use, due to realizing the raising of the reliability of scolding tin 21 on semiconductor element, therefore, even if semiconductor element 1 into
Also turn into the condition of high temperature for high temperature, surface electrode 11 and outer electrode 31, device also can be acted stably.
The scolding tin 21 on the dip portion 31a surfaces coating semiconductor element for be formed at outer electrode 31, accordingly, semiconductor element
On part the end shape of scolding tin 21 be in the recessed shape in the inner side formed with scolding tin central point HC, i.e. upper and lower rounding corner structure,
Therefore, it is possible to form rounding F1 and F2 in the side of semiconductor element 1, the side both sides of outer electrode 31.Dip portion 31a structure is,
With the vertical range DA of the scolding tin engagement metal film 13 of semiconductor element 1, from the scolding tin central point HC of semiconductor element 1 to outer
Side becomes larger, it is accordingly possible to ensure the insulation distance of the terminal part of semiconductor element 1 and outer electrode 31, and can press down
The effective thickness of scolding tin 21 on semiconductor element processed, therefore, it is possible to reduce from stress caused by scolding tin.
In this way, scolding tin 21 (scolding tin forming portion) has end on semiconductor element in the semiconductor device 101 of embodiment 1
Face shape, the end surface shape include the rounding F1 (the 1st curved shape) from surface electrode 11 (lateral electrode) surface and come
Rounding F2 (the 2nd curved shape) from the surface of outer electrode 31.The He of surface electrode 11 is resulted from respectively as a result, can realize
The reduction of scolding tin the engaging zones R11h and R31h of outer electrode 31 stress, therefore, it is possible to realize scolding tin on semiconductor element
The raising of 21 reliability.
In addition, there can be upper and lower rounding corner structure with scolding tin 21 on the semiconductor element of semiconductor device 101 and be somebody's turn to do
Upper and lower rounding corner structure has rounding F1 and rounding F2 form, and surface electrode 11 and outer electrode 31 are regarded in plane
When overlapping region be all set to scolding tin engaging zones R11h and R31h, therefore, it is possible to by realizing scolding tin engaging zones
The expansion of R11h and R31h area, to realize the raising of the energization ability between surface electrode 11 and outer electrode 31.
As a result, can obtain can be long-term use of and realizes the semiconductor device 101 of the raising of yield rate.
In addition, the planar shapes of scolding tin engaging zones R11h and R31h are rectangular shape, are likely to become and planar shaped
Shape is the similar relation of the high semiconductor element 1 of the tendency of rectangular shape, hereby it is possible to effectively realize weldering in the design phase
The expansion of tin engaging zones R11h and R31h formation area.
Also, scolding tin engaging zones R11h and R31h flat shape are in the chamfering rectangular shape after corner is chamfered, according to
This, can relax the stress concentration of scolding tin the engaging zones R11h and R31h on semiconductor element in scolding tin 21, further, it is possible to hold
Change places make scolding tin to corner infiltrate extend, can realize scolding tin engaging zones R11h and R31h reliability further raising and
Productive raising.
In addition, by the way that scolding tin engaging zones R11h and scolding tin engaging zones R31h are set as into plane apparent time is completely overlapped
The same shape of (coincidence), can more reliably scolding tin 21 forms rounding F1 and F2 on semiconductor element.
<Embodiment 2>
(structure)
Fig. 4 is the sectional view of the structure for the semiconductor device 102 for representing embodiment 2.Below, pair with shown in Fig. 1~Fig. 3
The same structure division of semiconductor device 101 of embodiment 1 mark same mark, and suitably omit the description, with implementation
Illustrated centered on the difference of mode 1.In addition, XYZ rectangular coordinate systems are shown in Fig. 4.
In the semiconductor device 102 of embodiment 2, substitute outer electrode 31 and used this point of outer electrode 50
It is different from embodiment 1.Outer electrode 50 is for example mother metal with metallic plate 51 in composition metal harden structure, on the surface of mother metal
Cu sheet metals 52 are formed with the back side, wherein, metallic plate 51 is made up of the linear expansion coefficient metal material lower than Cu.In addition, Fig. 4
Shown dip portion 50a, bottom surface sections 50m and region C12 is gazed at corresponding to the sagging of the semiconductor device 101 shown in Fig. 1~Fig. 3
Portion 31a, bottom surface sections 31m and gaze at region C11.
For example, by sticking (the copper shape of Cu sheet metals 52 on the surface of the linear expansion coefficient metallic plate 51 lower than Cu and the back side
Stratification), the outer electrode 50 of surface and the back side for Cu layers can be obtained.In addition, for example can be lower than Cu in linear expansion coefficient
On metallic plate 51, it is used as the Cu sheet metals 52 of Cu films by electroplating processing to be formed.Plating processing can also for example use no electricity
Electrolytic plating method, but used by regarding metallic plate 51 as electrode, the thick Cu sheet metals 52 of thickness can be relatively easily formed, because
This, preferably using electrolytic plating method.The metallic plate 51 lower than Cu as linear expansion coefficient, such as can use and contain Fe (iron)
Ni alloys.
(action, effect and effect)
By making outer electrode 50, for mother metal, linear expansion coefficient can be connect with the linear expansion coefficient metallic plate 51 lower than Cu
Nearly semiconductor element 1, therefore, it is possible to suppress when semiconductor device 102 act etc. in the cold cycling of generation it is caused outside
The deformation of portion's electrode 50.
Also, by forming 52 layers of Cu sheet metals on the surface of outer electrode 50 and the back side, outer electrode 50 can be reduced
Surface and the back side resistance, simultaneously, additionally it is possible to ensure the scolding tin zygosity of outer electrode 50 and with being welded on semiconductor element
The reliability of the joint interface of tin 21, therefore, it is possible to realize the higher semiconductor device 102 of reliability.
In this way, in the semiconductor device 102 of embodiment 2, can by be formed on outer electrode 50 surface and
The back side, as the cambial Cu sheet metals 52 of copper, to ensure energization performance and be soaked with the scolding tin of scolding tin on semiconductor element 21
Lubricant nature, and linear expansion coefficient can be made close to semiconductor element 1 by the metallic plate 51 for the mother metal for being used as outer electrode 50, because
This, in addition to the effect of embodiment 1, additionally it is possible to obtain and realize powered and scolding tin wellability and the reliability of device simultaneously
Effect.
<Embodiment 3>
(structure)
Fig. 5 is the explanation figure of the structure of the characteristic for the semiconductor device 103 for representing embodiment 3.Fig. 5 is represented and figure
The semiconductor for gazing at the embodiment 2 shown in region C11 or Fig. 4 dress in the semiconductor device 101 of embodiment 1 shown in 1
Put the structure for gazing at the corresponding positions of region C12 in 102.
Below, to same structure part mark it is same mark and omit the description, reference picture 5 with embodiment 1 and implement
Centered on the difference of mode 2, to be illustrated to the semiconductor device 103 of embodiment 3.
In outer electrode 31 (50), on the surface of the dip portion 31a (50a) including scolding tin engaging zones R31h, shape
The cover layer 32 better than outer electrode 31 into scolding tin wellability, this point are different from embodiment 1 and embodiment 2.
Cover layer 32 is, for example, the nickel cover layer as the metal film being made up of Ni.Cover layer 32 is for example only formed at outside
The surface of dip portion 31a (50a) in electrode 31, region in addition does not form cover layer 32, and exposes outer electrode 31
Surface.It is used as the method for cover layer 32 as Ni is formed, such as the method that Ni is formed with non-electrolytic plating method can be enumerated.
Because dip portion 31a is prominent from other regions of outer electrode 31 to the side of semiconductor element 1, therefore, it is possible to only by dip portion
31a is impregnated in electroplate liquid, and can easily carry out parcel plating.For example, it is also possible to by being powered outer electrode 31 to make
Electricity consumption electrolytic plating.
(action, effect and effect)
The semiconductor device 103 of embodiment 3 is except the embodiment 1 with outer electrode 31 or with outer electrode
Outside the effect of 50 embodiment 2, following effect is also obtained.
The table that semiconductor device 103 passes through the dip portion 31a including scolding tin engaging zones R31h in outer electrode 31
Face forms the scolding tin wellability cover layer 32 better than outer electrode 31, can promote on semiconductor element scolding tin 21 relative to sagging
Portion 31a infiltration extension, the rounding F2 of the side of outer electrode 31 is formed more reliably.
In addition, semiconductor device 103 is formed by the dip portion 31a optionally only on the surface of outer electrode 31
Cover layer 32, extend more reliably the infiltration of scolding tin 21 on semiconductor element and only stay in dip portion 31a, therefore obtain
Improve the effect of the shape controlling of scolding tin 21 on semiconductor element.
, can be with being relatively easy in addition, be used as cover layer 32 by using the nickel cover layer using Ni as constituent material
Method forms the scolding tin wellability cover layer 32 better than Cu, reliable thus, it is possible to the engagement that improves scolding tin engaging zones R31h
Property.
(variation)
As the variation of embodiment 3, the gold for constituent material with Au (gold) can be for example used as cover layer 32
Cover layer.By the golden cover layer that Au is formed with the nickel cover layer that is made up of Ni it is also possible to be formed by galvanoplastic.
By using golden cover layer as cover layer 32, reacted with the Sn (tin) as scolding tin main component
When, Sn-Au series intermetallic compounds are formed, but because 2 yuan of fusing points for being of Sn-Au series intermetallic compounds rise less, therefore,
It can suppress with being solidified as the scolding tin that the cover layer 32 of golden cover layer is reacted because fusing point rises.In addition, Au
Surface is not allowed oxidizable, high scolding tin wellability can be realized, therefore, it is possible to which the rounding of the side of outer electrode 31 is formed more reliably
F2。
<Embodiment 4>
(the 1st form：Structure)
Fig. 6 is the knot of the features for the semiconductor device 104A for representing the 1st form in the utility model embodiment 4
The explanation figure of structure.Fig. 6 is represented with gazing at region C11 or Fig. 4 institute in the semiconductor device 101 of the embodiment 1 shown in Fig. 1
The structure for gazing at the corresponding positions of region C12 in the semiconductor device 102 for the embodiment 2 shown.
Below, to same structure part mark it is same mark and omit the description, reference picture 6 with embodiment 1 and implement
Centered on the difference of mode 2, to be illustrated to the semiconductor device 104 of the 1st form as embodiment 4.
As shown in fig. 6, semiconductor device 104A is characterised by, in the face side of outer electrode 31 (50), than scolding tin
Engaging zones R31h is located on the dip portion peripheral part 31b of outer circumferential side formed with cover layer 33 (scolding tin, which is formed, prevents film).In addition,
In figure 6, using the region than dip portion 31a (50a) outer the week side of boss in outer electrode 31 as dip portion peripheral part 31b.
Cover layer 33 is formed useful as the scolding tin for the structure for hindering scolding tin extension prevents structure.Cover layer 33 for example makes
Formed with the scolding tin wellability constituent material lower than outer electrode 31.As cover layer 33, such as consider with solder resist
(solder resist) is the cover layer of constituent material.In this case, by the way that solder resist is printed in into outer electrode 31,
Be thermally dried, mask exposure, development, heat hardening, hereby it is possible to make dip portion 31a scolding tin engaging zones R31h
While exposing, the cover layer 33 using solder resist as constituent material is only optionally formed at dip portion peripheral part 31b.
(action and effect)
It is used as by being formed in outer electrode 31 in the dip portion peripheral part 31b than scolding tin engaging zones R31h in the outer part
Scolding tin forms the cover layer 33 for preventing structure, extends more reliably the infiltration of scolding tin 21 on semiconductor element and only stay in
Scolding tin engaging zones R31h, therefore the shape controlling of scolding tin 21 significantly more improves on semiconductor element.Now, by using
The scolding tin wellability cover layer 33 lower than outer electrode 31 is formed as scolding tin hinders structure, can be more reliably prevented from scolding tin to
Dip portion 31a outside infiltration extension.
By using structural material of the solder resist as cover layer 33, scolding tin infiltration extension can be reliably prevented, simultaneously
The raising with the cohesive of resin 41 can be realized.
(the 2nd form：Structure)
Fig. 7 is the knot of the features for the semiconductor device 104B for representing the 2nd form in the utility model embodiment 4
The explanation figure of structure.Fig. 7 is represented with gazing at region C11 or Fig. 4 institute in the semiconductor device 101 of the embodiment 1 shown in Fig. 1
The structure for gazing at the corresponding positions of region C12 in the semiconductor device 102 for the embodiment 2 shown.
Below, to same structure part mark it is same mark and omit the description, reference picture 7 with embodiment 1 and implement
Centered on the difference of mode 2, to be illustrated to the semiconductor device 104B of the 2nd form as embodiment 4.
As shown in the drawing, in the face side of outer electrode 31, leaned on as than scolding tin engaging zones R31h and dip portion 31a
The dip portion peripheral part 31b in the region in outside, being formed as scolding tin prevents structure formed with concavo-convex processing department 34 (concaveconvex structure).
Concavo-convex processing department 34 for example extrudes outer electrode 31 to manufacture by using the mould corresponding with the concavo-convex shape of processing department 34.Remove
Outside this, such as can also be on the dip portion peripheral part 31b of outer electrode 31 surface, being formed only makes and concavo-convex processing department 34
The resist of shape that exposes of the corresponding part of recess, be etched (etching) across resist, it is against corrosion to remove this
Agent, form concavo-convex processing department 34 accordingly.
In this way, the semiconductor device 104B of the 2nd form as embodiment 4, in the dip portion periphery of outer electrode 31
Portion 31b forms concavo-convex processing department 34, hereby it is possible to be more reliably prevented from the infiltration extension of the downward lappet 31a of scolding tin outside, simultaneously
The cohesive with resin 41 can be improved.
(effect)
The semiconductor device 104 (104A and 104B) of embodiment 4 is except the embodiment 1 with outer electrode 31 or tool
Have outside the effect of embodiment 2 of outer electrode 50, also obtain following effect.
In this way, the semiconductor device 104 of embodiment 4 is in the area of the scolding tin engaging zones R31h as outer electrode 31
The dip portion peripheral part 31b in domain, being provided as the scolding tin formation of cover layer 33 or concavo-convex processing department 34 prevents structure, hereby it is possible to
Prevent the downward lappet peripheral part 31b from forming scolding tin, thus, it is possible to form scolding tin 21 on semiconductor element with good stability
In rounding F2.
Semiconductor device 104A as the 1st form, which is formed by being used as scolding tin, prevents the cover layer 33 of film reliably to prevent
Only downward lappet peripheral part 31b forms scolding tin, improves scolding tin shape controlling, yield rate hereby it is possible to realization device and reliable
The raising of property.
As the 2nd form semiconductor device 104B by concavo-convex processing department 34 (concaveconvex structure) come reliably prevent to
Dip portion peripheral part 31b forms scolding tin, improves scolding tin shape controlling, the yield rate and reliability hereby it is possible to realization device
Improve.Also, when setting resin 41, resin 41 enters the recess of concavo-convex processing department 34, hereby it is possible to improve and resin 41
Cohesive, realize the further raising of semiconductor device 104B reliability.
<Other>
In the semiconductor device 101~104 (104A, 104B) of 1~embodiment of embodiment 4, IGBT works are listed
, can also be using other devices such as power MOSFET, commutation diode as half for the example of semiconductor element 1, but in addition
Conductor element 1 is formed.No matter which kind of situation, as long as dip portion 31a (50a) can be formed on outer electrode 31 (50), will
Dip portion 31a and the engagement of the scolding tin of semiconductor element 1, and form scolding tin rounding (rounding F1 and F2), it becomes possible to reach implementation
The effect of the raising of the energization ability and reliability of the effect of 1~embodiment of mode 4, i.e. realization device.
Also, in the utility model, as semiconductor element 1, have no reason to be particularly limited to power device, and can be with one
As apply semiconductor devices.In addition, in the range of with feature of the present utility model, various forms can be used.
The utility model is illustrated in detail, but described above is to illustrate in all respects, and not incite somebody to action this
Utility model is defined in this.It is contemplated that the infinite variety example not illustrated is both contained in the scope of the utility model.
That is, the utility model, can be by each embodiment independent assortment, or by each embodiment party in the range of its utility model
Formula is appropriately deformed, omitted.
Description of reference numerals
1：Semiconductor element；11：Surface electrode；12：Backplate；13：Scolding tin engagement metal film；14：Diaphragm；
21：Scolding tin on semiconductor element；22：Scolding tin under semiconductor element；31、35、50：Outer electrode；31a、50a：Dip portion；32、
33：Cover layer；34：Concavo-convex processing department；36：Coordination electrode；41：Resin；51：Metallic plate；52：Cu sheet metals；101~103,
104A、104B：Semiconductor device.
Claims (58)
- A kind of 1. semiconductor device, it is characterised in thatWith semiconductor element and outer electrode, wherein,The semiconductor element has side interarea and opposite side interarea, and provided with one with flat surfaces on the interarea of side Lateral electrode；The outer electrode is arranged at the top of a lateral electrode,The surface of the outer electrode and the surface of a lateral electrode are opposite,Also there is scolding tin forming portion, the scolding tin forming portion is formed on the surface of a lateral electrode and the table of the outer electrode Between face, make to electrically connect between a lateral electrode and the outer electrode,At least a portion of one lateral electrode and the outer electrode in the overlapping region of plane apparent time is defined as described one Lateral electrode and the 1st scolding tin engaging zones and the 2nd scolding tin engaging zones on the respective surface of the outer electrode,The outer electrode has the dip portion more prominent to the face side of a lateral electrode than other regions, the dip portion quilt It is arranged at the region for including the 2nd scolding tin engaging zones, and with making the outer electrode with scolding tin central point is close to Surface and a lateral electrode surface between vertical range shorten rake, wherein the scolding tin central point is described The center of 1st scolding tin engaging zones and the 2nd scolding tin engaging zones,To the 2nd scolding tin bonding land of the outer electrode since the 1st scolding tin engaging zones of a lateral electrode Domain has the end face shape for including the 1st curved shape and the 2nd curved shape formed with the scolding tin forming portion, the scolding tin forming portion Shape, wherein, the 1st curved shape is curved towards the direction of the scolding tin central point from surface to the top of a lateral electrode Song, the 2nd curved shape is from the surface of the outer electrode to the direction bending underneath towards the scolding tin central point.
- 2. semiconductor device according to claim 1, it is characterised in thatThe flat shape rectangular shaped of the 1st scolding tin engaging zones and the 2nd scolding tin engaging zones.
- 3. semiconductor device according to claim 2, it is characterised in thatRectangular shape as the 1st scolding tin engaging zones and the flat shape of the 2nd scolding tin engaging zones is in corner quilt Chamfering rectangular shape after chamfering.
- 4. semiconductor device according to claim 3, it is characterised in thatThe 1st scolding tin engaging zones and the 2nd scolding tin engaging zones are in the completely overlapped same shape of plane apparent time.
- 5. semiconductor device according to claim 3, it is characterised in thatThe dip portion has flat bottom surface sections, and the bottom surface sections include the scolding tin central point, and away from a lateral electrode The distance on surface is certain,Make the plan range from the periphery of the outer thoughtful bottom surface of the 2nd scolding tin engaging zones and the chamfering rectangular shape In corner radius of curvature it is equal.
- 6. semiconductor device according to claim 5, it is characterised in thatThe outer electrode has the through hole rearwardly penetrated from surface in the dip portion including the bottom surface sections.
- 7. according to semiconductor device according to any one of claims 1 to 6, it is characterised in thatThe outer electrode is the monomer structure using copper as constituent material.
- 8. according to semiconductor device according to any one of claims 1 to 6, it is characterised in thatThe outer electrode includes：Metallic plate, it is made up of the linear expansion coefficient metal material lower than copper；WithCopper forming layer, on its surface at least formed on the metallic plate, and using copper as constituent material.
- 9. according to semiconductor device according to any one of claims 1 to 6, it is characterised in thatAlso there is cover layer, the cover layer at least provided with the 2nd scolding tin engaging zones on the surface of the outer electrode, And formed by the scolding tin wellability constituent material more excellent than the outer electrode.
- 10. semiconductor device according to claim 7, it is characterised in thatAlso there is cover layer, the cover layer at least provided with the 2nd scolding tin engaging zones on the surface of the outer electrode, And formed by the scolding tin wellability constituent material more excellent than the outer electrode.
- 11. semiconductor device according to claim 8, it is characterised in thatAlso there is cover layer, the cover layer at least provided with the 2nd scolding tin engaging zones on the surface of the outer electrode, And formed by the scolding tin wellability constituent material more excellent than the outer electrode.
- 12. semiconductor device according to claim 9, it is characterised in thatThe cover layer is only formed in the dip portion on the surface of the outer electrode.
- 13. semiconductor device according to claim 9, it is characterised in thatThe cover layer is the nickel cover layer using nickel as constituent material.
- 14. semiconductor device according to claim 12, it is characterised in thatThe cover layer is the nickel cover layer using nickel as constituent material.
- 15. semiconductor device according to claim 9, it is characterised in thatThe cover layer is the golden cover layer using gold as constituent material.
- 16. semiconductor device according to claim 12, it is characterised in thatThe cover layer is the golden cover layer using gold as constituent material.
- 17. according to semiconductor device according to any one of claims 1 to 6, it is characterised in thatThe outer electrode has the dip portion peripheral part for being located at outer circumferential side than the 2nd scolding tin engaging zones,There is the dip portion peripheral part scolding tin, which to be formed, prevents structure, and the scolding tin, which is formed, prevents structure from preventing from forming the scolding tin The formation of scolding tin during forming portion.
- 18. semiconductor device according to claim 7, it is characterised in thatThe outer electrode has the dip portion peripheral part for being located at outer circumferential side than the 2nd scolding tin engaging zones,There is the dip portion peripheral part scolding tin, which to be formed, prevents structure, and the scolding tin, which is formed, prevents structure from preventing from forming the scolding tin The formation of scolding tin during forming portion.
- 19. semiconductor device according to claim 8, it is characterised in thatThe outer electrode has the dip portion peripheral part for being located at outer circumferential side than the 2nd scolding tin engaging zones,There is the dip portion peripheral part scolding tin, which to be formed, prevents structure, and the scolding tin, which is formed, prevents structure from preventing from forming the scolding tin The formation of scolding tin during forming portion.
- 20. semiconductor device according to claim 9, it is characterised in thatThe outer electrode has the dip portion peripheral part for being located at outer circumferential side than the 2nd scolding tin engaging zones,There is the dip portion peripheral part scolding tin, which to be formed, prevents structure, and the scolding tin, which is formed, prevents structure from preventing from forming the scolding tin The formation of scolding tin during forming portion.
- 21. semiconductor device according to claim 12, it is characterised in thatThe outer electrode has the dip portion peripheral part for being located at outer circumferential side than the 2nd scolding tin engaging zones,There is the dip portion peripheral part scolding tin, which to be formed, prevents structure, and the scolding tin, which is formed, prevents structure from preventing from forming the scolding tin The formation of scolding tin during forming portion.
- 22. semiconductor device according to claim 13, it is characterised in thatThe outer electrode has the dip portion peripheral part for being located at outer circumferential side than the 2nd scolding tin engaging zones,There is the dip portion peripheral part scolding tin, which to be formed, prevents structure, and the scolding tin, which is formed, prevents structure from preventing from forming the scolding tin The formation of scolding tin during forming portion.
- 23. semiconductor device according to claim 15, it is characterised in thatThe outer electrode has the dip portion peripheral part for being located at outer circumferential side than the 2nd scolding tin engaging zones,There is the dip portion peripheral part scolding tin, which to be formed, prevents structure, and the scolding tin, which is formed, prevents structure from preventing from forming the scolding tin The formation of scolding tin during forming portion.
- 24. semiconductor device according to claim 17, it is characterised in thatAlso there is scolding tin, which to be formed, prevents film, and the scolding tin, which is formed, prevents film to be formed at the described sagging of the face side of the outer electrode On portion's peripheral part,The scolding tin formed prevent film by the surface with forming the outer electrode material compared with the low material of scolding tin wellability Form, the scolding tin, which is formed, prevents structure from including scolding tin formation and preventing film.
- 25. semiconductor device according to claim 24, it is characterised in thatThe scolding tin, which is formed, prevents film using solder resist as constituent material.
- 26. semiconductor device according to claim 24, it is characterised in thatAlso there is concaveconvex structure, the concaveconvex structure is formed at the dip portion peripheral part of the face side of the outer electrode,The scolding tin, which is formed, prevents structure from including the concaveconvex structure.
- 27. according to semiconductor device according to any one of claims 1 to 6, it is characterised in thatThe 1st scolding tin engaging zones and the 2nd scolding tin engaging zones include multiple 1st scolding tin engaging zones and the multiple 2nd Scolding tin engaging zones,The dip portion includes the multiple dip portions corresponding with the multiple 2nd scolding tin engaging zones,The scolding tin forming portion includes relative with the multiple 1st scolding tin engaging zones and the multiple 2nd scolding tin engaging zones The multiple scolding tin forming portions answered.
- 28. semiconductor device according to claim 7, it is characterised in thatThe 1st scolding tin engaging zones and the 2nd scolding tin engaging zones include multiple 1st scolding tin engaging zones and the multiple 2nd Scolding tin engaging zones,The dip portion includes the multiple dip portions corresponding with the multiple 2nd scolding tin engaging zones,The scolding tin forming portion includes relative with the multiple 1st scolding tin engaging zones and the multiple 2nd scolding tin engaging zones The multiple scolding tin forming portions answered.
- 29. semiconductor device according to claim 8, it is characterised in thatThe 1st scolding tin engaging zones and the 2nd scolding tin engaging zones include multiple 1st scolding tin engaging zones and the multiple 2nd Scolding tin engaging zones,The dip portion includes the multiple dip portions corresponding with the multiple 2nd scolding tin engaging zones,The scolding tin forming portion includes relative with the multiple 1st scolding tin engaging zones and the multiple 2nd scolding tin engaging zones The multiple scolding tin forming portions answered.
- 30. semiconductor device according to claim 9, it is characterised in thatThe 1st scolding tin engaging zones and the 2nd scolding tin engaging zones include multiple 1st scolding tin engaging zones and the multiple 2nd Scolding tin engaging zones,The dip portion includes the multiple dip portions corresponding with the multiple 2nd scolding tin engaging zones,The scolding tin forming portion includes relative with the multiple 1st scolding tin engaging zones and the multiple 2nd scolding tin engaging zones The multiple scolding tin forming portions answered.
- 31. semiconductor device according to claim 12, it is characterised in thatThe 1st scolding tin engaging zones and the 2nd scolding tin engaging zones include multiple 1st scolding tin engaging zones and the multiple 2nd Scolding tin engaging zones,The dip portion includes the multiple dip portions corresponding with the multiple 2nd scolding tin engaging zones,The scolding tin forming portion includes relative with the multiple 1st scolding tin engaging zones and the multiple 2nd scolding tin engaging zones The multiple scolding tin forming portions answered.
- 32. semiconductor device according to claim 13, it is characterised in thatThe 1st scolding tin engaging zones and the 2nd scolding tin engaging zones include multiple 1st scolding tin engaging zones and the multiple 2nd Scolding tin engaging zones,The dip portion includes the multiple dip portions corresponding with the multiple 2nd scolding tin engaging zones,The scolding tin forming portion includes relative with the multiple 1st scolding tin engaging zones and the multiple 2nd scolding tin engaging zones The multiple scolding tin forming portions answered.
- 33. semiconductor device according to claim 15, it is characterised in thatThe 1st scolding tin engaging zones and the 2nd scolding tin engaging zones include multiple 1st scolding tin engaging zones and the multiple 2nd Scolding tin engaging zones,The dip portion includes the multiple dip portions corresponding with the multiple 2nd scolding tin engaging zones,The scolding tin forming portion includes relative with the multiple 1st scolding tin engaging zones and the multiple 2nd scolding tin engaging zones The multiple scolding tin forming portions answered.
- 34. semiconductor device according to claim 17, it is characterised in thatThe 1st scolding tin engaging zones and the 2nd scolding tin engaging zones include multiple 1st scolding tin engaging zones and the multiple 2nd Scolding tin engaging zones,The dip portion includes the multiple dip portions corresponding with the multiple 2nd scolding tin engaging zones,The scolding tin forming portion includes relative with the multiple 1st scolding tin engaging zones and the multiple 2nd scolding tin engaging zones The multiple scolding tin forming portions answered.
- 35. semiconductor device according to claim 24, it is characterised in thatThe 1st scolding tin engaging zones and the 2nd scolding tin engaging zones include multiple 1st scolding tin engaging zones and the multiple 2nd Scolding tin engaging zones,The dip portion includes the multiple dip portions corresponding with the multiple 2nd scolding tin engaging zones,The scolding tin forming portion includes relative with the multiple 1st scolding tin engaging zones and the multiple 2nd scolding tin engaging zones The multiple scolding tin forming portions answered.
- 36. semiconductor device according to claim 25, it is characterised in thatThe 1st scolding tin engaging zones and the 2nd scolding tin engaging zones include multiple 1st scolding tin engaging zones and the multiple 2nd Scolding tin engaging zones,The dip portion includes the multiple dip portions corresponding with the multiple 2nd scolding tin engaging zones,The scolding tin forming portion includes relative with the multiple 1st scolding tin engaging zones and the multiple 2nd scolding tin engaging zones The multiple scolding tin forming portions answered.
- 37. semiconductor device according to claim 26, it is characterised in thatThe 1st scolding tin engaging zones and the 2nd scolding tin engaging zones include multiple 1st scolding tin engaging zones and the multiple 2nd Scolding tin engaging zones,The dip portion includes the multiple dip portions corresponding with the multiple 2nd scolding tin engaging zones,The scolding tin forming portion includes relative with the multiple 1st scolding tin engaging zones and the multiple 2nd scolding tin engaging zones The multiple scolding tin forming portions answered.
- 38. according to semiconductor device according to any one of claims 1 to 6, it is characterised in thatAlso there is the resin of at least a portion for covering the outer electrode, the semiconductor element and the scolding tin forming portion.
- 39. semiconductor device according to claim 7, it is characterised in thatAlso there is the resin of at least a portion for covering the outer electrode, the semiconductor element and the scolding tin forming portion.
- 40. semiconductor device according to claim 8, it is characterised in thatAlso there is the resin of at least a portion for covering the outer electrode, the semiconductor element and the scolding tin forming portion.
- 41. semiconductor device according to claim 9, it is characterised in thatAlso there is the resin of at least a portion for covering the outer electrode, the semiconductor element and the scolding tin forming portion.
- 42. semiconductor device according to claim 12, it is characterised in thatAlso there is the resin of at least a portion for covering the outer electrode, the semiconductor element and the scolding tin forming portion.
- 43. semiconductor device according to claim 13, it is characterised in thatAlso there is the resin of at least a portion for covering the outer electrode, the semiconductor element and the scolding tin forming portion.
- 44. semiconductor device according to claim 15, it is characterised in thatAlso there is the resin of at least a portion for covering the outer electrode, the semiconductor element and the scolding tin forming portion.
- 45. semiconductor device according to claim 17, it is characterised in thatAlso there is the resin of at least a portion for covering the outer electrode, the semiconductor element and the scolding tin forming portion.
- 46. semiconductor device according to claim 24, it is characterised in thatAlso there is the resin of at least a portion for covering the outer electrode, the semiconductor element and the scolding tin forming portion.
- 47. semiconductor device according to claim 25, it is characterised in thatAlso there is the resin of at least a portion for covering the outer electrode, the semiconductor element and the scolding tin forming portion.
- 48. semiconductor device according to claim 26, it is characterised in thatAlso there is the resin of at least a portion for covering the outer electrode, the semiconductor element and the scolding tin forming portion.
- 49. semiconductor device according to claim 27, it is characterised in thatAlso there is the resin of at least a portion for covering the outer electrode, the semiconductor element and the scolding tin forming portion.
- 50. the semiconductor device according to claim 38, it is characterised in thatThe semiconductor element has the 1st linear expansion coefficient,The resin has 2nd linear expansion coefficient higher than the 1st linear expansion coefficient,The outer electrode has 3rd linear expansion coefficient higher than the 2nd linear expansion coefficient.
- 51. the semiconductor device according to claim 38, it is characterised in thatAlso there is scolding tin engagement metal film, the scolding tin engagement metal film on the surface of a lateral electrode at least formed on On the 1st scolding tin engaging zones,The scolding tin forming portion is formed on the surface of a lateral electrode across the scolding tin engagement metal film.
- 52. semiconductor device according to claim 50, it is characterised in thatAlso there is scolding tin engagement metal film, the scolding tin engagement metal film on the surface of a lateral electrode at least formed on On the 1st scolding tin engaging zones,The scolding tin forming portion is formed on the surface of a lateral electrode across the scolding tin engagement metal film.
- 53. semiconductor device according to claim 51, it is characterised in thatThe scolding tin engagement metal film includes the scolding tin engagement nickel film using nickel as constituent material.
- 54. semiconductor device according to claim 51, it is characterised in thatThe semiconductor element also has a diaphragm on the interarea of side, and the diaphragm is not at least formed on forming the side The region of electrode.
- 55. semiconductor device according to claim 53, it is characterised in thatThe semiconductor element also has a diaphragm on the interarea of side, and the diaphragm is not at least formed on forming the side The region of electrode.
- 56. semiconductor device according to claim 54, it is characterised in thatThe diaphragm is the polyimide film that thickness is 2~20 μm.
- 57. according to semiconductor device according to any one of claims 1 to 6, it is characterised in thatThe semiconductor element is the semiconductor element using carborundum as constituent material.
- 58. according to semiconductor device according to any one of claims 1 to 6, it is characterised in thatOne lateral electrode is made up of the material containing more than 95% aluminium.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2014/078926 WO2016067414A1 (en) | 2014-10-30 | 2014-10-30 | Semiconductor device and method for manufacturing same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207038515U true CN207038515U (en) | 2018-02-23 |
Family
ID=55856798
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201490001567.4U Expired - Lifetime CN207038515U (en) | 2014-10-30 | 2014-10-30 | Semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP6479036B2 (en) |
| CN (1) | CN207038515U (en) |
| WO (1) | WO2016067414A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111630644A (en) * | 2018-03-02 | 2020-09-04 | 新电元工业株式会社 | Semiconductor device and method for manufacturing the same |
| CN112703584A (en) * | 2018-09-26 | 2021-04-23 | 三菱电机株式会社 | Semiconductor device, power conversion device, and method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017204570A (en) * | 2016-05-11 | 2017-11-16 | 株式会社デンソー | Semiconductor device |
| US11183479B2 (en) * | 2017-03-30 | 2021-11-23 | Mitsubishi Electric Corporation | Semiconductor device, method for manufacturing the same, and power conversion device |
| WO2019167102A1 (en) * | 2018-02-27 | 2019-09-06 | 新電元工業株式会社 | Semiconductor device and method for producing semiconductor device |
| WO2019229829A1 (en) * | 2018-05-29 | 2019-12-05 | 新電元工業株式会社 | Semiconductor module |
| JP6457144B1 (en) * | 2018-09-19 | 2019-01-23 | 株式会社加藤電器製作所 | Semiconductor module |
| CN113056813B (en) | 2019-04-08 | 2024-03-12 | 新电元工业株式会社 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
| WO2020241240A1 (en) * | 2019-05-28 | 2020-12-03 | 株式会社オートネットワーク技術研究所 | Terminal-equipped flexible printed circuit board, vehicle wiring module, and power storage module |
| CN116134614A (en) * | 2020-07-20 | 2023-05-16 | 罗姆股份有限公司 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0438524Y2 (en) * | 1986-12-19 | 1992-09-09 | ||
| US5001545A (en) * | 1988-09-09 | 1991-03-19 | Motorola, Inc. | Formed top contact for non-flat semiconductor devices |
| JPH05315490A (en) * | 1992-05-07 | 1993-11-26 | Fuji Electric Co Ltd | Semiconductor element |
| JP4078993B2 (en) * | 2003-01-27 | 2008-04-23 | 三菱電機株式会社 | Semiconductor device |
| JP4400441B2 (en) * | 2004-12-14 | 2010-01-20 | 三菱電機株式会社 | Semiconductor device |
| JP4815905B2 (en) * | 2005-07-11 | 2011-11-16 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
| JP4968195B2 (en) * | 2008-06-24 | 2012-07-04 | 株式会社デンソー | Manufacturing method of electronic device |
| JP2010050395A (en) * | 2008-08-25 | 2010-03-04 | Mitsubishi Electric Corp | Semiconductor device, and method of manufacturing the same |
| JP5665572B2 (en) * | 2011-01-28 | 2015-02-04 | 三菱電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
-
2014
- 2014-10-30 JP JP2016556123A patent/JP6479036B2/en active Active
- 2014-10-30 WO PCT/JP2014/078926 patent/WO2016067414A1/en active Application Filing
- 2014-10-30 CN CN201490001567.4U patent/CN207038515U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111630644A (en) * | 2018-03-02 | 2020-09-04 | 新电元工业株式会社 | Semiconductor device and method for manufacturing the same |
| CN111630644B (en) * | 2018-03-02 | 2023-07-14 | 新电元工业株式会社 | Semiconductor device and method for manufacturing the same |
| CN112703584A (en) * | 2018-09-26 | 2021-04-23 | 三菱电机株式会社 | Semiconductor device, power conversion device, and method for manufacturing semiconductor device |
| CN112703584B (en) * | 2018-09-26 | 2024-05-14 | 三菱电机株式会社 | Semiconductor device, power conversion device, and method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2016067414A1 (en) | 2017-04-27 |
| WO2016067414A1 (en) | 2016-05-06 |
| JP6479036B2 (en) | 2019-03-06 |
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