JP4499577B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP4499577B2
JP4499577B2 JP2005011397A JP2005011397A JP4499577B2 JP 4499577 B2 JP4499577 B2 JP 4499577B2 JP 2005011397 A JP2005011397 A JP 2005011397A JP 2005011397 A JP2005011397 A JP 2005011397A JP 4499577 B2 JP4499577 B2 JP 4499577B2
Authority
JP
Japan
Prior art keywords
semiconductor
lead
electrode
wiring
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2005011397A
Other languages
Japanese (ja)
Other versions
JP2006202885A (en
Inventor
聡 平川
進吾 須藤
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2005011397A priority Critical patent/JP4499577B2/en
Publication of JP2006202885A publication Critical patent/JP2006202885A/en
Application granted granted Critical
Publication of JP4499577B2 publication Critical patent/JP4499577B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/3701Shape
    • H01L2224/37011Shape comprising apertures or cavities
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/3716Iron [Fe] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/3718Molybdenum [Mo] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754Coating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005Shape
    • H01L2224/4009Loop shape
    • H01L2224/40095Kinked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/40247Connecting the strap to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73221Strap and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01042Molybdenum [Mo]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Description

本発明は、半導体装置に関し、特に、半導体素子と外部電極とがリードで接続された電力用半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a power semiconductor device in which a semiconductor element and an external electrode are connected by leads.
電力用半導体装置に含まれる半導体素子から電気信号を取り出すために、半導体素子の表面電極と外部電極との間が、例えばアルミニウムワイヤ等の配線で接続される。また、最近では、配線抵抗を低減するために、ワイヤの代わりに板状のリードが配線に用いられている。更に、筐体となる封止樹脂との密着性を向上させるために、リードに粗面処理を施した構造も提案されている(例えば、特許文献1参照)。
特開2002−151554号公報
In order to take out an electric signal from a semiconductor element included in the power semiconductor device, the surface electrode and the external electrode of the semiconductor element are connected by a wiring such as an aluminum wire. Recently, in order to reduce wiring resistance, plate-like leads are used for wiring instead of wires. Furthermore, a structure in which the lead is subjected to a rough surface treatment in order to improve the adhesion with the sealing resin as a housing has been proposed (see, for example, Patent Document 1).
JP 2002-151554 A
しかしながら、板状のリード配線を用いた場合、封止樹脂がリード配線の下方に回り込みにくく、封止樹脂の未充填領域ができるという問題があった。かかる未充填領域は、封止樹脂の剥離の起点や絶縁不良の原因となり、電力用半導体装置の信頼性を低下させていた。特に、薄型化した電力用半導体装置において、未充填領域の発生が顕著であった。
また、リード配線は、ワイヤ配線に比較して幅が広いため、半導体素子の接合状態等を目視等で検査する場合にじゃまになり、検査工程が煩雑になるという問題もあった。
However, when the plate-like lead wiring is used, there is a problem in that the sealing resin does not easily enter the lower part of the lead wiring and an unfilled region of the sealing resin is formed. Such an unfilled region causes a starting point of peeling of the sealing resin and a cause of insulation failure, and reduces the reliability of the power semiconductor device. In particular, in the thinned power semiconductor device, the occurrence of unfilled regions was significant.
In addition, since the lead wiring is wider than the wire wiring, there is a problem that the inspection process becomes complicated because it is a hindrance when visually inspecting the bonding state of the semiconductor element or the like.
そこで、本発明は、半導体素子と外部電極とがリード配線で接続された半導体装置において、封止樹脂の未充填領域の発生を防ぎ、かつ試験工程が容易な半導体装置の提供を目的とする。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device in which a semiconductor element and an external electrode are connected by a lead wiring to prevent an unfilled region of a sealing resin from occurring and an easy test process.
本発明は、表面と裏面とを備えた半導体基板と、表面に設けられた第1電極と、裏面に設けられた第2電極と、表面に設けられ、第1電極と第2電極との間の電流を制御する制御電極とを備えた半導体素子と、半導体素子の第1電極に接続された接合部と、接合部から半導体素子の表面と略平行に延びた配線部とを備えたリードと、少なくとも半導体素子とリードを埋込む絶縁樹脂からなる筐体とを含む半導体装置であって、リードが配線部に貫通孔を有し、貫通孔の内部に絶縁樹脂が充填されていることを特徴とする半導体装置である。   The present invention provides a semiconductor substrate having a front surface and a back surface, a first electrode provided on the front surface, a second electrode provided on the back surface, and a surface provided between the first electrode and the second electrode. A semiconductor element comprising a control electrode for controlling the current of the semiconductor element, a junction connected to the first electrode of the semiconductor element, and a lead comprising a wiring part extending substantially parallel to the surface of the semiconductor element from the junction A semiconductor device including at least a semiconductor element and a housing made of an insulating resin that embeds the lead, wherein the lead has a through hole in the wiring portion, and the through hole is filled with the insulating resin. This is a semiconductor device.
以上のように、本発明にかかる半導体装置では、リードに設けられた貫通孔を通って封止樹脂が充填できるため、特に薄型の半導体装置においても完全な樹脂封止が可能となる。また、貫通孔を通して目視等による検査が可能となり、検査工程が簡略化できる。   As described above, in the semiconductor device according to the present invention, since the sealing resin can be filled through the through hole provided in the lead, complete resin sealing is possible even in a particularly thin semiconductor device. Moreover, inspection by visual inspection or the like can be performed through the through hole, and the inspection process can be simplified.
以下に、図面を参照しながら、本発明の好適な実施の形態について説明する。なお、以下の説明では、「上」、「下」、「左」、「右」およびこれらの用語を含む名称を適宜使用するが、これらの方向は図面を参照した発明の理解を容易にするために用いるものであり、実施形態を上下反転、あるいは任意の方向に回転した形態も、当然に本願発明の技術的範囲に含まれる。   Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the following description, “top”, “bottom”, “left”, “right” and names including these terms are used as appropriate, but these directions facilitate understanding of the invention with reference to the drawings. Therefore, a mode in which the embodiment is inverted upside down or rotated in an arbitrary direction is naturally included in the technical scope of the present invention.
実施の形態1.
図1は、全体が100で表される、本発明の実施の形態1にかかる電力用半導体装置の斜視図であり、図2は、図1をI−I方向に見た場合の断面図である。図1において、理解が容易となるように、樹脂筐体等を省略してある。
Embodiment 1 FIG.
FIG. 1 is a perspective view of a power semiconductor device according to a first embodiment of the present invention, represented as a whole by 100, and FIG. 2 is a cross-sectional view of FIG. 1 viewed in the II direction. is there. In FIG. 1, the resin casing and the like are omitted for easy understanding.
電力用半導体装置100は、放熱ブロック1を含む。放熱ブロック1は、電気伝導率、熱伝導率の高いものが好ましく、例えば厚さ3mmの銅板からなる。放熱ブロック1の上には、IGBT2の第2主電極であるコレクタ電極(図示せず)およびFWDi(フリーホイールダイオード)3の裏面電極がはんだ4によって、電気的かつ機械的に接続されている。IGBT2は、例えば厚さが0.25mm、縦横の長さがそれぞれ12mmであり、FWDi3は、例えば厚さが0.25mm、縦の長さが13.5mm、横の長さが12mmである。また、はんだ4には、例えば厚さが0.15mmのSn−Ag−Cu系はんだが用いられる。
放熱ブロック1は、IGBT2およびFWDi3の放熱手段と、両素子の裏面側の配線との双方を兼ねる。
The power semiconductor device 100 includes a heat dissipation block 1. The heat dissipating block 1 preferably has a high electric conductivity and high heat conductivity, and is made of, for example, a copper plate having a thickness of 3 mm. On the heat dissipation block 1, a collector electrode (not shown), which is a second main electrode of the IGBT 2, and a back electrode of the FWDi (free wheel diode) 3 are electrically and mechanically connected by solder 4. For example, the IGBT 2 has a thickness of 0.25 mm and a vertical and horizontal length of 12 mm, respectively. The FWDi 3 has a thickness of 0.25 mm, a vertical length of 13.5 mm, and a horizontal length of 12 mm, for example. As the solder 4, for example, Sn-Ag-Cu solder having a thickness of 0.15 mm is used.
The heat dissipating block 1 serves as both the heat dissipating means of the IGBT 2 and FWDi 3 and the wiring on the back side of both elements.
IGBT2の第1主電極であるエミッタ電極(図示せず)およびFWDi3の表面電極には、例えば厚さ0.3mm、幅10mmのCuからなるリード5が、はんだ4を用いて接合されている。具体的には、IGBT2およびFWDi3の表面には、はんだ接合性の良好な金属膜として、最表面からAu/Ni/Mo/Alの積層金属膜(図示せず)が蒸着により形成されており、この金属膜上にリード5が接合される。
リード5は、IGBT2との接合部5A、FWDi3との接合部5B、および段差部5Eを介して接合部5A、5Bに接続された配線部5C、5Dを有する。段差部5Eの高さは0.3mmで、リード5を折り曲げて形成されている。接合部5A、5BとIGBT2およびFWDi3の電極とは、それぞれ電気的に接続されている。はんだ4には、例えば厚さが0.1mmのSn−Ag−Cu系はんだが用いられる。接合部5A、5Bと配線部5C、5Dは、略平行となっている。
For example, a lead 5 made of Cu having a thickness of 0.3 mm and a width of 10 mm is joined to the emitter electrode (not shown) which is the first main electrode of the IGBT 2 and the surface electrode of the FWDi 3 by using the solder 4. Specifically, a multilayer metal film (not shown) of Au / Ni / Mo / Al is formed by vapor deposition from the outermost surface as a metal film having good solderability on the surfaces of IGBT2 and FWDi3, Leads 5 are bonded onto the metal film.
The lead 5 has a joint part 5A with the IGBT 2, a joint part 5B with the FWDi3, and wiring parts 5C and 5D connected to the joint parts 5A and 5B through the step part 5E. The step portion 5E has a height of 0.3 mm and is formed by bending the lead 5. Junction parts 5A and 5B and the electrodes of IGBT2 and FWDi3 are electrically connected to each other. For the solder 4, for example, Sn—Ag—Cu solder having a thickness of 0.1 mm is used. Junction part 5A, 5B and wiring part 5C, 5D are substantially parallel.
放熱ブロック1およびリード5は、それぞれリードフレームからなる電極端子6A、6Bに電気的に接続されており、外部と電流の入出力が行われる。   The heat dissipating block 1 and the lead 5 are electrically connected to electrode terminals 6A and 6B made of a lead frame, respectively, and current is input / output from / to the outside.
リード5と電極端子6Bとは、放熱ブロック1の外側において、例えば超音波溶接などを用いて接続される。放熱ブロック1の近傍で接合する場合は、固定治具などを放熱ブロック1上に配置する必要が有り、治具の干渉や工具の取り合い等の干渉を避ける工夫が必要となる。このため、リード5と電極端子6Bとの接合工程が煩雑にならないように、放熱ブロック1の外側で接合するのが好ましい。   The lead 5 and the electrode terminal 6B are connected to the outside of the heat dissipation block 1 using, for example, ultrasonic welding. When joining in the vicinity of the heat radiating block 1, it is necessary to arrange a fixing jig or the like on the heat radiating block 1, and it is necessary to devise measures to avoid interference such as jig interference and tool holding. For this reason, it is preferable to join outside the heat dissipation block 1 so that the joining process of the lead 5 and the electrode terminal 6B does not become complicated.
IGBT2の第3の電極であるゲート電極(図示せず)と、電極端子6A、6Bと共にリードフレームから形成された電極端子6Cとは、例えばアルミニウムのボンディングワイヤ7で接続されている。更に、放熱ブロック1、IGBT2、FWDi3、リード5等は、トランスファモールド法を用いて、エポキシ樹脂等の熱硬化性樹脂により樹脂封止され、樹脂筐体8が形成される。   A gate electrode (not shown) which is a third electrode of the IGBT 2 and an electrode terminal 6C formed from the lead frame together with the electrode terminals 6A and 6B are connected by an aluminum bonding wire 7, for example. Further, the heat dissipation block 1, IGBT2, FWDi3, leads 5 and the like are sealed with a thermosetting resin such as an epoxy resin using a transfer molding method, and the resin casing 8 is formed.
放熱ブロック1の裏面には、例えば、厚さが0.2mmで、樹脂筐体8よりも熱伝導性に優れた、エポキシ系材料を主とする絶縁層9が固着されており、電力用半導体装置100と、裏面に取り付けられる放熱フィン(図示せず)などとの絶縁を保つ構造となっている。
なお、樹脂封止後にリードフレームが切断され、それぞれの電極端子6A、6B、6Cの樹脂筐体8から露出した部分が、外部端子となる。
On the back surface of the heat dissipation block 1, for example, an insulating layer 9 mainly made of an epoxy material having a thickness of 0.2 mm and superior in thermal conductivity to the resin casing 8 is fixed. The structure is such that insulation is maintained between the device 100 and a radiating fin (not shown) attached to the back surface.
Note that the lead frame is cut after resin sealing, and the portions of the electrode terminals 6A, 6B, 6C exposed from the resin casing 8 serve as external terminals.
リード5の接合部5A、5Bの間の配線部5C、および接合部5Bと電極端子6Bとの接続部の間には直径が略2mmの円形の貫通孔10が設けられている。
このように、本実施の形態1にかかる電力用半導体装置100では、放熱ブロック1と対向する位置にあるリード5に、貫通孔10が設けられている。
A circular through hole 10 having a diameter of approximately 2 mm is provided between the wiring portion 5C between the joint portions 5A and 5B of the lead 5 and between the joint portion between the joint portion 5B and the electrode terminal 6B.
As described above, in the power semiconductor device 100 according to the first exemplary embodiment, the through hole 10 is provided in the lead 5 at a position facing the heat dissipation block 1.
貫通孔を有しないリードを用いた場合、放熱ブロック1とリード5の間には略0.8mmの間隙が設けられ、IGBT2およびFWDi3の表面とリード5(折り曲げ部)の間には略0.4mmの間隙が設けられる。放熱ブロック1とリード5は互いに電気的に絶縁されている必要がある。この場合、空気のみでは空間絶縁距離が不足するため、この空間に絶縁樹脂を充填することが必要となる。また、IGBT2、FWDi3の外周部もおいて、それぞれの素子の表裏の沿面絶縁距離を確保するために、絶縁樹脂が充填されることが必要である。   When a lead having no through hole is used, a gap of approximately 0.8 mm is provided between the heat dissipation block 1 and the lead 5, and approximately 0. 0 is provided between the surface of the IGBT 2 and FWDi 3 and the lead 5 (bending portion). A 4 mm gap is provided. The heat dissipation block 1 and the lead 5 must be electrically insulated from each other. In this case, since the space insulating distance is insufficient with only air, it is necessary to fill this space with an insulating resin. Moreover, in order to ensure the creeping insulation distance between the front and back surfaces of the respective elements in the outer peripheral portions of the IGBT2 and FWDi3, it is necessary to be filled with an insulating resin.
しかしながら、リード5の幅が例えば10mmの場合には、リード5の横側から中央部までの距離は5mmと長くなる。また、樹脂が充填される領域の、放熱ブロック1とリード5との間隔は、上述のように0.8mmや、0.4mmである。このため、特に、高さが0.4mmの領域には樹脂が充填されにくく、およそ10%の確率で未充填領域が残るという問題があった。   However, when the width of the lead 5 is, for example, 10 mm, the distance from the side of the lead 5 to the center is as long as 5 mm. Moreover, the space | interval of the thermal radiation block 1 and the lead | read | reed 5 of the area | region with which resin is filled is 0.8 mm and 0.4 mm as mentioned above. For this reason, in particular, there is a problem that an area having a height of 0.4 mm is hardly filled with resin, and an unfilled area remains with a probability of approximately 10%.
これに対して、樹脂の流入距離を短くしたり高さを大きくすることが、未充填領域をなくすためには効果的であるため、リード5の幅を小さくすることや接合部5A、5Bの曲げ高さを大きくすることによって樹脂の流入を容易にすることも可能である。しかしながら、かかる手段では、リード5に通電可能な電流の容量が小さくなるという問題が発生し、また、高さを大きくすると、電力用半導体装置の薄型化が困難になるという問題もあった。   On the other hand, shortening the resin inflow distance or increasing the height is effective for eliminating the unfilled region. Therefore, it is possible to reduce the width of the lead 5 and the bonding portions 5A and 5B. It is also possible to facilitate the inflow of the resin by increasing the bending height. However, this means has a problem that the capacity of the current that can be passed through the lead 5 is reduced, and if the height is increased, it is difficult to reduce the thickness of the power semiconductor device.
そこで、電力用半導体装置100では、リード5に貫通孔10を設けることにより、貫通孔10を通って樹脂を充填できるようにした。この結果、IGBT2、FWDi3の外周部への樹脂の流入距離が従来の半分以下となり、特に、外周部の中央近傍では貫通孔10からの距離を2mmまで短縮することが可能となり、未充填領域の発生を著しく軽減できた。   Therefore, in the power semiconductor device 100, the lead 5 is provided with the through hole 10 so that the resin can be filled through the through hole 10. As a result, the inflow distance of the resin to the outer peripheral portion of the IGBT 2 and FWDi 3 is less than half of the conventional one, and in particular, the distance from the through hole 10 can be shortened to 2 mm near the center of the outer peripheral portion. The occurrence was significantly reduced.
以上のように、本実施の形態1にかかる電力用半導体装置100では、トランスファモールドにおける樹脂の注入工程において、放熱ブロック1とリード5の狭隘な間隙、IGBT2とFWDi3との間の更に狭隘な間隙に樹脂の未充填領域を残すことなく注入することが可能となり、絶縁特性などに悪影響を及ぼすことなく薄型パッケージを製造することが可能となる。   As described above, in the power semiconductor device 100 according to the first embodiment, in the resin injection process in the transfer mold, a narrow gap between the heat dissipation block 1 and the lead 5 and a narrower gap between the IGBT 2 and the FWDi 3. It is possible to inject without leaving an unfilled region of resin, and a thin package can be manufactured without adversely affecting the insulation characteristics.
なお、電力用半導体装置100では、IGBTを用いる場合について説明したが、IGBTと同じくゲート配線を有する電力用半導体素子であるMOSFET等でも同様の効果を得ることができる。また、電力用の半導体素子のみならず、他の小電流制御用の半導体素子にも、かかる構造を適用しても構わない。   In the power semiconductor device 100, the case where the IGBT is used has been described. However, the same effect can be obtained with a MOSFET or the like which is a power semiconductor element having a gate wiring like the IGBT. Further, such a structure may be applied not only to a power semiconductor element but also to other small current control semiconductor elements.
また、本実施の形態では、はんだ4の材料としてSn−Ag−Cu系はんだを示したが、Sn−Pb系はんだやAu−Sn系、Au−Si系はんだ等の、半導体素子の接合に適用可能な他のはんだ材料を用いてもかまわない。また、Agペーストなどの比較的熱伝導率の高い導電性接着剤を用いても良い。   In this embodiment, Sn—Ag—Cu based solder is shown as the material of the solder 4. However, it is applied to joining of semiconductor elements such as Sn—Pb based solder, Au—Sn based, Au—Si based solder. Other possible solder materials may be used. Alternatively, a conductive adhesive having a relatively high thermal conductivity such as an Ag paste may be used.
リード5の材質としてCuを用いたが、半導体素子の主材料であるSiとの熱膨張率の差を小さくするために、CuとMoとのクラッド材料やCuとインバーとのクラッド材料、42Alloyやインバーなどの鉄系材料にNiやSn等のメッキを施した材料をリード5として使用しても良い。   Although Cu was used as the material of the lead 5, in order to reduce the difference in thermal expansion coefficient from Si which is the main material of the semiconductor element, a cladding material of Cu and Mo, a cladding material of Cu and Invar, 42 Alloy, A material obtained by plating an iron-based material such as Invar with Ni or Sn may be used as the lead 5.
IGBT2のエミッタ電極(図示せず)上に形成する金属膜としてAu/Ni/Mo/Alの積層構造を用いたが、かかる積層構造の作成には、金属製のマスクパターンを用いた真空蒸着やスパッタリング、ウェハ上に有機系材料からなるレジストパターンを形成して行うAu/Ni/Alの無電解メッキなどを用いることができる。金属膜としては、Ni、Ag、Au、Pd、Cu、はんだなどの、はんだの濡れ性の良い金属層を最表面に形成していれば良い。
なお、導電性接着剤を用いる場合には、はんだの濡れ性の良い金属膜を必ずしも最表面に形成する必要はないが、金属層の酸化によって電気抵抗が増加するため、Auなどの酸化防止層を最表面に形成することが好ましい。
A Au / Ni / Mo / Al laminated structure was used as the metal film formed on the emitter electrode (not shown) of the IGBT 2. For the production of such a laminated structure, vacuum deposition using a metal mask pattern or Sputtering, Au / Ni / Al electroless plating performed by forming a resist pattern made of an organic material on the wafer, and the like can be used. As the metal film, a metal layer having good solder wettability such as Ni, Ag, Au, Pd, Cu, or solder may be formed on the outermost surface.
When a conductive adhesive is used, it is not always necessary to form a metal film with good solder wettability on the outermost surface. However, since the electrical resistance increases due to oxidation of the metal layer, an anti-oxidation layer such as Au is used. Is preferably formed on the outermost surface.
本実施の形態1では、熱封止樹脂および筐体の樹脂材料に関しては、本実施の形態1においては、熱硬化性樹脂を用いたトランスファモールド法により樹脂筐体8が形成しているが、代わりに、PPS(ポリフェニルサルファイド)などの熱可塑性樹脂を用いたインジェクションモールド法によって形成しても構わない。   In the first embodiment, regarding the heat sealing resin and the resin material of the casing, in the first embodiment, the resin casing 8 is formed by a transfer molding method using a thermosetting resin. Instead, it may be formed by an injection molding method using a thermoplastic resin such as PPS (polyphenyl sulfide).
本実施の形態1では、放熱ブロック1の裏面にはエポキシ系の絶縁層9が固着され、リード5および引き出し電極部5Aは樹脂筐体8によって封止された形状となっている。このように、放熱ブロック1やリード5、引き出し電極5Aを外部表面に対して絶縁構造とすることで、例えば、数百ボルトから数キロボルトの絶縁耐圧が求められる、複数の電力用半導体装置100を近接配置したシステムにおいても、絶縁を必要とする部分の沿面距離を小さくすることができる。これにより、例えば、冷却フィンの小型化が可能となり、システム全体の小型化、軽量化、低コスト化が可能となる。   In the first embodiment, an epoxy insulating layer 9 is fixed to the back surface of the heat dissipation block 1, and the lead 5 and the extraction electrode portion 5 </ b> A are sealed by the resin casing 8. As described above, by providing the heat dissipation block 1, the lead 5, and the extraction electrode 5 </ b> A with an insulating structure with respect to the external surface, for example, a plurality of power semiconductor devices 100 that are required to have a withstand voltage of several hundred volts to several kilovolts are provided. Even in a system arranged close to each other, it is possible to reduce the creepage distance of a portion requiring insulation. As a result, for example, the cooling fins can be reduced in size, and the entire system can be reduced in size, weight, and cost.
なお、電力用半導体装置100で選択される材料や半導体素子は、以下で述べる他の実施の形態2〜5にも適用することができる。ここで、半導体素子は、表面と裏面とを備えた半導体基板と、表面に設けられた第1電極と、裏面に設けられた第2電極と、表面に設けられ、第1電極と第2電極との間の電流を制御する制御電極とを備えた素子をいうものとする。   The materials and semiconductor elements selected in power semiconductor device 100 can also be applied to other second to fifth embodiments described below. Here, the semiconductor element includes a semiconductor substrate having a front surface and a back surface, a first electrode provided on the front surface, a second electrode provided on the back surface, and a first electrode and a second electrode provided on the surface. And a control electrode for controlling the current between the two.
実施の形態2.
図3は、全体を200で表される、本発明の実施の形態2にかかる電力用半導体装置の断面図である。図3中、図1と同一符合は、同一又は相当箇所を示す。
電力用半導体装置200では、IGBT2およびFWDi3が、はんだ4を用いて絶縁基板11に電気的、機械的に接続されている。絶縁基板11は、AlN(窒化アルミ)板と、その両面に固着された、厚さが0.25mmのCuの配線パターン11Bからなる。IGBT2およびFWDi3は、配線パターンに11Bに電気的に接続されている。
Embodiment 2. FIG.
FIG. 3 is a cross-sectional view of the power semiconductor device according to the second embodiment of the present invention, indicated as a whole by 200. 3, the same reference numerals as those in FIG. 1 denote the same or corresponding parts.
In the power semiconductor device 200, the IGBT 2 and FWDi 3 are electrically and mechanically connected to the insulating substrate 11 using the solder 4. The insulating substrate 11 is composed of an AlN (aluminum nitride) plate and a Cu wiring pattern 11B having a thickness of 0.25 mm fixed to both sides thereof. IGBT2 and FWDi3 are electrically connected to the wiring pattern 11B.
絶縁基板11の裏面には、厚さ0.25mmのはんだ4によって、厚さ3mmのCuからなるベース板12が接合されている。
更に、ベース板12の外周には、接着剤(図示せず)を用いて、PPS(ポリフェニルサルファイド)樹脂を用いたケース13が接着され、筐体の一部を形成している
A base plate 12 made of Cu having a thickness of 3 mm is joined to the back surface of the insulating substrate 11 by a solder 4 having a thickness of 0.25 mm.
Further, a case 13 using PPS (polyphenyl sulfide) resin is bonded to the outer periphery of the base plate 12 using an adhesive (not shown) to form a part of the housing.
IGBT2およびFWDi3の表面にはリード5の接合部5A、5Bがはんだ4により接合されている。   Joined portions 5A and 5B of leads 5 are joined to the surfaces of IGBT2 and FWDi3 by solder 4.
ケース13には、外部電極6A、6B、6Cがインサート成型により取り付けられており、リード5や絶縁基板11の配線パターン11Bとは、例えば超音波溶接により接合される。また、IGBT2のゲート電極とは、アルミニウムワイヤ7により電気的に接続される。   External electrodes 6A, 6B, 6C are attached to the case 13 by insert molding, and are joined to the leads 5 and the wiring pattern 11B of the insulating substrate 11 by, for example, ultrasonic welding. The gate electrode of the IGBT 2 is electrically connected by an aluminum wire 7.
また、接合部5Aと接合部5Bの間の配線部5Cと、および接合部5Bと外部電極6Bとの間の部分に、貫通孔10が設けられている。   Moreover, the through-hole 10 is provided in the wiring part 5C between the joining part 5A and the joining part 5B, and the part between the joining part 5B and the external electrode 6B.
ケース13内には、内部の絶縁を確保するためにシリコーンゲル14が充填され、約125℃でキュアされる。更に、シリコーンゲル14を覆うように蓋部15が設けられる。   The case 13 is filled with silicone gel 14 to ensure internal insulation and cured at about 125 ° C. Furthermore, a lid 15 is provided so as to cover the silicone gel 14.
シリコーンゲル14がケース13内に充填される際に、リード5の下方には、リード5に設けられた貫通孔10からもシリコーンゲル14が注入される。この結果、リード5の下方において、シリコーンゲル14の未充填領域の発生が防止でき、絶縁信頼性の高い電力用半導体装置200を得ることができる。   When the silicone gel 14 is filled in the case 13, the silicone gel 14 is also injected below the lead 5 from the through hole 10 provided in the lead 5. As a result, the generation of an unfilled region of the silicone gel 14 under the lead 5 can be prevented, and the power semiconductor device 200 with high insulation reliability can be obtained.
また、シリコーンゲル14を、真空注入、真空脱泡する場合にも、貫通孔10からの注入、脱泡が可能となり、シリコーンゲル14の未充填領域の発生を防止できる。   Further, even when the silicone gel 14 is vacuum-injected or vacuum-degassed, the injection and degassing from the through hole 10 can be performed, and the generation of an unfilled region of the silicone gel 14 can be prevented.
このため、リード5の曲げ高さ(段差部の高さ)を小さくすることができ、薄型の電力用半導体装置200を提供することが可能となる。   For this reason, the bending height (height of the stepped portion) of the lead 5 can be reduced, and a thin power semiconductor device 200 can be provided.
実施の形態3.
図4は、全体が300で表される、本発明の実施の形態3にかかる電力用半導体装置の斜視図である。図4中、図1と同一符号は同一または相当箇所を示す。また、図4において、理解が容易となるように、樹脂筐体等を省略してある。
Embodiment 3 FIG.
FIG. 4 is a perspective view of the power semiconductor device according to the third embodiment of the present invention, indicated as a whole by 300. 4, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. Further, in FIG. 4, the resin casing and the like are omitted for easy understanding.
電力用半導体装置300では、リード5の配線部5Cが、IGBT2等の半導体素子の表面(または放熱ブロック1の表面)に対して略平行に配置された板状体となっている。配線部5Cの両側から接合部5A、5Bが延び、その一部が段差部を兼ねるとともに、先端においてIGBT2等と接合されている。段差の高さは1mmであり、接合部5A、5Bは、配線部5Cから両側に延びて、U字形に折り返されて段差部を形成し、その先がIGBT2等と接合されている。配線部5Cの両側から延びた接合部5Aは、互いにその先端がIGBT2の上で向き合うようになっている。   In the power semiconductor device 300, the wiring portion 5 </ b> C of the lead 5 is a plate-like body that is disposed substantially parallel to the surface of the semiconductor element such as the IGBT 2 (or the surface of the heat dissipation block 1). The joint portions 5A and 5B extend from both sides of the wiring portion 5C. A part of the joint portions 5A and 5B also serves as a step portion, and is joined to the IGBT 2 and the like at the tip. The height of the step is 1 mm, and the joint portions 5A and 5B extend from the wiring portion 5C to both sides, are folded back in a U shape to form a step portion, and the tip is joined to the IGBT 2 or the like. The joint portions 5A extending from both sides of the wiring portion 5C have their tips facing each other on the IGBT 2.
IGBT2およびFWDi3との接合部5A、5Bの上方の配線部5Cには、それぞれリード5の配線方向の長さが5mmで、最大幅が2mmの楕円形の貫通孔10Aが設けられている。
また、IGBT2とFWDi3とに挟まれた冷却ブロック1上の配線部5C、およびFWDi3より外方の配線部5Cには、直径が略2mmの略円形の貫通孔10が設けられている。
In the wiring portion 5C above the joint portions 5A and 5B to the IGBT 2 and FWDi3, an elliptical through hole 10A having a length in the wiring direction of the lead 5 of 5 mm and a maximum width of 2 mm is provided.
Further, a substantially circular through hole 10 having a diameter of approximately 2 mm is provided in the wiring portion 5C on the cooling block 1 sandwiched between the IGBT 2 and the FWDi3 and the wiring portion 5C outside the FWDi3.
図5には示していないが、冷却ブロック1やIGBT2等は、図2に示したように、トランスファモールド法を用いて、絶縁樹脂からなる樹脂状態で封止される。   Although not shown in FIG. 5, the cooling block 1, the IGBT 2, and the like are sealed in a resin state made of an insulating resin by using a transfer mold method as shown in FIG. 2.
本実施の形態にかかる電力用半導体装置300では、リード5に貫通孔10Aを設けることにより、リード5の下方において封止樹脂の未充填領域の発生を防止できるとともに、IGBT2等の半導体素子の周辺部でリード5と封止樹脂との密着性を向上させることができる。   In the power semiconductor device 300 according to the present embodiment, by providing the lead 5 with the through hole 10A, generation of an unfilled region of the sealing resin under the lead 5 can be prevented, and the periphery of the semiconductor element such as the IGBT 2 can be prevented. This can improve the adhesion between the lead 5 and the sealing resin.
また、IGBT2とFWDi3の間や、FWDi3とリードフレームにて形成される外部電極5Cとの間にも貫通孔10を設けることにより、更に、放熱ブロック1とリード5との間隙への樹脂の充填が容易となる。   Further, by providing a through hole 10 between the IGBT 2 and the FWDi 3 or between the FWDi 3 and the external electrode 5C formed by the lead frame, the resin is filled in the gap between the heat dissipation block 1 and the lead 5. Becomes easy.
加えて、IGBT2やFWDi3との接合部5A、5Bが、両側から互いに向き合うように形成され、その上方のリード5に貫通孔10Aを設けることにより、接合部5A、5Bのはんだフィレットの状態などを目視等で検査することが容易となり、リード5の接合状態の検査工程を短時間で、簡単に行うことができる。   In addition, the joints 5A and 5B to the IGBT 2 and FWDi 3 are formed so as to face each other from both sides, and by providing a through hole 10A in the lead 5 thereabove, the state of the solder fillet of the joints 5A and 5B, etc. Inspection by visual inspection or the like becomes easy, and the inspection process of the bonding state of the lead 5 can be easily performed in a short time.
更に、電力用半導体装置の熱特性を評価する場合においても、貫通孔の無い構造では、IGBT2表面、FWDi3表面の温度実測は、予め熱電対を取り付けた熱特性を測定するためのサンプルを別途作成する必要があったが、貫通孔10、10Aを設けることによってサーモグラフィを用いた測定が可能となり、別途測定用サンプルを作製する必要がなくなった。また、測定誤差の少ない正確な温度測定が可能となった。   Furthermore, even when evaluating the thermal characteristics of power semiconductor devices, in the case of a structure without through-holes, the temperature measurement of the IGBT2 surface and FWDi3 surface is separately prepared for measuring the thermal characteristics with a thermocouple attached in advance. However, by providing the through holes 10 and 10A, the measurement using the thermography becomes possible, and it is not necessary to separately prepare a measurement sample. In addition, accurate temperature measurement with little measurement error is possible.
実施の形態4.
図5は、全体が400で表される、本発明の実施の形態4にかかる電力用半導体装置の斜視図である。図5中、図1と同一符号は同一または相当箇所を示す。また、図5において、理解が容易となるように、樹脂筐体等を省略してある。
Embodiment 4 FIG.
FIG. 5 is a perspective view of the power semiconductor device according to the fourth embodiment of the present invention, indicated as a whole by 400. In FIG. 5, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. Further, in FIG. 5, a resin casing or the like is omitted for easy understanding.
電力用半導体装置400では、IGBT2およびFWDi3との接合部5A、5Bの上方のリード5(配線部5C)には、それぞれ直径が2mmの円形の貫通孔10が、配線方向に2つずつ形成されている。他の構造は、上述の電力用半導体装置300と同様である。   In the power semiconductor device 400, two circular through holes 10 each having a diameter of 2 mm are formed in the wiring direction in the leads 5 (wiring portions 5C) above the joint portions 5A and 5B with the IGBT 2 and the FWDi 3, respectively. ing. Other structures are the same as those of the power semiconductor device 300 described above.
かかる電力用半導体装置400では、リード5の機械的剛性、電気伝導面積を著しく減少させることなく、リード5および接合部5A、5Bとの狭隘な間隙への封止樹脂の充填が容易となる。また、IGBT2やFWDi3表面のはんだ4の外観検査や、電力用半導体装置の熱特性評価を容易に行うことができる。   In such a power semiconductor device 400, the sealing resin can be easily filled into a narrow gap between the lead 5 and the joints 5A and 5B without significantly reducing the mechanical rigidity and the electric conduction area of the lead 5. Further, the appearance inspection of the solder 4 on the surface of the IGBT 2 or the FWDi 3 and the thermal characteristic evaluation of the power semiconductor device can be easily performed.
なお、図6は、電力用半導体装置400に用いることができる、他のリード5の斜視図である。図6では、リード5の接合部5A、5Bが、配線部5Cとは別部材から形成されている。リード5の配線部5Cと接合部5A、5Bとは、例えば、ろう付けや溶接などにより接続される。   FIG. 6 is a perspective view of another lead 5 that can be used in the power semiconductor device 400. In FIG. 6, the joint portions 5A and 5B of the lead 5 are formed from members different from the wiring portion 5C. The wiring portion 5C of the lead 5 and the joint portions 5A and 5B are connected by, for example, brazing or welding.
図6に示すようなリード5では、リード5の厚さを1.0mm、接合部5A、5Bの厚さを0.3mmとし、両者の厚さに差異を設けたり、接合部5A、5Bを、リード5の材料と比べて熱膨張率の小さい材料から形成したりすることができる。これにより、接合部5A、5BとIGBT2、FWDi3とを接続する例えばはんだ4の熱応力による破壊を抑制することが可能となり、より信頼性の高く、環境変化の影響を受けにくい電力用半導体装置を得ることが可能となる。   In the lead 5 as shown in FIG. 6, the thickness of the lead 5 is 1.0 mm and the thickness of the joint portions 5A and 5B is 0.3 mm. The lead 5 can be made of a material having a smaller coefficient of thermal expansion than the material of the lead 5. As a result, it is possible to suppress breakage due to thermal stress of, for example, the solder 4 that connects the joints 5A and 5B and the IGBTs 2 and FWDi3. Can be obtained.
実施の形態5.
図7は、本発明の実施の形態5にかかる電力用半導体装置に用いるリードの展開図であり、図8は、図7のリードを用いた、全体が500で表される電力用半導体装置の斜視図である。図7、8中、図1と同一符号は同一または相当箇所を示す。また、図8において、理解が容易となるように、樹脂筐体等を省略してある。
Embodiment 5 FIG.
FIG. 7 is a developed view of leads used in the power semiconductor device according to the fifth embodiment of the present invention. FIG. 8 is a diagram of a power semiconductor device represented by 500 as a whole using the leads in FIG. It is a perspective view. 7 and 8, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. Further, in FIG. 8, a resin casing or the like is omitted for easy understanding.
電力用半導体装置500では、リード5のIGBT2およびFWDi3との接合部5A、5Bがそれぞれ櫛歯状になっており、それぞれU字形に折り曲げられてIGBT2等に接合されている。
IGBT2、FWDi3と接合された接合部5A、5Bの上方に位置するリード5(配線部5C)には貫通孔10Aが設けられている。また、IGBT2とFWDi3との間の、冷却ブロック1の上方に位置するリード5(配線部5C)には、貫通孔10Aより開口面積の小さい貫通孔10が設けられている。
In the power semiconductor device 500, the joint portions 5A and 5B of the lead 5 with the IGBT 2 and FWDi 3 are comb-shaped, respectively, bent into a U shape, and joined to the IGBT 2 or the like.
A through hole 10A is provided in the lead 5 (wiring part 5C) located above the joints 5A and 5B joined to the IGBT2 and FWDi3. Further, the lead 5 (wiring part 5C) located above the cooling block 1 between the IGBT 2 and the FWDi 3 is provided with a through hole 10 having an opening area smaller than the through hole 10A.
かかる電力用半導体装置500では、半導体素子であるIGBT2やFWDi3とリード5の接合部5A、5Bとの接合面積が小さくなる。この結果、電力用半導体装置全体に温度サイクルが付加された場合に、はんだ4にかかる熱応力が小さくなり、破損等が防止できる。   In such a power semiconductor device 500, the junction area between the semiconductor element IGBT2 or FWDi3 and the joints 5A and 5B of the lead 5 is reduced. As a result, when a temperature cycle is applied to the entire power semiconductor device, the thermal stress applied to the solder 4 is reduced, and damage or the like can be prevented.
また、接合部5A、5Bでは、はんだ量のばらつきにより一部が未接合となる可能性が有り、何らかの形での検査が必要となる。リード5に貫通孔10Aを形成することにより、IGBT2およびFWDi3との接合部がそれぞれの半導体素子の直上から目視等で確認でき、検査工程の簡略化が可能となる。   In addition, the joint portions 5A and 5B may be partially unjoined due to variations in the amount of solder, and some form of inspection is required. By forming the through hole 10A in the lead 5, the joint between the IGBT 2 and the FWDi 3 can be visually confirmed from directly above the respective semiconductor elements, and the inspection process can be simplified.
特に、図7の展開図を示したように、それぞれ櫛歯状に分割された接合部を折り曲げた場合に、その直上に貫通孔10Aが位置するような構成とすることが好ましい。   In particular, as shown in the development view of FIG. 7, it is preferable that the through-hole 10 </ b> A is positioned immediately above the joint portions that are divided into comb teeth.
なお、冷却ブロック1の上方に位置するリード5(配線部5C)設けられた貫通孔10は、樹脂を充填する際に未充填領域を残さないために形成されたものであり、貫通穴10Aに比べて面積が小さくても構わない。   The through hole 10 provided in the lead 5 (wiring part 5C) located above the cooling block 1 is formed so as not to leave an unfilled region when filling with resin, and is formed in the through hole 10A. The area may be smaller than that.
本発明の実施の形態1にかかる電力用半導体装置の斜視図である。1 is a perspective view of a power semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態1にかかる電力用半導体装置の断面図である。It is sectional drawing of the semiconductor device for electric power concerning Embodiment 1 of this invention. 本発明の実施の形態2にかかる電力用半導体装置の断面図である。It is sectional drawing of the semiconductor device for electric power concerning Embodiment 2 of this invention. 本発明の実施の形態3にかかる電力用半導体装置の斜視図である。It is a perspective view of the semiconductor device for electric power concerning Embodiment 3 of this invention. 本発明の実施の形態4にかかる電力用半導体装置の斜視図である。It is a perspective view of the semiconductor device for electric power concerning Embodiment 4 of this invention. 本発明の実施の形態4にかかる電力用半導体装置に用いられるリードの概略図である。It is the schematic of the lead | read | reed used for the power semiconductor device concerning Embodiment 4 of this invention. 本発明の実施の形態5にかかる電力用半導体装置に用いられるリードの展開図である。It is an expanded view of the lead | read | reed used for the power semiconductor device concerning Embodiment 5 of this invention. 本発明の実施の形態5にかかる電力用半導体装置の斜視図である。It is a perspective view of the semiconductor device for electric power concerning Embodiment 5 of this invention.
符号の説明Explanation of symbols
1 放熱ブロック、2 IGBT、3 FWDi、4 はんだ、5 リード、6A、6B、6C 外部端子、7 アルミニウムワイヤ、8 樹脂筐体、9 絶縁層、10、10A 貫通孔、100 電力用半導体装置。

DESCRIPTION OF SYMBOLS 1 Heat radiation block, 2 IGBT, 3 FWDi, 4 Solder, 5 Lead, 6A, 6B, 6C External terminal, 7 Aluminum wire, 8 Resin housing | casing, 9 Insulating layer 10, 10A Through-hole, 100 Semiconductor device for electric power.

Claims (4)

  1. 表面と裏面とを備えた半導体基板と、該表面に設けられた第1電極と、該裏面に設けられた第2電極と、該表面に設けられ、該第1電極と該第2電極との間の電流を制御する制御電極とを備えた第1の半導体素子と、
    少なくとも表面電極と裏面電極とを備えた第2の半導体素子と、
    該第1の半導体素子の該第1電極に接続された接合部と、該第2の半導体素子の該表面電極に接続された接合部と、該接合部から半導体素子の表面と略平行に延びた配線部とを備えたリードと、
    該第1の半導体素子の該第2電極と、該第2の半導体素子の該裏面電極とが固着された主表面を有する配線パターンと、
    少なくとも該第1の半導体素子と、該第2の半導体素子と、該リードとを埋込む絶縁樹脂を有する筐体とを備えた半導体装置であって、
    該リードは、該配線パターンの主表面と対向する領域内に貫通孔を有し、該貫通孔の内部に該絶縁樹脂が充填されていることを特徴とする半導体装置。
    A semiconductor substrate having a front surface and a back surface, a first electrode provided on the front surface, a second electrode provided on the back surface, a first electrode provided on the front surface, and the first electrode and the second electrode A first semiconductor element comprising a control electrode for controlling the current between;
    A second semiconductor element comprising at least a front electrode and a back electrode;
    A junction connected to the first electrode of the first semiconductor element; a junction connected to the surface electrode of the second semiconductor element; and extending substantially parallel to the surface of the semiconductor element from the junction. A lead having a wiring portion,
    A wiring pattern having a main surface to which the second electrode of the first semiconductor element and the back electrode of the second semiconductor element are fixed;
    A semiconductor device comprising at least the first semiconductor element, the second semiconductor element, and a housing having an insulating resin that embeds the lead,
    The lead has a through hole in a region facing the main surface of the wiring pattern, and the insulating resin is filled in the through hole.
  2. 上記配線部が、上記半導体素子の表面に対して略平行でありかつ該表面を覆うように、段差部を介して上記接合部に接続されていることを特徴とする請求項1に記載の半導体装置。   2. The semiconductor according to claim 1, wherein the wiring part is connected to the junction part through a step part so as to be substantially parallel to and cover the surface of the semiconductor element. apparatus.
  3. 上記配線部の該配線部を挟んで対向する位置に、上記接合部が接続され、該配線部と該接合部とが対向する部分には上記絶縁樹脂が充填されていることを特徴とする請求項2に記載の半導体装置。   The bonding portion is connected to a position of the wiring portion facing each other with the wiring portion interposed therebetween, and a portion where the wiring portion and the bonding portion face each other is filled with the insulating resin. Item 3. The semiconductor device according to Item 2.
  4. 上記配線部の貫通孔が、更に、上記半導体素子の表面を覆っている部分に形成され、接合部もしくは接合する接合材の一部を覆うように設けられていることを特徴とする請求項2または3に記載の半導体装置。 Claims through-hole of the wiring portion, further, also in the portion that covers the surface of the upper Symbol semiconductor element is formed, characterized in that is provided so as to cover a part of the joint or the joining material for joining Item 4. The semiconductor device according to Item 2 or 3.
JP2005011397A 2005-01-19 2005-01-19 Semiconductor device Active JP4499577B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005011397A JP4499577B2 (en) 2005-01-19 2005-01-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005011397A JP4499577B2 (en) 2005-01-19 2005-01-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2006202885A JP2006202885A (en) 2006-08-03
JP4499577B2 true JP4499577B2 (en) 2010-07-07

Family

ID=36960625

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005011397A Active JP4499577B2 (en) 2005-01-19 2005-01-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JP4499577B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103065978A (en) * 2012-12-25 2013-04-24 佛山市蓝箭电子股份有限公司 Composite loading ligature method of insulated gate bipolar translator (IGBT) device

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4967701B2 (en) * 2007-02-19 2012-07-04 三菱電機株式会社 Power semiconductor device
JP5165302B2 (en) * 2007-07-31 2013-03-21 オンセミコンダクター・トレーディング・リミテッド Semiconductor device and manufacturing method thereof
JP2009277959A (en) * 2008-05-16 2009-11-26 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
JP4666185B2 (en) * 2008-06-26 2011-04-06 三菱電機株式会社 Semiconductor device
JP5151837B2 (en) * 2008-09-10 2013-02-27 富士電機株式会社 Manufacturing method of semiconductor device
JP5185956B2 (en) * 2010-01-06 2013-04-17 三菱電機株式会社 Power semiconductor device
JP5368357B2 (en) * 2010-04-01 2013-12-18 三菱電機株式会社 Electrode member and semiconductor device using the same
JP5790039B2 (en) * 2010-07-23 2015-10-07 富士電機株式会社 Semiconductor device
WO2012127696A1 (en) * 2011-03-24 2012-09-27 三菱電機株式会社 Power semiconductor module and power unit device
JP5863602B2 (en) * 2011-08-31 2016-02-16 三菱電機株式会社 Power semiconductor device
JP5820696B2 (en) * 2011-11-07 2015-11-24 新電元工業株式会社 Semiconductor device manufacturing method and semiconductor device manufacturing jig
JP6084367B2 (en) * 2012-04-06 2017-02-22 株式会社 日立パワーデバイス Semiconductor device
JP2013232495A (en) * 2012-04-27 2013-11-14 Mitsubishi Electric Corp Semiconductor device
JP5924164B2 (en) 2012-07-06 2016-05-25 株式会社豊田自動織機 Semiconductor device
JP5696696B2 (en) * 2012-08-03 2015-04-08 株式会社豊田自動織機 Semiconductor device
JP5418654B2 (en) * 2012-10-09 2014-02-19 富士電機株式会社 Semiconductor device
KR101443968B1 (en) * 2012-10-29 2014-09-23 삼성전기주식회사 Power module package and method of manufacturing the same
JP6012533B2 (en) * 2013-04-05 2016-10-25 三菱電機株式会社 Power semiconductor device
JP6152893B2 (en) * 2013-09-30 2017-06-28 富士電機株式会社 Semiconductor device, method for assembling semiconductor device, component for semiconductor device, and unit module
CN105706236B (en) * 2014-01-27 2019-03-01 三菱电机株式会社 The manufacturing method of electrode terminal, power semiconductor device and power semiconductor device
JP2017073406A (en) * 2014-02-24 2017-04-13 三菱電機株式会社 Electrode lead and semiconductor device
JP2016018866A (en) * 2014-07-08 2016-02-01 三菱電機株式会社 Power module
JP6292066B2 (en) * 2014-07-25 2018-03-14 三菱電機株式会社 Power semiconductor device
JP6451747B2 (en) 2014-11-28 2019-01-16 富士電機株式会社 Semiconductor device
JP6613806B2 (en) 2015-10-23 2019-12-04 富士電機株式会社 Semiconductor device
DE112016005397T5 (en) * 2015-11-25 2018-08-09 Mitsubishi Electric Corporation POWER SEMICONDUCTOR DEVICE
JP6750263B2 (en) 2016-03-18 2020-09-02 富士電機株式会社 Power semiconductor module
DE112016007372T5 (en) * 2016-10-24 2019-07-11 Mitsubishi Electric Corporation Semiconductor device and manufacturing method therefor
CN110959189A (en) * 2017-08-01 2020-04-03 株式会社村田制作所 High frequency module
JP6440794B1 (en) * 2017-09-22 2018-12-19 三菱電機株式会社 Semiconductor device
CN111602240A (en) 2018-03-02 2020-08-28 新电元工业株式会社 Resin-encapsulated semiconductor device
JPWO2019194272A1 (en) * 2018-04-06 2020-10-22 三菱電機株式会社 Semiconductor device, power conversion device, and manufacturing method of semiconductor device
WO2020071102A1 (en) * 2018-10-05 2020-04-09 富士電機株式会社 Semiconductor device, semiconductor module and vehicle

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002151554A (en) * 2000-08-31 2002-05-24 Nec Corp Semiconductor device
JP2002314018A (en) * 2001-04-18 2002-10-25 Toshiba Corp Semiconductor device and its manufacturing method
JP2004146577A (en) * 2002-10-24 2004-05-20 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2004221516A (en) * 2002-11-22 2004-08-05 Toyota Industries Corp Semiconductor module and lead therefor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6867481B2 (en) * 2003-04-11 2005-03-15 Fairchild Semiconductor Corporation Lead frame structure with aperture or groove for flip chip in a leaded molded package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002151554A (en) * 2000-08-31 2002-05-24 Nec Corp Semiconductor device
JP2002314018A (en) * 2001-04-18 2002-10-25 Toshiba Corp Semiconductor device and its manufacturing method
JP2004146577A (en) * 2002-10-24 2004-05-20 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2004221516A (en) * 2002-11-22 2004-08-05 Toyota Industries Corp Semiconductor module and lead therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103065978A (en) * 2012-12-25 2013-04-24 佛山市蓝箭电子股份有限公司 Composite loading ligature method of insulated gate bipolar translator (IGBT) device
CN103065978B (en) * 2012-12-25 2015-04-08 佛山市蓝箭电子股份有限公司 Composite loading ligature method of insulated gate bipolar translator (IGBT) device

Also Published As

Publication number Publication date
JP2006202885A (en) 2006-08-03

Similar Documents

Publication Publication Date Title
US9504154B2 (en) Semiconductor device
US9917031B2 (en) Semiconductor device, and method for assembling semiconductor device
JP5572678B2 (en) Semiconductor device including a clad base plate
JP5588956B2 (en) Power semiconductor device
US6914325B2 (en) Power semiconductor module
JP4567773B2 (en) Power semiconductor device
JP5383621B2 (en) Power semiconductor device
JP5272191B2 (en) Semiconductor device and manufacturing method of semiconductor device
US8030749B2 (en) Semiconductor device
US6998707B2 (en) Semiconductor device having radiation structure
US9240371B2 (en) Semiconductor module, semiconductor device having semiconductor module, and method of manufacturing semiconductor module
JP4453498B2 (en) Power semiconductor module and manufacturing method thereof
US7705443B2 (en) Semiconductor device with lead frame including conductor plates arranged three-dimensionally
US9035453B2 (en) Semiconductor device
KR101505551B1 (en) Semiconductor power module package with temperature sensor mounted thereon and method of fabricating the same
JP5936679B2 (en) Semiconductor device
JP3357220B2 (en) Semiconductor device
JP4468115B2 (en) Semiconductor device
CN107210238B (en) Power module
US7728413B2 (en) Resin mold type semiconductor device
JP5253455B2 (en) Power semiconductor device
JP4640345B2 (en) Power semiconductor device
US7239016B2 (en) Semiconductor device having heat radiation plate and bonding member
JP2004266096A (en) Semiconductor device and method for manufacturing it, and electronic device
JP2010027814A (en) Power semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20061214

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20081209

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090804

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090928

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100119

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100319

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100413

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100415

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130423

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4499577

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130423

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140423

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250