JP2001284525A - Semiconductor chip and semiconductor device - Google Patents

Semiconductor chip and semiconductor device

Info

Publication number
JP2001284525A
JP2001284525A JP2000097911A JP2000097911A JP2001284525A JP 2001284525 A JP2001284525 A JP 2001284525A JP 2000097911 A JP2000097911 A JP 2000097911A JP 2000097911 A JP2000097911 A JP 2000097911A JP 2001284525 A JP2001284525 A JP 2001284525A
Authority
JP
Japan
Prior art keywords
heat
substrate
joined
semiconductor device
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000097911A
Other languages
Japanese (ja)
Other versions
JP3630070B2 (en
Inventor
Yutaka Fukuda
豊 福田
Kazuo Kajimoto
一雄 梶本
Kazuhito Nomura
和仁 野村
Takeshi Miyajima
健 宮嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2000097911A priority Critical patent/JP3630070B2/en
Priority to US09/717,227 priority patent/US6703707B1/en
Priority to FR0015130A priority patent/FR2801423B1/en
Priority to DE10058446A priority patent/DE10058446B8/en
Priority to DE10066445A priority patent/DE10066445B4/en
Priority to DE10066442A priority patent/DE10066442B4/en
Priority to DE10066443A priority patent/DE10066443B8/en
Priority to DE10066441A priority patent/DE10066441B4/en
Priority to DE10066446A priority patent/DE10066446B4/en
Publication of JP2001284525A publication Critical patent/JP2001284525A/en
Priority to US10/321,365 priority patent/US6693350B2/en
Priority to US10/699,828 priority patent/US6992383B2/en
Priority to US10/699,837 priority patent/US6960825B2/en
Priority to US10/699,746 priority patent/US6998707B2/en
Priority to US10/699,784 priority patent/US20040089941A1/en
Priority to US10/699,785 priority patent/US6891265B2/en
Priority to US10/699,954 priority patent/US6967404B2/en
Priority to US10/699,838 priority patent/US6798062B2/en
Priority to US10/699,744 priority patent/US20040089940A1/en
Application granted granted Critical
Publication of JP3630070B2 publication Critical patent/JP3630070B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip in which external stress can be relaxed and a semiconductor device in which external stress being applied to an incorporated semiconductor chip can be relaxed. SOLUTION: Electrodes 112, 115 on one side 1a and the other side 1b of IGBT 11 and FWD 12 are made of pure Al and a barrier metal 111 is formed between the one side 1a of a substrate 110 and the electrode 112. One side 5a of a DBC substrate 4 is bonded to the other side 1b of the chips 11, 12 and the end part 23a of a heat dissipation member 20 on one side bonded to one side 1a of the chip is bonded to one side 5a of the DBC substrate 4. A heat dissipation member 24 on the other side is bonded to the other side 5b of the DBC substrate 4 and a heat dissipation plane 9 is formed on the heat dissipation member 24 on the other side.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体チップおよ
びその実装構造に関し、特にパワー素子が形成された半
導体チップを用いる場合に好適である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip and a mounting structure thereof, and is particularly suitable when a semiconductor chip on which a power element is formed is used.

【０００２】[0002]

【従来の技術】従来、パワーデバイスが形成された半導
体チップ（以下、単にチップという）は、半田等の接合
部材を介して、Ｃｕ等からなる放熱部材に接合して放熱
を行っている。近年、その放熱効率を向上させるため
に、チップの表裏両面から放熱を行うべく、チップにお
けるトランジスタやコンデンサ等のデバイスが形成され
ている素子形成領域にも放熱部材を設けるようになって
いる。2. Description of the Related Art Conventionally, a semiconductor chip on which a power device is formed (hereinafter simply referred to as a chip) is radiated by bonding to a radiating member made of Cu or the like via a bonding member such as solder. In recent years, in order to improve the heat radiation efficiency, a heat radiation member has been provided also in an element formation region of the chip where devices such as transistors and capacitors are formed in order to radiate heat from both front and back surfaces of the chip.

【０００３】図４は、チップの一例としてのＩＧＢＴ
（Insulated Gate Bipolar Transistor）の概略断面図
である。図４に示すように、チップＪ１にはＳｉ（珪
素）からなる基板Ｊ２においてデバイスＪ３が形成され
ている。また、デバイスＪ３の表面には、Ａｌ（アルミ
ニウム）に１％程度のＳｉを含んだ金属からなるエミッ
タ電極（配線）Ｊ４が形成されている。FIG. 4 shows an IGBT as an example of a chip.
It is a schematic sectional drawing of (Insulated Gate Bipolar Transistor). As shown in FIG. 4, a device J3 is formed on a substrate J2 made of Si (silicon) on a chip J1. On the surface of the device J3, an emitter electrode (wiring) J4 made of a metal containing Al (aluminum) containing about 1% of Si is formed.

【０００４】ところで、この電極Ｊ４として不純物を含
まないＡｌ（以下、純Ａｌという）を用いると、基板と
電極とが直接接触する部分であるコンタクト部Ｊ５にお
いて、ＳｉがＡｌ中に溶解することで生じるアロイスパ
イクが生じる。そして、このアロイスパイクが、例えば
ＰＮ接合を破壊するなどしてデバイスの特性に大きな影
響を与える。従って、ＡｌにＳｉを含有させることによ
り、このアロイスパイクの発生を抑制している。When Al containing no impurity (hereinafter referred to as pure Al) is used as the electrode J4, Si is dissolved in Al at the contact portion J5 where the substrate and the electrode are in direct contact. The resulting alloy spike occurs. The alloy spike has a great effect on the characteristics of the device, for example, by destroying the PN junction. Therefore, the generation of this alloy spike is suppressed by adding Si to Al.

【０００５】[0005]

【発明が解決しようとする課題】しかし、Ａｌに過剰の
Ｓｉが含有されていると、デバイス表面のゲート電極部
Ｊ６の絶縁膜などにおいてＳｉ微粒子が析出（以下、Ｓ
ｉノジュール析出という）する。そして、チップにワイ
ヤを超音波接合する場合は、上記電極上にワイヤボンド
するが、この際、上記Ｓｉノジュール析出による析出粒
付近にワイヤボンドすると、析出粒がボンディング時の
振動エネルギーを受け、析出粒を起点としてデバイスＪ
３及びゲート電極部Ｊ６にクラックが生じる。However, if Al contains excessive Si, Si fine particles are deposited on the insulating film of the gate electrode portion J6 on the device surface (hereinafter referred to as S).
i-nodule precipitation). When the wire is ultrasonically bonded to the chip, the wire is bonded on the electrode. At this time, if the wire is bonded near the precipitated particle due to the Si nodule precipitation, the deposited particle receives vibration energy during bonding, and Device J starting from a grain
3 and the gate electrode portion J6 are cracked.

【０００６】ところで、近年、パワー素子を小型化する
要望があり、これに伴い、セルピッチ（図４においてＬ
で示している）が細かくなっている。また、オン抵抗を
下げるためゲートをトレンチ構造とすること等にもより
セルピッチＬがさらに細かくなり、例えば４μｍ以下の
ものも現れてきている。In recent years, there has been a demand for downsizing the power element. In response to this, the cell pitch (L in FIG.
) Are finer. Further, the cell pitch L is further reduced by forming the gate in a trench structure in order to reduce the on-resistance, and for example, those having a cell pitch L of 4 μm or less have appeared.

【０００７】そして、セルピッチＬが細かくなるほど、
上述のように、析出粒に機械的な応力が集中することに
より、デバイスＪ３にクラックが発生するという問題が
深刻になる。As the cell pitch L becomes finer,
As described above, the problem that cracks occur in the device J3 due to the concentration of mechanical stress on the precipitated grains becomes serious.

【０００８】一方、図４のエミッタ電極Ｊ４およびコレ
クタ電極Ｊ７の外側に放熱部材を接合させる等して、チ
ップＪ１を一対の放熱部材で挟んだ構成に着目する。こ
の場合、ＳｉからなるチップＪ１の熱膨張係数と、Ｃｕ
等からなる放熱部材の熱膨張係数の差が大きいため、冷
熱サイクルにおいて大きな熱応力が発生する。ここで、
Ｓｉを含むＡｌは、純Ａｌよりも弾性率が大きいため、
電極Ｊ４、Ｊ７における熱応力の緩和が不十分となる。
その結果、特に素子形成面側では、例えばチップのエミ
ッタセルＪ８及びゲート電極部Ｊ６に熱応力が集中し、
ゲート電圧の閾値（以下、Ｖｔとする）等の電気特性が
変動することが懸念される。On the other hand, attention will be paid to a configuration in which a chip J1 is sandwiched between a pair of heat radiating members, such as by bonding a heat radiating member to the outside of the emitter electrode J4 and the collector electrode J7 in FIG. In this case, the thermal expansion coefficient of the chip J1 made of Si and Cu
Since the difference in the thermal expansion coefficient between the heat radiating members made of the above is large, a large thermal stress is generated in the cooling / heating cycle. here,
Since Al containing Si has a higher elastic modulus than pure Al,
Relaxation of thermal stress in the electrodes J4 and J7 becomes insufficient.
As a result, especially on the element forming surface side, thermal stress concentrates on, for example, the emitter cell J8 and the gate electrode portion J6 of the chip,
There is a concern that electrical characteristics such as a threshold of a gate voltage (hereinafter, referred to as Vt) fluctuate.

【０００９】また、放熱部材を素子形成領域（例えば、
図４ではエミッタセルＪ８の形成領域）にも設け、さら
に、冷却部材としての外部放熱フィン等に圧接する場合
は、チップにおける放熱部材の端部と接触する部分にお
いて、上記圧接による応力が集中することが考えられ
る。そのため、チップＪ１やチップＪ１に形成されたデ
バイスＪ３及びゲート電極部Ｊ６が割れたり、デバイス
Ｊ３の電気特性が変動したりする可能性がある。Further, the heat radiating member is formed in an element forming region (for example,
In FIG. 4, it is also provided in the area where the emitter cell J8 is formed), and when it is pressed against an external radiating fin or the like as a cooling member, the stress due to the above-mentioned pressing is concentrated at a portion of the chip that contacts the end of the radiating member. It is possible. Therefore, there is a possibility that the chip J1, the device J3 and the gate electrode portion J6 formed on the chip J1 are broken, and the electric characteristics of the device J3 fluctuate.

【００１０】特に、大電流を流すパワーデバイスにおい
ては、上述のような、機械的応力および熱応力の集中に
より、特定セルに電流集中してデバイスが熱破壊するこ
とが懸念される。In particular, in a power device in which a large current flows, there is a concern that a current is concentrated in a specific cell and the device is thermally damaged due to the concentration of mechanical stress and thermal stress as described above.

【００１１】本発明は、上記問題点に鑑み、外部から加
えられる応力を緩和することができる半導体チップを提
供することを１つの目的とし、組み込まれた半導体チッ
プに加わる応力を緩和することができる半導体装置を提
供することを他の目的とする。SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a semiconductor chip capable of reducing externally applied stress, and to reduce the stress applied to a built-in semiconductor chip. Another object is to provide a semiconductor device.

【００１２】[0012]

【課題を解決するための手段】上記目的を達成するた
め、請求項１に記載の発明では、Ｓｉからなる基板（１
１０）における素子形成面（１ａ）に形成した電極（１
１２、１１３）が、不純物を含まない純Ａｌであり、電
極（１１２、１１３）と基板（１１０）との間にバリア
メタル（１１１）を形成していることを特徴としてい
る。To achieve the above object, according to the first aspect of the present invention, a substrate (1) made of Si is provided.
The electrode (1) formed on the element formation surface (1a) in (10)
12, 113) is pure Al containing no impurities, and is characterized in that a barrier metal (111) is formed between the electrodes (112, 113) and the substrate (110).

【００１３】半導体チップ（１１）を放熱部材と接合さ
せた場合に、不純物を含まないＡｌは弾性率が小さいた
め、半導体チップ（１１）と放熱部材との熱膨張係数の
違いにより発生する熱応力を緩和することができる。When the semiconductor chip (11) is joined to a heat dissipating member, Al that does not contain impurities has a small elastic modulus, so that the thermal stress generated due to the difference in the coefficient of thermal expansion between the semiconductor chip (11) and the heat dissipating member. Can be alleviated.

【００１４】また、電極（１１２、１１３）と基板（１
１０）との間にバリアメタル（１１１）を形成している
ため、ＳｉがＡｌ中に溶解することを防止し、アロイス
パイクの発生を防止することができる。その結果、電極
（１１２、１１３）としてＳｉが含まれていない純Ａｌ
を用いることができるため、素子形成面（１ａ）付近に
おけるＳｉのノジュール析出を防止することができ、電
極（１１２、１１３）にワイヤボンドした際にＳｉの析
出粒に機械的な応力が集中することを防止することがで
きる。従って、外部から加えられる応力を緩和すること
ができる半導体チップ（１１）を提供することができ
る。The electrodes (112, 113) and the substrate (1)
10), the barrier metal (111) is formed, so that dissolution of Si in Al can be prevented, and generation of alloy spikes can be prevented. As a result, pure Al containing no Si was used as the electrodes (112, 113).
Can be used, so that nodule precipitation of Si in the vicinity of the element formation surface (1a) can be prevented, and when wire bonding to the electrodes (112, 113), mechanical stress concentrates on the precipitated particles of Si. Can be prevented. Therefore, it is possible to provide the semiconductor chip (11) that can reduce the stress applied from the outside.

【００１５】この場合、請求項２に記載の発明のよう
に、基板（１１０）における素子形成面（１ａ）とは反
対側の面（１ｂ）に形成した電極（１１５）を、不純物
を含まない純Ａｌにすることができる。これにより、半
導体チップ（１１）の素子形成面（１ａ）とは反対側の
面（１ｂ）に放熱部材を接合する場合も、半導体チップ
（１１）と放熱部材との熱膨張係数の違いにより発生す
る熱応力を緩和することができる。In this case, the electrode (115) formed on the surface (1b) of the substrate (110) opposite to the element formation surface (1a) does not contain impurities. It can be pure Al. Accordingly, even when the heat radiating member is bonded to the surface (1b) of the semiconductor chip (11) opposite to the element forming surface (1a), the heat radiating member is generated due to a difference in thermal expansion coefficient between the semiconductor chip (11) and the heat radiating member. Thermal stress can be reduced.

【００１６】請求項３に記載の発明では、Ｓｉ基板（１
１０）からなる半導体チップ（１１）の素子形成面であ
る一面（１ａ）側に、放熱部材（２１）を接合した半導
体装置において、一面（１ａ）に形成した電極（１１
２、１１３）が不純物を含まない純Ａｌであり、電極
（１１２、１１３）と半導体チップ（１１）の基板（１
１０）との間にバリアメタル（１１１）を形成している
ことを特徴としている。According to the third aspect of the present invention, the Si substrate (1
In a semiconductor device in which a heat dissipating member (21) is joined to one surface (1a) side of a semiconductor chip (11) made of 10), which is an element forming surface, an electrode (11) formed on one surface (1a)
2 and 113) are pure Al containing no impurities, and the electrodes (112 and 113) and the substrate (1) of the semiconductor chip (11) are used.
And (10) a barrier metal (111) is formed.

【００１７】これにより、請求項１の発明と同様の理由
から、組み込まれた半導体チップ（１１）に加わる応力
を緩和することができる半導体装置を提供することがで
きる。Thus, for the same reason as the first aspect of the present invention, it is possible to provide a semiconductor device capable of reducing the stress applied to the semiconductor chip (11) incorporated therein.

【００１８】また、この場合においても、請求項２の発
明と同様に、一面（１ａ）とは反対側の他面（１ｂ）に
形成した電極（１１５）を、不純物を含まない純Ａｌに
する（請求項４の発明）と良い。Also in this case, similarly to the invention of claim 2, the electrode (115) formed on the other surface (1b) opposite to the one surface (1a) is made of pure Al containing no impurities. (Invention of claim 4) is good.

【００１９】また、請求項５に記載の発明では、請求項
３または４の発明において、放熱部材（２０）からの放
熱方向が、半導体チップ（１１）における一面（１ａ）
から、一面（１ａ）とは反対側の他面（１ｂ）へ向かう
方向となっていることを特徴としている。According to a fifth aspect of the present invention, in the third or fourth aspect, the direction of heat radiation from the heat radiating member (20) is one surface (1a) of the semiconductor chip (11).
From the first surface (1a) to the other surface (1b) opposite to the one surface (1a).

【００２０】本発明によれば、例えば、半導体チップ
（１１）の他面（１ｂ）側において冷却部材を設けた場
合、放熱を行うために冷却部材を放熱部材に圧接する際
に、半導体チップ（１１）の一面（１ａ）側に圧接によ
る応力が集中することを防止できる。従って、特に、組
み込まれた半導体チップ（１１）の、素子形成面（１
ａ）に加わる応力を緩和することができる半導体装置を
提供することができる。According to the present invention, for example, when a cooling member is provided on the other surface (1b) side of the semiconductor chip (11), the semiconductor chip ( 11) It is possible to prevent stress due to pressure contact from being concentrated on one surface (1a) side. Therefore, in particular, the element formation surface (1) of the embedded semiconductor chip (11)
It is possible to provide a semiconductor device capable of relaxing the stress applied to a).

【００２１】また、請求項６に記載の発明では、請求項
３または４の発明において、半導体チップ（１１）にお
ける一面（１ａ）とは反対側の他面（１ｂ）に放熱部材
（２４）を接合し、他面（１ｂ）側に接合した放熱部材
（２４）が、外部の冷却部材と接合する部分である放熱
面（９）を有しており、一面（１ａ）側に接合した放熱
部材（２０）と、他面（１ｂ）側に接合した放熱部材
（２４）とを接合して、一面（１ａ）側からの放熱を放
熱面（９）で行うことを特徴としている。According to a sixth aspect of the present invention, in the third or fourth aspect of the present invention, the heat radiation member (24) is provided on the other surface (1b) of the semiconductor chip (11) opposite to the one surface (1a). The heat dissipating member (24) joined to the other surface (1b) has a heat dissipating surface (9) which is a portion joined to an external cooling member, and the heat dissipating member joined to one surface (1a) side. (20) and a heat radiating member (24) bonded to the other surface (1b) side, and heat is radiated from one surface (1a) side to the heat radiating surface (9).

【００２２】これにより、各々の放熱部材（２０、２
４）からの放熱方向を、請求項５の発明と同様に、半導
体チップ（１１）における一面（１ａ）から他面（１
ｂ）へ向かう方向とすることができ、請求項５の発明と
同様の効果を発揮することができる。Thus, each heat radiation member (20, 2
The direction of heat radiation from 4) is changed from one surface (1a) to the other surface (1
The direction can be directed to b), and the same effect as the invention of claim 5 can be exhibited.

【００２３】また、この場合、請求項７に記載の発明の
ように、一面（１ａ）側に接合した放熱部材（２０）
と、他面（１ｂ）側に接合した放熱部材（２４）とを、
高熱伝導絶縁基板（４）を介して接合すると、一面（１
ａ）側に接合した放熱部材（２０）と他面（１ｂ）側に
接合した放熱部材（２４）との電気的な絶縁を行い、さ
らに熱伝導も確保することができる。In this case, the heat dissipating member (20) joined to the one surface (1a) side as in the invention of claim 7
And a heat radiating member (24) joined to the other surface (1b) side,
When joined via the high thermal conductive insulating substrate (4), one surface (1
The heat radiation member (20) joined to the a) side and the heat radiation member (24) joined to the other surface (1b) side are electrically insulated, and furthermore, heat conduction can be secured.

【００２４】なお、上記各手段の括弧内の符号は、後述
する実施形態に記載の具体的手段との対応関係を示すも
のである。The reference numerals in parentheses of the above means indicate the correspondence with specific means described in the embodiments described later.

【００２５】[0025]

【発明の実施の形態】（本実施形態）本実施形態は、半
導体チップとしてＩＧＢＴを用いた例について示す。図
１は、本実施形態の半導体装置の概略断面図である。図
１に示すように、例えば、Ｓｉ基板からなる半導体チッ
プとしてのＩＧＢＴ１１およびＦＷＤ（フリーホイール
ダイオード）１２を用いる。このＩＧＢＴ１１およびＦ
ＷＤ１２の各々の素子形成面である一面１ａ側には、各
々のチップ１１、１２の放熱を行うための第１および第
２の放熱部材２１、２２が、半田３１を介して接合され
ている。DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment) This embodiment shows an example in which an IGBT is used as a semiconductor chip. FIG. 1 is a schematic sectional view of the semiconductor device of the present embodiment. As shown in FIG. 1, for example, an IGBT 11 and a FWD (freewheel diode) 12 as semiconductor chips made of a Si substrate are used. This IGBT11 and F
First and second heat radiating members 21 and 22 for radiating heat of the respective chips 11 and 12 are joined to one surface 1a side of the WD 12 via the solder 31 on the one surface 1a side.

【００２６】また、この第１および第２の放熱部材２
１、２２における、各々のチップ１１、１２と接合され
た面とは反対側の面に対して、半田３２を介して第３の
放熱部材２３が接合されている。そして、これらの第１
〜第３の放熱部材２１〜２３により一面側の放熱部材２
０を形成している。The first and second heat radiating members 2
A third heat radiating member 23 is joined to the surfaces of the first and second chips 22 opposite to the surfaces joined to the respective chips 11 and 12 via solder 32. And these first
To the heat radiation member 2 on one side by the third heat radiation members 21 to 23
0 is formed.

【００２７】この第３の放熱部材２３は、突出部２３ｂ
を有する板状のもので、その厚み方向の断面形状が突出
部２３ｂを短辺とする略Ｌ字型になっており、Ｌ字の長
辺部において第１および第２の放熱部材２１、２２が接
合している。また、各々のチップ１１、１２の断面方向
から見ると、突出部２３ｂの先端部２３ａが、各々のチ
ップ１１、１２の他面１ｂとほぼ同じ高さになってい
る。ここで、第１〜第３の放熱部材２１〜２３は例えば
Ｃｕからなるものを用いることができる。The third heat radiating member 23 has a protrusion 23b
The cross-sectional shape in the thickness direction is substantially L-shaped with the protruding portion 23b as a short side, and the first and second heat radiating members 21 and 22 at the long side of the L-shape. Are joined. Further, when viewed from the cross-sectional direction of each of the chips 11 and 12, the tip 23a of the protruding portion 23b is substantially at the same height as the other surface 1b of each of the chips 11 and 12. Here, the first to third heat radiation members 21 to 23 can be made of, for example, Cu.

【００２８】また、各々のチップ１１、１２の他面１ｂ
側には、高熱伝導絶縁基板としてのＤＢＣ（ダイレクト
ボンディングカッパ）基板４が配置されている。このＤ
ＢＣ基板４は、ＡｌＮ（窒化アルミニウム）基板５の両
面５ａ、５ｂに銅箔５１〜５４がパターニングされてな
る。The other surface 1b of each chip 11, 12
On the side, a DBC (direct bonding copper) substrate 4 as a high thermal conductive insulating substrate is arranged. This D
The BC substrate 4 is formed by patterning copper foils 51 to 54 on both surfaces 5 a and 5 b of an AlN (aluminum nitride) substrate 5.

【００２９】そして、各々のチップ１１、１２の他面１
ｂ側が、ＤＢＣ基板４における一面５ａ側の第１の銅箔
５１に対して半田３３を介して接合されている。また、
第３の放熱部材２３における突出部２３ｂの先端部２３
ａが、ＤＢＣ基板４における一面５ａ側の第２の銅箔５
２に対して、半田３４を介して接合されている。Then, the other surface 1 of each of the chips 11 and 12
The b side is joined to the first copper foil 51 on the one surface 5a side of the DBC substrate 4 via the solder 33. Also,
Tip portion 23 of projecting portion 23b of third heat dissipation member 23
a is the second copper foil 5 on the one surface 5a side of the DBC substrate 4
2 are joined via solder 34.

【００３０】次に、ＩＧＢＴ１１の電極（配線）部分の
構成について述べる。図２は、図１における破線で囲ん
だＡ部の拡大図であり、その構成を概略的に示す図であ
る。図２に示すように、ＩＧＢＴ１１の基板１１０にお
ける一面１ａ側にはバリアメタル１１１が形成されてい
る。Next, the configuration of the electrode (wiring) portion of the IGBT 11 will be described. FIG. 2 is an enlarged view of a portion A surrounded by a broken line in FIG. 1, and is a diagram schematically showing the configuration thereof. As shown in FIG. 2, a barrier metal 111 is formed on one surface 1 a side of the substrate 110 of the IGBT 11.

【００３１】また、その上に一面側の電極としてのエミ
ッタ電極１１２およびワイヤボンド用ランド１１３が、
純Ａｌで形成されている。ここで、バリアメタル１１１
は基板１１０側から、Ｔｉ（チタン）、ＴｉＮ（チタン
ナイドライド）の順に積層されて形成されてなり、その
厚さは、例えば０．１μｍ程度である。また、この一面
側の電極１１２、１１３の厚さは、例えば５μｍ程度に
すると良い。An emitter electrode 112 and a wire bonding land 113 as an electrode on one surface are provided thereon.
It is formed of pure Al. Here, the barrier metal 111
Is formed by laminating Ti (titanium) and TiN (titanium hydride) in this order from the substrate 110 side, and the thickness thereof is, for example, about 0.1 μm. In addition, the thickness of the electrodes 112 and 113 on one surface side is preferably set to, for example, about 5 μm.

【００３２】また、エミッタ電極１１２には半田と良好
に接続するための金属膜１１４が形成されている。この
金属膜１１４は、エミッタ電極１１２側から、Ｔｉ、Ｎ
ｉ（ニッケル）およびＡｕ（金）の順に積層されて形成
されており、合わせて例えば、０．６μｍ程度の厚さと
なっている。そして、この金属膜１１４に対して、上述
のように半田３１を介して第１の放熱部材２１が接合さ
れている。ここで、半田３１および第１の放熱部材２１
の厚さは、例えば、各々０．１ｍｍ、１．５ｍｍ程度に
することができる。The emitter electrode 112 is provided with a metal film 114 for good connection with solder. The metal film 114 is formed of Ti, N from the emitter electrode 112 side.
It is formed by laminating i (nickel) and Au (gold) in this order, and has a thickness of, for example, about 0.6 μm. Then, the first heat radiating member 21 is joined to the metal film 114 via the solder 31 as described above. Here, the solder 31 and the first heat dissipation member 21
Can be, for example, about 0.1 mm and about 1.5 mm, respectively.

【００３３】一方、基板１１０の他面１ｂ側には、バリ
アメタルを形成せずに、純Ａｌからなる他面側の電極と
してのコレクタ電極１１５が形成されている。このコレ
クタ電極１１５は、例えば０．２μｍ程度の厚さにする
ことができる。また、コレクタ電極１１５に対しては、
上記エミッタ電極１１２と同様にして、金属膜１１６が
形成されており、この金属膜１１６が半田３３を介して
ＤＢＣ基板４の一面５ａ側の第１の銅箔５１と接合され
ている。On the other hand, on the other surface 1b side of the substrate 110, a collector electrode 115 as an electrode on the other surface made of pure Al is formed without forming a barrier metal. This collector electrode 115 can have a thickness of, for example, about 0.2 μm. Further, for the collector electrode 115,
A metal film 116 is formed in the same manner as the emitter electrode 112, and the metal film 116 is joined to the first copper foil 51 on the one surface 5 a side of the DBC substrate 4 via the solder 33.

【００３４】なお、ＦＷＤ１２も電極部分の構成はＩＧ
ＢＴ１１と同様にしてある。The FWD 12 also has an electrode portion of IG
It is the same as BT11.

【００３５】次に、図１および図２に示すように、エミ
ッタ電極１１２と外部端子であるリード（エミッタ端
子）６１との通電を行うために、第３の放熱部材２３と
リード６１とが接続端子６ａで電気的に接続されてい
る。また、ＤＢＣ基板４にはランド５３が形成されてお
り、このランド５３とＩＧＢＴ１１の一面１ａにおける
ワイヤボンド用ランド１１３とが、ワイヤ７によりワイ
ヤボンドされ、ＤＢＣ基板４のランド５３とゲート端子
８とがワイヤ７によりワイヤボンドされている。Next, as shown in FIGS. 1 and 2, the third heat dissipating member 23 is connected to the lead 61 in order to conduct electricity between the emitter electrode 112 and the lead (emitter terminal) 61 which is an external terminal. The terminals 6a are electrically connected. A land 53 is formed on the DBC substrate 4, and the land 53 and the wire bonding land 113 on one surface 1 a of the IGBT 11 are wire-bonded with the wire 7, and the land 53 and the gate terminal 8 of the DBC substrate 4 are connected to each other. Are wire-bonded by the wire 7.

【００３６】ここで、ワイヤ７としては、ＡｕやＡｌ
等、一般的にワイヤボンドに使われるものを用いること
ができる。このＤＢＣ基板４のランド５３は、ワイヤボ
ンド用ランド１１３とゲート端子８との中継のために設
けられたものである。Here, Au or Al is used as the wire 7.
For example, those generally used for wire bonding can be used. The land 53 of the DBC substrate 4 is provided for relaying between the land 113 for wire bonding and the gate terminal 8.

【００３７】また、ＤＢＣ基板４の裏面５ｂ側に形成さ
れた銅箔５４には、半田３５を介して第４の放熱部材
（他面側の放熱部材）２４が接合されている。つまり、
一面側の放熱部材２０と他面側の放熱部材２４とが、Ｄ
ＢＣ基板４を介して接合され、各々の放熱部材２０、２
４の電気的な絶縁、および熱伝導が確保されている。A fourth heat radiating member (heat radiating member on the other surface) 24 is joined to the copper foil 54 formed on the back surface 5b side of the DBC substrate 4 via a solder 35. That is,
The heat dissipating member 20 on one side and the heat dissipating member 24 on the other side are D
The heat radiating members 20, 2
4, electrical insulation and heat conduction are ensured.

【００３８】そして、上述の各々の部材が樹脂１００に
より封止されている。この際、他面側の放熱部材２４に
おける、ＤＢＣ基板４と接合した面とは反対側の面が露
出して放熱面９となっている。ここで、樹脂１００とし
ては、例えばエポキシ系のモールド樹脂を用いることが
できる。Each of the above members is sealed with the resin 100. At this time, the surface of the other side of the heat radiating member 24 opposite to the surface bonded to the DBC substrate 4 is exposed to serve as the heat radiating surface 9. Here, as the resin 100, for example, an epoxy-based mold resin can be used.

【００３９】次に、本実施形態の半導体装置における各
部の電気的な接続のより詳細な構成について、図３を参
照して述べる。図３は、図１の白抜き矢印方向から見た
場合の半導体装置を模式的に示す上面図である。なお、
図１は図３におけるＢ−Ｂ断面に相当する。図３に示す
ように、本実施形態の半導体装置はＩＧＢＴ１１とＦＷ
Ｄ１２が２組、組み込まれている。Next, a more detailed configuration of the electrical connection of each part in the semiconductor device of this embodiment will be described with reference to FIG. FIG. 3 is a top view schematically showing the semiconductor device when viewed from the direction of the outlined arrow in FIG. In addition,
FIG. 1 corresponds to a BB section in FIG. As shown in FIG. 3, the semiconductor device according to the present embodiment includes the IGBT 11 and the FW.
Two sets of D12 are incorporated.

【００４０】一面側の放熱部材２０（２１〜２３）は、
図中、一点鎖線で示され、上述のように、接続端子６ａ
を介してエミッタ端子６１と電気的に接続されている。
また、ＤＢＣ基板４の第１の銅箔５１は、２組のＩＧＢ
Ｔ１１とＦＷＤ１２における他面１ｂ側の電極の全てと
接合され、ＤＢＣ基板４の第２の銅箔５２と接触しない
ようにして、突出している。また、この突出した部分５
１ａとリードであるコレクタ端子６２とが、接続端子６
ｂを介して電気的に接続されている。The heat dissipating members 20 (21 to 23) on one side are
In the figure, the connection terminal 6a is indicated by an alternate long and short dash line, as described above.
And is electrically connected to the emitter terminal 61 via the.
Further, the first copper foil 51 of the DBC substrate 4 has two sets of IGBs.
It is joined to all of the electrodes on the other surface 1b side of T11 and FWD12, and protrudes so as not to contact the second copper foil 52 of the DBC substrate 4. In addition, this protruding portion 5
1a and the collector terminal 62 as a lead are connected to the connection terminal 6
b and are electrically connected.

【００４１】そして、この様な構成の半導体装置は、放
熱面９を外部の冷却部材（外部放熱器）としての放熱フ
ィン（図示せず）にネジ止め等により圧接して固定す
る。これにより、各々のチップ１１、１２の一面１ａ側
からは、一面側の放熱部材２０、ＤＢＣ基板４、および
他面側の放熱部材２４を介して、放熱面９から放熱され
る。つまり、各々のチップ１１、１２の一面１ａ側から
の放熱方向が、各々のチップ１１、１２における一面１
ａから他面１ｂへ向かう方向（図１における上から下へ
向かう方向）となっている。In the semiconductor device having such a configuration, the heat radiating surface 9 is fixed to a heat radiating fin (not shown) as an external cooling member (external radiator) by pressing with a screw or the like. As a result, heat is radiated from the heat radiating surface 9 from the one surface 1a side of each of the chips 11, 12 via the heat radiating member 20, the DBC substrate 4, and the heat radiating member 24 on the other surface. In other words, the direction of heat radiation from one surface 1a side of each chip 11, 12 is
The direction is from a to the other surface 1b (direction from top to bottom in FIG. 1).

【００４２】一方、各々のチップ１１、１２の他面１ｂ
側からは、ＤＢＣ基板４、および他面側の放熱部材２４
を介して、放熱面９から放熱される。従って、チップが
組み込まれた半導体装置において、各々のチップ１１、
１２における一面１ａおよび他面１ｂ、そして放熱面９
の位置関係がこの順になっており、放熱面９を外部の冷
却部材と接合するなどして、各々のチップ１１、１２の
両面１ａ、１ｂからの放熱を、主として放熱面９におい
て行っている。On the other hand, the other surface 1b of each of the chips 11, 12
From the side, the DBC substrate 4 and the heat dissipating member 24 on the other side.
The heat is dissipated from the heat dissipating surface 9 via. Therefore, in the semiconductor device in which the chips are incorporated, each chip 11,
The first surface 1a and the other surface 1b, and the heat radiation surface 9 in 12
Are arranged in this order, and heat is radiated mainly from the heat radiating surface 9 from both surfaces 1a and 1b of the chips 11 and 12 by bonding the heat radiating surface 9 to an external cooling member.

【００４３】次に、本実施形態の半導体装置の製造方法
について述べる。まず、上述のようなバリアメタル１１
１、エミッタ電極１１２、コレクタ電極１１５、および
金属膜１１４、１１６等を有するＩＧＢＴ１１、および
ＦＷＤ１２を用意する。これらの電極１１２、１１５や
バリアメタル１１１、金属膜１１４、１１６等は、例え
ばスパッタ等により形成することができる。そして、各
々のチップ１１、１２の一面１ａに対して、第１および
第２の放熱部材２１、２２を半田付けする。Next, a method of manufacturing the semiconductor device of the present embodiment will be described. First, the barrier metal 11 as described above
1. An IGBT 11 and an FWD 12 having an emitter electrode 112, a collector electrode 115, and metal films 114 and 116 are prepared. The electrodes 112 and 115, the barrier metal 111, the metal films 114 and 116, and the like can be formed by, for example, sputtering or the like. Then, the first and second heat radiating members 21 and 22 are soldered to one surface 1a of each of the chips 11 and 12.

【００４４】次に、一面５ａおよび他面５ｂに銅箔５１
〜５４がパターニングされたＤＢＣ基板４を用意し、所
定の位置にＩＧＢＴ１１およびＦＷＤ１２を半田付けす
る。その後、第３の放熱部材２３を、第１および第２の
放熱部材２１、２２、およびＤＢＣ基板４に対して半田
付けする。この第３の放熱部材２３の半田付けにおいて
は、第１および第２の放熱部材２１、２２との接合部分
よりも、ＤＢＣ基板４との接合部分において半田を少し
厚くしておき、半田付けの際の高さのバラツキを吸収す
るようにしておく。Next, a copper foil 51 is provided on one surface 5a and the other surface 5b.
The DBC substrate 4 on which the .about.54 is patterned is prepared, and the IGBT 11 and the FWD 12 are soldered to predetermined positions. After that, the third heat radiation member 23 is soldered to the first and second heat radiation members 21 and 22 and the DBC substrate 4. In the soldering of the third heat radiating member 23, the solder is slightly thicker at the joint with the DBC substrate 4 than at the joint with the first and second heat radiating members 21 and 22. Make sure that the height variation is absorbed.

【００４５】この各々半田付けは、リフロー等により行
うと良く、また半田付けの順に、用いる半田の融点を徐
々に下げるようにすると、初めに接合された半田に影響
を及ぼすこと無く、好適に半田付けすることができる。The soldering is preferably performed by reflow or the like. If the melting point of the solder to be used is gradually lowered in the order of the soldering, it is preferable that the soldering is effected without affecting the solder joined first. Can be attached.

【００４６】そして、エミッタ端子６１およびコレクタ
端子６２と第３の放熱部材２３との接続、およびＩＧＢ
Ｔ１１とゲート端子８とのワイヤボンドを行う。続い
て、ＤＢＣ基板４に第４の放熱部材２４を半田付けし、
最後に、樹脂封止して完成する。The connection between the emitter terminal 61 and the collector terminal 62 and the third heat dissipating member 23 and the IGB
Wire bonding between T11 and the gate terminal 8 is performed. Subsequently, the fourth heat radiation member 24 is soldered to the DBC substrate 4,
Finally, resin sealing is completed.

【００４７】ところで、本実施形態によれば、純Ａｌは
弾性率が小さいため、各々のチップ１１、１２と各放熱
部材２１〜２４との熱膨張係数の違いにより発生する熱
応力を緩和することができる。具体的には、純Ａｌの弾
性率は７２ＧＰａであり、１％のＳｉを含有するＡｌの
弾性率は約７５ＧＰａである。そして、Ｓｉを含有する
Ａｌを用い、製造過程において、上記従来技術で用いた
図４に示すコンタクト部Ｊ５やゲート電極部Ｊ６の表面
にＳｉが偏析した場合、Ｓｉの弾性率は１３０ＧＰａで
あるため、局所的には熱応力を緩和する能力が非常に小
さくなる。According to the present embodiment, since pure Al has a small elastic modulus, the thermal stress generated due to the difference in the thermal expansion coefficient between each of the chips 11 and 12 and each of the heat radiating members 21 to 24 is reduced. Can be. Specifically, the elastic modulus of pure Al is 72 GPa, and the elastic modulus of Al containing 1% Si is about 75 GPa. Then, when Si containing Al is segregated on the surface of the contact portion J5 or the gate electrode portion J6 shown in FIG. 4 used in the above-described conventional technique in the manufacturing process, the elastic modulus of Si is 130 GPa. However, the ability to relieve thermal stress locally becomes very small.

【００４８】特に、ＩＧＢＴ１１のエミッタ電極１１２
を純Ａｌとすることにより、例えばエミッタセルに応力
が集中し、Ｖｔ等の電気特性が変動することを抑制する
ことができる。従って、電気的な信頼性の高いチップお
よび半導体装置を提供することができる。また、各々の
チップ１１、１２の他面１ｂ側の電極を純Ａｌとするこ
とにより、熱応力に起因する各々のチップ１１、１２の
反りを低減することができる。In particular, the emitter electrode 112 of the IGBT 11
Is made of pure Al, for example, it is possible to suppress the concentration of stress in the emitter cell and the fluctuation of electrical characteristics such as Vt. Therefore, a highly reliable chip and semiconductor device can be provided. In addition, since the electrodes on the other surface 1b side of the chips 11 and 12 are made of pure Al, warpage of the chips 11 and 12 due to thermal stress can be reduced.

【００４９】また、電極１１２、１１３、１１５にＳｉ
が含まれていないため、Ｓｉノジュール析出を防止する
ことができる。これは、ワイヤボンド用ランド１１３に
おいて特に効果を発揮する。上記課題で述べたように、
ワイヤボンド用ランド１１３付近のＳｉ基板１１０にお
ける絶縁膜（図示せず）等にＳｉの析出粒が形成され、
この析出粒にワイヤボンドの際の機械的な振動（応力）
が集中することにより、絶縁膜およびＳｉ基板１１０に
おけるデバイスにクラックが生じるという問題を解消す
ることができる。The electrodes 112, 113, and 115 have Si
Since Si is not contained, Si nodule precipitation can be prevented. This is particularly effective in the land 113 for wire bonding. As mentioned in the above task,
Si precipitates are formed on an insulating film (not shown) of the Si substrate 110 near the wire bonding lands 113, and the like.
Mechanical vibration (stress) during wire bonding to these precipitates
Concentration can solve the problem that cracks occur in the device on the insulating film and the Si substrate 110.

【００５０】この様に、電極１１２、１１３、１１５を
純Ａｌとすることにより、外部から加えられる応力を緩
和する、つまり純Ａｌがクッションの様な働きをする半
導体チップ、および、組み込まれた半導体チップに加わ
る応力を緩和することができる半導体装置を提供するこ
とができる。As described above, by making the electrodes 112, 113, and 115 pure Al, the stress applied from the outside is relieved, that is, the semiconductor chip in which pure Al acts like a cushion, and the embedded semiconductor. A semiconductor device capable of reducing stress applied to a chip can be provided.

【００５１】ただし、純Ａｌを基板１１０であるＳｉに
直接接触させると、アロイスパイクが生じるため、電極
１１２、１１３と基板１１０との間にバリアメタル１１
１を形成し、このアロイスパイクの発生を防止してい
る。なお、ＩＧＢＴ１１の他面１ｂ側にはバリアメタル
を形成していないが、他面１ｂ側においてアロイスパイ
クが発生しても、一面１ａ側に形成されたデバイスまで
到達しないと思われるため、バリアメタルを形成しなく
ても良い。However, if pure Al is brought into direct contact with Si as the substrate 110, an alloy spike occurs, so that the barrier metal 11 is located between the electrodes 112 and 113 and the substrate 110.
1 to prevent the generation of the alloy spike. Although no barrier metal is formed on the other surface 1b side of the IGBT 11, even if an alloy spike occurs on the other surface 1b side, it is considered that the device does not reach the device formed on the one surface 1a side. Need not be formed.

【００５２】また、例えば、チップを一対の放熱部材で
挟んでなり、その各々の放熱部材に放熱面を有するよう
な半導体装置では、外部の冷却部材により半導体装置を
挟んで圧接して、放熱面と冷却部材とを接触させる。し
かし、この様な構成では、挟んだ際の圧接応力がチップ
に集中してしまう。Further, for example, in a semiconductor device in which a chip is sandwiched between a pair of heat radiating members, and each of the heat radiating members has a heat radiating surface, the semiconductor device is pressed and sandwiched by an external cooling member to form a heat radiating surface. And the cooling member. However, in such a configuration, the pressure contact stress when sandwiched is concentrated on the chip.

【００５３】それに対し、本実施形態では、主として半
導体装置の外部に対して放熱を行う放熱面９が、各々の
チップ１１、１２における他面１ｂ側に形成されてい
る。この様な構成では、放熱を行うために、冷却部材で
半導体装置を挟む構成にする必要が無いため、放熱面９
を外部の冷却部材に強固に接続しても、各々のチップ１
１、１２に大きな応力は加わらない。On the other hand, in the present embodiment, the heat radiating surface 9 for mainly radiating heat to the outside of the semiconductor device is formed on the other surface 1b side of each of the chips 11 and 12. In such a configuration, it is not necessary to adopt a configuration in which the semiconductor device is sandwiched between the cooling members in order to perform heat radiation.
Each chip 1 can be connected even if it is firmly connected to an external cooling member.
No large stress is applied to 1,12.

【００５４】さらに、各々のチップ１１、１２に対して
は、一面１ａ側にも他面１ｂ側にも放熱部材２１、２
２、２４が接合されているため、各々のチップ１１、１
２の両面１ａ、１ｂからの放熱が行われる。Further, for each of the chips 11 and 12, the heat dissipating members 21 and 2 are provided on one surface 1a side and on the other surface 1b side.
2 and 24 are joined, so that each chip 11, 1
The heat is radiated from the two surfaces 1a and 1b.

【００５５】従って、各々のチップ１１、１２の両面１
ａ、１ｂからの放熱効果を確保した状態で、各々のチッ
プ１１、１２やチップに形成されたデバイスが割れるこ
とを防止することができる構成となっている。特に、各
々のチップ１１、１２の他面１ｂ側に放熱面９が形成さ
れているため、各々のチップの一面１ａ側に応力が集中
することを防止でき、一面１ａ側に形成されたデバイス
の電気特性の変動を抑えることができる。Therefore, both sides 1 of each chip 11, 12
In this state, the chips 11 and 12 and the devices formed on the chips can be prevented from cracking while the heat radiation effect from a and 1b is secured. In particular, since the heat radiating surface 9 is formed on the other surface 1b side of each of the chips 11, 12, it is possible to prevent stress from being concentrated on one surface 1a of each chip, and to reduce the device formed on the one surface 1a side. Variations in electrical characteristics can be suppressed.

【００５６】また、半導体装置の内部で用いた絶縁基板
であるＤＢＣ基板４により、この放熱面９は各々のチッ
プ１１、１２との電気的な絶縁が確保されている。この
ため、外部の冷却部材との接合において、電気的な絶縁
を考慮する必要が無い。また、１枚の絶縁基板４によっ
て、各々のチップの一面１ａ側および他面１ｂ側の両方
との絶縁を確保することができる。The heat dissipation surface 9 is electrically insulated from the chips 11 and 12 by the DBC substrate 4 which is an insulating substrate used inside the semiconductor device. For this reason, it is not necessary to consider electrical insulation in joining with the external cooling member. In addition, with one insulating substrate 4, it is possible to secure insulation between both the one surface 1a side and the other surface 1b side of each chip.

【００５７】なお、本実施形態では、主として放熱を行
う放熱面９が、各々のチップ１１、１２における他面１
ｂ側に形成されているが、例えば、第３の放熱部材２３
を樹脂１００の外に露出させる等して、他の部分で放熱
を補うようにしても良い。ただし、この場合、第３の放
熱部材２３における露出した部分を、外部の冷却部材に
強固に接触させる等して、チップ１１、１２の素子形成
面１ａに圧接応力が加わらないようにする。また、チッ
プ１１、１２の素子形成面１ａに圧接応力が加わらなけ
れば半導体装置を挟んで固定してもいい。In the present embodiment, the heat radiation surface 9 for mainly dissipating heat is the other surface 1 of each of the chips 11 and 12.
The third heat radiating member 23 is formed on the b side.
May be exposed to the outside of the resin 100, or the like, to compensate for heat radiation in other portions. However, in this case, the exposed portion of the third heat radiating member 23 is firmly brought into contact with an external cooling member, for example, so that no pressure contact stress is applied to the element forming surfaces 1a of the chips 11, 12. Further, the semiconductor device may be fixed with the semiconductor device sandwiched between the device forming surfaces 1a of the chips 11 and 12 as long as no pressure contact stress is applied.

【００５８】また、各々のチップ１１、１２のデバイス
の保護に着目する場合は、各々のチップの他面１ｂ側の
電極１１５は、純Ａｌでなくても良い。また、第１〜第
３の放熱部材２１〜２３は別体で形成して半田付けする
例について示したが、一体で形成しても良い。When attention is paid to the protection of the devices of the chips 11 and 12, the electrodes 115 on the other surface 1b of each chip may not be made of pure Al. Although the first to third heat dissipating members 21 to 23 are formed separately and soldered, they may be formed integrally.

【００５９】また、ＦＷＤ１２の電極は、熱応力等の問
題が無ければ、特に純Ａｌにしなくても良い。また、一
面側の放熱部材２０と他面側の放熱部材２４との絶縁が
必要無ければ、ＡｌＮからなるＤＢＣ基板４を用いなく
ても良い。また、ＤＢＣ基板４のランド５３は、ＩＧＢ
Ｔ１１のワイヤボンド用ランド１１３とゲート端子８と
を直接ワイヤボンドできれば設けなくても良い。The electrode of the FWD 12 need not be made of pure Al unless there is a problem such as thermal stress. Further, if it is not necessary to insulate the heat radiating member 20 on one surface and the heat radiating member 24 on the other surface, the DBC substrate 4 made of AlN may not be used. The land 53 of the DBC substrate 4 is
It is not necessary to provide the land 113 for wire bonding of T11 and the gate terminal 8 if wire bonding can be performed directly.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本実施形態における半導体装置の概略断面図で
ある。FIG. 1 is a schematic sectional view of a semiconductor device according to an embodiment.

【図２】本実施形態におけるＩＧＢＴの構成を示す断面
図である。FIG. 2 is a cross-sectional view illustrating a configuration of the IGBT according to the embodiment.

【図３】本実施形態における半導体装置の上面図であ
る。FIG. 3 is a top view of the semiconductor device according to the embodiment.

【図４】従来のＩＧＢＴを部分的に示す概略断面図であ
る。FIG. 4 is a schematic sectional view partially showing a conventional IGBT.

【符号の説明】[Explanation of symbols]

１ａ…素子形成面、４…高熱伝導絶縁基板、９…放熱
面、１１、１２…半導体チップ、２０〜２４…放熱部
材、１１０…基板、１１１…バリアメタル、１１２、１
１３…一面側の電極、１１５…他面側の電極。1a: Element formation surface, 4: High thermal conductive insulating substrate, 9: Heat dissipation surface, 11, 12: Semiconductor chip, 20 to 24: Heat dissipation member, 110: Substrate, 111: Barrier metal, 112, 1
13: electrode on one side, 115: electrode on the other side.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 野村 和仁 愛知県刈谷市昭和町１丁目１番地 株式会 社デンソー内 (72)発明者 宮嶋 健 愛知県刈谷市昭和町１丁目１番地 株式会 社デンソー内 Ｆターム(参考） 5F036 AA01 BB01 BC06 5F044 EE04 EE06  ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kazuhito Nomura 1-1-1, Showa-cho, Kariya, Aichi Prefecture Inside Denso Corporation (72) Inventor Ken Miyajima 1-1-1, Showa-cho, Kariya City, Aichi Prefecture Denso Corporation F-term (reference) 5F036 AA01 BB01 BC06 5F044 EE04 EE06

Claims (7)

【特許請求の範囲】[Claims] 【請求項１】 Ｓｉからなる基板（１１０）よりなり、 前記基板（１１０）における素子形成面（１ａ）に形成
された電極（１１２、１１３）が、不純物を含まない純
Ａｌであり、 前記電極（１１２、１１３）と前記基板（１１０）との
間に、ＳｉがＡｌ中に溶解することを防止するバリアメ
タル（１１１）が形成されていることを特徴とする半導
体チップ。An electrode (112, 113) formed on an element formation surface (1a) of the substrate (110) is made of pure Al containing no impurities, and the electrode (112) is made of Si. A semiconductor chip, wherein a barrier metal (111) for preventing Si from being dissolved in Al is formed between (112, 113) and the substrate (110). 【請求項２】 前記基板（１１０）における前記素子形
成面（１ａ）とは反対側の面（１ｂ）に形成された電極
（１１５）が、不純物を含まない純Ａｌであることを特
徴とする請求項１に記載の半導体チップ。2. An electrode (115) formed on a surface (1b) of the substrate (110) opposite to the element formation surface (1a) is made of pure Al containing no impurities. The semiconductor chip according to claim 1. 【請求項３】 Ｓｉ基板（１１０）からなる半導体チッ
プ（１１）の素子形成面である一面（１ａ）側に、前記
半導体チップ（１１）の放熱を行うための放熱部材（２
０）が接合されてなる半導体装置において、 前記一面（１ａ）に形成された電極（１１２、１１３）
が不純物を含まない純Ａｌであり、 前記電極（１１２、１１３）と前記半導体チップ（１
１）の基板（１１０）との間に、ＳｉがＡｌ中に溶解す
ることを防止するバリアメタル（１１１）が形成されて
いることを特徴とする半導体装置。3. A heat radiating member (2) for radiating heat of the semiconductor chip (11) is provided on one surface (1a) side of the semiconductor chip (11) formed of a Si substrate (110), which is an element forming surface.
0), the electrodes (112, 113) formed on the one surface (1a).
Is pure Al containing no impurities, and the electrodes (112, 113) and the semiconductor chip (1) are
A semiconductor device, wherein a barrier metal (111) for preventing Si from being dissolved in Al is formed between the substrate and the substrate (1). 【請求項４】 前記半導体チップ（１１）における前記
一面（１ａ）とは反対側の他面（１ｂ）に形成された電
極（１１５）が、不純物を含まない純Ａｌであることを
特徴とする請求項３に記載の半導体装置。4. An electrode (115) formed on the other surface (1b) of the semiconductor chip (11) opposite to the one surface (1a) is made of pure Al containing no impurities. The semiconductor device according to claim 3. 【請求項５】 前記放熱部材（２０）からの放熱方向
が、前記半導体チップ（１１）における前記一面（１
ａ）から、前記一面（１ａ）とは反対側の他面（１ｂ）
へ向かう方向となっていることを特徴とする請求項３ま
たは４に記載の半導体装置。5. The heat radiation direction from the heat radiation member (20) is directed to the one surface (1) of the semiconductor chip (11).
From a), the other surface (1b) opposite to the one surface (1a)
The semiconductor device according to claim 3, wherein the semiconductor device is directed toward the semiconductor device. 【請求項６】 前記半導体チップ（１１）における前記
一面（１ａ）とは反対側の他面（１ｂ）側に放熱部材
（２４）が接合され、 前記他面（１ｂ）側に接合された放熱部材（２４）が、
外部の冷却部材と接合される部分である放熱面（９）を
有しており、 前記一面（１ａ）側に接合された放熱部材（２０）と、
前記他面（１ｂ）側に接合された放熱部材（２４）とが
接合されて、前記一面（１ａ）側からの放熱が前記放熱
面（９）で行われることを特徴とする請求項３または４
に記載の半導体装置。6. A heat dissipation member (24) is joined to the other surface (1b) of the semiconductor chip (11) opposite to the one surface (1a), and a heat dissipation member is joined to the other surface (1b). The member (24)
A heat dissipation member (20) joined to the one surface (1a) side, having a heat dissipation surface (9) which is a portion joined to an external cooling member;
The heat dissipation member (24) joined to the other surface (1b) side is joined, and heat dissipation from the one surface (1a) side is performed on the heat dissipation surface (9). 4
3. The semiconductor device according to claim 1. 【請求項７】 前記一面（１ａ）側に接合された放熱部
材（２０）と、前記他面（１ｂ）側に接合された放熱部
材（２４）とが、高熱伝導絶縁基板（４）を介して接合
されていることを特徴とする請求項６に記載の半導体装
置。7. A heat dissipating member (20) joined to the one surface (1a) side and a heat dissipating member (24) joined to the other surface (1b) side via a high heat conductive insulating substrate (4). The semiconductor device according to claim 6, wherein the semiconductor device is joined by bonding.
JP2000097911A 1999-11-24 2000-03-30 Semiconductor chip and semiconductor device Expired - Fee Related JP3630070B2 (en)

Priority Applications (18)

Application Number Priority Date Filing Date Title
JP2000097911A JP3630070B2 (en) 2000-03-30 2000-03-30 Semiconductor chip and semiconductor device
US09/717,227 US6703707B1 (en) 1999-11-24 2000-11-22 Semiconductor device having radiation structure
FR0015130A FR2801423B1 (en) 1999-11-24 2000-11-23 SEMICONDUCTOR DEVICE WITH RADIANT STRUCTURE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING ELECTRONIC INSTRUMENT
DE10058446A DE10058446B8 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating components
DE10066445A DE10066445B4 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating structure
DE10066442A DE10066442B4 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating structure
DE10066443A DE10066443B8 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating components
DE10066441A DE10066441B4 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating components
DE10066446A DE10066446B4 (en) 1999-11-24 2000-11-24 Method for producing an electronic component with two emission components
US10/321,365 US6693350B2 (en) 1999-11-24 2002-12-18 Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure
US10/699,828 US6992383B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,837 US6960825B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,746 US6998707B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,784 US20040089941A1 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,785 US6891265B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,954 US6967404B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,838 US6798062B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,744 US20040089940A1 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure

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