JP7495225B2 - Semiconductor Device - Google Patents

Semiconductor Device Download PDF

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JP7495225B2
JP7495225B2 JP2019226762A JP2019226762A JP7495225B2 JP 7495225 B2 JP7495225 B2 JP 7495225B2 JP 2019226762 A JP2019226762 A JP 2019226762A JP 2019226762 A JP2019226762 A JP 2019226762A JP 7495225 B2 JP7495225 B2 JP 7495225B2
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semiconductor element
bonding layer
aluminum sheet
semiconductor device
conductor member
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JP2021097113A (en
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林太郎 淺井
宏文 伊藤
正則 臼井
敏一 佐藤
智幸 庄司
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Denso Corp
Toyota Central R&D Labs Inc
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Toyota Central R&D Labs Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本明細書が開示する技術は、半導体装置に関する。 The technology disclosed in this specification relates to semiconductor devices.

特許文献１に、半導体装置が開示されている。この半導体装置は、半導体素子に、接合層を介して接合された基材を備える。接合層は鉛（Ｐｂ）を含有しないはんだ（いわゆる鉛フリーはんだ）によって形成される。 Patent Document 1 discloses a semiconductor device. This semiconductor device includes a substrate that is bonded to a semiconductor element via a bonding layer. The bonding layer is formed from solder that does not contain lead (Pb) (so-called lead-free solder).

特開２０１５－１３５９５６号公報JP 2015-135956 A

一般に、半導体装置では、半導体素子や基材といった構成要素の線膨張係数が互いに相違することから、高温環境下において、その線膨張係数の相違に起因する熱応力が発生する。この熱応力は、接合層やその近傍において高まりやすく、そこを起点として発生した亀裂によって、半導体素子が損傷を受けるおそれがある。この点において、接合層が鉛を含有するはんだで形成されていれば、自身の塑性変形によって、接合層は熱応力の緩和に有効に機能する。それに対して、鉛（Ｐｂ）を含有しないはんだは、Ｐｂを含有するものと比較して、塑性変形し難いという特徴を有する。従って、上記した半導体装置のように、接合層が鉛を含有しないはんだで形成されていると、接合層における熱応力の緩和効果が低いために、接合層やその近傍で亀裂が発生しやすく、半導体素子が損傷を受けるおそれが高くなる。本明細書では、このような問題を解決又は少なくとも軽減し得る技術を提供する。 In general, in a semiconductor device, the linear expansion coefficients of components such as a semiconductor element and a substrate are different from each other, and therefore, in a high-temperature environment, thermal stress occurs due to the difference in the linear expansion coefficient. This thermal stress is likely to increase in the bonding layer or its vicinity, and cracks that originate from there may damage the semiconductor element. In this regard, if the bonding layer is formed of solder containing lead, the bonding layer effectively functions to relieve thermal stress by its own plastic deformation. In contrast, solder that does not contain lead (Pb) has the characteristic of being less susceptible to plastic deformation compared to solder that contains Pb. Therefore, as in the semiconductor device described above, if the bonding layer is formed of solder that does not contain lead, the effect of relaxing thermal stress in the bonding layer is low, so cracks are likely to occur in the bonding layer or its vicinity, and the semiconductor element is more likely to be damaged. This specification provides a technology that can solve or at least reduce such problems.

本明細書が開示する半導体装置は、半導体素子と、半導体素子の電極に、アルミニウムシートを介して接合された導体部材とを備え、電極とアルミシートとの間、及びアルミニウムシートと導体部材との間には、液相拡散接合層又は銀粒子焼結接合層による接合層が形成されており、導体部材の接合層に接する面の周縁には、少なくとも部分的に切欠き部が形成されている。 The semiconductor device disclosed in this specification comprises a semiconductor element and a conductive member bonded to an electrode of the semiconductor element via an aluminum sheet, and a bonding layer formed between the electrode and the aluminum sheet and between the aluminum sheet and the conductive member is a liquid phase diffusion bonding layer or a silver particle sintered bonding layer, and a notch is formed at least partially on the periphery of the surface of the conductive member that contacts the bonding layer.

アルミニウムシートは延性を有するため、熱応力に対して応力緩和部として作用する。さらには、アルミニウムシートは、液相拡散接合層又は銀粒子焼結接合層といった、当該アルミニウムシートよりも機械的強度が高い接合層を介して、半導体素子の電極や導体部材に接合されている。このような構成によると、半導体装置の内部で過大な熱応力が発生したときに、アルミニウムシートで優先的に亀裂が発生しやすく、半導体素子が損傷を受けることが抑制される。但し、アルミニウムシートの亀裂が、半導体素子側の界面で発生してしまうと、その亀裂が半導体素子にも進展するおそれが生じる。そのことから、アルミニウムシートに対して半導体素子とは反対側に位置する導体部材には、接合層に接する面の周縁に、切欠き部が形成されている。このような構成によると、アルミニウムシートに生じる熱応力を、当該切欠き部の近傍で意図的に集中させることができ、アルミニウムシートの亀裂を、半導体素子とは反対側の界面で発生させることができる。このように、本明細書が開示する半導体装置の構造によると、熱応力による半導体素子の損傷を有意に抑制することができる。 Since the aluminum sheet has ductility, it acts as a stress relief part against thermal stress. Furthermore, the aluminum sheet is bonded to the electrodes of the semiconductor element and the conductor member through a bonding layer having a higher mechanical strength than the aluminum sheet, such as a liquid phase diffusion bonding layer or a silver particle sintered bonding layer. With this configuration, when excessive thermal stress occurs inside the semiconductor device, cracks tend to occur preferentially in the aluminum sheet, and damage to the semiconductor element is suppressed. However, if a crack in the aluminum sheet occurs at the interface on the semiconductor element side, there is a risk that the crack will also progress to the semiconductor element. For this reason, a notch is formed on the periphery of the surface that contacts the bonding layer in the conductor member located on the opposite side of the aluminum sheet from the semiconductor element. With this configuration, the thermal stress generated in the aluminum sheet can be intentionally concentrated in the vicinity of the notch, and the crack in the aluminum sheet can be generated at the interface on the opposite side of the semiconductor element. In this way, the structure of the semiconductor device disclosed in this specification can significantly suppress damage to the semiconductor element due to thermal stress.

実施例の半導体装置１０の内部構造を模式的に示す断面図。1 is a cross-sectional view showing a schematic internal structure of a semiconductor device 10 according to an embodiment of the present invention. 図１中のＩＩ部の拡大図。FIG. 2 is an enlarged view of part II in FIG. 図２中のＩＩＩ部の拡大図。FIG. 3 is an enlarged view of part III in FIG. 2 . 実施例の半導体装置１０に発生した亀裂５０を模式的に示す断面図。FIG. 2 is a cross-sectional view showing a schematic diagram of a crack 50 generated in the semiconductor device 10 of the embodiment. 比較例の半導体装置に発生した亀裂５０を模式的に示す断面図。FIG. 11 is a cross-sectional view showing a schematic diagram of a crack 50 generated in a semiconductor device of a comparative example. 切欠き部２５の寸法を示す図。FIG. 4 is a diagram showing the dimensions of a cutout portion 25.

図面を参照して、実施例の半導体装置１０について説明する。半導体装置１０は電力制御装置に採用され、例えばインバータやコンバータといった電力変換回路の一部を構成することができる。ここでいう電力制御装置は、特に限定されないが、例えば電気自動車や、ハイブリッド自動車や、燃料電池車等に搭載され、電源とモータとの間で電力変換を行うものであってよい。 The semiconductor device 10 of the embodiment will be described with reference to the drawings. The semiconductor device 10 is employed in a power control device, and can form part of a power conversion circuit such as an inverter or converter. The power control device referred to here is not particularly limited, but may be mounted on an electric vehicle, a hybrid vehicle, a fuel cell vehicle, etc., and may perform power conversion between a power source and a motor.

図１に示すように、半導体装置１０は、半導体素子２０及び封止体１２を備える。半導体素子２０は、封止体１２の内部に封止されている。封止体１２は、例えばエポキシ樹脂といった絶縁性を有する材料を用いて構成されている。半導体素子２０は、パワー半導体素子であって、一対の主電極２０ａと２０ｂと、一又は複数の信号パッド２０ｃを有する。一対の主電極２０ａ、２０ｂは、電力回路用の電極であって、第１主電極と第２主電極とを含む。第１主電極２０ａ及び信号パッド２０ｃは、半導体素子２０の一方の表面に位置しており、第２主電極２０ｂは、半導体素子２０の他方の表面に位置している。 As shown in FIG. 1, the semiconductor device 10 includes a semiconductor element 20 and an encapsulant 12. The semiconductor element 20 is encapsulated inside the encapsulant 12. The encapsulant 12 is made of an insulating material such as epoxy resin. The semiconductor element 20 is a power semiconductor element and has a pair of main electrodes 20a and 20b and one or more signal pads 20c. The pair of main electrodes 20a, 20b are electrodes for a power circuit and include a first main electrode and a second main electrode. The first main electrode 20a and the signal pad 20c are located on one surface of the semiconductor element 20, and the second main electrode 20b is located on the other surface of the semiconductor element 20.

半導体素子２０は、例えばＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）又は、ＩＧＢＴ（Insulated Gate Bipolar Transistor）といった、一対の主電極２０ａ、２０ｂの間を電気的に導通及び遮断するスイッチング素子である。但し、半導体素子２０の数や種類については、特に限定されない。半導体素子２０を構成する半導体材料には、例えばケイ素（Ｓｉ）、炭化ケイ素（ＳｉＣ）又は窒化ガリウム（ＧａＮ）又は他の種類の半導体材料を採用することができる。 The semiconductor element 20 is a switching element that electrically connects and disconnects a pair of main electrodes 20a, 20b, such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). However, the number and type of the semiconductor elements 20 are not particularly limited. The semiconductor material constituting the semiconductor element 20 may be, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or other types of semiconductor materials.

一対の主電極２０ａ、２０ｂ及び信号パッド２０ｃは、アルミニウム系又は他の金属といった導体材料を用いて構成されている。信号パッド２０ｃは、信号回路用の電極であって、前述したように、第１主電極２０ａと同じく、半導体素子２０の前記一方の表面に位置している。 The pair of main electrodes 20a, 20b and the signal pad 20c are made of a conductive material such as aluminum or other metals. The signal pad 20c is an electrode for a signal circuit, and as described above, like the first main electrode 20a, is located on the one surface of the semiconductor element 20.

半導体装置１０は、封止体１２の内外に亘って延びる信号端子４０をさらに備える。信号端子４０は、封止体１２の内部において、ボンディングワイヤ４２を介して信号パッド２０ｃに接続されている。 The semiconductor device 10 further includes a signal terminal 40 that extends from the inside to the outside of the encapsulation body 12. The signal terminal 40 is connected to the signal pad 20c inside the encapsulation body 12 via a bonding wire 42.

図１から図２に示すように、半導体装置１０は、上側アルミニウムシート２６と下側アルミニウムシート２８と、導体部材２４と、放熱板２２、３０をさらに備える。上側アルミニウムシート２６と下側アルミニウムシート２８は、半導体素子２０を介して互いに対向している。半導体素子２０の第１主電極２０ａは、上側アルミニウムシート２６に対向しており、第２接合層３３を介して上側アルミニウムシート２６の一方の表面（図中の下面）に接合されている。半導体素子２０の第２主電極２０ｂは、下側アルミニウムシート２８に対向しており、第３接合層３４を介して下側アルミニウムシート２８の一方の表面（図中の上面）に接合されている。下側アルミニウムシート２８の他方の表面（図中の下面）は、第４接合層３５を介して下側放熱板３０に接合されている。 1 and 2, the semiconductor device 10 further includes an upper aluminum sheet 26, a lower aluminum sheet 28, a conductor member 24, and heat sinks 22 and 30. The upper aluminum sheet 26 and the lower aluminum sheet 28 face each other via the semiconductor element 20. The first main electrode 20a of the semiconductor element 20 faces the upper aluminum sheet 26 and is bonded to one surface (the lower surface in the figure) of the upper aluminum sheet 26 via a second bonding layer 33. The second main electrode 20b of the semiconductor element 20 faces the lower aluminum sheet 28 and is bonded to one surface (the upper surface in the figure) of the lower aluminum sheet 28 via a third bonding layer 34. The other surface (the lower surface in the figure) of the lower aluminum sheet 28 is bonded to the lower heat sink 30 via a fourth bonding layer 35.

導体部材２４は、概して板形状あるいはブロック形状の部材であり、上面２４ａと、上面２４ａとは反対側に位置する下面２４ｂとを有する。導体部材２４は、封止体１２内に位置しており、導体部材２４の下面２４ｂは、第１接合層３２を介して上側アルミニウムシート２６の他方の表面（図中の上面）に接合されている。導体部材２４は、例えば銅又はその他の金属といった導電性を有する材料を用いて構成されている。即ち、導体部材２４は、半導体素子２０に電気的に接続されている。下面２４ｂの周縁には、少なくとも部分的に切欠き部２５が形成されている。この切欠き部２５の作用効果については、後段において詳細に説明する。一方、導体部材２４の上面２４ａは、上側放熱板２２に第５接合層３６を介して接合されている。 The conductor member 24 is generally a plate-shaped or block-shaped member, and has an upper surface 24a and a lower surface 24b located opposite the upper surface 24a. The conductor member 24 is located within the sealing body 12, and the lower surface 24b of the conductor member 24 is bonded to the other surface (the upper surface in the figure) of the upper aluminum sheet 26 via a first bonding layer 32. The conductor member 24 is made of a conductive material such as copper or other metal. That is, the conductor member 24 is electrically connected to the semiconductor element 20. A notch 25 is formed at least partially on the periphery of the lower surface 24b. The effect of the notch 25 will be described in detail later. Meanwhile, the upper surface 24a of the conductor member 24 is bonded to the upper heat sink 22 via a fifth bonding layer 36.

上側放熱板２２及び下側放熱板３０は、例えば銅、アルミニウム、その他の金属といった熱伝導性に優れた材料で構成されている。放熱板２２、３０は、概して直方体形状又は板形状の部材であり、上面と上面とは反対側に位置する下面を有する。上側放熱板２２の上面は、封止体１２の上面において外部に露出されている。また、上側放熱板２２の下面は、前述したように第５接合層３６を介して導体部材２４に接合されている。即ち上側放熱板２２は、半導体素子２０と電気的及び熱的に接続されている。これにより、上側放熱板２２は、半導体素子２０の熱を外部に放出する放熱板としても機能する。 The upper heat sink 22 and the lower heat sink 30 are made of a material with excellent thermal conductivity, such as copper, aluminum, or other metals. The heat sinks 22, 30 are generally rectangular or plate-shaped members, and have an upper surface and a lower surface located opposite the upper surface. The upper surface of the upper heat sink 22 is exposed to the outside at the upper surface of the sealing body 12. In addition, the lower surface of the upper heat sink 22 is bonded to the conductor member 24 via the fifth bonding layer 36 as described above. In other words, the upper heat sink 22 is electrically and thermally connected to the semiconductor element 20. As a result, the upper heat sink 22 also functions as a heat sink that dissipates heat from the semiconductor element 20 to the outside.

下側放熱板３０の下面は、封止体１２の下面において外部に露出されている。また、下側放熱板３０の上面は、前述したように第４接合層３５を介して下側アルミニウムシート２８に接合されている。即ち、下側放熱板３０は、半導体素子２０と電気的及び熱的に接続されている。これにより、下側放熱板３０も上側放熱板２２と同様に、半導体素子２０の熱を外部に放出する放熱板として機能する。 The lower surface of the lower heat sink 30 is exposed to the outside at the lower surface of the sealing body 12. In addition, the upper surface of the lower heat sink 30 is bonded to the lower aluminum sheet 28 via the fourth bonding layer 35 as described above. In other words, the lower heat sink 30 is electrically and thermally connected to the semiconductor element 20. As a result, the lower heat sink 30, like the upper heat sink 22, also functions as a heat sink that dissipates heat from the semiconductor element 20 to the outside.

図３に示すように、第１接合層３２は層構造を有し、第１金属層３２ａと、中間層３２ｂと、第２金属層３２ｃを含む。第１接合層３２では、導体部材２４から離れる方向に向かって、第１金属層３２ａ、中間層３２ｂ、第２金属層３２ｃが順に並んでいる。第１接合層３２は、液相拡散接合法又は銀粒子焼結接合法によって形成されている。これらの接合手法（液相拡散接合法又は銀粒子焼結接合法）に使用される元素は、特に限定されない。例えば、ＮｉとＳｎを使用し、液相拡散接合層によって接合された場合、第１金属層３２ａはＮｉ層であり、中間層３２ｂはＮｉ－Ｓｎ合金層であり、第２金属層３２ｃはＮｉ層である。 3, the first bonding layer 32 has a layered structure and includes a first metal layer 32a, an intermediate layer 32b, and a second metal layer 32c. In the first bonding layer 32, the first metal layer 32a, the intermediate layer 32b, and the second metal layer 32c are arranged in this order in the direction away from the conductor member 24. The first bonding layer 32 is formed by a liquid phase diffusion bonding method or a silver particle sintering bonding method. The elements used in these bonding methods (liquid phase diffusion bonding method or silver particle sintering bonding method) are not particularly limited. For example, when Ni and Sn are used and bonded by a liquid phase diffusion bonding layer, the first metal layer 32a is a Ni layer, the intermediate layer 32b is a Ni-Sn alloy layer, and the second metal layer 32c is a Ni layer.

図示省略しているが、本開示の半導体装置１０では、上側アルミニウムシート２６と第１主電極２０ａとの間の接合、及び下側アルミニウムシート２８と第２主電極２０ｂとの間の接合、及び下側アルミニウムシート２８と下側放熱板３０との間の接合、及び上側放熱板２２と上側アルミニウムシート２６との間の接合においても、上述した第１接合層３２と同様の層構造とすることができる。即ち、信号端子４０を除く半導体装置１０の構成要素をそれぞれを接合する接合層３２、３３、３４、３５、３６は、それぞれ液相拡散接合法又は銀粒子焼結接合法によって形成される層構造を有してよく、使用される元素は用途に応じて適宜採用されてよい。アルミニウムシート２６、２８は、延性を有する他の材料によって構成されてもよい。 Although not shown, in the semiconductor device 10 of the present disclosure, the bonding between the upper aluminum sheet 26 and the first main electrode 20a, the bonding between the lower aluminum sheet 28 and the second main electrode 20b, the bonding between the lower aluminum sheet 28 and the lower heat sink 30, and the bonding between the upper heat sink 22 and the upper aluminum sheet 26 can have a layer structure similar to that of the first bonding layer 32 described above. That is, the bonding layers 32, 33, 34, 35, and 36 that bond the components of the semiconductor device 10, except for the signal terminal 40, may each have a layer structure formed by a liquid phase diffusion bonding method or a silver particle sintering bonding method, and the elements used may be appropriately adopted depending on the application. The aluminum sheets 26 and 28 may be made of other materials having ductility.

一般に、半導体装置１０では、半導体素子２０や導体部材２４といった構成要素の線膨張係数が互いに相違することから、高温環境下において、その線膨張係数の相違に起因する熱応力が発生する。この熱応力は、一般に、接合層やその近傍において高まりやすく、そこを起点として発生した亀裂によって、半導体素子２０が損傷を受けるおそれがある。この点に関して、アルミニウムシート２６、２８は延性を有するため、熱応力に対して応力緩和部として作用する。さらには、アルミニウムシート２６、２８は、当該アルミニウムシート２６、２８よりも機械的強度が高い接合層３２、３３、３４、３５、３６を介して、半導体装置１０の構成要素である主電極２０ａ、２０ｂ又は導体部材２４に接合されている。このような構成によると、半導体装置１０の内部で過大な熱応力が発生したときに、アルミニウムシート２６、２８で優先的に亀裂（いわゆるクラック）が生じる。 In general, in the semiconductor device 10, the linear expansion coefficients of the components such as the semiconductor element 20 and the conductor member 24 are different from each other, and therefore, in a high-temperature environment, thermal stress occurs due to the difference in the linear expansion coefficients. This thermal stress generally tends to increase in the bonding layer or its vicinity, and the semiconductor element 20 may be damaged by cracks that originate there. In this regard, the aluminum sheets 26, 28 have ductility and therefore act as stress relief parts against thermal stress. Furthermore, the aluminum sheets 26, 28 are bonded to the main electrodes 20a, 20b or the conductor member 24, which are components of the semiconductor device 10, via bonding layers 32, 33, 34, 35, 36 that have higher mechanical strength than the aluminum sheets 26, 28. With this configuration, when excessive thermal stress occurs inside the semiconductor device 10, cracks (so-called cracks) occur preferentially in the aluminum sheets 26, 28.

この点に関して実施例では、図４に示すように、上側アルミニウムシート２６に対して半導体素子２０と反対側に位置する導体部材２４には、第１接合層３２に接する面の周縁の少なくとも一部に、切欠き部２５が形成されている。このような構成によると、上側アルミニウムシート２６に生じる熱応力を、当該切欠き部２５の近傍に意図的に集中させることができ、上側アルミニウムシート２６に発生する亀裂５０を、半導体素子２０とは反対側の界面、つまり第１接合層３２と接する界面で発生させることができる。 In this regard, in the embodiment, as shown in FIG. 4, the conductor member 24 located on the opposite side of the upper aluminum sheet 26 from the semiconductor element 20 has a notch 25 formed in at least a part of the periphery of the surface that contacts the first bonding layer 32. With this configuration, the thermal stress generated in the upper aluminum sheet 26 can be intentionally concentrated in the vicinity of the notch 25, and the cracks 50 generated in the upper aluminum sheet 26 can be generated at the interface on the opposite side of the semiconductor element 20, that is, the interface that contacts the first bonding layer 32.

例えば、図５に示すように、仮に導体部材２４に切欠き部がない構造であると、半導体装置１０の内部で過大な熱応力が発生した場合、上側アルミニウムシート２６において亀裂５０が発生し、亀裂５０が半導体素子２０と接する界面で発生するおそれがある。そうすると、発生した亀裂５０が半導体素子２０にも進展し、半導体素子２０が損傷を受けるおそれがある。 For example, as shown in FIG. 5, if the conductor member 24 does not have a notch, when excessive thermal stress occurs inside the semiconductor device 10, a crack 50 may occur in the upper aluminum sheet 26, and the crack 50 may occur at the interface with the semiconductor element 20. If this occurs, the crack 50 may propagate into the semiconductor element 20, causing damage to the semiconductor element 20.

図６を参照して、導体部材２４の寸法に対する切欠き部２５の寸法例を示す。導体部材２４の長さをＬｍｍとし、高さをＴｍｍとする。切欠き部２５の長さａは、０．００５ｍｍ以上かつＬの４分の１以下である。また切欠き部２５の高さｂは、具体的には０．００５ｍｍ以上かつＴの２分の１以下である。 Referring to FIG. 6, an example of the dimensions of the cutout portion 25 relative to the dimensions of the conductor member 24 is shown. The length of the conductor member 24 is L mm, and its height is T mm. The length a of the cutout portion 25 is 0.005 mm or more and 1/4 of L or less. Specifically, the height b of the cutout portion 25 is 0.005 mm or more and 1/2 of T or less.

以上いくつかの具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。本明細書又は図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものである。 Although several specific examples have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples given above. The technical elements described in this specification or drawings exhibit technical usefulness either alone or in various combinations.

１０：半導体装置
１２：封止体
２０：半導体素子
２０ａ、２０ｂ：主電極
２０ｃ：信号電極
２２、３０：放射板
２４：構造部材
２５：切欠き部
２６、２８：アルミニウムシート
３２、３３、３４、３５、３６：接合層
３２ａ、３２ｃ：金属層
３２ｂ：中間層
４０：信号端子
４２：ボンディングワイヤ 10: Semiconductor device 12: Sealing body 20: Semiconductor element 20a, 20b: Main electrode 20c: Signal electrode 22, 30: Radiation plate 24: Structural member 25: Notch portion 26, 28: Aluminum sheet 32, 33, 34, 35, 36: Bonding layer 32a, 32c: Metal layer 32b: Intermediate layer 40: Signal terminal 42: Bonding wire

Claims (1)

半導体素子と、
前記半導体素子の電極に、アルミニウムシートを介して接合された導体部材と、
を備え、
前記電極と前記アルミニウムシートとの間、及び、前記アルミニウムシートと前記導体部材との間には、液相拡散接合層又は銀粒子焼結接合層による接合層が形成されており、
前記導体部材の前記接合層に接する面の周縁には、少なくとも部分的に切欠き部が形成されており、
前記導体部材の前記接合層に接する面と、前記切欠き部における前記導体部材の表面とが成す角度は、９０°よりも大きい、
半導体装置。 A semiconductor element;
a conductive member joined to an electrode of the semiconductor element via an aluminum sheet;
Equipped with
A bonding layer is formed between the electrode and the aluminum sheet, and between the aluminum sheet and the conductor member, using a liquid phase diffusion bonding layer or a silver particle sintered bonding layer;
a notch is formed at least partially on a periphery of a surface of the conductor member that contacts the bonding layer ,
an angle formed between a surface of the conductor member in contact with the bonding layer and a surface of the conductor member at the notch portion is greater than 90° ;
Semiconductor device.
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JP2006032888A (en) 2004-06-17 2006-02-02 Renesas Technology Corp Semiconductor device and manufacturing method for semiconductor device
JP2018025571A (en) 2014-12-17 2018-02-15 株式会社リコー Image forming apparatus
JP2019079891A (en) 2017-10-23 2019-05-23 トヨタ自動車株式会社 Semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006032888A (en) 2004-06-17 2006-02-02 Renesas Technology Corp Semiconductor device and manufacturing method for semiconductor device
JP2018025571A (en) 2014-12-17 2018-02-15 株式会社リコー Image forming apparatus
JP2019079891A (en) 2017-10-23 2019-05-23 トヨタ自動車株式会社 Semiconductor device

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