JP6303776B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP6303776B2
JP6303776B2 JP2014093248A JP2014093248A JP6303776B2 JP 6303776 B2 JP6303776 B2 JP 6303776B2 JP 2014093248 A JP2014093248 A JP 2014093248A JP 2014093248 A JP2014093248 A JP 2014093248A JP 6303776 B2 JP6303776 B2 JP 6303776B2
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semiconductor element
semiconductor device
heat sink
semiconductor
sealing resin
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JP2015211178A (en
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寺井　護
護 寺井
哲 根岸
哲 根岸
山本　圭
圭 山本
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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Description

この発明は、半導体素子を樹脂で封止してなる半導体装置に関するものである。   The present invention relates to a semiconductor device formed by sealing a semiconductor element with a resin.

半導体素子を用いた半導体装置は、半導体素子をエポキシ樹脂などの熱硬化性樹脂で封止したモールド型と、ゲル状樹脂で封止したゲル封止型が使用されている。特にモールド封止型の半導体装置は小型で信頼性に優れており、取り扱いが容易であることから、空調機器の制御などに広く用いられている。また、近年は、モーター制御を行う自動車の動力制御などにも使用されている。   As a semiconductor device using a semiconductor element, a mold type in which the semiconductor element is sealed with a thermosetting resin such as an epoxy resin and a gel sealing type in which the semiconductor element is sealed with a gel resin are used. In particular, a mold-sealed semiconductor device is small and excellent in reliability, and is easy to handle. Therefore, it is widely used for controlling air-conditioning equipment. In recent years, it is also used for power control of automobiles that perform motor control.

従来の半導体装置では、小型化・大容量化を目的として放熱性を向上させるために熱伝導性に優れた金属からなるヒートシンクを設け、半導体素子で発熱した熱を拡散する手法を取り入れている。例えば、銅製のヒートシンク上に半導体素子がはんだ等により接合されている樹脂封止型半導体装置がある（例えば特許文献１）。   In the conventional semiconductor device, in order to improve heat dissipation for the purpose of downsizing and increasing the capacity, a heat sink made of a metal having excellent thermal conductivity is provided, and a method of diffusing the heat generated by the semiconductor element is adopted. For example, there is a resin-sealed semiconductor device in which a semiconductor element is bonded to a copper heat sink by solder or the like (for example, Patent Document 1).

また、はんだの熱疲労現象による信頼性の低下を抑制する目的で、半導体基板接着部が半導体基板の面積と同等またはわずかに広い面積を持つ突起部をもつ凸型の断面形状をもつ銅製のリードフレームを用い、２種類の樹脂を用いてモールドされている。樹脂封止半導体装置がある（例えば特許文献２）。   In addition, in order to suppress a decrease in reliability due to the thermal fatigue phenomenon of solder, the lead made of copper having a convex cross-sectional shape with a protrusion having a semiconductor substrate bonding portion having an area equal to or slightly larger than the area of the semiconductor substrate It is molded using two types of resins using a frame. There is a resin-encapsulated semiconductor device (for example, Patent Document 2).

特開平１−２７０３３６号公報（第２０９頁、第１図）JP-A-1-270336 (page 209, FIG. 1) 特許昭６１−５８９７９号（第８７頁、第２図）Patent 61-58979 (page 87, Fig. 2)

一方、従来のＳｉ（Ｓｉｌｉｃｏｎ）製半導体素子に比べて、低損失、高耐圧、高温動作が可能な化合物半導体素子として、例えばＳｉＣ（Ｓｉｌｉｃｏｎ Ｃａｒｂｉｄｅ）製半導体素子の半導体装置への適用が進められている。ＳｉＣ製半導体素子は、これらの利点が注目され適用開発が進められているが、Ｓｉ製半導体素子と比較して弾性率が高いことや、これまで以上のより厳しい温度環境下で動作することとなり、これまで以上に半導体素子にかかる応力が増大している。特許文献１および特許文献２に記載の樹脂封止した半導体装置においては、特にヒートサイクル時に半導体素子と封止樹脂界面にかかる応力は、これまで以上に高くなる。その結果、半導体素子と封止樹脂との界面で剥離が生じたり、半導体素子端部付近の封止樹脂にクラックが生じるため、半導体装置の絶縁信頼性低下を招くという問題点があった。   On the other hand, compared to conventional Si (Silicon) semiconductor elements, for example, SiC (Silicon Carbide) semiconductor elements are applied to semiconductor devices as compound semiconductor elements capable of low loss, high breakdown voltage, and high temperature operation. Yes. SiC semiconductor elements are being developed and applied with attention to these advantages, but they have a higher elastic modulus than Si semiconductor elements and operate in a more severe temperature environment than ever. The stress applied to the semiconductor element is increasing more than ever. In the resin-encapsulated semiconductor device described in Patent Document 1 and Patent Document 2, the stress applied to the interface between the semiconductor element and the encapsulating resin particularly during a heat cycle is higher than ever. As a result, peeling occurs at the interface between the semiconductor element and the sealing resin, or cracks occur in the sealing resin in the vicinity of the end of the semiconductor element, leading to a decrease in insulation reliability of the semiconductor device.

本発明は、上記のような課題を解決するためになされたもので、ヒートサイクルに起因する半導体素子と封止樹脂の界面で生じる剥離や、半導体素子端部付近の封止樹脂に生じるクラックを抑制又はクラックの進展を抑制することで、絶縁信頼性の確保が可能な半導体装置を得るものである。   The present invention has been made in order to solve the above-described problems, and is capable of preventing peeling that occurs at the interface between the semiconductor element and the sealing resin due to heat cycles and cracks that occur in the sealing resin near the edge of the semiconductor element. A semiconductor device capable of ensuring insulation reliability is obtained by suppressing the suppression or the progress of cracks.

我々は、上記課題を克服するため鋭意検討を行った結果、半導体素子を搭載する凸状の搭載面を有する金属部を用い、搭載面の面積が半導体素子の面積以下の構造を有する場合に優れた信頼性が得られることが明らかとなり、さらに詳細に検討を行うことで発明に到ったものである。   As a result of intensive studies to overcome the above-mentioned problems, we have a metal part with a convex mounting surface on which a semiconductor element is mounted, which is excellent when the area of the mounting surface is less than the area of the semiconductor element. It has become clear that high reliability can be obtained, and the present invention has been made through further detailed studies.

この発明に係る半導体装置は、半導体素子と、前記半導体素子の電極が形成された面の周縁内に収まり前記半導体素子を搭載する搭載面を有する凸状の搭載部を備えた金属部と、前記半導体素子と前記金属部とを封止する封止樹脂とを備え、前記搭載部の厚さ（Ａ）は、０．２５ｍｍ＜Ａ≦２．５ｍｍである。
A semiconductor device according to the present invention includes a semiconductor element, and a metal part including a convex mounting part having a mounting surface that fits within a periphery of a surface on which the electrode of the semiconductor element is formed and mounts the semiconductor element, A sealing resin for sealing the semiconductor element and the metal part is provided , and the thickness (A) of the mounting part is 0.25 mm <A ≦ 2.5 mm .

この発明は、金属部に半導体素子の面積よりも小さな面積の半導体素子の搭載面を設けたことで、ヒートサイクル時の半導体素子と封止樹脂界面とに発生する応力を低減したので、半導体素子端部に発生する封止樹脂の剥離やクラックの発生を抑制することが可能となり、絶縁信頼性の高い半導体装置が得られる。   Since the present invention reduces the stress generated in the semiconductor element and the sealing resin interface during the heat cycle by providing a mounting surface of the semiconductor element having an area smaller than the area of the semiconductor element in the metal portion. It is possible to suppress peeling of the sealing resin and cracks generated at the end, and a semiconductor device with high insulation reliability can be obtained.

この発明の実施の形態１の半導体装置の断面構造模式図である。It is a cross-sectional structure schematic diagram of the semiconductor device of Embodiment 1 of this invention. この発明の実施の形態１の半導体装置の半導体素子を搭載した金属部であるヒートシンクの上面構図模式図である。It is a top surface composition schematic diagram of the heat sink which is a metal part which mounts the semiconductor element of the semiconductor device of Embodiment 1 of this invention. この発明の実施の形態１の半導体装置に用いるヒートシンクの半導体素子の搭載部の断面構造模式図である。It is a cross-sectional structure schematic diagram of the mounting part of the semiconductor element of the heat sink used for the semiconductor device of Embodiment 1 of this invention. この発明の実施の形態１の半導体装置に用いるヒートシンクの半導体素子の搭載部の断面構造模式図である。It is a cross-sectional structure schematic diagram of the mounting part of the semiconductor element of the heat sink used for the semiconductor device of Embodiment 1 of this invention. この発明の実施の形態１の半導体装置に用いるヒートシンクの半導体素子の搭載部の断面構造模式図である。It is a cross-sectional structure schematic diagram of the mounting part of the semiconductor element of the heat sink used for the semiconductor device of Embodiment 1 of this invention. この発明の実施の形態１の他の半導体装置の断面構造模式図である。It is a cross-sectional structure schematic diagram of the other semiconductor device of Embodiment 1 of this invention. この発明の実施の形態１の他の半導体装置の断面構造模式図である。It is a cross-sectional structure schematic diagram of the other semiconductor device of Embodiment 1 of this invention. この発明の実施の形態１の他の半導体装置の上面構造模式図および断面構造模式図である。It is the upper surface structure schematic diagram and sectional structure schematic diagram of the other semiconductor device of Embodiment 1 of this invention. この発明の実施の形態２の半導体装置の断面構造模式図である。It is a cross-sectional structure schematic diagram of the semiconductor device of Embodiment 2 of this invention. この発明の実施の形態２の他の半導体装置の断面構造模式図である。It is a cross-sectional structure schematic diagram of the other semiconductor device of Embodiment 2 of this invention. この発明の実施の形態３の半導体装置の断面構造模式図である。It is a cross-sectional structure schematic diagram of the semiconductor device of Embodiment 3 of this invention.

実施の形態１．
図１は、この発明の実施の形態１の半導体装置の断面構造模式図である。図１において、半導体装置１００は、半導体素子１、リードフレーム２、金属部であるヒートシンク３、ボンディングワイヤ４、絶縁層５、金属板６、封止樹脂７、接合材８を備える。 Embodiment 1 FIG.
1 is a schematic cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention. In FIG. 1, a semiconductor device 100 includes a semiconductor element 1, a lead frame 2, a heat sink 3 as a metal part, a bonding wire 4, an insulating layer 5, a metal plate 6, a sealing resin 7, and a bonding material 8.

半導体素子１は、ＭＯＳＦＥＴ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）やＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）などの電力制御用半導体素子や還流ダイオードなどの電力用半導体素子が用いられる。また、半導体素子１は、その構造に応じて、表面側に表面電極、裏面側に裏面電極が形成されている。そして、回路構成に応じて、半導体素子１は、表面電極または裏面電極が接合材８によってヒートシンク３に接合される。さらに、回路構成に応じて、ＡｌやＣｕ、Ａｕ等のボンディングワイヤ４を用いて、半導体素子１、リードフレーム２、ヒートシンク３がそれぞれ接続されている。また、図１では、一つのモールドされた半導体装置に半導体素子が２個しか搭載されていないが、これに限定するものではなく、使用される用途に応じて必要な個数の半導体素子を搭載することができる。 The semiconductor element 1 is a power control semiconductor element such as a MOSFET (Metal Oxide Field Effect Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor), or a power semiconductor element such as a free-wheeling diode. Further, the semiconductor element 1 has a surface electrode on the front side and a back electrode on the back side according to the structure. Depending on the circuit configuration, the front surface electrode or the back surface electrode of the semiconductor element 1 is bonded to the heat sink 3 by the bonding material 8 . Furthermore, the semiconductor element 1, the lead frame 2, and the heat sink 3 are connected to each other using bonding wires 4 such as Al, Cu, and Au according to the circuit configuration. Further, in FIG. 1, only two semiconductor elements are mounted on a single molded semiconductor device. However, the present invention is not limited to this, and a necessary number of semiconductor elements are mounted according to the intended use. be able to.

接合材８は、はんだや銀などの熱溶融部材を用いて半導体素子１とヒートシンク３とを搭載するのが一般的であるが、電気的に接続されていれば接合方法は特に限定されず、例えば半導体素子１とヒートシンク３を超音波によって直接接合していてもよい。ヒートシンク３は、半導体素子１の発熱に対して熱抵抗を低減することを目的としている。 Junction member 8 is for mounting the semiconductor element 1 and the heat sink 3 using a hot-melt member such as solder or silver is generally, bonding methods as long as they are electrically connected is not particularly limited For example, the semiconductor element 1 and the heat sink 3 may be directly joined by ultrasonic waves. The heat sink 3 is intended to reduce the thermal resistance against the heat generated by the semiconductor element 1.

ヒートシンク３は、半導体素子１を搭載する搭載面を有する凸状の搭載部を備える。ヒートシンク３の半導体素子１が搭載されている面の反対側の面には、金属板６である銅箔付き絶縁層５が設けられている。絶縁層５は絶縁シートを用いることができる。絶縁シートは、エポキシ樹脂に熱伝導性に優れるシリカ、アルミナ、窒化ホウ素、窒化アルミニウム等の無機粉末が少なくとも１種以上充填されており、これらの無機粉末は単独でも複数の組合せでもよい。また、銅箔の絶縁シートが貼り付けられた面の反対側の面では銅箔面は露出している。この銅箔面は、半導体素子１の発熱による放熱性を確保するだけでなく、絶縁層５が外部からの接触により傷がつかないための保護層としての役目も果たしている。この目的を満たすものであれば、銅箔である必要もなく、アルミなどの金属箔でも構わない。また、金属板６を金属箔としたが、金属箔に限定されるものではなく、金属箔と同様な効果を得られれば特に限定されることはなく、例えば、アルミなどの金属板も適用可能である。   The heat sink 3 includes a convex mounting portion having a mounting surface on which the semiconductor element 1 is mounted. An insulating layer 5 with a copper foil as a metal plate 6 is provided on the surface of the heat sink 3 opposite to the surface on which the semiconductor element 1 is mounted. The insulating layer 5 can use an insulating sheet. In the insulating sheet, an epoxy resin is filled with at least one inorganic powder such as silica, alumina, boron nitride, and aluminum nitride that has excellent thermal conductivity. These inorganic powders may be used alone or in combination. The copper foil surface is exposed on the surface opposite to the surface on which the copper foil insulating sheet is attached. This copper foil surface not only secures heat dissipation due to heat generation of the semiconductor element 1, but also serves as a protective layer for preventing the insulating layer 5 from being damaged by external contact. As long as this purpose is satisfied, it is not necessary to use a copper foil, and a metal foil such as aluminum may be used. Moreover, although the metal plate 6 is a metal foil, the metal plate 6 is not limited to the metal foil, and is not particularly limited as long as the same effect as the metal foil can be obtained. For example, a metal plate such as aluminum is also applicable. It is.

封止樹脂７は、リードフレーム２やヒートシンク３に搭載された半導体素子１やボンディングワイヤ４であるＡｌワイヤ、絶縁シートなどの全体を封止するようにトランスファーモールドされている。封止樹脂７は、エポキシ樹脂に熱膨張係数の小さい溶融シリカ等の無機粉末や熱伝導性が優れるアルミナなどが充填されている。エポキシ樹脂は、半導体装置１００の放熱性や動作時の発熱量、動作温度にもよるが、一般的なオルトクレゾールノボラック型やジシクロペンタジエン型などを用いる事ができる。しかし、半導体素子１が保護できれば特に限定されることはなく、例えば、ＳｉＣなどを用いた半導体素子１の動作温度の高温化によりナフタレン型や多官能型を用いた耐熱性の高い樹脂を用いることもできる。   The sealing resin 7 is transfer molded so as to seal the semiconductor element 1 mounted on the lead frame 2 and the heat sink 3, the Al wire as the bonding wire 4, the insulating sheet, and the like. The sealing resin 7 is an epoxy resin filled with inorganic powder such as fused silica having a small coefficient of thermal expansion, alumina with excellent thermal conductivity, or the like. As the epoxy resin, a general ortho-cresol novolak type, a dicyclopentadiene type, or the like can be used depending on the heat dissipation of the semiconductor device 100, the amount of heat generated during operation, and the operating temperature. However, there is no particular limitation as long as the semiconductor element 1 can be protected. For example, a highly heat-resistant resin using a naphthalene type or a polyfunctional type is used by increasing the operating temperature of the semiconductor element 1 using SiC or the like. You can also.

また、温度サイクルなどの信頼性試験で発生する熱応力を想定した場合、封止樹脂７の熱膨張係数は、環境温度を想定した範囲内において、熱拡散板であるヒートシンク３の熱膨張係数と半導体素子１の熱膨張係数の間に収めておくことが望ましい。熱膨張係数の違いにより、温度差が生じた場合には、半導体素子１と封止樹脂７との接触面でのひずみの違いが生じ、応力が発生する。したがって、熱拡散板であるヒートシンク３に搭載されている半導体素子１との応力を想定した場合には、両者の熱膨張係数の間の封止樹脂７を適用することが望ましい。ＳｉＣ素子に用いる封止樹脂の場合、一般的に線膨脹係数は１０〜１３×１０−６（１／Ｋ）程度の間で調整される。 In addition, when thermal stress generated in a reliability test such as a temperature cycle is assumed, the thermal expansion coefficient of the sealing resin 7 is equal to the thermal expansion coefficient of the heat sink 3 that is a thermal diffusion plate within the range where the environmental temperature is assumed. It is desirable to keep it between the thermal expansion coefficients of the semiconductor element 1. When a temperature difference occurs due to a difference in thermal expansion coefficient, a difference in strain occurs at the contact surface between the semiconductor element 1 and the sealing resin 7 and a stress is generated. Therefore, when the stress with the semiconductor element 1 mounted on the heat sink 3 which is a thermal diffusion plate is assumed, it is desirable to apply the sealing resin 7 between the thermal expansion coefficients of both. In the case of a sealing resin used for an SiC element, generally, the linear expansion coefficient is adjusted between about 10 to 13 × 10 −6 (1 / K).

図２は、この発明の実施の形態１の半導体装置の半導体素子を搭載した金属部であるヒートシンクの上面構図模式図である。図２（ａ）は、ヒートシンク３の半導体素子１の搭載面３ａが四角形の場合、図２（ｂ）は、ヒートシンク３の半導体素子１の搭載面３ｂが角部に丸みを持たせた場合の上面構造模式図である。便宜上、半導体素子１は点線にて大きさを図示している。図２に示すように、ヒートシンク３の半導体素子１の搭載面の面積は半導体素子１の面積よりも小さくなっている。ヒートシンク３に接する側の半導体素子１の面積をα、ヒートシンク３の半導体素子１の搭載面の面積をβとすると、これらの面積の関係は１＞β／α≧１／２を満たす必要がある。ここで、半導体素子１の面積は、半導体素子１の電極が形成されている面の面積である。また、半導体素子１の搭載面の面積は、半導体素子１を搭載部に搭載したときの搭載面を上面から見た時の面積である。また、ヒートシンク３の半導体素子１の搭載面は、半導体素子１の電極が形成されている面の周縁内に収まる大きさである。   FIG. 2 is a schematic top view of a heat sink that is a metal part on which the semiconductor element of the semiconductor device according to the first embodiment of the present invention is mounted. 2A shows a case where the mounting surface 3a of the semiconductor element 1 of the heat sink 3 is square, and FIG. 2B shows a case where the mounting surface 3b of the semiconductor element 1 of the heat sink 3 has rounded corners. It is an upper surface structure schematic diagram. For convenience, the size of the semiconductor element 1 is illustrated by a dotted line. As shown in FIG. 2, the area of the mounting surface of the semiconductor element 1 of the heat sink 3 is smaller than the area of the semiconductor element 1. Assuming that the area of the semiconductor element 1 on the side in contact with the heat sink 3 is α and the area of the mounting surface of the semiconductor element 1 of the heat sink 3 is β, the relationship between these areas needs to satisfy 1> β / α ≧ 1/2. . Here, the area of the semiconductor element 1 is the area of the surface on which the electrode of the semiconductor element 1 is formed. The area of the mounting surface of the semiconductor element 1 is an area when the mounting surface when the semiconductor element 1 is mounted on the mounting portion is viewed from the upper surface. The mounting surface of the heat sink 3 on which the semiconductor element 1 is mounted has a size that fits within the periphery of the surface on which the electrode of the semiconductor element 1 is formed.

ヒートシンク３の半導体素子１の搭載面３ａの面積βが半導体素子１の面積αよりも大きくなると、半導体素子１と封止樹脂７の界面で剥離が生じ、信頼性の低下を招く。また、ヒートシンク３の半導体素子１の搭載面３ａの面積βが半導体素子の面積αの１／２よりも小さくなると、ヒートシンクが本来の放熱効果を十分に発揮できず、半導体素子１の熱暴走や半導体素子１の破壊を招く。ヒートシンク３の半導体素子１の搭載面の形状は半導体素子１の相似縮小形（３ａ）、半導体素子１の同形状から角部（端部）のみ丸みを持たせたもの（３ｂ）を例示しているが、本発明の目的が達成されるものであれば特に限定されず、これらの組み合わせ、又は曲線や多角形で形成されていても良い。   When the area β of the mounting surface 3 a of the semiconductor element 1 of the heat sink 3 is larger than the area α of the semiconductor element 1, peeling occurs at the interface between the semiconductor element 1 and the sealing resin 7, leading to a decrease in reliability. Further, when the area β of the mounting surface 3a of the semiconductor element 1 of the heat sink 3 is smaller than ½ of the area α of the semiconductor element, the heat sink cannot sufficiently exhibit the original heat dissipation effect, The semiconductor element 1 is destroyed. The shape of the mounting surface of the semiconductor element 1 of the heat sink 3 is exemplified by a similar reduction type (3a) of the semiconductor element 1 and a shape (3b) in which only corners (ends) of the semiconductor element 1 are rounded. However, it is not particularly limited as long as the object of the present invention can be achieved, and a combination thereof, a curve, or a polygon may be used.

図３は、この発明の実施の形態１の半導体装置に用いるヒートシンクの半導体素子の搭載部の断面構造模式図である。図３（ａ）は、図１に示したヒートシンク３の半導体素子１の搭載部３ｃと同様の形状である。図３（ｂ）は、ヒートシンク３の半導体素子１の搭載部３ｄの側面部の形状を半導体素子１の搭載面に向かって狭くなるテーパー形状としている。図３（ｂ）のようなヒートシンク３の構造にした場合は、半導体素子１で発熱した熱のヒートシンク３への広がりが、図３（ａ）に示した構造よりも有利になり、より高熱動作が必要な半導体装置（モジュール）に適した構造である。また、図３（ｃ）は、ヒートシンク３の半導体素子１の搭載部３ｅの側面部の形状を半導体素子１の搭載面に向かって広くなるテーパー形状としている。図３（ｃ）のようなヒートシンク３の構造にした場合は、半導体素子１からヒートシンク３への熱の広がりは悪化するものの、封止樹脂７とヒートシンク３との食い付きが向上することから、構造的に剥離耐性が必要なモジュールに適した構造である。このように図３に示したヒートシンク３の半導体素子１の搭載部の形状は、上記の事例に縛られるものではなく、本発明の目的が達成されるものであれば特に限定されない。   FIG. 3 is a schematic cross-sectional view of the mounting portion of the semiconductor element of the heat sink used in the semiconductor device according to the first embodiment of the present invention. FIG. 3A shows the same shape as the mounting portion 3c of the semiconductor element 1 of the heat sink 3 shown in FIG. In FIG. 3B, the shape of the side surface portion of the mounting portion 3 d of the semiconductor element 1 of the heat sink 3 is a tapered shape that becomes narrower toward the mounting surface of the semiconductor element 1. In the case of the heat sink 3 structure as shown in FIG. 3B, the spread of heat generated in the semiconductor element 1 to the heat sink 3 becomes more advantageous than the structure shown in FIG. This is a structure suitable for a semiconductor device (module) that requires In FIG. 3C, the shape of the side surface portion of the mounting portion 3 e of the semiconductor element 1 of the heat sink 3 is a tapered shape that becomes wider toward the mounting surface of the semiconductor element 1. When the structure of the heat sink 3 as shown in FIG. 3C is used, the spread of heat from the semiconductor element 1 to the heat sink 3 is deteriorated, but the biting between the sealing resin 7 and the heat sink 3 is improved. This structure is suitable for modules that require structural peel resistance. As described above, the shape of the mounting portion of the semiconductor element 1 of the heat sink 3 shown in FIG. 3 is not limited to the above example, and is not particularly limited as long as the object of the present invention is achieved.

図４は、この発明の実施の形態１の半導体装置に用いるヒートシンクの半導体素子の搭載部の断面構造模式図である。図４（ａ）は、ヒートシンク３と半導体素子１の搭載部３ｃの凸部が一体的に形成されたものであり、削りだしや鋳造、プレス加工等によって形成する。図４（ｂ）は、別体のヒートシンク３の半導体素子１の搭載部３ｆとヒートシンク１１とをはんだ８等の導電性接合剤で形成した場合である。図４（ｃ）は、銅製の半導体素子１の搭載部３ｇとアルミ等のヒートシンク１２とを直接接合して形成した場合である。これらのいずれの方法を用いても本発明の目的に達成することができる。また、図４（ｂ）および図４（ｃ）は用いる金属が１種類以上であっても良く、本発明の目的が達成されるものであれば特に限定されない。   FIG. 4 is a schematic cross-sectional structure diagram of the mounting portion of the semiconductor element of the heat sink used in the semiconductor device according to the first embodiment of the present invention. In FIG. 4A, the heat sink 3 and the convex portion of the mounting portion 3c of the semiconductor element 1 are integrally formed, and are formed by cutting, casting, pressing or the like. FIG. 4B shows a case where the mounting portion 3 f of the semiconductor element 1 of the separate heat sink 3 and the heat sink 11 are formed of a conductive bonding agent such as solder 8. FIG. 4C shows a case where the mounting portion 3g of the copper semiconductor element 1 and the heat sink 12 such as aluminum are directly joined. Any of these methods can be used to achieve the object of the present invention. In addition, FIG. 4B and FIG. 4C are not particularly limited as long as one or more kinds of metals are used and the object of the present invention is achieved.

図５は、この発明の実施の形態１の半導体装置に用いるヒートシンクの半導体素子の搭載部の断面構造模式図である。図５（ａ）には、半導体装置１００の全体構造の断面構造模式図を示す。図５（ｂ）には、図５（ａ）中の点線で囲んだ半導体素子１の搭載部３ｃの部分を拡大した断面構造模式図を示す。図５（ｂ）に示したように、ヒートシンク３の半導体素子１の搭載部３ｃの凸部の厚さをＡ、搭載部３ｃの凸部を含めたヒートシンク３の厚さをＢとすると、これらの厚さの関係は０．９２＞Ａ／Ｂ＞０．０８を満たす必要がある。半導体素子１の搭載部３ｃの凸部の厚さＡが、ヒートシンク３の厚さＢの０．０８倍を下回ると、封止樹脂７の半導体素子１の下面側への回り込み量が減少するので、封止樹脂７による半導体素子１の抑え込みが弱くなり、半導体素子１と封止樹脂７との界面で剥離が生じ、半導体装置１００の信頼性が著しく損なわれる。また、半導体素子１の端部とヒートシンク３がより近接するため、ヒートサイクル時の半導体素子１の端部と封止樹脂７の界面とに発生する応力が大きくなり、封止樹脂７の剥離やクラックが生じて信頼性が低下する。逆に、半導体素子１の搭載部３ａの凸部の厚さＡが、ヒートシンク３の厚さＢの０．９２倍を超えると、ヒートシンク３の本来の役目である放熱性が低下し、半導体素子１の温度が上昇して半導体素子１の破壊が生じてしまう。   FIG. 5 is a schematic cross-sectional view of the mounting portion of the semiconductor element of the heat sink used in the semiconductor device according to the first embodiment of the present invention. FIG. 5A shows a schematic sectional view of the entire structure of the semiconductor device 100. FIG. 5B is a schematic cross-sectional structure diagram in which a portion of the mounting portion 3c of the semiconductor element 1 surrounded by a dotted line in FIG. As shown in FIG. 5B, when the thickness of the convex portion of the mounting portion 3c of the semiconductor element 1 of the heat sink 3 is A and the thickness of the heat sink 3 including the convex portion of the mounting portion 3c is B, these The relation of the thickness needs to satisfy 0.92> A / B> 0.08. If the thickness A of the convex portion of the mounting portion 3c of the semiconductor element 1 is less than 0.08 times the thickness B of the heat sink 3, the amount of the sealing resin 7 that wraps around the lower surface of the semiconductor element 1 decreases. The suppression of the semiconductor element 1 by the sealing resin 7 becomes weak, peeling occurs at the interface between the semiconductor element 1 and the sealing resin 7, and the reliability of the semiconductor device 100 is significantly impaired. Further, since the end portion of the semiconductor element 1 and the heat sink 3 are closer, the stress generated at the end portion of the semiconductor element 1 and the interface between the sealing resin 7 during the heat cycle increases, Cracks occur and reliability decreases. On the other hand, if the thickness A of the convex portion of the mounting portion 3a of the semiconductor element 1 exceeds 0.92 times the thickness B of the heat sink 3, the heat dissipation, which is the original function of the heat sink 3, is reduced. The temperature of 1 rises and the semiconductor element 1 is destroyed.

さらに、ヒートシンク３の半導体素子１の搭載部３ｃの凸部の厚さＡは、０．２５＜Ａ≦２．５ｍｍを満たす必要がある。半導体素子１の搭載部３ｃの凸部の厚さＡが、０．２５ｍｍを下回ると、封止樹脂７の半導体素子１の下面側への回り込み量が減少するので、封止樹脂７による半導体素子１の抑え込みが弱くなり、半導体素子１と封止樹脂７との界面で剥離が生じ、半導体装置１００の信頼性が著しく損なわれる。また、半導体素子１の端部とヒートシンク３がより近接するため、ヒートサイクル時の半導体素子１の端部と封止樹脂７の界面とに発生する応力が大きくなり、封止樹脂７の剥離やクラックが生じて信頼性が低下する。逆に、半導体素子１の搭載部３ａの凸部の厚さＡが、２．５ｍｍを超えると、ヒートシンク３の本来の役目である放熱性が低下し、半導体素子１の温度が上昇して半導体素子１の破壊が生じてしまう。   Furthermore, the thickness A of the convex portion of the mounting portion 3c of the semiconductor element 1 of the heat sink 3 needs to satisfy 0.25 <A ≦ 2.5 mm. When the thickness A of the convex portion of the mounting portion 3c of the semiconductor element 1 is less than 0.25 mm, the amount of the sealing resin 7 that wraps around the lower surface side of the semiconductor element 1 is reduced. 1 is weakened, peeling occurs at the interface between the semiconductor element 1 and the sealing resin 7, and the reliability of the semiconductor device 100 is significantly impaired. Further, since the end portion of the semiconductor element 1 and the heat sink 3 are closer, the stress generated at the end portion of the semiconductor element 1 and the interface between the sealing resin 7 during the heat cycle increases, Cracks occur and reliability decreases. On the other hand, if the thickness A of the convex portion of the mounting portion 3a of the semiconductor element 1 exceeds 2.5 mm, the heat dissipation, which is the original function of the heat sink 3, is reduced, and the temperature of the semiconductor element 1 is increased and the semiconductor element 1 is heated. The element 1 is destroyed.

図６および図７は、図１に示した本実施の形態１における半導体装置１００以外の電気的接続方法を用いた半導体装置に関する図である。   6 and 7 are diagrams relating to a semiconductor device using an electrical connection method other than the semiconductor device 100 according to the first embodiment shown in FIG.

図６は、この発明の実施の形態１の他の半導体装置の断面構造模式図である。図６において、半導体装置２００は、半導体素子１、リードフレーム２、金属部であるヒートシンク３、絶縁層５、金属板６、封止樹脂７、接合材８、接続端子１３、接続バー１４を備える。   FIG. 6 is a schematic sectional view of another semiconductor device according to the first embodiment of the present invention. In FIG. 6, the semiconductor device 200 includes a semiconductor element 1, a lead frame 2, a heat sink 3 as a metal part, an insulating layer 5, a metal plate 6, a sealing resin 7, a bonding material 8, a connection terminal 13, and a connection bar 14. .

図６に示した半導体装置２００では、半導体装置２００内部の電気的接続は接続端子１３と接続バー１４とを用いて行っている。例えば、接続端子１３は、円筒形状のものを用いることができる。また、接続バー１４としては、この接続端子１３の円筒形状と接続可能な形状であれば良い。   In the semiconductor device 200 shown in FIG. 6, electrical connection inside the semiconductor device 200 is performed using the connection terminals 13 and the connection bars 14. For example, the connection terminal 13 can be cylindrical. Further, the connection bar 14 may have any shape that can be connected to the cylindrical shape of the connection terminal 13.

図７は、この発明の実施の形態１の他の半導体装置の断面構造模式図である。図８は、この発明の実施の形態１の他の半導体装置の上面構造模式図および断面構造模式図である。図８（ａ）は、半導体装置３００の上面構造模式図であり、モールド樹脂７で覆われた外観図である。図８（ｂ）は、モールド樹脂７を透過して見た場合の半導体装置３００の上面構造模式図である。図８（ｃ）は、点線ＡＡにおける半導体装置３００の断面構造模式図である。図８（ｄ）は、点線ＢＢにおける半導体装置３００の断面構造模式図である。図７、図８において、半導体装置３００は、半導体素子１、リードフレーム２、金属部であるヒートシンク３、ボンディングワイヤ４、絶縁層５、金属板６、封止樹脂７、接合材８を備える。なお、図７は、図８（ｂ）の点線ＡＡにおける断面を紙面上側から見た図で、図８（ｃ）は点線ＡＡにおける断面を紙面下側から見た図である。   FIG. 7 is a schematic sectional view of another semiconductor device according to the first embodiment of the present invention. FIG. 8 is a schematic top view and a schematic cross-sectional view of another semiconductor device according to the first embodiment of the present invention. FIG. 8A is a schematic top view of the semiconductor device 300 and is an external view covered with the mold resin 7. FIG. 8B is a schematic top view of the structure of the semiconductor device 300 when viewed through the mold resin 7. FIG. 8C is a schematic sectional view of the semiconductor device 300 taken along a dotted line AA. FIG. 8D is a schematic sectional view of the semiconductor device 300 taken along the dotted line BB. 7 and 8, the semiconductor device 300 includes a semiconductor element 1, a lead frame 2, a heat sink 3 as a metal part, a bonding wire 4, an insulating layer 5, a metal plate 6, a sealing resin 7, and a bonding material 8. 7 is a view of the cross section taken along the dotted line AA in FIG. 8B from the upper side of the drawing, and FIG. 8C is a view of the cross section taken along the dotted line AA from the lower side of the drawing.

図７、図８に示した半導体装置３００では、半導体装置３００内部の電気的接続はリードフレーム２とボンディングワイヤ４とを用いて行っている。図６、図７および図８において、金属板６を用いたが、金属板に限定されるものでなく、銅箔やアルミ箔などの金属箔でも同様の効果を得ることができる。   In the semiconductor device 300 shown in FIGS. 7 and 8, the electrical connection inside the semiconductor device 300 is performed using the lead frame 2 and the bonding wire 4. 6, 7, and 8, the metal plate 6 is used. However, the metal plate 6 is not limited to the metal plate, and the same effect can be obtained with a metal foil such as a copper foil or an aluminum foil.

このように、電気的な接続は、所望の電流密度の電流を流すことが可能な接続方法を用いれば特に限定されない。また、回路構成等に応じた配線部材や配線形態を選択することで、さまざまな構成の半導体装置の形成が可能である。さらに、同一半導体装置内であっても、切断する位置により断面形状が異なる場合もある。いずれの接続形態の半導体装置においても、本発明を適用することで同様な信頼性向上の効果を得ることができる。   Thus, the electrical connection is not particularly limited as long as a connection method capable of flowing a current having a desired current density is used. Further, by selecting a wiring member and a wiring form according to the circuit configuration and the like, it is possible to form semiconductor devices having various configurations. Furthermore, even within the same semiconductor device, the cross-sectional shape may differ depending on the cutting position. In any connection type semiconductor device, the same reliability improvement effect can be obtained by applying the present invention.

以上のように構成された半導体装置においては、半導体素子１を半導体素子１よりも面積が小さいヒートシンク３の半導体素子１の搭載面３ａに搭載したので、封止樹脂７の体積に対するヒートシンク３の体積の割合が減少することで、ヒートサイクルに起因して発生する応力を低減することができる。その結果、半導体素子１と封止樹脂７との界面で生じる封止樹脂７の剥離や封止樹脂７のクラックを防止することができ、半導体装置の絶縁信頼性の向上が可能となる。   In the semiconductor device configured as described above, since the semiconductor element 1 is mounted on the mounting surface 3 a of the semiconductor element 1 of the heat sink 3 having a smaller area than the semiconductor element 1, the volume of the heat sink 3 with respect to the volume of the sealing resin 7. By reducing the ratio, the stress generated due to the heat cycle can be reduced. As a result, peeling of the sealing resin 7 and cracking of the sealing resin 7 that occur at the interface between the semiconductor element 1 and the sealing resin 7 can be prevented, and the insulation reliability of the semiconductor device can be improved.

また、半導体素子１を半導体素子１よりも面積が小さいヒートシンク３の半導体素子１の搭載面３ａに搭載した応力低減構造となっていることから、封止樹脂７に求められる弾性率や樹脂強度などの要求特性値の許容幅が広がり、半導体装置の生産性向上、低コスト化につながる。   Further, since the semiconductor element 1 has a stress reduction structure in which the semiconductor element 1 is mounted on the mounting surface 3a of the semiconductor element 1 having a smaller area than the semiconductor element 1, the elastic modulus and resin strength required for the sealing resin 7 and the like. This increases the allowable range of required characteristic values, leading to improved productivity of semiconductor devices and lower costs.

実施の形態２．
本実施の形態２においては、実施の形態１で用いたヒートシンクを含む冷却構造において、絶縁層として絶縁シートから絶縁基板に変更した点が異なる。このように絶縁層として絶縁基板を用いて構成した場合においても、ヒートサイクルに起因して発生する応力を低減することができる。その結果、半導体素子１と封止樹脂７との界面で生じる封止樹脂７の剥離や封止樹脂７のクラックを防止することができ、半導体装置の絶縁信頼性の向上が可能となる。 Embodiment 2. FIG.
The second embodiment is different in that the insulating structure is changed from an insulating sheet to an insulating substrate in the cooling structure including the heat sink used in the first embodiment. As described above, even when the insulating layer is used as the insulating layer, the stress generated due to the heat cycle can be reduced. As a result, peeling of the sealing resin 7 and cracking of the sealing resin 7 that occur at the interface between the semiconductor element 1 and the sealing resin 7 can be prevented, and the insulation reliability of the semiconductor device can be improved.

図９および図１０は、図７に示した本実施の形態１における半導体装置３００において、他の電気的接続方法を用いた半導体装置に関する図である。   FIGS. 9 and 10 are diagrams relating to the semiconductor device using another electrical connection method in the semiconductor device 300 according to the first embodiment shown in FIG.

図９は、この発明の実施の形態２における半導体装置の断面構造模式図である。基本的な構成は実施の形態１と同様であるが、半導体素子１を搭載するヒートシンク３を含む冷却部分の構成が異なる。   FIG. 9 is a schematic sectional view of a semiconductor device according to the second embodiment of the present invention. Although the basic configuration is the same as that of the first embodiment, the configuration of the cooling portion including the heat sink 3 on which the semiconductor element 1 is mounted is different.

図９において、半導体装置４００は、半導体素子１、リードフレーム２、金属部であるヒートシンク３、封止樹脂７、接合材８、絶縁基板１５、金属板６を備える。   In FIG. 9, the semiconductor device 400 includes a semiconductor element 1, a lead frame 2, a heat sink 3 as a metal part, a sealing resin 7, a bonding material 8, an insulating substrate 15, and a metal plate 6.

すなわち、実施の形態１では、絶縁層５として絶縁シートを用いているが、本実施の形態２においては、絶縁層５として絶縁シート５の替わりに絶縁基板１５を用いている。絶縁基板１５は、絶縁性のセラミック基板である。絶縁基板１５のいずれかの面に金属部であるヒートシンク３と金属板６とが配置されている。半導体素子１が搭載される面の電極部が凸部を有している構成になっている。絶縁層５として絶縁基板１５を用いている以外は実施の形態１の図７に示した半導体装置３００と同様の構成である。   That is, in Embodiment 1, an insulating sheet is used as the insulating layer 5, but in Embodiment 2, an insulating substrate 15 is used instead of the insulating sheet 5 as the insulating layer 5. The insulating substrate 15 is an insulating ceramic substrate. The heat sink 3 and the metal plate 6 which are metal parts are disposed on any surface of the insulating substrate 15. The electrode part on the surface on which the semiconductor element 1 is mounted has a convex part. The structure is the same as that of the semiconductor device 300 shown in FIG. 7 of the first embodiment except that the insulating substrate 15 is used as the insulating layer 5.

図１０は、本発明の実施の形態２における他の半導体装置の断面構造模式図である。図１０において、半導体装置５００は、半導体素子１、リードフレーム２、金属部であるヒートシンク３、封止樹脂７、接合材８、ベース板９、絶縁基板１５、金属板６を備える。半導体装置５００のように、絶縁基板１５の下部の金属板１６の下部にさらに応力低減や放熱のために金属製のベース板９を備える構造をとることもできる。基本的な構成は実施の形態１の図７に示した半導体装置３００と同様であるが、半導体素子１を搭載するヒートシンク３を含む部分の構成が異なる。すなわち、実施の形態１では、絶縁層５として絶縁シートを用いているが、本実施の形態２の他の半導体装置５００においては、絶縁層５として絶縁シート５の替わりに絶縁基板１５を用いている。絶縁基板１５は絶縁性のセラミック基板である。絶縁基板１５のいずれかの面に金属部であるヒートシンク３と金属板１６とが配置されている。さらに、絶縁基板１５の下部の金属板６の下部にベース板９を備えている以外は、実施の形態１の図７に示した半導体装置３００と同様の構成である。ベース板９として、銅モリブデン（ＣｕＭｏ）合金やアルミシリコンカーバイド（ＡｌＳｉＣ）合金等を用いることができる。   FIG. 10 is a schematic cross-sectional structure diagram of another semiconductor device according to the second embodiment of the present invention. In FIG. 10, the semiconductor device 500 includes a semiconductor element 1, a lead frame 2, a heat sink 3 as a metal part, a sealing resin 7, a bonding material 8, a base plate 9, an insulating substrate 15, and a metal plate 6. As in the semiconductor device 500, a structure in which a metal base plate 9 is further provided under the metal plate 16 below the insulating substrate 15 to further reduce stress and dissipate heat can be employed. Although the basic configuration is the same as that of the semiconductor device 300 shown in FIG. 7 of the first embodiment, the configuration of the portion including the heat sink 3 on which the semiconductor element 1 is mounted is different. That is, in the first embodiment, an insulating sheet is used as the insulating layer 5, but in another semiconductor device 500 of the second embodiment, the insulating substrate 15 is used instead of the insulating sheet 5 as the insulating layer 5. Yes. The insulating substrate 15 is an insulating ceramic substrate. The heat sink 3 and the metal plate 16 which are metal parts are disposed on either surface of the insulating substrate 15. Further, the configuration is the same as that of the semiconductor device 300 shown in FIG. 7 of the first embodiment except that the base plate 9 is provided below the metal plate 6 below the insulating substrate 15. As the base plate 9, a copper molybdenum (CuMo) alloy, an aluminum silicon carbide (AlSiC) alloy, or the like can be used.

以上のように構成された半導体装置においては、半導体素子１を半導体素子１よりも面積が小さいヒートシンク３の半導体素子１の搭載面３ａに搭載したので、封止樹脂７の体積に対するヒートシンク３の体積の割合が減少することで、ヒートサイクルに起因して発生する応力を低減することができる。その結果、半導体素子１と封止樹脂７との界面で生じる封止樹脂７の剥離や封止樹脂７のクラックを防止することができ、半導体装置の絶縁信頼性の向上が可能となる。   In the semiconductor device configured as described above, since the semiconductor element 1 is mounted on the mounting surface 3 a of the semiconductor element 1 of the heat sink 3 having a smaller area than the semiconductor element 1, the volume of the heat sink 3 with respect to the volume of the sealing resin 7. By reducing the ratio, the stress generated due to the heat cycle can be reduced. As a result, peeling of the sealing resin 7 and cracking of the sealing resin 7 that occur at the interface between the semiconductor element 1 and the sealing resin 7 can be prevented, and the insulation reliability of the semiconductor device can be improved.

なお、本実施の形態２で用いるヒートシンクは、実施の形態１で示したヒートシンク３の形状（図２、図３）や構成（図４）を用いることができることは言うまでもない。   Needless to say, the heat sink used in the second embodiment can use the shape (FIGS. 2 and 3) and the configuration (FIG. 4) of the heat sink 3 shown in the first embodiment.

また、半導体素子１を半導体素子１よりも面積が小さいヒートシンク３の半導体素子１の搭載面３ａに搭載した応力低減構造となっていることから、封止樹脂７に求められる弾性率や樹脂強度などの要求特性値の許容幅が広がり、半導体装置の生産性向上、低コスト化につながる。   Further, since the semiconductor element 1 has a stress reduction structure in which the semiconductor element 1 is mounted on the mounting surface 3a of the semiconductor element 1 having a smaller area than the semiconductor element 1, the elastic modulus and resin strength required for the sealing resin 7 and the like. This increases the allowable range of required characteristic values, leading to improved productivity of semiconductor devices and lower costs.

実施の形態３．
本実施の形態３においては、実施の形態１および実施の形態２で用いた封止樹脂で全体を覆ったモールド型の半導体装置において、モールド型から枠材を用いて周囲を囲い、枠材の内部を封止樹脂にて充填するケース型に変更した点が異なる。このように半導体装置をケース型とした場合においても、ヒートサイクルに起因して発生する応力を低減することができる。その結果、半導体素子１と封止樹脂７との界面で生じる封止樹脂７の剥離や封止樹脂７のクラックを防止することができ、半導体装置の絶縁信頼性の向上が可能となる。 Embodiment 3 FIG.
In the third embodiment, in the mold type semiconductor device that is entirely covered with the sealing resin used in the first and second embodiments, the frame material is used to surround the periphery of the mold material, The difference is that the interior is changed to a case mold filled with sealing resin. Thus, even when the semiconductor device is a case type, the stress generated due to the heat cycle can be reduced. As a result, peeling of the sealing resin 7 and cracking of the sealing resin 7 that occur at the interface between the semiconductor element 1 and the sealing resin 7 can be prevented, and the insulation reliability of the semiconductor device can be improved.

図１１は、本発明の実施の形態３における半導体装置の断面構造模式図である。図１１において、半導体装置６００は、半導体素子１、金属部であるヒートシンク３、絶縁層５、封止樹脂７、接合材８、ベース板９、ケース部材１０、電極端子１６を備える。基本的な構成は実施の形態１と同様であるが、モジュールの製造方法がモールディング方式であるモールド型ではなく、ポッティング方式であるケース型となっている。すなわち、本実施の形態はベース板９の上に、絶縁層５である高耐熱性の絶縁樹脂がシート状に形成され（絶縁シート）、さらにこのシート状絶縁樹脂の上に半導体素子１が搭載される搭載面を有する電極部が凸部を有しているヒートシンク３が形成されている。さらに、ベース板９を取り囲むように、電極端子１６を有したケース部材１０が取り付けられ、内部にはポッティングによる封止樹脂７で封止されている。それ以外は実施の形態１と同様である。   FIG. 11 is a schematic sectional view of a semiconductor device according to the third embodiment of the present invention. In FIG. 11, a semiconductor device 600 includes a semiconductor element 1, a heat sink 3 that is a metal part, an insulating layer 5, a sealing resin 7, a bonding material 8, a base plate 9, a case member 10, and electrode terminals 16. Although the basic configuration is the same as that of the first embodiment, the module manufacturing method is not a mold type that is a molding method but a case type that is a potting method. That is, in this embodiment, a highly heat-resistant insulating resin that is the insulating layer 5 is formed in a sheet shape on the base plate 9 (insulating sheet), and the semiconductor element 1 is mounted on the sheet-shaped insulating resin. The heat sink 3 is formed in which the electrode portion having the mounting surface has a convex portion. Further, a case member 10 having electrode terminals 16 is attached so as to surround the base plate 9, and the inside is sealed with a sealing resin 7 by potting. The rest is the same as in the first embodiment.

以上のように構成された半導体装置においては、半導体素子１を半導体素子１よりも面積が小さいヒートシンク３の半導体素子１の搭載面３ａに搭載したので、封止樹脂７の体積に対するヒートシンク３の体積の割合が減少することで、ヒートサイクルに起因して発生する応力を低減することができる。その結果、半導体素子１と封止樹脂７との界面で生じる封止樹脂７の剥離や封止樹脂７のクラックを防止することができ、半導体装置の絶縁信頼性の向上が可能となる。   In the semiconductor device configured as described above, since the semiconductor element 1 is mounted on the mounting surface 3 a of the semiconductor element 1 of the heat sink 3 having a smaller area than the semiconductor element 1, the volume of the heat sink 3 with respect to the volume of the sealing resin 7. By reducing the ratio, the stress generated due to the heat cycle can be reduced. As a result, peeling of the sealing resin 7 and cracking of the sealing resin 7 that occur at the interface between the semiconductor element 1 and the sealing resin 7 can be prevented, and the insulation reliability of the semiconductor device can be improved.

また、半導体素子１を半導体素子１よりも面積が小さいヒートシンク３の半導体素子１の搭載面３ａに搭載した応力低減構造となっていることから、封止樹脂７に求められる弾性率や樹脂強度などの要求特性値の許容幅が広がり、半導体装置の生産性向上、低コスト化につながる。なお、本実施の形態３で用いるヒートシンク３は、実施の形態１で示したヒートシンクの形状（図２、図３）や構成（図４）を用いることができることは言うまでもない。   Further, since the semiconductor element 1 has a stress reduction structure in which the semiconductor element 1 is mounted on the mounting surface 3a of the semiconductor element 1 having a smaller area than the semiconductor element 1, the elastic modulus and resin strength required for the sealing resin 7 and the like. This increases the allowable range of required characteristic values, leading to improved productivity of semiconductor devices and lower costs. Needless to say, the heat sink 3 used in the third embodiment can use the shape (FIGS. 2 and 3) and the configuration (FIG. 4) of the heat sink shown in the first embodiment.

[実施例]
実施の形態１における図１に示した半導体装置１００を用いて、比較検討を行った。ＳｉＣ製半導体素子１を一方の面に接合し、他方の面に絶縁層５を設けたヒートシンク３にリードフレーム２を接合し、全体をエポキシ樹脂で封止したモールド型半導体装置を作製した。表１に試作・評価した各種半導体装置の信頼性試験結果を示す。表１には、ＳｉＣ製半導体素子１の接合材搭載側の面積をＳ（ｃｈｉｐ）、ヒートシンク３の凸部のチップ搭載面の面積をＳ（ＨＳ）、ヒートシンク３の厚さをＬ（ＨＳ）（図５におけるＢ）、ヒートシンク３の凸部の厚さをL（凸）（図５におけるＡ）、で示した。ヒートシンク３とリードフレーム２は放熱性を考えて銅とした。ヒートシンク３上には、半導体素子１として、温度センサ付きＭＯＳＦＥＴとショットキーバリアダイオード（ＳＢＤ：Ｓｃｈｏｔｔｋｙ Ｂａｒｒｉｅｒ Ｄｉｏｄｅ）の２種を搭載した。なお、面積はπ＝３として計算、少数第３位で四捨五入している。 [Example]
A comparative study was performed using the semiconductor device 100 shown in FIG. A semiconductor device 1 made of SiC was bonded to one surface, a lead frame 2 was bonded to a heat sink 3 provided with an insulating layer 5 on the other surface, and a mold type semiconductor device was produced in which the whole was sealed with epoxy resin. Table 1 shows the reliability test results of various semiconductor devices that were prototyped and evaluated. Table 1 shows the area on the bonding material mounting side of the SiC semiconductor element 1 as S (chip), the area of the chip mounting surface of the convex portion of the heat sink 3 as S (HS), and the thickness of the heat sink 3 as L (HS). (B in FIG. 5), the thickness of the convex portion of the heat sink 3 is indicated by L (convex) (A in FIG. 5). The heat sink 3 and the lead frame 2 were made of copper in consideration of heat dissipation. On the heat sink 3, as the semiconductor element 1, two kinds of MOSFETs with a temperature sensor and a Schottky Barrier Diode (SBD) are mounted. The area is calculated with π = 3, rounded to the second decimal place.

封止樹脂７は、ガラス転移点（Ｔｇ）が約１９０℃のエポキシ樹脂にシリカを８２重量％充填し、熱膨張係数を１２×１０−６（１／Ｋ）となるものを用いた。 As the sealing resin 7, an epoxy resin having a glass transition point (Tg) of about 190 ° C. filled with 82% by weight of silica and having a thermal expansion coefficient of 12 × 10 −6 (1 / K) was used.

このようなヒートシンク３上に半導体素子１を接合し、半導体素子１とヒートシンク３の必要な場所にボンディングワイヤ４およびリードフレーム２にて電気的接続を行い、リードフレーム２や絶縁層５と合わせてトランスファーモールドによる樹脂封止を行った。樹脂封止は約１８０℃で１２０秒間行い、金型取り出し後にオーブンにて１８０℃、４時間のポストモールドキュア（ＰＭＣ：Ｐｏｓｔ Ｍｏｌｄ Ｃｕｒｅ）を実施した。   The semiconductor element 1 is bonded onto the heat sink 3, and the semiconductor element 1 and the heat sink 3 are electrically connected to the necessary locations by the bonding wires 4 and the lead frame 2, and are combined with the lead frame 2 and the insulating layer 5. Resin sealing by transfer molding was performed. Resin sealing was performed at about 180 ° C. for 120 seconds, and after mold removal, post mold cure (PMC) was performed in an oven at 180 ° C. for 4 hours.

半導体装置の信頼性試験は、温度サイクル試験にて実施した。温度サイクル試験は冷熱衝撃試験機（ＥＳＰＥＣ製ＴＳＤ−１００）に半導体装置を投入し、高温槽内の温度を−６０℃と１８０℃との間を繰り返し往復させて実施させた。信頼性の判定基準は、温度サイクル（Ｈ／Ｃ）試験が１０００サイクル経過後に剥離無きこととした。剥離有無の判断は、超音波映像装置（日立エンジニアリング・アンド・サービス製ＦｉｎｅＳＡＴ）で観察して実施した。また、連続動作時温度（Ｔｊ（ｏｐ））の測定は、ＭＯＳＦＥＴの温度センサを用いて実施した。定格の６５００Ｖでモジュールを動作させ、この動作時のチップ温度を測定した。信頼性の判断基準は、定格動作時のチップ温度が１７５℃を超えないこととした。   The reliability test of the semiconductor device was performed by a temperature cycle test. The temperature cycle test was performed by putting the semiconductor device into a thermal shock tester (TSP-100 manufactured by ESPEC) and repeatedly reciprocating the temperature in the high temperature bath between -60 ° C and 180 ° C. The criterion for reliability was that the temperature cycle (H / C) test had no peeling after 1000 cycles. Judgment of the presence or absence of peeling was carried out by observing with an ultrasonic imaging apparatus (FineSAT manufactured by Hitachi Engineering & Service). The temperature during continuous operation (Tj (op)) was measured using a MOSFET temperature sensor. The module was operated at the rated 6500 V, and the chip temperature during this operation was measured. The criterion for determining reliability is that the chip temperature during rated operation does not exceed 175 ° C.

実施例１〜９は用いる半導体素子１のサイズ：Ｓ(chip)は８１ｍｍ2、ヒートシンク３の厚み：Ｌ（ＨＳ）は３ｍｍ、Ｌ（凸）は１ｍｍと同一で、ヒートシンク３の凸部の面積：Ｓ（ＨＳ）だけを振った半導体装置の結果を示している。Ｓ（ＨＳ）の面積がチップサイズ以上である場合、ヒートサイクル時に封止樹脂と半導体素子の間で剥離が生じるため信頼性はＮＧであった。また、Ｓ（ＨＳ）の面積が小さくなるにつれ、Ｈ／Ｃ回数は向上し、反対にチップ温度は除々に上昇する（実施例２〜８）。さらに、Ｓ（ＨＳ）の面積が小さくなり、３６ｍｍ2以下になった場合にチップ温度が１７７℃になり、信頼性がＮＧとなった。以上の結果より、半導体素子１及びヒートシンク３の凸部の面積は１＞Ｓ（ＨＳ）／Ｓ（ｃｈｉｐ）≧１／２の関係を満たせば信頼性を有する半導体装置を得ることができる。 In Examples 1 to 9, the size of the semiconductor element 1 used: S (chip) is 81 mm 2 , the thickness of the heat sink 3: L (HS) is 3 mm, and L (convex) is the same as 1 mm. : Shows the result of the semiconductor device with only S (HS). When the area of S (HS) is equal to or larger than the chip size, the reliability is NG because peeling occurs between the sealing resin and the semiconductor element during the heat cycle. Further, as the area of S (HS) becomes smaller, the number of H / C increases, and on the contrary, the chip temperature gradually increases (Examples 2 to 8). Furthermore, when the area of S (HS) was reduced to 36 mm 2 or less, the chip temperature was 177 ° C., and the reliability was NG. From the above results, a semiconductor device having reliability can be obtained if the areas of the convex portions of the semiconductor element 1 and the heat sink 3 satisfy the relationship of 1> S (HS) / S (chip) ≧ 1/2.

実施例１０〜１２は、実施例５のヒートシンク３の凸部の厚みＬ（凸）を薄くした半導体装置の結果を示している。Ｌ（凸）が薄くなるにつれてチップ温度は低下傾向になるが、Ｈ／Ｃ回数は減少傾向であった。さらにＬ（凸）が薄くなった実施例１２ではＨ／Ｃ耐性の悪化により信頼性がＮＧとなった。以上の結果より、Ｌ（凸）／Ｌ（ＨＳ）＞０．０８の条件を満たす半導体装置が信頼性を有することが明らかとなった。   Examples 10 to 12 show the results of the semiconductor device in which the thickness L (convex) of the convex portion of the heat sink 3 of Example 5 is thinned. As L (convex) becomes thinner, the chip temperature tends to decrease, but the number of times of H / C tends to decrease. Furthermore, in Example 12 in which L (convex) became thinner, the reliability became NG due to the deterioration of the H / C resistance. From the above results, it became clear that the semiconductor device satisfying the condition of L (convex) / L (HS)> 0.08 has reliability.

実施例１３〜１５は、実施例５のヒートシンク３の凸部の厚みＬ（凸）を厚くした半導体装置の結果を示している。Ｌ（凸）が厚くなるにつれてＨ／Ｃ耐性は１２００回以上を維持しており良好であるが、チップ温度は上昇傾向であった。さらに、Ｌ（凸）が厚くなった実施例１５ではチップ温度が１８０℃となり、信頼性がＮＧとなった。以上の結果より、０．９２＞Ｌ（凸）／Ｌ（ＨＳ）の条件を満たす半導体装置が信頼性を有することが明らかとなった。   Examples 13 to 15 show the results of the semiconductor device in which the thickness L (convex) of the convex portion of the heat sink 3 of Example 5 was increased. As L (convex) becomes thicker, the H / C resistance is good at maintaining 1200 times or more, but the chip temperature tends to rise. Furthermore, in Example 15 where L (convex) became thick, the chip temperature became 180 ° C., and the reliability became NG. From the above results, it became clear that the semiconductor device satisfying the condition of 0.92> L (convex) / L (HS) has reliability.

実施例１６〜１９はチップサイズの異なる半導体素子１を用いた半導体素子の信頼性評価の結果を示すが、実施例１〜１５で得られた知見と同様の傾向が見られた。これらの結果より、Ｓ(ｃｈｉｐ)、Ｓ（ＨＳ）、Ｌ（ＨＳ）、Ｌ（凸）のサイズ制約は他の半導体素子１でも同様であり、普遍的であることが明らかとなった。   Examples 16 to 19 show the results of reliability evaluation of semiconductor elements using the semiconductor elements 1 having different chip sizes, but the same tendency as the findings obtained in Examples 1 to 15 was observed. From these results, it was clarified that the size constraints of S (chip), S (HS), L (HS), and L (convex) are the same in the other semiconductor elements 1 and are universal.

実施例２０〜２２は厚みの異なるヒートシンク３を用いた半導体装置の信頼性評価の結果を示すが、実施例１２〜１５で得られた知見と同様の傾向が見られた。これらの結果より、Ｌ（ＨＳ）、Ｌ（凸）のサイズ制約は他の半導体素子１でも同様であり、普遍的であることが明らかとなった。   Examples 20 to 22 show the results of the reliability evaluation of the semiconductor device using the heat sinks 3 having different thicknesses. The same tendency as the findings obtained in Examples 12 to 15 was observed. From these results, it was clarified that the size constraints of L (HS) and L (convex) are the same in the other semiconductor elements 1 and are universal.

Figure 0006303776
Figure 0006303776

１ 半導体素子、２ リードフレーム、３ ヒートシンク、３ａ，３ｂ ヒートシンクの搭載面、３ｃ，３ｄ，３ｅ，３ｆ ヒートシンクの半導体素子搭載部、４ ボンディングワイヤ、５ 絶縁層、６ 金属板（金属箔）、７ 封止樹脂、８ 接合材、９ ベース板、１０ ケース部材、１１ ヒートシンク部材、１２ ヒートシンク部材、１３ 接続端子、１４ 接続バー、１５ セラミック基板、１６ 電極端子、１００，２００，３００，４００，５００，６００ 半導体装置。   DESCRIPTION OF SYMBOLS 1 Semiconductor element, 2 Lead frame, 3 Heat sink, 3a, 3b Heat sink mounting surface, 3c, 3d, 3e, 3f Heat sink semiconductor element mounting portion, 4 Bonding wire, 5 Insulating layer, 6 Metal plate (metal foil), 7 Sealing resin, 8 bonding material, 9 base plate, 10 case member, 11 heat sink member, 12 heat sink member, 13 connection terminal, 14 connection bar, 15 ceramic substrate, 16 electrode terminal, 100, 200, 300, 400, 500, 600 Semiconductor device.

Claims (11)

半導体素子と、
前記半導体素子の電極が形成された面の周縁内に収まり前記半導体素子を搭載する搭載面を有する凸状の搭載部を備えた金属部と、
前記半導体素子と前記金属部とを封止する封止樹脂と、
を備え、
前記搭載部の厚さ（Ａ）は、０．２５ｍｍ＜Ａ≦２．５ｍｍであることを特徴とする半導体装置。 A semiconductor element;
A metal part having a convex mounting part that has a mounting surface for mounting the semiconductor element within a periphery of the surface on which the electrode of the semiconductor element is formed;
Sealing resin for sealing the semiconductor element and the metal part;
With
A thickness (A) of the mounting portion is 0.25 mm <A ≦ 2.5 mm. 前記搭載部は、前記金属部と一体的に形成されていることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the mounting portion is formed integrally with the metal portion. 前記搭載部は、前記金属部と別体で形成されていることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the mounting portion is formed separately from the metal portion. 前記搭載部は、前記金属部と同じ材料で形成されていることを特徴とする請求項１から請求項３のいずれか１項に記載の半導体装置。 The mounting portion, the semiconductor device according to any one of claims 1 to 3, characterized in that it is formed of the same material as said metal part. 前記搭載部は、前記金属部と異なる材料で形成されていることを特徴とする請求項３に記載の半導体装置。 The semiconductor device according to claim 3 , wherein the mounting portion is made of a material different from that of the metal portion. 前記搭載部の厚さ（Ａ）と前記搭載部の厚さを含む前記金属部の厚さ（Ｂ）との関係は、０．０８＜Ａ／Ｂ＜０．９２であることを特徴とする請求項２から請求項５のいずれか１項に記載の半導体装置。 The relationship between the thickness (A) of the mounting portion and the thickness (B) of the metal portion including the thickness of the mounting portion is 0.08 <A / B <0.92. the semiconductor device according to any one of the preceding claims 2. 前記搭載部は、側面部を有し、前記側面部がテーパー形状であることを特徴とする請求項1から請求項６のいずれか１項に記載の半導体装置。 The mounting portion includes a side surface portion, the semiconductor device according to any one of claims 1 to 6, wherein the side portion is tapered. 前記金属部の前記搭載部が配置された面との反対面側に絶縁層が接合されていることを特徴とする請求項１から請求項７のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 7, wherein an insulating layer is bonded to the opposite side of the mounting portion is disposed surface of the metal portion. 前記絶縁層は、絶縁シートであることを特徴とする請求項８に記載の半導体装置。 The semiconductor device according to claim 8 , wherein the insulating layer is an insulating sheet. 前記絶縁層は、セラミック部材であることを特徴とする請求項８に記載の半導体装置。 The semiconductor device according to claim 8 , wherein the insulating layer is a ceramic member. 前記半導体素子は、半導体材料として炭化ケイ素を用いたことを特徴とする請求項１から請求項１０のいずれか１項に記載の半導体装置。 The semiconductor device, the semiconductor device according to any one of claims 1 0 to claim 1, characterized by using silicon carbide as a semiconductor material.
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