JP2008545279A - Schottky diode with improved surge capability - Google Patents

Schottky diode with improved surge capability Download PDF

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JP2008545279A
JP2008545279A JP2008519694A JP2008519694A JP2008545279A JP 2008545279 A JP2008545279 A JP 2008545279A JP 2008519694 A JP2008519694 A JP 2008519694A JP 2008519694 A JP2008519694 A JP 2008519694A JP 2008545279 A JP2008545279 A JP 2008545279A
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diode
die
heat sink
package
anode
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カルタ，ロッサーノ
メルリン，ルイージ
ラッフォ，ディエーゴ
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Infineon Technologies Americas Corp
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International Rectifier Corp USA
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Abstract

ＳｉＣ又はＳｉのショットキーダイオード・ダイは、そのエピタキシャルアノード面（アノードコンタクト２５の露出面）がデバイスパッケージ内の最良のヒートシンク（パッケージの金属リードフレーム３０の頂面）に接続させるようにしてマウントされる。これにより、デバイスのサージ電流能力が実質的に増大される。  The SiC or Si Schottky diode die is mounted so that its epitaxial anode surface (exposed surface of the anode contact 25) connects to the best heat sink in the device package (the top surface of the package metal lead frame 30). The This substantially increases the surge current capability of the device.

Description

本発明は半導体デバイスに関し、より具体的には、ショットキーダイオードのサージ能力を向上させる構造に関する。   The present invention relates to a semiconductor device, and more particularly to a structure for improving the surge capability of a Schottky diode.

炭化ケイ素（ＳｉＣ）ショットキーダイオードは周知であり、シリコン（Ｓｉ）の場合の対応部分と比較して、低いスイッチング損失、高い降伏電圧、及び小容積且つ軽量という特性を有する。故に、このデバイスは、例えばコンバータ／インバータやモータ駆動などの数多くの用途において、Ｓｉショットキーダイオードを置き換えるものである。   Silicon carbide (SiC) Schottky diodes are well known and have the characteristics of low switching loss, high breakdown voltage, and small volume and light weight compared to their counterparts in silicon (Si). Thus, this device replaces the Si Schottky diode in many applications such as converter / inverter and motor drive.

しかしながら、例えば定格６００Ｖのような高電圧ＳｉＣショットキーダイオードは、等価なＳｉデバイスよりサージ能力が低い。斯くして、サージ耐性が重要である例えばＡＣ／ＤＣ力率補正回路などの用途において、従来のＳｉＣショットキーダイオードのサージ能力は等価なＳｉショットキーダイオードと比較して１／４に低下してしまっていた。   However, a high voltage SiC Schottky diode with a rating of 600 V, for example, has a lower surge capability than an equivalent Si device. Thus, in applications where surge resistance is important, such as AC / DC power factor correction circuits, the surge capability of conventional SiC Schottky diodes is reduced to ¼ compared to equivalent Si Schottky diodes. I was sorry.

本発明は、サージ能力が向上されたショットキーダイオードを提供することを目的とする。   An object of the present invention is to provide a Schottky diode with improved surge capability.

本発明に従って、ＳｉＣショットキー・ダイ、又は更にはシリコン（Ｓｉ）ショットキー・ダイは、該ダイの最も熱い側であるエピタキシャルアノード側から熱を一層効率的に除去し、それにより“自己加熱”の影響を抑制するように構成されたパッケージ内に搭載される。この自己加熱はＳｉＣショットキーダイオード及びそれに等価なＳｉショットキーダイオードのサージ能力を低下させる原因であると、本発明の発明者によって認識されたものである。   In accordance with the present invention, a SiC Schottky die, or even a silicon (Si) Schottky die, more efficiently removes heat from the hottest side of the die, the epitaxial anode side, thereby “self-heating”. It is mounted in a package configured to suppress the influence of This self-heating has been recognized by the inventor of the present invention as a cause of reducing the surge capability of SiC Schottky diodes and equivalent Si Schottky diodes.

これは、ダイのアノード側を導電性ヒートシンク面に十分に結合させてダイをマウントすることによって達成される。故に、ＳｉＣダイ又はＳｉダイはその通常の向きから裏返しにされ、アクティブ領域を囲むガードリングは、ガードリングを短絡させることなくアクティブなアノード領域がヒートシンク面にはんだ付け、あるいは導電性接着剤で固定され得るように、十分に絶縁される。支持面はＴＯ−２２０型パッケージ等で使用される従来からのリードフレームであってもよいし、DirectFET（登録商標）型の外囲器の導電性の“缶（can）”の内面であってもよい。このDirectFET（登録商標）型の外囲器又はパッケージは、米国特許第６６２４５２２号明細書に示されている。なお、この特許明細書の開示内容全体は参照することによりここに組み込まれる。   This is accomplished by mounting the die with the anode side of the die well bonded to the conductive heat sink surface. Therefore, the SiC die or Si die is flipped from its normal orientation, and the guard ring surrounding the active area is soldered to the heat sink surface or fixed with conductive adhesive without short circuiting the guard ring Well insulated so that it can be done. The support surface may be a conventional lead frame used in TO-220 type packages or the like, or the inner surface of a conductive “can” of a DirectFET® type envelope. Also good. This DirectFET® type envelope or package is shown in US Pat. No. 6,624,522. The entire disclosure of this patent specification is incorporated herein by reference.

ヒートシンク面へのアノードの良好な電気的且つ／或いは熱的な接続を確保するため、同時継続中の米国特許出願第１１／２５５０２１号（出願日：２００５年１０月２０日）に示されている種類の、はんだ付け可能な頂部金属が、特にはＳｉＣダイである、ダイのアノード面上に形成される。なお、この米国特許出願の開示内容全体は参照することによりここに組み込まれる。   To ensure good electrical and / or thermal connection of the anode to the heat sink surface, it is shown in co-pending US patent application Ser. No. 11 / 255,021 (filing date: October 20, 2005). A kind of solderable top metal is formed on the anode face of the die, in particular a SiC die. The entire disclosure of this US patent application is hereby incorporated by reference.

本発明の発明者によって、ＳｉＣショットキーダイオードの熱解析及び電気解析が行われ、等価なＳｉデバイスに対するサージ能力の低下は、ダイが生成熱を効率的に放散することができないときの、大電流で比較的長いパルス条件下でのダイの“自己発熱”に関係していることが突き止められた。このことは、大電流では正の温度係数がデバイス破壊に至る電圧降下を熱的に低下させるので、順方向導通状態でのデバイス性能に限界をもたらす。   The inventors of the present invention have performed thermal and electrical analysis of SiC Schottky diodes and the reduced surge capability for equivalent Si devices is a large current when the die cannot efficiently dissipate the generated heat. And was found to be related to die “self-heating” under relatively long pulse conditions. This places a limit on device performance in the forward conduction state, since at high currents a positive temperature coefficient thermally reduces the voltage drop leading to device breakdown.

これは、（例えば４Ｈ、３Ｃ、６Ｈ等の様々なポリタイプの何れかを有する）ＳｉＣの特性に起因するものであり、特に、典型的なＳｉＣデバイスの頂部エピタキシャル成長層において通常見受けられるような低濃度にドープされた材料を有するとき、温度に大きく依存する。   This is due to the properties of SiC (eg, having any of a variety of polytypes such as 4H, 3C, 6H, etc.), especially as low as typically found in the top epitaxial growth layers of typical SiC devices. When having a highly doped material, it is highly temperature dependent.

故に、図１に示されるように計算とシミュレーションとにより、自己発熱（Ｒｔｈ＝２．５Ｋ／Ｗ）に起因して温度が順電圧及び順電流に強く影響することが本発明の発明者によって認識された。図１において、電流の飽和がはっきりと見て取れる。 Therefore, the calculation and simulation as shown in FIG. 1 show that the temperature strongly affects the forward voltage and forward current due to self-heating (R th = 2.5 K / W). Recognized. In FIG. 1, the saturation of the current can be clearly seen.

この影響は低濃度ドープされた材料（すなわち、アノードのショットキーコンタクトを担持するエピタキシャル層）に強く依存する。故に、この層における移動度は温度とともに、
μ（Ｔ）＝μ０［Ｔ／３００］−２．５
という公式に従って低下する。ここで、μ０＝４００である。 This effect is strongly dependent on the lightly doped material (ie, the epitaxial layer carrying the anode Schottky contact). Therefore, the mobility in this layer, along with the temperature,
μ (T) = μ 0 [T / 300] −2.5
It decreases according to the formula. Here, μ 0 = 400.

以上より、高い接合部温度Ｔｊでの低い移動度は、高い抵抗率、高い順電圧Ｖｆ、及び乏しいサージ能力をもたらすことが理解される。なお、同じ分析がＳｉＣショットキー・ダイとＳｉショットキー・ダイとに当てはまり、本発明の利益はこれらに同等に適用され得るものである。 From the above, it can be seen that low mobility at high junction temperature T j results in high resistivity, high forward voltage V f , and poor surge capability. It should be noted that the same analysis applies to SiC Schottky dies and Si Schottky dies, and the benefits of the present invention can be equally applied to these.

本発明に従って、また上記の理解に従って、ダイのエピタキシャルシリコン側（アノード）はダイの最も温度が高い側であるので、このエピタキシャル側の冷却を改善することが極めて重要である。故に、ダイのエピタキシャル側は、該ダイのパッケージ内で利用可能な最良の熱放散面に接触するべきである。この面は、プラスチックパッケージにおけるダイを支持するリードフレームであり、あるいは、DirectFET（登録商標）型パッケージにおける缶内部の頂面である。   In accordance with the present invention and in accordance with the above understanding, it is very important to improve the cooling of this epitaxial side, since the epitaxial silicon side (anode) of the die is the hottest side of the die. Thus, the epitaxial side of the die should contact the best heat dissipation surface available in the die package. This surface is the lead frame that supports the die in the plastic package, or the top surface inside the can in the DirectFET® type package.

このため、ＳｉＣ又はその他のダイは、エピタキシャル層が標準パッケージのカソードの位置に来るように裏返されなければならない。エピタキシャル面の頂部金属は好ましくは、はんだ付け可能なものであり、例えば、先述の米国特許出願第１１／２５５０２１にて開示されているはんだ付け可能な頂部金属が用いられる。ここではダイのカソード側であるデバイスの背面側の金属は、好適な如何なる接合可能な金属であってもよい。   For this reason, the SiC or other die must be turned over so that the epitaxial layer is at the cathode location of the standard package. The top metal of the epitaxial surface is preferably solderable, for example the solderable top metal disclosed in the aforementioned US patent application Ser. No. 11/255021 is used. The metal on the back side of the device, here the cathode side of the die, can be any suitable bondable metal.

裏返されたダイが用いられるとき、デバイスの終端領域がリードフレームに接触することを防止するために特別な保護が必要である。理解されるように、好適なエポキシ樹脂の保護マスク等が用いられ得る。   When flipped dies are used, special protection is required to prevent the device termination area from contacting the lead frame. As will be appreciated, a suitable epoxy resin protective mask or the like may be used.

続いて、図４を参照するに、従来技術に係るＳｉＣショットキーダイオードデバイス20と該デバイスのパッケージの少なくとも一部とが示されている。ショットキー・ダイはダイ21として示されており、基板22及び頂部エピ層23を有している。ＳｉＣの抵抗率及び厚さは、例えば６００Ｖといった要求遮断電圧に基づく。障壁金属（バリアメタル）界面24はエピ層23の頂面であり、Ａｌ又は何らかの接合可能な金属であり得る好適なアノードコンタクト25を受けている。デバイスのアクティブ領域は、拡散された終端ガードリング26によって終端処理されており、ガードリング26は酸化物とし得る好適な絶縁層27によって保護されている。なお、Ｓｉショットキー・ダイにおいても同様の構造が存在する。   With continued reference to FIG. 4, a prior art SiC Schottky diode device 20 and at least a portion of the package of the device are shown. The Schottky die is shown as die 21 and has a substrate 22 and a top epi layer 23. The resistivity and thickness of SiC are based on the required cut-off voltage, for example 600V. The barrier metal (barrier metal) interface 24 is the top surface of the epi layer 23 and receives a suitable anode contact 25 which can be Al or some bondable metal. The active area of the device is terminated by a diffused termination guard ring 26, which is protected by a suitable insulating layer 27, which can be an oxide. A similar structure exists in the Si Schottky die.

基板22のカソード側は、例えばＣｒＮｉＡｇの三層構造又は何らかの好適なはんだ付け可能金属とし得るカソード電極28を受けている。   The cathode side of the substrate 22 receives a cathode electrode 28, which can be, for example, a three layer structure of CrNiAg or any suitable solderable metal.

ダイ21のパッケージは、例えば図４の金属リードフレーム30等のヒートシンク面を含んでいる。パッケージに含まれるその他の如何なる金属層もダイ21の良好なヒートシンクとして機能する。図４において、ダイ22は、良好な熱的接続が得られるように、リードフレーム30にはんだ付けされるか、導電性の接合剤又はエポキシ樹脂によって固定されるかしている。ヒートシンク30は、しばしば、パッケージのカソードコンタクトとしても機能する。   The package of the die 21 includes a heat sink surface such as the metal lead frame 30 of FIG. Any other metal layer included in the package functions as a good heat sink for die 21. In FIG. 4, the die 22 is either soldered to the lead frame 30 or fixed with a conductive bonding agent or epoxy resin so as to obtain a good thermal connection. The heat sink 30 often also functions as the package cathode contact.

そして、パッケージはダイ21を完全に収容するための何らかの好適手法にて完成される。   The package is then completed in any suitable manner for fully accommodating the die 21.

上述のように、この構造は予想外に乏しいサージ能力をもたらす。   As mentioned above, this structure results in unexpectedly poor surge capability.

本発明によれば、図４のダイ21は、該ダイのエピ側23がパッケージの最良のヒートシンク面と接触するように裏返される。   In accordance with the present invention, the die 21 of FIG. 4 is turned over so that the epi side 23 of the die contacts the best heat sink surface of the package.

図５において、図４の要素と相等しい要素は同一の参照符号を有している。しかしながら、ガードリング26が不意に金属体30に接触することを防止するため、コンタクト25の端部の周囲と終端保護27の下方とにエポキシ樹脂から成る保護体40が追加されている。また、アノードコンタクト25をヒートシンク30に熱的且つ電気的に接続するため、はんだペースト41が用いられている。   In FIG. 5, elements that are the same as those in FIG. 4 have the same reference numerals. However, in order to prevent the guard ring 26 from inadvertently contacting the metal body 30, a protective body 40 made of an epoxy resin is added around the end of the contact 25 and below the terminal protection 27. A solder paste 41 is used to connect the anode contact 25 to the heat sink 30 thermally and electrically.

図２は、２５℃にした図４のデバイスに関して、様々な電流値の０．５ｍｓパルスに対する順電圧を時間の関数として示している。図示された複数の曲線は、１５Ａ（最も下の曲線）から４０Ａ（最も上の曲線）までのパルスに対するものであり、中間のパルス電流は１７，２０、２２、２５、２７、３０、３２、３５及び３７Ａである。３７Ａ及び４０Ａのレベルでは急激な順電圧の増加が見られる。   FIG. 2 shows the forward voltage as a function of time for 0.5 ms pulses of various current values for the device of FIG. 4 at 25.degree. The curves shown are for pulses from 15A (bottom curve) to 40A (top curve), with intermediate pulse currents of 17, 20, 22, 25, 27, 30, 32, 35 and 37A. There is a rapid increase in forward voltage at the 37A and 40A levels.

図３は、新規な発明を包含する図５のダイに関して、図２と同様の曲線を示している。順電圧は実質的に低下されており、故に、より大きい電流値のパルスでのダイの加熱が抑制されている。   FIG. 3 shows a similar curve to FIG. 2 for the die of FIG. 5 that includes the novel invention. The forward voltage is substantially reduced, so that heating of the die with higher current pulses is suppressed.

本発明はその具体的な実施形態に関連して説明されてきたが、この他の数多くの変形及び改良、並びにこの他の適用が当業者には明らかになるであろう。故に、本発明はここで開示された具体例によって限定されるものではない。   Although the present invention has been described with reference to specific embodiments thereof, many other variations and modifications and other applications will become apparent to those skilled in the art. Accordingly, the present invention is not limited by the specific examples disclosed herein.

様々な温度におけるＳｉＣショットキーダイオードの順電圧及び順電流を示す図である。It is a figure which shows the forward voltage and forward current of a SiC Schottky diode in various temperature. 図４の従来技術に係るパッケージで２５℃にした場合の、様々な電流値の０．５ｍｓパルスに対する順電圧の測定値を、時間の関数として示す図である。FIG. 5 is a diagram showing measured values of forward voltage as a function of time for a 0.5 ms pulse of various current values when the package according to the related art of FIG. 図５に示されるように本発明に従ったショットキー・ダイがマウントされた場合の、順電圧の低下を示す図２と同様の図である。FIG. 6 is a view similar to FIG. 2 showing the drop in forward voltage when a Schottky die according to the present invention is mounted as shown in FIG. アノード層、すなわち、エピタキシャル成長層がパッケージのメインヒートシンクから離れた側にある従来技術に係るＳｉＣショットキーダイオードを示す断面図である。FIG. 2 is a cross-sectional view showing a prior art SiC Schottky diode with an anode layer, ie, an epitaxially grown layer, on the side of the package away from the main heat sink. 図４の構造においてダイが裏返され、より熱い側であるダイのエピ面側が、デバイスのパッケージ又は組立体のメインヒートシンクに面し、且つそれに熱的に結合された構造を示す断面図である。FIG. 5 is a cross-sectional view showing a structure in which the die is turned over in the structure of FIG. 4 and the hotter side of the die faces the main heat sink of the device package or assembly and is thermally coupled thereto.

Claims (11)

本体領域と、該本体領域上のエピタキシャル形成領域とを有する半導体ウェハ；
前記エピタキシャル形成領域上のアノードコンタクト、及び前記本体領域の底面に接するカソード電極；及び
前記ウェハ用の外囲器；
を有するショットキーダイオードであって、
前記外囲器は、表面を有する主ヒートシンクを含み；
前記アノードコンタクトは、前記ウェハのアノード側からの熱の除去を最大化し、それにより当該ダイオードのサージ能力を実質的に向上させるように、前記主ヒートシンクの前記表面に熱的に接続され且つ固定されている；
ダイオード。 A semiconductor wafer having a body region and an epitaxial formation region on the body region;
An anode contact on the epitaxial formation region, and a cathode electrode in contact with a bottom surface of the body region; and an envelope for the wafer;
A Schottky diode having
The envelope includes a main heat sink having a surface;
The anode contact is thermally connected and secured to the surface of the main heat sink to maximize heat removal from the anode side of the wafer and thereby substantially improve the surge capability of the diode. ing;
diode. 少なくとも前記本体領域はシリコン又は炭化ケイ素から成る、請求項１に記載のダイオード。   The diode of claim 1, wherein at least the body region comprises silicon or silicon carbide. 前記アノードコンタクトははんだ付け可能な材料である、請求項２に記載のダイオード。   The diode of claim 2, wherein the anode contact is a solderable material. 前記エピタキシャル形成領域の頂部内にあり、且つ前記アノードコンタクトを取り囲むガードリングの拡散層；及び前記ガードリングと前記主ヒートシンクの前記表面との間の絶縁体リング；を更に含む請求項２に記載のダイオード。   The guard ring diffusion layer in the top of the epitaxial formation region and surrounding the anode contact; and an insulator ring between the guard ring and the surface of the main heat sink. diode. 前記エピタキシャル形成領域の頂部内にあり、且つ前記アノードコンタクトを取り囲むガードリングの拡散層；及び前記ガードリングと前記主ヒートシンクの前記表面との間の絶縁体リング；を更に含む請求項３に記載のダイオード。   The guard ring diffusion layer in the top of the epitaxial formation region and surrounding the anode contact; and an insulator ring between the guard ring and the surface of the main heat sink. diode. 前記主ヒートシンクはリードフレームである、請求項２に記載のダイオード。   The diode of claim 2, wherein the main heat sink is a lead frame. 前記主ヒートシンクはリードフレームである、請求項３に記載のダイオード。   The diode of claim 3, wherein the main heat sink is a lead frame. 前記主ヒートシンクはリードフレームである、請求項５に記載のダイオード。   6. The diode of claim 5, wherein the main heat sink is a lead frame. パッケージはダイを受け入れる浅いカップを有するDirectFET型のパッケージであり；且つアノード電極は前記カップの頂部の内面に接続されている、請求項２に記載のダイオード。   The diode of claim 2, wherein the package is a DirectFET type package having a shallow cup to receive the die; and the anode electrode is connected to the inner surface of the top of the cup. パッケージはダイを受け入れる浅いカップを有するDirectFET型のパッケージであり；且つアノード電極は前記カップの頂部の内面に接続されている、請求項３に記載のダイオード。   4. The diode of claim 3, wherein the package is a DirectFET type package having a shallow cup to receive the die; and the anode electrode is connected to the top inner surface of the cup. パッケージはダイを受け入れる浅いカップを有するDirectFET型のパッケージであり；且つアノード電極は前記カップの頂部の内面に接続されている、請求項５に記載のダイオード。   6. The diode of claim 5, wherein the package is a DirectFET type package having a shallow cup to receive a die; and the anode electrode is connected to the top inner surface of the cup.
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