JP7415413B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device.

Conventionally, silicon (Si) has been used as a constituent material of power semiconductor devices that control high voltages and large currents. Power semiconductor devices include bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). There are several types, and these can be used depending on the purpose. It is being

For example, bipolar transistors and IGBTs have higher current densities than MOSFETs and can handle large currents, but cannot be switched at high speed. Specifically, bipolar transistors can only be used at a switching frequency of about several kHz, and IGBTs can only be used at switching frequencies of about several tens of kHz. On the other hand, power MOSFETs have a lower current density than bipolar transistors and IGBTs, making it difficult to increase the current, but they are capable of high-speed switching operations up to several MHz.

However, there is a strong demand in the market for power semiconductor devices that combine high current and high speed, and efforts are being focused on improving IGBTs and power MOSFETs, and development has now progressed to near the material limit. . Semiconductor materials to replace silicon are being considered from the perspective of power semiconductor devices, and silicon carbide (SiC) is a semiconductor material that can be used to create (manufacture) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics. is attracting attention.

Silicon carbide is a chemically very stable semiconductor material, has a wide band gap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. Furthermore, silicon carbide has a maximum electric field strength that is at least one order of magnitude higher than that of silicon, so it is expected to be a semiconductor material that can sufficiently reduce on-resistance. These characteristics of silicon carbide also apply to, for example, gallium nitride (GaN), which is a wide bandgap semiconductor having a wider bandgap than other silicones. Therefore, by using a wide bandgap semiconductor, it is possible to increase the breakdown voltage of a semiconductor device.

The trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor substrate (semiconductor chip), and the trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor substrate (semiconductor chip). A channel (inversion layer) is formed. Therefore, compared to a planar gate structure in which a channel is formed along the front surface of the semiconductor substrate, the density of unit cells (constituent units of an element) per unit area can be increased, and the current density per unit area can be increased. It is advantageous in terms of cost because it can increase The planar gate structure is a MOS gate structure in which a flat MOS gate is provided on the front surface of a semiconductor substrate.

In addition, as the current density of the device increases, the rate of temperature rise increases depending on the volume occupied by the unit cell, causing problems such as bonding wires to peel off, so it is difficult to improve discharge efficiency and stabilize reliability. In order to achieve this, a double-sided cooling structure is required. The double-sided cooling structure is a structure that improves the heat dissipation of the entire semiconductor substrate by dissipating heat generated in the semiconductor substrate to the outside from both sides of the semiconductor substrate. In the double-sided cooling structure, the heat generated in the semiconductor substrate is radiated through cooling fins that are in contact with the back surface of the semiconductor substrate via a metal base plate, and are radiated through a terminal whose one end is bonded to the front surface of the semiconductor substrate. Heat is radiated from the metal bar to which the other end of the terminal pin is connected via the pin.

In order to further improve reliability, the device has a highly functional structure by arranging high-performance parts such as a current sensing part, a temperature sensing part, and an overvoltage protection part on the same semiconductor substrate as the vertical MOSFET, which is the main semiconductor element. is proposed. When creating a highly functional structure, in order to stably form a highly functional part, a region where only the highly functional part is placed in the active region, separated from the unit cell of the main semiconductor element and adjacent to the edge termination region. will be provided. The active region is a region through which a main current flows when the main semiconductor element is turned on. The edge termination region is a region for relaxing the electric field on the front surface side of the semiconductor substrate and maintaining a breakdown voltage. Withstand voltage is the limit voltage at which an element will not malfunction or break down.

The structure of a conventional silicon carbide semiconductor device will be explained using a trench MOSFET as an example. FIG. 12 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. As shown in FIG. 12, in trench MOSFET 150, n ^- type silicon carbide epitaxial layer 102 is deposited on the front surface of n + -type silicon carbide substrate 101. An n-type high concentration region 106 is provided on the surface side of the n-type silicon carbide epitaxial layer 102 on the side opposite to the n ⁺ type silicon carbide substrate 101 side. Further, a first p ⁺ -type base region 104 is selectively provided in the surface layer of the n-type high concentration region 106 on the side opposite to the n ⁺ -type silicon carbide substrate 101 side. A second p ⁺ -type base region 105 is selectively provided in the n-type high concentration region 106 so as to cover the entire bottom surface of the trench 118 .

Further, the conventional trench MOSFET 150 further includes a p-type silicon carbide epitaxial layer 103, an n ⁺ type source region 107, a p ⁺⁺ type contact region 108, a gate insulating film 109, a gate electrode 110, an interlayer insulating film 111, a source electrode 113, a back electrode 114, a trench 118, a source electrode pad 115, and a drain electrode pad (not shown).

The source electrode 113 is provided on the n ⁺ type source region 107 and the p ^{+ +} type contact region 108, and the source electrode pad 115 is provided on the source electrode 113. The source electrode pad 115 is a multilayer film in which a first TiN film 125, a first Ti film 126, a second TiN film 127, a second Ti film 128, and an Al alloy film 129 are laminated in this order. Further, a second plating film 116, a second solder 117, an external electrode pin 119, a first protective film 121, and a second protective film 123 are provided on the source electrode pad 115.

In addition, by not forming a channel directly under the triple point where the plating film, protective film, and source electrode contact each other, current will not flow to the area where stress is concentrated, and the stress will be concentrated at the area where stress is concentrated. A semiconductor device that can suppress characteristic deterioration due to the above-mentioned characteristics is known (for example, see Patent Document 1 below).

Furthermore, even if the electrode has at least one protective layer having a hardness equal to or higher than that of Ta (tantalum) and a Cu bonding wire is used as the bonding wire, a power semiconductor device that does not cause chip cracks can be obtained. It is publicly known (for example, see Patent Document 2 below).

International Publication No. 2017/047283 Japanese Patent Application Publication No. 2014-082367

However, in the pin-type double-sided cooling structure, when the ends of the external electrode pins 119 are joined with the solder 117, it is difficult to control the angle between the solder 117 and the plating 116, which increases stress on the element active region. Furthermore, as the frequency of semiconductor devices increases, the temperature generated in the elements increases, and as the number of parallel elements and the number of modules that make up the elements increase, stress on the elements becomes locally concentrated. . This concentration of stress deteriorates various characteristics of the semiconductor device and reduces its reliability. In the worst case, the interlayer insulating film 111 will crack, causing a short circuit between the gate electrode 109 and the source electrode 113, resulting in a defective semiconductor device.

SUMMARY OF THE INVENTION In order to solve the above-described problems with the prior art, it is an object of the present invention to provide a semiconductor device that suppresses fluctuations in various characteristics during high frequency operation and is less likely to break down and is highly reliable.

In order to solve the above problems and achieve the objects of the present invention, a semiconductor device according to the present invention has the following features. In the semiconductor device, a first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate is provided on a front surface of a first conductive type semiconductor substrate. A second semiconductor layer of a second conductivity type is selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate side. A first semiconductor region of a first conductivity type is selectively provided in a surface layer of the second semiconductor layer on a side opposite to the semiconductor substrate side. A gate insulating layer is provided in contact with the second semiconductor layer. A gate electrode is provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor layer. A first electrode is provided on surfaces of the second semiconductor layer and the first semiconductor region. A metal plate is provided on the entire surface of the first electrode with a first solder interposed therebetween. A protective film is selectively provided on the metal plate. A pin-shaped electrode is connected to the metal plate via a second solder, and a second electrode is provided on the back surface of the semiconductor substrate. The first semiconductor region is not provided in the second semiconductor layer facing the end of the metal plate.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal plate is a copper plate and has a thickness of 5 μm or more.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal plate has a thickness of 20 μm or more and 5000 μm or less.

Further, in the semiconductor device according to the invention described above, the first solder has a higher melting point than the second solder.

Further, in the above-described invention, the semiconductor device according to the present invention further includes a trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer, and the gate electrode is arranged in the trench. It is characterized in that it is provided inside with the gate insulating film interposed therebetween.

Further, in the semiconductor device according to the above-described invention, a plating film is provided on the first electrode, and the metal plate is provided on the plating film via the first solder. Features.

According to the invention described above, the metal plate is provided on the source electrode pad via the first solder. Thereby, the stress applied to the second solder when fixing the external electrode pin can be dispersed and made uniform, and stress can be prevented from being locally concentrated in a specific region of the silicon carbide semiconductor device. Therefore, fluctuations in various characteristics due to high current density during high frequency operation can be significantly improved.

According to the semiconductor device according to the present invention, variations in various characteristics during high frequency operation are suppressed, and the semiconductor device has the effect of being less likely to be destroyed and having high reliability.

FIG. 1 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view (part 1) showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 2 is a cross-sectional view (part 2) showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (Part 3). FIG. 4 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 4). FIG. 5 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (part 5). FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (Part 6). 2 is a graph showing the rate of change in leakage current of a silicon carbide semiconductor device according to an embodiment and a conventional silicon carbide semiconductor device. 1 is a graph showing a rate of change in on-voltage of a silicon carbide semiconductor device according to an embodiment and a conventional silicon carbide semiconductor device. 7 is a graph showing the rate of change in threshold values of a silicon carbide semiconductor device according to an embodiment and a conventional silicon carbide semiconductor device. FIG. 3 is a cross-sectional view showing another structure of the metal plate of the silicon carbide semiconductor device according to the embodiment. FIG. 2 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, a layer or region prefixed with n or p means that electrons or holes are the majority carriers, respectively. Furthermore, + and - appended to n and p mean that the impurity concentration is higher or lower than that of a layer or region to which n or p is not appended, respectively. If the notation of n or p including + and - is the same, it indicates that the concentrations are close, but the concentrations are not necessarily equal. Note that in the following description of the embodiment and the accompanying drawings, similar components are denoted by the same reference numerals, and overlapping description will be omitted. In addition, in this specification, in the notation of Miller index, "-" means a bar attached to the index immediately after it, and by adding "-" in front of the index, it represents a negative index.

(Embodiment)
The semiconductor device according to the embodiment is configured using a semiconductor having a wider band gap than silicon (Si) (referred to as a wide band gap semiconductor). The structure of the semiconductor device according to this embodiment will be explained using an example in which silicon carbide (SiC) is used as a wide bandgap semiconductor. FIG. 1 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 1 shows the structure of the portion where the active region 40 connects to the edge termination region 41. As shown in FIG.

The silicon carbide semiconductor device according to the embodiment is a trench MOSFET 50 that includes a MOS gate with a trench gate structure on the front surface (the surface on the side of p-type silicon carbide epitaxial layer 3 described later) of the semiconductor substrate. The silicon carbide semiconductor substrate includes an n ⁺ type silicon carbide substrate (first conductivity type semiconductor substrate) 1 made of silicon carbide, an n type silicon carbide epitaxial layer (first conductivity type first semiconductor layer) 2 and a p type carbide substrate. A silicon epitaxial layer (second conductivity type second semiconductor layer) 3 is epitaxially grown in order. N-type high concentration region 6 may be epitaxially grown on n-type silicon carbide epitaxial layer 2 .

A MOS gate with a trench gate structure includes a p-type silicon carbide epitaxial layer 3, an n ⁺ -type source region (first semiconductor region of the first conductivity type) 7, a p ^++- type contact region 8, a trench 18, a gate insulating film 9, and It is composed of a gate electrode 10.

Specifically, the trench 18 penetrates the p-type silicon carbide epitaxial layer 3 in the depth direction z from the front surface of the semiconductor substrate, and extends into the n-type high concentration region 6 (where the n-type high concentration region 6 is provided). If not, the n-type silicon carbide epitaxial layer 2 (hereinafter referred to as (2)) is reached. The depth direction z is a direction from the front surface to the back surface of the semiconductor substrate. The trenches 18 are arranged, for example, in a striped pattern.

Inside the trench 18, a gate insulating film 9 is provided along the inner wall of the trench 18, and a gate electrode 10 is provided on the gate insulating film 9 so as to be buried inside the trench 18. The gate electrode 10 in one trench 18 and the adjacent mesa regions (regions between adjacent trenches 18) with the gate electrode 10 in between constitute one unit cell of the main semiconductor element. Although only two trench MOS structures are shown in FIG. 1, more trench MOS gate (insulated gates made of metal-oxide film-semiconductor) structures may be arranged in parallel.

An n-type region (hereinafter referred to as an n-type high concentration region) 6 is formed in the surface layer of the n-type silicon carbide epitaxial layer 2 on the source side (source electrode 13 side described later) so as to be in contact with the p-type silicon carbide epitaxial layer 3. may be provided. The n-type high concentration region 6 is a so-called current spreading layer (CSL) that reduces carrier spreading resistance. This n-type high concentration region 6 is provided uniformly in a direction parallel to the substrate front surface (the front surface of the semiconductor substrate) so as to cover the inner wall of the trench 18, for example.

N-type high concentration region 6 reaches a position deeper from the interface with p-type silicon carbide epitaxial layer 3 toward the drain side (back electrode 14 side described later) than the bottom surface of trench 18 . Inside the n-type high concentration region 6, first and second p ⁺ -type base regions 4 and 5 may be selectively provided, respectively. First p ⁺ -type base region 4 is provided between adjacent trenches 18 (mesa region), separated from second p ⁺ -type base region 5 and trench 18 , and is in contact with p-type silicon carbide epitaxial layer 3 . The second p ⁺ -type base region 5 covers at least the bottom surface of the bottom surface and bottom corner portions of the trench 18 . The bottom corner portion of the trench 18 is the boundary between the bottom surface and the sidewall of the trench 18.

The pn junction between the first and second p ⁺ -type base regions 4 and 5 and the n-type silicon carbide epitaxial layer 2 is formed at a deeper position on the drain side than the bottom surface of the trench 18 . The first and second p ⁺ -type base regions 4 and 5 may be provided inside the n-type silicon carbide epitaxial layer 2 without providing the n-type high concentration region 6 . The depth positions of the drain side ends of the first and second p ⁺ type base regions 4 and 5 are such that the pn junction between the first and second p ⁺ type base regions 4 and 5 and the n-type silicon carbide epitaxial layer 2 is located at the bottom of the trench 18. It only needs to be located at a deeper position on the drain side, and can be changed in various ways according to design conditions. The first and second p ⁺ -type base regions 4 and 5 can prevent a high electric field from being applied to the gate insulating film 9 along the bottom surface of the trench 18 .

An n ⁺ -type source region 7 is selectively provided inside the p-type silicon carbide epitaxial layer 3 . A p ⁺⁺ type contact region 8 may be selectively provided so as to be in contact with the n ⁺ type source region 7 . The n ⁺ -type source region 7 is in contact with the gate insulating film 9 on the side wall of the trench 18 and faces the gate electrode 10 via the gate insulating film 9 on the side wall of the trench 18 .

The interlayer insulating film 11 is provided over the entire front surface of the semiconductor substrate so as to cover the gate electrode 10 . A contact hole is formed in the interlayer insulating film 11 so as to penetrate the interlayer insulating film 11 in the depth direction z and reach the front surface of the substrate.

The source electrode (first electrode) 13 is in ohmic contact with the semiconductor substrate (n ⁺ type source region 7 ) within the contact hole, and is electrically insulated from the gate electrode 10 by the interlayer insulating film 11 . A source electrode pad 15 is provided on the source electrode 13 . The source electrode pad 15 is a multilayer film in which a first TiN film 25, a first Ti film 26, a second TiN film 27, a second Ti film 28, and an Al alloy film 29 are laminated. When the p ⁺⁺ type contact region 8 is provided, the source electrode 13 makes ohmic contact with the p ⁺⁺ type contact region 8 . If p ⁺⁺ type contact region 8 is not provided, source electrode 13 is in ohmic contact with p type silicon carbide epitaxial layer 3 .

A first plating film 33 is provided on the source electrode pad 15 , and a metal plate 30 is provided on the first plating film 33 via a first solder 32 . Specifically, the insulating film 12 of the edge termination region 41 is provided to cover the source electrode pad 15 of the active region 40, the third protective film 31 is provided on the insulating film 12, and the third protective film 31 is provided on the insulating film 12. A metal plate 30 is provided in the opening of 31 via a first plating film 33 and a first solder 32 .

The metal plate 30 is a flat film made of metal such as copper (Cu). The metal plate 30 is provided so as to cover the entire surface of the active region 40 . Further, the metal plate 30 may be provided so as to partially cover the edge termination region 41. It is preferable that metal plate 30 be thicker in order to relieve stress when external electrode pins 19 (described later) are joined with second solder 17 and to thermally cool the silicon carbide semiconductor device. The metal plate 30 is at least thicker than the first plating film 33, and specifically has a thickness of 5 μm or more. In order to efficiently relieve stress on the external electrode pins 19, the metal plate 30 preferably has a thickness of 20 μm or more and 5000 μm or less.

As described above, when the external electrode pin 119 is bonded onto the plating film 116 with the second solder 117, the bonding may occur depending on the angle between the external electrode pin 119 and the second solder 117 formed on the plating film 116. This stress deteriorates the characteristics of the silicon carbide semiconductor device. For example, when a silicon carbide semiconductor device operates at a high frequency and the current density increases, variations in various characteristics tend to occur. In particular, leakage current between the drain and source increases due to the threshold at low currents.

In contrast, in the embodiment, by providing the metal plate 30 on the source electrode pad 15, the stress applied to the external electrode pin 19 and the second solder 17 that fixes it can be dispersed and made uniform. can. This can prevent stress from being locally concentrated in a specific region of the silicon carbide semiconductor device, and can significantly improve variations in various characteristics due to high current density during high frequency operation.

Further, as shown in FIG. 1, when the metal plate 30 is provided so as to cover the entire surface of the active region 40, it is preferable that the structure of the active region 40 directly under the end of the metal plate 30 is a region that does not function as a MOS. The region that does not function as a MOS is a region where no channel is formed because n ⁺ type source region 7 is not provided inside p-type silicon carbide epitaxial layer 3, as shown in FIG. The end of the metal plate 30 is a region where the stress dispersed by the metal plate 30 is concentrated, and by not allowing this region to function as a MOS, various characteristics of the silicon carbide semiconductor device deteriorate and reliability decreases. can be suppressed. Further, it is possible to suppress damage to interlayer insulating film 11 due to this stress, short circuit between gate electrode 10 and source electrode 13, and failure of the silicon carbide semiconductor device.

One end of the external electrode pin 19 is bonded onto the metal plate 30 via the second solder 17. The other end of the external electrode pin 19 is joined to a metal bar (not shown) arranged to face the front surface of the semiconductor substrate. Further, the other end of the external electrode pin 19 is exposed outside the case (not shown) in which the semiconductor chip is mounted, and is electrically connected to an external device (not shown).

The surface of the metal plate 30 is covered with a first protective film 21 except for the area where the second solder 17 is provided. Specifically, the first protective film 21 is provided to cover the metal plate 30 , and the external electrode pin 19 is connected to the metal plate 30 exposed through the opening of the first protective film 21 via the second solder 17 . are joined. The first protective film 21 is, for example, a polyimide film.

Further, it is preferable that the first solder 32 has a higher melting point than the second solder 17. In this case, during bonding with the second solder 17, the portion bonded with the first solder 32 will not melt. Therefore, the heat treatment for joining the source electrode pad 15 and the metal plate 30 with the first solder 32 and the heat treatment for joining the metal plate 30 and the external electrode pin 19 with the second solder 17 are performed separately. It can be implemented as a process.

A back electrode (second electrode) 14 serving as a drain electrode is provided on the back surface of the semiconductor substrate. A drain electrode pad (not shown) is provided on the back electrode 14.

(Method for manufacturing a silicon carbide semiconductor device according to an embodiment)
Next, a method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. 2 to 7 are cross-sectional views showing a state in the middle of manufacturing a silicon carbide semiconductor device according to an embodiment.

First, an n ⁺ type silicon carbide substrate 1 made of n type silicon carbide is prepared. Then, a first n ^- type silicon carbide epitaxial layer 2a made of silicon carbide is formed on the first main surface of this n + type silicon carbide substrate 1 to a thickness of, for example, 30 μm while doping with an n-type impurity, for example, nitrogen atoms (N). Epitaxially grow to a certain thickness. The state up to this point is shown in FIG.

Next, an ion implantation mask having a predetermined opening is formed using, for example, an oxide film on the surface of first n-type silicon carbide epitaxial layer 2a by photolithography. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film to form a lower first p ⁺ -type base region 4a and a second p ⁺ -type base region 5 having a depth of about 0.5 μm.

Further, the distance between the adjacent lower first p ⁺ type base region 4a and second p ⁺ type base region 5 is formed to be about 1.5 μm. The impurity concentration of the lower first p ⁺ type base region 4a and the second p ⁺ type base region 5 is set to, for example, about 5×10 ¹⁸ /cm ³ .

Next, a part of the ion implantation mask is removed, and an n-type impurity such as nitrogen is ion-implanted into the opening to a part of the surface region of the first n-type silicon carbide epitaxial layer 2a to a depth of, for example, 0. A lower n-type high concentration region 6a having a thickness of about 5 μm may be formed. The impurity concentration of the lower n-type high concentration region 6a is set to, for example, about 1×10 ¹⁷ /cm ³ . The state up to this point is shown in FIG.

Next, a second n-type silicon carbide epitaxial layer 2b doped with an n-type impurity such as nitrogen is formed to a thickness of about 0.5 μm on the surface of the first n-type silicon carbide epitaxial layer 2a. The impurity concentration of second n-type silicon carbide epitaxial layer 2b is set to be approximately 3×10 ¹⁵ /cm ³ . Thereafter, first n-type silicon carbide epitaxial layer 2a and second n-type silicon carbide epitaxial layer 2b are combined to form n-type silicon carbide epitaxial layer 2.

Next, on the surface of second n-type silicon carbide epitaxial layer 2b, an ion implantation mask having a predetermined opening is formed using, for example, an oxide film by photolithography. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film, and an upper first p ⁺ type base region 4b with a depth of about 0.5 μm is formed so as to overlap the lower first p ⁺ type base region 4a. do. The lower first p ⁺ -type base region 4 a and the upper first p ⁺ -type base region 4 b form a continuous region, and become the first p ⁺ -type base region 4 . The impurity concentration of the upper first p ⁺ -type base region 4b is set to, for example, about 5×10 ¹⁸ /cm ³ .

Next, a part of the ion implantation mask is removed, and an n-type impurity such as nitrogen is ion-implanted into the opening to a part of the surface region of second n-type silicon carbide epitaxial layer 2b to a depth of, for example, 0. The upper n-type high concentration region 6b having a thickness of about 5 μm may be formed. The impurity concentration of the upper n-type high concentration region 6b is set to, for example, about 1×10 ¹⁷ /cm ³ . The upper n-type high concentration region 6b and the lower n-type high concentration region 6a are formed so as to be at least partially in contact with each other to form the n-type high concentration region 6. However, this n-type high concentration region 6 may or may not be formed over the entire surface of the substrate. The state up to this point is shown in FIG.

Next, on the surface of n-type silicon carbide epitaxial layer 2, p-type silicon carbide epitaxial layer 3 is formed to a thickness of about 1.1 μm by epitaxial growth. The impurity concentration of p-type silicon carbide epitaxial layer 3 is set to about 4×10 ¹⁷ /cm ³ . After the p-type silicon carbide epitaxial layer 3 is formed by epitaxial growth, p-type impurities such as aluminum may be further ion-implanted into the channel region of the p-type silicon carbide epitaxial layer 2. .

Next, on the surface of p-type silicon carbide epitaxial layer 3, an ion implantation mask having a predetermined opening is formed using, for example, an oxide film by photolithography. N-type impurities such as nitrogen (N) and phosphorus (P) are ion-implanted into this opening to form n ⁺ -type source region 7 in a part of the surface of p-type silicon carbide epitaxial layer 3 . Next, the ion implantation mask used to form n ⁺ type source region 7 is removed, and an ion implantation mask having a predetermined opening is formed using the same method to form the surface of p type silicon carbide epitaxial layer 3. A p ⁺⁺ type contact region 8 may be formed by ion-implanting a p type impurity such as phosphorus into a portion of the contact region 8 . The impurity concentration of p ⁺⁺ type contact region 8 is set to be higher than the impurity concentration of p type silicon carbide epitaxial layer 3 . The state up to this point is shown in FIG.

Next, heat treatment (annealing) is performed in an inert gas atmosphere at about 1700° C. to form the first p ⁺ type base region 4 , the second p ⁺ type base region 5 , the n ⁺ type source region 7 and the p ⁺ type contact region 8 . Perform activation processing. Note that, as described above, each ion implantation region may be activated at once by one heat treatment, or each ion implantation region may be activated by performing heat treatment every time ion implantation is performed.

Next, on the surface of p-type silicon carbide epitaxial layer 3, a trench forming mask having a predetermined opening is formed using, for example, an oxide film by photolithography. Next, by dry etching, a trench 18 is formed which penetrates the p-type silicon carbide epitaxial layer 3 and reaches the n-type high concentration region 6(2). The bottom of the trench 18 may reach the second p ⁺ -type base region 5 formed in the n-type high concentration region 6 (2). Next, the trench forming mask is removed. The state up to this point is shown in FIG.

Next, gate insulating film 9 is formed along the surface of n ⁺ -type source region 7 and the bottom and sidewalls of trench 18 . This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1000° C. in an oxygen atmosphere. Further, the gate insulating film 9 may be formed by a method of depositing by a chemical reaction such as high temperature oxidation (HTO).

Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed to fill the trench 18. This polycrystalline silicon layer is patterned by photolithography and left inside the trench 18, thereby forming the gate electrode 10.

Next, a film of, for example, phosphor glass is formed to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10, thereby forming an interlayer insulating film 11. Next, a barrier metal made of titanium (Ti), titanium nitride (TiN), or a stack of titanium and titanium nitride may be formed to cover the interlayer insulating film 11. Interlayer insulating film 11 and gate insulating film 9 are patterned by photolithography to form contact holes exposing n ⁺ type source region 7 and p ^{+ +} type contact region 8. If p ⁺⁺ type contact region 8 is not formed, a contact hole exposing n ⁺ type source region 7 and p type silicon carbide epitaxial layer 3 is formed. Thereafter, heat treatment (reflow) is performed to planarize the interlayer insulating film 11. The state up to this point is shown in FIG. Further, after forming the contact hole in the interlayer insulating film 11, a barrier metal made of titanium (Ti), titanium nitride (TiN), or a stack of titanium and titanium nitride may be formed. In this case, a contact hole is provided in the barrier metal to expose the n ⁺ type source region 7 and the p ^{+ +} type contact region 8.

Next, a conductive film that will become the source electrode 13 is formed in the contact hole provided in the interlayer insulating film 11 and on the interlayer insulating film 11 . The conductive film is, for example, a nickel (Ni) film. Further, a nickel (Ni) film is similarly formed on the second main surface of n ⁺ -type silicon carbide substrate 1. Thereafter, a heat treatment is performed at a temperature of, for example, about 970° C. to silicide the nickel film inside the contact hole to form the source electrode 13. At the same time, the nickel film formed on the second main surface becomes back electrode 14 that forms an ohmic contact with n ⁺ type silicon carbide substrate 1 . Thereafter, the unreacted nickel film is selectively removed, leaving the source electrode 13 only in the contact hole, for example.

Next, by sputtering, for example, first TiN film 25, first Ti film 26, second TiN film 27, and second Ti film 28 are formed so as to cover source electrode 13 and interlayer insulating film 11 on the front surface of the silicon carbide semiconductor substrate. are laminated in order, and then an Al alloy film 29 is formed to have a thickness of, for example, about 5 μm. The Al alloy film 29 may be an Al film. The Al alloy film 29 is, for example, an Al-Si film or an Al-Si-Cu film. This conductive film is patterned by photolithography and left in the active region of the entire device, thereby forming the source electrode pad 15.

Next, after forming a polyimide film on the Al alloy film 29, the polyimide film is selectively removed by photolithography and etching to form a third protective film 31, and an opening is formed in the third protective film 31. form. Next, a first plating film 33 is formed on the Al alloy film 29 exposed in the opening of the third protective film 31. Next, the metal plate 30 is bonded onto the first plating film 33 using the first solder 32 . The metal plate 30 may be formed on the Al alloy film 29 by a plating method or the like.

Next, after forming a polyimide film on the metal plate 30, the polyimide film is selectively removed by photolithography and etching to form the first protective film 21 and to form an opening in the first protective film 21. Form.

Thereafter, external electrode pins 19 are formed on the metal plate 30 exposed through the opening of the first protective film 21 via the second solder 17. In the manner described above, the silicon carbide semiconductor device shown in FIG. 1 is completed.

FIG. 8 is a graph showing the rate of change in leakage current of the silicon carbide semiconductor device according to the embodiment and the conventional silicon carbide semiconductor device. In FIG. 8, the horizontal axis indicates the operating frequency of the silicon carbide semiconductor device, and the unit is kHz. The vertical axis indicates the rate of change in leakage current between the drain and source before and after operation at the frequency of the horizontal axis, and the unit is %. In FIG. 8, the line indicated by B indicates the characteristics of the conventional silicon carbide semiconductor device, and the line indicated by A indicates the characteristics of the silicon carbide semiconductor device according to the embodiment.

As shown in FIG. 8, in the conventional silicon carbide semiconductor device, as the operating frequency increases and the current density becomes higher, the leakage current increases and the characteristics deteriorate. On the other hand, in the silicon carbide semiconductor device according to the embodiment, even when the operating frequency increases and the current density becomes high, the leakage current does not increase, and the deterioration of the leakage current is significantly improved.

FIG. 9 is a graph showing the rate of change in on-voltage of the silicon carbide semiconductor device according to the embodiment and the conventional silicon carbide semiconductor device. In FIG. 9, the horizontal axis indicates the operating frequency of the silicon carbide semiconductor device, and the unit is kHz. The vertical axis indicates the rate of change in the on-voltage (Von) before and after operation at the frequency of the horizontal axis, and the unit is %. In FIG. 9, the line indicated by B indicates the characteristics of the conventional silicon carbide semiconductor device, and the line indicated by A indicates the characteristics of the silicon carbide semiconductor device according to the embodiment.

As shown in FIG. 9, in the conventional silicon carbide semiconductor device, as the operating frequency increases and the current density becomes higher, the on-voltage increases and the characteristics deteriorate. On the other hand, in the silicon carbide semiconductor device according to the embodiment, even when the operating frequency increases and the current density becomes high, the on-voltage does not increase, and the deterioration of the on-voltage is significantly improved.

FIG. 10 is a graph showing the rate of change in threshold values of the silicon carbide semiconductor device according to the embodiment and the conventional silicon carbide semiconductor device. In FIG. 10, the horizontal axis indicates the operating frequency of the silicon carbide semiconductor device, and the unit is kHz. The vertical axis indicates the rate of change in the threshold value before and after operating at the frequency of the horizontal axis, and the unit is %. In FIG. 10, the line indicated by B indicates the characteristics of the conventional silicon carbide semiconductor device, and the line indicated by A indicates the characteristics of the silicon carbide semiconductor device according to the embodiment.

As shown in FIG. 10, in the conventional silicon carbide semiconductor device, as the operating frequency increases and the current density becomes higher, the threshold value increases and the characteristics deteriorate. On the other hand, in the silicon carbide semiconductor device according to the embodiment, even when the operating frequency increases and the current density becomes high, the threshold value does not increase, and the deterioration of the threshold value is significantly improved.

FIG. 11 is a cross-sectional view showing another structure of the metal plate of the silicon carbide semiconductor device according to the embodiment. The metal plate 30 is not a flat film and may have a protrusion 34 as shown in FIG. The stress at the time of joining can be further reduced. It is also possible to use the protrusion 34 as the external electrode pin 19 by making the protrusion 34 in FIG. 11 into a long rod shape. In this case, there is no need to bond the external electrode pins 19, so stress during bonding can be eliminated. Further, in FIG. 11, there is only one protrusion 34, but the protrusion 34 may be provided as many times as the external electrode pins 19 are connected to.

As described above, according to the silicon carbide semiconductor device according to the embodiment, the metal plate is provided on the source electrode pad via the first solder. Thereby, the stress applied to the second solder when fixing the external electrode pin can be dispersed and made uniform, and stress can be prevented from being locally concentrated in a specific region of the silicon carbide semiconductor device. Therefore, fluctuations in various characteristics due to high current density during high frequency operation can be significantly improved.

As described above, the present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part, impurity concentration, etc. are variously set according to required specifications. Furthermore, in each of the above embodiments, the case where silicon carbide is used as the wide bandgap semiconductor is explained as an example, but it is also applicable to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). It is. Furthermore, in each of the embodiments, the first conductivity type is n type and the second conductivity type is p type, but the present invention can be similarly applied even if the first conductivity type is p type and the second conductivity type is n type. It works.

As described above, the semiconductor device according to the present invention is useful as a power semiconductor device used in power converters such as inverters, power supplies for various industrial machines, igniters of automobiles, and the like.

1, 101 n ⁺ type silicon carbide substrate 2, 102 n type silicon carbide epitaxial layer 2a 1st n type silicon carbide epitaxial layer 2b 2nd n type silicon carbide epitaxial layer 3, 103 p type silicon carbide epitaxial layer 4, 104 1st p ⁺ type Base region 4a Lower first p ⁺ type base region 4b Upper first p ⁺ type base region 5, 105 Second p ⁺ type base region 6, 106 N type high concentration region 6a Lower n type high concentration region 6b Upper n type high concentration region 7 , 107 n ⁺ type source region 8, 108 p ⁺⁺ type contact region 9, 109 gate insulating film 10, 110 gate electrode 11, 111 interlayer insulating film 12 insulating film 13, 113 source electrode 14, 114 back electrode 15, 115 source Electrode pads 16, 116 Second plating film 17, 117 Second solder 18, 118 Trench 19, 119 External electrode pin 21, 121 First protective film 23, 123 Second protective film 25, 125 First TiN film 26, 126 First Ti Film 27, 127 Second TiN film 28, 128 Second Ti film 29, 129 Al alloy film 30 Metal plate 31 Third protective film 32 First solder 33 First plating film 34 Projection 40 Active region 41 Edge termination region 50, 150 Trench Type MOSFET

Claims (6)

a semiconductor substrate of a first conductivity type;
a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate;
a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate side;
a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer on the opposite side to the semiconductor substrate side;
a gate insulating film in contact with the second semiconductor layer;
a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor layer;
a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region;
a metal plate provided on the entire surface of the first electrode via a first solder;
a protective film selectively provided on the metal plate;
a pin-shaped electrode connected to the metal plate via a second solder;
a second electrode provided on the back surface of the semiconductor substrate;
Equipped with
A semiconductor device characterized in that the first semiconductor region is not provided in the second semiconductor layer facing an end of the metal plate . 2. The semiconductor device according to claim 1, wherein the metal plate is a copper film and has a thickness of 5 μm or more. 3. The semiconductor device according to claim 2, wherein the metal plate has a thickness of 20 μm or more and 5000 μm or less. 4. The semiconductor device according to claim 1, wherein the first solder has a higher melting point than the second solder. further comprising a trench penetrating the first semiconductor region and the second semiconductor layer and reaching the first semiconductor layer,
5. The semiconductor device according to claim 1, wherein the gate electrode is provided inside the trench with the gate insulating film interposed therebetween. 2. The semiconductor device according to claim 1, wherein a plating film is provided on the first electrode, and the metal plate is provided on the plating film via the first solder.

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