JP7318226B2 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.

Conventionally, silicon (Si) has been used as a constituent material of power semiconductor devices that control high voltages and large currents. There are multiple types of power semiconductor devices, including bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). It is

For example, bipolar transistors and IGBTs have higher current densities than MOSFETs and can handle large currents, but cannot be switched at high speed. Specifically, bipolar transistors are limited to use at a switching frequency of about several kHz, and IGBTs are limited to use at a switching frequency of about several tens of kHz. On the other hand, a power MOSFET has a lower current density than a bipolar transistor or an IGBT, making it difficult to increase the current, but it is capable of high-speed switching operation up to several MHz.

However, there is a strong demand in the market for power semiconductor devices that combine large current and high speed, and efforts have been made to improve IGBTs and power MOSFETs. . From the viewpoint of power semiconductor devices, semiconductor materials that can replace silicon are being investigated, and silicon carbide (SiC) is a semiconductor material that can be used to fabricate (manufacture) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics. is attracting attention.

Silicon carbide is a chemically very stable semiconductor material, has a wide bandgap of 3 eV, and can be extremely stably used as a semiconductor even at high temperatures. In addition, since silicon carbide has a maximum electric field strength that is one order of magnitude higher than that of silicon, silicon carbide is expected as a semiconductor material capable of sufficiently reducing the on-resistance. Such features of silicon carbide also apply to wide bandgap semiconductors such as gallium nitride (GaN), which have a wider bandgap than other types of silicon. Therefore, by using a wide bandgap semiconductor, it is possible to increase the breakdown voltage of the semiconductor device.

In such a high-voltage semiconductor device using silicon carbide, the switching loss that occurs during on-off operation is reduced, so when used in an inverter, the carrier frequency is one order of magnitude higher than that of conventional semiconductor devices using silicon. applied in When a semiconductor device is applied at a high frequency, the temperature of heat generated in the chip increases, which affects the reliability of the semiconductor device. In particular, a bonding wire is joined to the front surface electrode on the front surface side of the substrate as a wiring material for extracting the potential of the front surface electrode to the outside. If used in , the adhesion between the front electrode and the bonding wire will decrease, affecting reliability.

Since the silicon carbide semiconductor device may be used at a high temperature of 230° C. or more, pin-shaped external terminal electrodes may be soldered to the front surface electrodes instead of bonding wires. This can prevent the adhesion between the front electrode and the external terminal electrode from deteriorating.

FIG. 15 is a top view showing the structure of a conventional silicon carbide semiconductor device. As shown in FIG. 15, a semiconductor chip 150 is provided with an edge termination region 141 that surrounds the active region 140 and retains the breakdown voltage at the outer periphery of the active region 140 through which the main current flows. The active region 140 is provided with a gate electrode pad 122 electrically connected to the gate electrode through the gate polysilicon electrode 133 and a source electrode pad 115 electrically connected to the source electrode.

A first protective film 121 is provided on the source electrode pad 115, and an external terminal electrode (not shown) is provided on the plated film 116 in the first protective film 121 via solder (not shown). Similarly, the gate electrode pad 122 is also provided with a first protective film (not shown) and a plating film (not shown), and an external terminal electrode (not shown) is provided on the plating film via solder (not shown). be done.

FIG. 16 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device taken along line AA' in FIG. As shown in FIG. 16, a trench MOSFET 150 is shown as a conventional silicon carbide semiconductor device. In trench MOSFET 150 , n type silicon carbide epitaxial layer 102 is deposited on the front surface of n ⁺ type silicon carbide substrate 101 . An n-type high concentration region 106 is provided on the surface side of the n-type silicon carbide epitaxial layer 102 opposite to the n ⁺ -type silicon carbide substrate 101 side. A second p ⁺ -type base region 105 is selectively provided in the n-type high-concentration region 106 so as to cover the entire bottom surface of the trench 118 . A first p ⁺ -type base region 104 is selectively provided in the surface layer of the n-type high-concentration region 106 opposite to the n ⁺ -type silicon carbide substrate 101 side.

Further, the conventional trench MOSFET 150 further includes a p-type base layer 103, an n ⁺ -type source region 107, a p ^++- type contact region 108, a gate insulating film 109, a gate electrode 110, an interlayer insulating film 111, a source electrode 113, A back electrode 114, a source electrode pad 115 and a drain electrode pad (not shown) are provided.

The source electrode pad 115 is formed by laminating a first TiN film 125, a first Ti film 126, a second TiN film 127, a second Ti film 128 and an Al alloy film 129, for example. A plating film 116 , solder 117 , external terminal electrodes 119 , a first protective film 121 and a second protective film 123 are provided above the source electrode pad 115 .

In addition, the gate electrode pad portion is provided with a gate electrode pad 122 electrically connected to the gate electrode 110 while being insulated from the p ⁺⁺ -type contact region 108 by the interlayer insulating film 111 .

In the gate electrode pad portion, a region of the silicon carbide semiconductor substrate facing the gate electrode pad in the depth direction has a lower recombination rate of carriers than other regions, thereby reducing the threshold voltage Vth of the MOSFET and the built-in PN diode. A technique for suppressing fluctuations in the forward voltage Vf of the semiconductor device and maintaining the reliability of the semiconductor device is known (see, for example, Patent Document 1 below).

WO2018/135147

A vertical MOSFET having a conventional structure incorporates a built-in pn diode formed of a p-type base layer 103, an n-type heavily doped region 106, and an n-type silicon carbide epitaxial layer 102 as a body diode between a source and a drain. This built-in pn diode can be operated by applying a high potential to the source electrode 113, and the p ⁺⁺ -type contact region 108, the p-type base layer 103, the n-type heavily doped region 106, and the n-type silicon carbide epitaxial layer are separated from each other. A current flows in the direction toward n ⁺ -type silicon carbide substrate 101 via 102 .

Also in the gate electrode pad portion, a built-in diode composed of an n-type semiconductor substrate and a p-type semiconductor region is formed, functions as a diode, and conducts current. There is a problem that when the built-in diode is turned on and off, carriers are concentrated in the peripheral portion of the p-type semiconductor region of the gate electrode pad portion (for example, region S in FIG. 16), resulting in a decrease in cut-off current during switching.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method of manufacturing a semiconductor device that can prevent a reduction in cut-off current of a PN diode incorporated in the semiconductor device, in order to solve the above-described problems of the prior art.

In order to solve the above problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. A semiconductor device includes an active region through which a main current flows in an ON state and a gate electrode pad portion. The active region includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type provided on a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, and the first semiconductor layer. a second conductive type second semiconductor layer provided on the surface opposite to the semiconductor substrate side, and a surface layer of the second semiconductor layer on the opposite side to the semiconductor substrate side. a first semiconductor region of a first conductivity type provided in the second semiconductor layer; a gate insulating film in contact with the second semiconductor layer; a first electrode provided on the surface of the second semiconductor layer and the first semiconductor region; and a second electrode provided on the back surface of the semiconductor substrate. The gate electrode pad portion includes the semiconductor substrate, the first semiconductor layer, and a third semiconductor layer of a second conductivity type provided on a surface of the first semiconductor layer opposite to the semiconductor substrate. and a gate electrode pad electrically connected to the gate electrode, selectively provided via an interlayer insulating film on the surface of the third semiconductor layer opposite to the semiconductor substrate. The third semiconductor layer has a rectangular planar shape , and low lifetime regions are provided only at four corners of the third semiconductor layer .

Further, according to the semiconductor device of the present invention, in the above invention, helium is implanted into the low lifetime region.

Further, in the semiconductor device according to the present invention, in the above invention, the low lifetime region is provided at an interface in the depth direction between the third semiconductor layer and the first semiconductor layer. .

Further, in the semiconductor device according to the present invention, in the above-described invention, the semiconductor device includes a current detection region having the semiconductor substrate and the first semiconductor layer in common with the active region; a temperature detection region having one semiconductor layer in common with the active region; The second semiconductor layers of the current detection region and the temperature detection region are spaced apart from each other , and the second semiconductor layers of the current detection region and the temperature detection region have a planar shape. A lifetime area is provided.

Further, in the semiconductor device according to the present invention, in the above-described invention, the MOS structure further has a trench penetrating the first semiconductor region and the second semiconductor layer and reaching the first semiconductor layer; An electrode is provided inside the trench via the gate insulating film.

In order to solve the above problems and achieve the object of the present invention, a method of manufacturing a semiconductor device according to the present invention has the following features. In a method of manufacturing a semiconductor device having an active region having a MOS structure through which a main current flows when in an ON state and a gate electrode pad portion, first, on the front surface of a semiconductor substrate of a first conductivity type, impurities lower than those of the semiconductor substrate are formed. A first step of forming a first semiconductor layer of a first conductivity type with a high concentration is performed. Next, a second step of forming a second conductivity type second semiconductor layer on the surface of the first semiconductor layer opposite to the semiconductor substrate is performed. Next, a third step of selectively forming a first semiconductor region of the first conductivity type in the surface layer of the second semiconductor layer on the side opposite to the semiconductor substrate is performed. Next, a fourth step of selectively forming a first semiconductor region of the first conductivity type in the surface layer of the second semiconductor layer on the side opposite to the semiconductor substrate is performed. Next, a fifth step of forming low lifetime regions only at four corners of the second semiconductor layer of the gate electrode pad portion is performed. Next, a sixth step of forming a gate insulating film in contact with the second semiconductor layer is performed. Next, a seventh step of forming a gate electrode on the surface of the gate insulating film opposite to the surface in contact with the second semiconductor layer is performed. Next, an eighth step of forming a first electrode on the surfaces of the second semiconductor layer and the first semiconductor region is performed. Next, a ninth step of forming a second electrode on the back surface of the semiconductor substrate is performed. In the first step, the semiconductor substrate of the gate electrode pad portion and the first semiconductor layer of the gate electrode pad portion are formed in common with the semiconductor substrate of the active region and the first semiconductor layer of the active region. In the fourth step, the third semiconductor layer is formed into a rectangular planar shape.

According to the invention described above, the low lifetime regions are provided at the four corners of the p-type base layer (second conductivity type second semiconductor layer) of the gate electrode pad portion. As a result, concentration of carriers in the four corners of the p-type base layer can be suppressed, and the cut-off current can be increased.

According to the semiconductor device and the method for manufacturing a semiconductor device according to the present invention, it is possible to prevent a reduction in cut-off current of a PN diode built in the semiconductor device.

1 is a top view showing the structure of a silicon carbide semiconductor device according to a first embodiment; FIG. 2 is a cross-sectional view showing the structure of the silicon carbide semiconductor device along line A-A' in FIG. 1 of the first embodiment; FIG. FIG. 4 is a top view showing another structure of the silicon carbide semiconductor device according to the first embodiment; 5 is a graph showing relative values of breaking currents of the silicon carbide semiconductor device according to the first embodiment and a conventional silicon carbide semiconductor device; 1 is a cross-sectional view schematically showing a state in the middle of manufacturing a silicon carbide semiconductor device according to an embodiment (No. 1); FIG. FIG. 2 is a cross-sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 2); FIG. 3 is a cross-sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 3); FIG. 4 is a cross-sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 4); FIG. 5 is a cross-sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 5); FIG. 6 is a cross-sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 6); FIG. 10 is a top view showing the structure of a silicon carbide semiconductor device according to a second embodiment; FIG. 12 is a cross-sectional view showing the structure of the A-A' portion of FIG. 11 of the silicon carbide semiconductor device according to the second embodiment; 12 is a cross-sectional view showing the structure of the B-B' portion of FIG. 11 of the silicon carbide semiconductor device according to the second embodiment; FIG. FIG. 11 is a top view showing another structure of the silicon carbide semiconductor device according to the second embodiment; It is a top view which shows the structure of the conventional silicon carbide semiconductor device. 16 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device taken along line A-A' in FIG. 15; FIG.

Preferred embodiments of a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p mean that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached, respectively. When the notations of n and p including + and - are the same, it indicates that the concentrations are close, and the concentrations are not necessarily the same. In the following description of the embodiments and accompanying drawings, the same configurations are denoted by the same reference numerals, and overlapping descriptions are omitted. Also, in this specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after it, and adding "-" before the index indicates a negative index.

(Embodiment 1)
A semiconductor device according to the present invention is configured using a wide bandgap semiconductor. In the embodiments, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET as an example.

FIG. 1 is a top view showing the structure of the silicon carbide semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor chip 50 is provided with an edge termination region 41 that surrounds the active region 40 and retains the breakdown voltage at the outer periphery of the active region 40 through which the main current flows.

As shown in FIG. 1, a semiconductor chip 50 has a main semiconductor element 15a and a gate electrode pad portion 22a on the same semiconductor substrate made of silicon carbide. The main semiconductor element 15a is a vertical MOSFET in which a drift current flows in the vertical direction (the depth direction z of the semiconductor substrate) in the ON state, and is composed of a plurality of unit cells (functional units: not shown) arranged adjacently. and perform the main action.

The main semiconductor element 15a is provided in an effective region (region functioning as a MOS gate) 1a of the active region 40. As shown in FIG. The effective region 1 a of the active region 40 is a region through which the main current flows when the main semiconductor element 15 a is turned on, and is surrounded by the edge termination region 41 . In the effective region 1a of the active region 40, the source electrode pad 15 of the main semiconductor element 15a is provided on the front surface of the semiconductor substrate. The source electrode pad 15 has, for example, a rectangular planar shape, and covers substantially the entire effective region 1a of the active region 1, for example.

The edge termination region 41 is a region between the active region 40 and the side surface of the chip, and is a region for alleviating the electric field on the front surface side of the semiconductor substrate to maintain the breakdown voltage (withstand voltage). The edge termination region 41 is provided with, for example, a p-type region forming a guard ring or a junction termination extension (JTE) structure, a field plate, a breakdown voltage structure (not shown) such as RESURF. The withstand voltage is the limit voltage at which the element does not malfunction or break down.

A gate electrode pad 22 is provided in the gate electrode pad portion 22a. The gate electrode pad 22 has, for example, a substantially rectangular planar shape. Gate electrode pad 22 is provided on p-type base layer 3g described below (see FIG. 2). A first p + -type base region 4g having the same size as the p-type base layer 3g is provided on the entire lower surface of the p ^- type base layer 3g. The p-type base layer 3g and the first p ⁺ -type base region 4g of the gate electrode pad 22 have, for example, a substantially rectangular planar shape.

As shown in FIG. 1, low lifetime regions 60 are provided at the four corners of the first p ⁺ -type base region 4g, which are the four corners of the bottom of the gate electrode pad portion 22a. FIG. 1 shows the planar positional relationship among the low lifetime region 60, the p-type base layer 3g and the gate electrode pad 22, and the sectional positional relationship is shown in FIG. 2 below. The low lifetime region 60 is formed by, for example, helium (He) irradiation. The low lifetime region 60 can prevent carriers from concentrating on the four corners of the bottom of the first p ⁺ -type base region 4g. By switching with this structure, the breaking current can be increased.

Also, the low lifetime regions 60 are provided only at the four corners of the first p ⁺ -type base region 4g. Therefore, in the PN junction region where the low lifetime region 60 is not provided, the characteristics of the built-in diode do not change, and deterioration of the characteristics of the built-in diode is reduced.

Also, the low lifetime region 60 may have another shape as long as it covers the four corners of the first p ⁺ -type base region 4g. For example, it may be circular or L-shaped. Also, the low lifetime region 60 may have a shape covering the four sides of the gate electrode pad 22 . In this case, since RonA increases as the area of the low lifetime region 60 increases, it is preferable that the area of the low lifetime region 60 is as small as possible.

FIG. 2 is a cross-sectional view showing the structure of the silicon carbide semiconductor device along line A-A' in FIG. 1 according to the embodiment. FIG. 2 shows a cross-sectional structure along a cutting line AA' extending from a part of the effective region 1a of the active region 40 of FIG. 1 through the gate electrode pad portion 22a to another part of the effective region 1a. show.

As shown in FIG. 2, a semiconductor chip 50 of the silicon carbide semiconductor device according to the embodiment includes a first main surface (front surface) of an n ⁺ -type silicon carbide substrate (first conductivity type semiconductor substrate) 1, For example, an n-type silicon carbide epitaxial layer (first conductivity type first semiconductor layer) 2 is deposited on the (0001) plane (Si plane).

The n ⁺ -type silicon carbide substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). The n-type silicon carbide epitaxial layer 2 is a low-concentration n-type drift layer doped with, for example, nitrogen at an impurity concentration lower than that of the n ⁺ -type silicon carbide substrate 1 . An n-type high-concentration region 6 may be provided on the surface of the n-type silicon carbide epitaxial layer 2 opposite to the n ⁺ -type silicon carbide substrate 1 side. N-type high-concentration region 6 is a high-concentration n-type drift layer having an impurity concentration lower than n ⁺ -type silicon carbide substrate 1 and higher than n-type silicon carbide epitaxial layer 2 .

n-type high-concentration region 6 (n-type silicon carbide epitaxial layer 2 if n-type high-concentration region 6 is not provided, hereinafter abbreviated as (2)) opposite to n ⁺ -type silicon carbide substrate 1 side A p-type base layer (second conductivity type second semiconductor layer) 3 is provided on the surface side of the side. Hereinafter, the n ⁺ -type silicon carbide substrate 1, the n-type silicon carbide epitaxial layer 2, and the p-type base layer 3 are collectively referred to as a silicon carbide semiconductor substrate.

As shown in FIG. 2 , a back surface electrode 14 is provided on the second main surface of n ⁺ -type silicon carbide substrate 1 (the back surface, that is, the back surface of the silicon carbide semiconductor substrate). The back electrode 14 constitutes a drain electrode. A drain electrode pad (not shown) is provided on the surface of the back electrode 14 .

A striped trench structure is formed on the first main surface side (p-type base layer 3 side) of the silicon carbide semiconductor substrate. Specifically, trench 18 penetrates p-type base layer 3 from the surface of p-type base layer 3 opposite to n ⁺ -type silicon carbide substrate 1 (the first main surface side of the silicon carbide semiconductor substrate). and reaches the n-type high-concentration region 6(2). A gate insulating film 9 is formed on the bottom and sidewalls of the trench 18 along the inner wall of the trench 18 , and a striped gate electrode 10 is formed inside the gate insulating film 9 in the trench 18 . Gate electrode 10 is insulated from n-type high-concentration region 6 ( 2 ) and p-type base layer 3 by gate insulating film 9 . A part of the gate electrode 10 protrudes from above the trench 18 toward a source electrode pad 15, which will be described later.

A first p + -type base region 4 is selected for the surface layer ^of the n-type high-concentration region 6 (2) on the side opposite to the n ⁺ -type silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate). is provided A second p ⁺ -type base region 5 is formed under the trench 18 , and the width of the second p ⁺ -type base region 5 is wider than the width of the trench 18 . The first p ⁺ -type base region 4 and the second p ⁺ -type base region 5 are doped with aluminum, for example.

A structure in which a part of the first p ⁺ -type base region 4 is extended to the trench 18 side and connected to the second p ⁺ -type base region 5 may be employed. In this case, a part of the first p ⁺ -type base region 4 is oriented in a direction (hereinafter referred to as a first direction) orthogonal to x in which the first p ⁺ -type base region 2 and the second p ⁺ -type base region 5 are arranged. , and the second direction) y, the n-type high-concentration regions 6(2) may be alternately and repeatedly arranged in a planar layout. For example, a structure in which part of the first p ⁺ -type base region 4 extends to the trench 18 sides on both sides in the first direction x and is connected to part of the second p ⁺ -type base region 5 is periodically arranged in the second direction y. can be placed in The reason for this is that the holes generated when the avalanche breakdown occurs at the junction of the second p ⁺ -type base region 5 and the n-type silicon carbide epitaxial layer 2 are efficiently evacuated to the source electrode 13 , so that they are transferred to the gate insulating film 9 . This is for reducing the burden and increasing the reliability.

Inside the p-type base layer 3, an n ⁺ -type source region (first conductivity type first semiconductor region) 7 is selectively provided on the substrate first main surface side. A p ⁺⁺ type contact region 8 may also be provided. The n ⁺ -type source region 7 is in contact with the trench 18 . Also, the n ⁺ -type source region 7 and the p ⁺⁺ -type contact region 8 are in contact with each other.

Further, the n-type high-concentration region 6 (2) is a region sandwiched between the first p ⁺ -type base region 4 and the second p ⁺ -type base region 5 of the surface layer of the n-type silicon carbide epitaxial layer 2 on the substrate first main surface side. and the region sandwiched between the p-type base layer 3 and the second p ⁺ -type base region 5 .

Interlayer insulating film 11 is provided all over the first main surface side of the silicon carbide semiconductor substrate so as to cover gate electrode 10 embedded in trench 18 . Source electrode 13 is in contact with n ⁺ -type source region 7 and p-type base layer 3 through a contact hole opened in interlayer insulating film 11 when p ^{++ -type} contact region 8 is not provided. If the p ⁺⁺ -type contact region 8 is provided, it contacts the n ⁺ -type source region 7 and the p ⁺⁺ -type contact region 8 . The source electrode 13 is made of, for example, a NiSi film. A contact hole opened in the interlayer insulating film 11 has a stripe shape corresponding to the shape of the gate electrode 10 . Source electrode 13 is electrically insulated from gate electrode 10 by interlayer insulating film 11 . A source electrode pad 15 is provided on the source electrode 13 . The source electrode pad 15 is formed by laminating a first TiN film 25, a first Ti film 26, a second TiN film 27, a second Ti film 28 and an Al alloy film 29, for example. A barrier metal (not shown) may be provided between the source electrode 13 and the interlayer insulating film 11 to prevent diffusion of metal atoms from the source electrode 13 to the gate electrode 10 side, for example.

A plated film 16 is selectively provided on the upper portion of the source electrode pad 15 , and solder 17 is selectively provided on the surface side of the plated film 16 . The solder 17 is provided with an external terminal electrode 19 which is a wiring material for extracting the potential of the source electrode 13 to the outside. The external terminal electrode 19 has a needle-like pin shape and is joined to the source electrode pad 15 in an upright state.

A portion of the surface of the source electrode pad 15 other than the plated film 16 is covered with a first protective film 21 . Specifically, first protective film 21 is provided to cover source electrode pad 15 , and external terminal electrode 19 is joined to the opening of first protective film 21 via plating film 16 and solder 17 . there is A boundary between the plated film 16 and the first protective film 21 is covered with a second protective film 23 . The first protective film 21 and the second protective film 23 are polyimide films, for example.

Further, as shown in FIG. 2, the gate electrode pad portion 22a of the silicon carbide semiconductor device of the silicon carbide semiconductor device according to the embodiment is formed in the first electrode pad portion 22a of the n ⁺ -type silicon carbide substrate (first conductivity type semiconductor substrate) 1. An n-type silicon carbide epitaxial layer 2 is deposited on a main surface (front surface), for example, the (0001) plane (Si surface), and a p-type base layer 3g is provided on the surface layer of the n-type silicon carbide epitaxial layer 2. there is A p ⁺⁺ -type contact region 8 may also be provided. The p ⁺⁺ type contact region 8 is provided on the first main surface side of the substrate. A first p + -type base region 4g having the same size as the p-type base layer 3g is provided on the entire lower surface of the p ^- type base layer 3g. That is, the depth of the p-type region of the gate electrode pad portion 22a is the same as that of the first p ⁺ -type base region 4 of the main semiconductor element 15a. In this configuration, the first p ⁺ -type base region 4g and the p-type base layer 3g of the gate electrode pad portion 22a can be formed simultaneously with the main semiconductor element 15a, thereby simplifying the manufacturing process. However, it is not limited to this configuration. For example, a p-type region having a uniform concentration may be formed in a combined region of the first p ⁺ -type base region 4g and the p-type base layer 3g. Further, the depth of the p-type region of the gate electrode pad portion 22a may be made shallower than the first p ⁺ -type base region 4 of the main semiconductor element 15a. As a result, the resistance value of the built-in diode increases, so that the diode current in the gate electrode pad portion 22a can be further reduced. In order to make the depth of the p-type region of the gate electrode pad portion 22a shallower than that of the main semiconductor element 15a, for example, the first p ⁺ -type base region 4g should not be formed in the gate electrode pad portion 22a.

An interlayer insulating film 11 is provided on the p ^++- type contact region 8 (the p ^- type base layer 3 when the p++-type contact region 8 is not provided, hereinafter abbreviated as (3)). A source electrode pad 15 and a gate electrode pad 22 are provided apart from each other on insulating film 11 . The source electrode pad 15 is electrically connected to the p ⁺⁺ -type contact region 8 (3) through the opening of the interlayer insulating film 11 . Gate electrode pad 22 is electrically connected to gate electrode 10 .

At four corners of the bottom of the first p ⁺ -type base region 4g, a low level is formed near the interface between the first p ⁺ -type base region 4g and the n-type silicon carbide epitaxial layer 2 in the depth direction (direction from the source electrode 13 to the drain electrode 14). A lifetime region 60 is provided. Also, the low lifetime region 60 preferably does not reach the p ⁺⁺ type contact region 8(3). When first p ⁺ -type base region 4g is not formed and the bottom of p-type base layer 3g is in contact with n-type silicon carbide epitaxial layer 2, low lifetime regions 60 are provided at the four corners of p-type base layer 3g. .

FIG. 3 is a top view showing another structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3 shows the positional relationship on the plane of the low lifetime region 60, the p-type base layer 3g and the gate electrode pad 22, and the positional relationship on the cross section is the same as in FIG. As shown in FIG. 3, gate resistor 34 is provided between gate electrode pad 22 and gate polysilicon electrode 33 . When the silicon carbide semiconductor elements are connected in parallel and used without connecting an external chip resistor, the gate resistor 34 enables uniform operation of the elements even if there are variations in characteristics among the silicon carbide semiconductor elements. can.

FIG. 4 is a graph showing relative values of breaking currents of the silicon carbide semiconductor device according to the first embodiment and a conventional silicon carbide semiconductor device. In FIG. 4, the vertical axis indicates the relative value of the breaking current, and as shown in FIG. 4, the silicon carbide semiconductor device according to the first embodiment has a higher breaking current than the conventional silicon carbide semiconductor device. I know there is.

(Method for Manufacturing Silicon Carbide Semiconductor Device According to First Embodiment)
Next, a method for manufacturing the silicon carbide semiconductor device according to the first embodiment will be described. 5 to 10 are cross-sectional views schematically showing states in the process of manufacturing the silicon carbide semiconductor device according to the first embodiment.

First, an n ⁺ -type silicon carbide substrate 1 made of n-type silicon carbide is prepared. Then, on the first main surface of this n ⁺ -type silicon carbide substrate 1, a first n-type silicon carbide epitaxial layer 2a made of silicon carbide while being doped with n-type impurities such as nitrogen atoms is formed to a thickness of, for example, about 30 μm. epitaxially grown up to This first n-type silicon carbide epitaxial layer 2 a becomes n-type silicon carbide epitaxial layer 2 . The state up to this point is shown in FIG.

Next, on the surface of first n-type silicon carbide epitaxial layer 2a, an ion implantation mask having a predetermined opening is formed of, for example, an oxide film by photolithography. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film to form a lower first p ⁺ -type base region 4a having a depth of about 0.5 μm. A second p ⁺ -type base region 5 that forms the bottom of the trench 18 may be formed at the same time as the lower first p ⁺ -type base region 4a. The adjacent lower first p ⁺ -type base region 4a and the second p ⁺ -type base region 5 are formed so that the distance therebetween is about 1.5 μm. The impurity concentration of the lower first p ⁺ -type base region 4a and the second p ⁺ -type base region 5 is set to about 5×10 ¹⁸ /cm ³ , for example.

Next, a portion of the ion implantation mask is removed, and an n-type impurity such as nitrogen is ion-implanted into the opening to implant a portion of the surface region of the first n-type silicon carbide epitaxial layer 2a to a depth of, for example, 0.5 mm. A lower n-type high concentration region 6a having a thickness of about 5 μm is provided. The impurity concentration of the lower n-type high concentration region 6a is set to about 1×10 ¹⁷ /cm ³ , for example. The state up to this point is shown in FIG.

Next, a second n-type silicon carbide epitaxial layer 2b doped with an n-type impurity such as nitrogen is formed on the surface of first n-type silicon carbide epitaxial layer 2a to a thickness of about 0.5 μm. The impurity concentration of second n-type silicon carbide epitaxial layer 2b is set to about 3×10 ¹⁵ /cm ³ . Thereafter, the n-type silicon carbide epitaxial layer 2 is formed by combining the first n-type silicon carbide epitaxial layer 2a and the second n-type silicon carbide epitaxial layer 2b.

Next, on the surface of second n-type silicon carbide epitaxial layer 2b, an ion implantation mask having a predetermined opening is formed of, for example, an oxide film by photolithography. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film to form an upper first p ⁺ -type base region 4b having a depth of about 0.5 μm so as to overlap the lower first p ⁺ -type base region 4a. do. The lower first p ⁺ -type base region 4 a and the upper first p ⁺ -type base region 4 b form a continuous region to become the first p ⁺ -type base region 4 . The impurity concentration of the upper first p ⁺ -type base region 4b is set to about 5×10 ¹⁸ /cm ³ , for example.

Next, a portion of the ion implantation mask is removed, and an n-type impurity such as nitrogen is ion-implanted into the opening to implant a portion of the surface region of the second silicon carbide epitaxial layer 2b to a depth of, for example, 0.5 μm. An upper n-type high-concentration region 6b is provided. The impurity concentration of the upper n-type high concentration region 6b is set to about 1×10 ¹⁷ /cm ³ , for example. The upper n-type high concentration region 6b and the lower n-type high concentration region 6a are formed so as to be in contact with each other at least partially to form the n-type high concentration region 6. As shown in FIG. However, this n-type high-concentration region 6 may or may not be formed over the entire surface of the substrate. The state up to this point is shown in FIG.

Next, a p-type base layer 3 doped with a p-type impurity such as aluminum is formed on the surface of the n-type silicon carbide epitaxial layer 2 to a thickness of about 1.3 μm. The impurity concentration of p-type base layer 3 is set to about 4×10 ¹⁷ /cm ³ .

Next, on the surface of the p-type base layer 3, an ion implantation mask having a predetermined opening is formed of, for example, an oxide film by photolithography. An n-type impurity such as phosphorus (P) is ion-implanted into this opening to form an n ⁺ -type source region 7 in a portion of the surface of the p-type base layer 3 . The impurity concentration of the n ⁺ -type source region 7 is set higher than that of the p-type base layer 3 . Next, the ion implantation mask used for forming the n ⁺ -type source region 7 is removed, and an ion implantation mask having a predetermined opening is formed by the same method. A p ⁺⁺ type contact region 8 may be formed by ion-implanting a p-type impurity such as aluminum into the region. The impurity concentration of the p ⁺⁺ -type contact region 8 is set higher than that of the p-type base layer 3 . The state up to this point is shown in FIG.

Through the steps up to this point, n-type silicon carbide epitaxial layer 2 is deposited on gate electrode pad portion 22 a , and p-type base layer 3 and p ⁺⁺ -type contact region 8 are formed inside n-type silicon carbide epitaxial layer 2 .

Next, heat treatment (annealing) is performed in an inert gas atmosphere at about 1700° C. to form the first p ⁺ -type base region 4 , the second p ⁺ -type base region 5 , the n ⁺ -type source region 7 and the p ⁺⁺ -type contact region 8 . Perform activation processing. As described above, the ion-implanted regions may be activated collectively by one heat treatment, or may be activated by heat treatment each time ion implantation is performed.

Next, on the surface of the p-type base layer 3, a trench forming mask having a predetermined opening is formed of, for example, an oxide film by photolithography. Next, dry etching is performed to form a trench 18 that penetrates the p-type base layer 3 and reaches the n-type high concentration region 6 (2). The bottom of the trench 18 may reach the second p ⁺ -type base region 5 formed in the n-type heavily doped region 6(2). Next, the trench formation mask is removed. The state up to this point is shown in FIG.

Next, gate insulating film 9 is formed along the surface of n ⁺ -type source region 7 and along the bottom and side walls of trench 18 . This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1000° C. in an oxygen atmosphere. Also, the gate insulating film 9 may be formed by a method of depositing by a chemical reaction such as high temperature oxide (HTO).

Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9 . This polycrystalline silicon layer may be formed so as to fill the trench 18 . The gate electrode 10 is formed by patterning this polycrystalline silicon layer by photolithography and leaving it inside the trench 18 .

Next, an interlayer insulating film 11 is formed by depositing, for example, phosphorous glass to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10 . Next, a barrier metal (not shown) made of titanium (Ti) or titanium nitride (TiN) may be formed to cover the interlayer insulating film 11 . Interlayer insulating film 11 and gate insulating film 9 are patterned by photolithography to form contact holes exposing n ⁺ -type source region 7 and p ⁺⁺ -type contact region 8 . Thereafter, heat treatment (reflow) is performed to planarize the interlayer insulating film 11 . The state up to this point is shown in FIG.

Interlayer insulating film 11 is selectively removed to form a film of nickel (Ni) or Ti on the surface of the silicon carbide semiconductor substrate. Next, a film of Ni or Ti is formed on the back side of the n ⁺ -type silicon carbide substrate 1 while protecting the surface. Next, heat treatment is performed at about 1000° C. to form ohmic conductivity on the surface side of the silicon carbide semiconductor substrate and the surface side of the back surface of n ⁺ -type silicon carbide substrate 1 .

Next, a conductive film to be the source electrode 13 is provided on the interlayer insulating film 11 so as to be in contact with the ohmic electrode portion formed in the contact hole. This conductive film is selectively removed to leave the source electrode 13 only in the contact hole, and the n ⁺ -type source region 7 and the p ⁺⁺ -type contact region 8 are brought into contact with the source electrode 13 . Next, the source electrode 13 other than the contact holes is selectively removed.

Next, an electrode pad that will become source electrode pad 15 is deposited on source electrode 13 on the front surface of the silicon carbide semiconductor substrate and in the opening of interlayer insulating film 11 by, for example, a sputtering method. For example, a first TiN film 25, a first Ti film 26, a second TiN film 27, and a second Ti film 28 are laminated by sputtering, and an Al alloy film 29 is formed to a thickness of about 5 μm, for example. The Al alloy film 29 may be an Al film. The Al alloy film 29 is, for example, an Al--Si film or an Al--Si--Cu film. A source electrode pad 15 is formed by patterning this conductive film by photolithography and leaving it in the active region 40 of the entire device. The thickness of the portion of the electrode pad on the interlayer insulating film 11 may be, for example, 5 μm. The electrode pads may be made of, for example, aluminum containing 1% silicon (Al--Si). Next, the source electrode pads 15 are selectively removed.

Next, at the interface between the n-type silicon carbide epitaxial layer 2 of the gate electrode pad portion 22a and the first p ⁺ -type base region 4g, a lifetime killer is implanted in the vicinity of the four corner regions of the first p ⁺ -type base region 4g, A low lifetime region 60 is formed. For example, an oxide film mask for ion implantation is formed by photolithography and etching, and low lifetime region 60 is formed by ion-implanting helium from the back side of the silicon carbide semiconductor substrate. It is preferable to form the low lifetime region 60 before forming the drain electrode 14 . Also, the lifetime killer may be implanted from the front surface side of the silicon carbide semiconductor substrate. Also, the lifetime killer may be, for example, proton.

Next, films of titanium (Ti), nickel (Ni) and gold (Au), for example, are formed in this order on the surface of the drain electrode 14 as a drain electrode pad.

Next, a polyimide film is formed to cover the source electrode pad 15 . Next, the polyimide film is selectively removed by photolithography and etching to form the first protective films 21 covering the source electrode pads 15, and the first protective films 21 are opened.

Next, the plated film 16 is selectively formed on the source electrode pad 15, and the second protective film 23 covering each boundary between the plated film 16 and the first protective film 21 is formed. Next, external terminal electrodes 19 are formed on the plated film 16 with solder 17 interposed therebetween.

As described above, according to the silicon carbide semiconductor device of the first embodiment, the low lifetime regions are provided at the four corners of the p-type base layer of the gate electrode pad portion. As a result, concentration of carriers in the four corners of the p-type base layer can be suppressed, and the cut-off current can be increased.

(Embodiment 2)
FIG. 11 is a top view showing the structure of the silicon carbide semiconductor device according to the second embodiment. The silicon carbide semiconductor device according to the second embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that highly functional region 3 a is provided in active region 40 adjacent to edge termination region 41 . be. The highly functional region 3a has, for example, a substantially rectangular planar shape. The high-performance area 3a is provided with high-performance sections such as a current sensing section 37a, a temperature sensing section 35a, an overvoltage protection section (not shown), and an arithmetic circuit section (not shown). In FIG. 11, the current sensing section 37a and the temperature sensing section 35a are illustrated as the high-performance section. good.

The current sensing section 37a has a function of detecting an overcurrent (OC: Over Current) flowing through the main semiconductor element 15a. The current sensing portion 37a is a vertical MOSFET including several unit cells having the same configuration as the main semiconductor element 15a. The temperature sensing section 35a has a function of detecting the temperature of the main semiconductor element 15a using the temperature characteristics of the diode. The overvoltage protector is a diode that protects the main semiconductor element 15a from overvoltage (OV: Over Voltage) such as surge.

In the highly functional region 3 a , current sensing electrodes are formed on the front surface of the semiconductor substrate along the boundary between the active region 40 and the edge termination region 41 and apart from the source electrode pad 15 and the edge termination region 41 . The OC pad 37 of the portion 37a, the anode electrode pad 35 and the cathode electrode pad 36 of the temperature sensing portion 35a, and the gate electrode pad 22 of the gate electrode pad portion 22a are provided. These electrode pads have, for example, a substantially rectangular planar shape. Also, these electrode pads may be provided apart from each other.

Although not shown in FIG. 11, the highly functional portions such as the current sensing portion 37a and the temperature sensing portion 35a also have the same semiconductor substrate structure as the gate electrode pad portion 22a (see FIG. 13). . For this reason, low lifetime regions 60 are provided at the four corners of the p-type base layer 3 of the highly functional portion, similarly to the gate electrode pad portion 22a (see FIG. 13). The low lifetime region 60 can prevent carriers from concentrating on the four corners of the p-type base layer 3 . By switching with this structure, the breaking current can be increased.

12 is a cross-sectional view showing the structure of the silicon carbide semiconductor device along line A-A' in FIG. 11 according to the second embodiment. Since the structure of the active region 40 is the same as that of the first embodiment, description thereof is omitted. Further, since the structure of the current sensing portion 37a is similar to that of the active region 40, the description thereof will be omitted.

As shown in FIG. 12, the temperature sensing portion 35a of the silicon carbide semiconductor device according to the second embodiment has a first main surface (front surface) of an n ⁺ -type silicon carbide substrate (first conductivity type semiconductor substrate) 1. ), for example, the (0001) plane (Si plane), the n-type silicon carbide epitaxial layer 2 is deposited on the substrate first main surface side of the n-type silicon carbide epitaxial layer 2 to form a second p ⁺ -type base region 5 and a p-type base layer. 3 is provided. Inside the p-type base layer 3, a p ⁺⁺ -type contact region 8 may be provided on the substrate first main surface side.

A field insulating film 80 is provided on the p ⁺⁺ -type contact region 8 ( 3 ), and a p-type polysilicon layer 81 and an n-type polysilicon layer 82 are provided on the field insulating film 80 . The p-type polysilicon layer 81 and the n-type polysilicon layer 82 are polysilicon diodes formed by pn junctions. Instead of p-type polysilicon layer 81 and n-type polysilicon layer 82, a diffusion diode formed by a pn junction between a p-type diffusion region and an n-type diffusion region may be used as temperature sensing portion 35a. In this case, for example, inside an n-type isolation region (not shown) selectively formed inside the second p ⁺ -type base region 5, a p-type diffusion region and an n-type diffusion region forming a diffusion diode are selectively formed. should be formed to

Anode electrode pad 35 is electrically connected to p-type polysilicon layer 81 through anode electrode 84 . Cathode electrode pad 36 is electrically connected to n-type polysilicon layer 82 via cathode electrode 85 . An external terminal electrode 19 is joined to the anode electrode pad 35 and the cathode electrode pad 36 via the plating film 16 and the solder 17, respectively, similarly to the source electrode pad 22 of the main semiconductor element 15a. 2 is protected by a protective film 23 .

As shown in FIG. 12 , a back surface electrode 14 is provided on the second main surface of n ⁺ -type silicon carbide substrate 1 (the back surface, that is, the back surface of the silicon carbide semiconductor substrate). The back electrode 14 constitutes a drain electrode. A drain electrode pad (not shown) is provided on the surface of the back electrode 14 .

FIG. 13 is a cross-sectional view showing the structure of the silicon carbide semiconductor device taken along line BB′ of FIG. 11 according to the second embodiment. In FIG. 13, the structure above (in the positive direction of the z-axis) above the p ⁺⁺ -type contact region 8(3) is omitted. As shown in FIG. 13, p-type base layer 3 is provided in n-type silicon carbide epitaxial layer 2 in gate electrode pad portion 22a, temperature sensing portion 35a and current sensing portion 37a. The p-type base layer 3 of the gate electrode pad portion 22a, the temperature sensing portion 35a, and the current sensing portion 37a is shared with the p-type base layer 3 of the main semiconductor element 15a. An active region 37 b is provided between p-type base layers 3 .

As shown in FIG. 13, the p-type base layer 3 of the gate electrode pad portion 22a, the temperature sensing portion 35a and the current sensing portion 37a may be separated from the p-type base layer 3 of the main semiconductor element 15a by a predetermined distance. By doing so, the built-in diode composed of the p-type base layer 3 and the n-type silicon carbide epitaxial layer 2 of the gate electrode pad portion 22a, the temperature sensing portion 35a and the current sensing portion 37a does not operate. This is to prevent minority carriers from entering the current sensing section 37 when the current sensing section 37 is present in the portion.

Also, the p-type base layers 3 of the temperature sensing portion 35a and the current sensing portion 37a may be connected. When minority carriers of a built-in diode formed by adjacent p-type and n-type regions enter into the active region 37b of the current sensing portion, the substantial current density at the time of switching increases and the semiconductor device is damaged. This is because they are easily destroyed.

As shown in FIG. 13, in the current sensing portion 37a, the temperature sensing portion 35a and the gate electrode pad portion 22a included in the highly functional region 3a, there is a low life in the vicinity of the interface between the p-type base layer 3 and the n-type silicon carbide epitaxial layer 2. A time field 60 is provided. Also, the low lifetime region 60 preferably does not reach the p ⁺⁺ -type contact region 8 .

FIG. 14 is a top view showing another structure of the silicon carbide semiconductor device according to the second embodiment. As shown in FIG. 14, gate resistor 34 is provided between gate electrode pad 22 and gate polysilicon electrode 33 . Also in the structure shown in FIG. 14, similarly to FIG. A lifetime region 60 is provided.

(Method for Manufacturing Silicon Carbide Semiconductor Device According to Second Embodiment)
In the second embodiment, the manufacturing method of the active region 40 is the same as that of the first embodiment, so the description is omitted. Further, since the manufacturing method of the current sensing portion 37a is the same as the manufacturing method of the active region 40, the description thereof will be omitted.

The temperature sensing portion 35a is formed as follows. Prior to forming the electrode pads, a p-type polysilicon layer 81, an n-type polysilicon layer 82, an interlayer insulating layer 83, an anode electrode 84 and a cathode electrode 85 are formed on the field insulating film 80 in the temperature sensing portion 35a by a general method. to form

Further, the p-type polysilicon layer 81 and the n-type polysilicon layer 82 of the temperature sensing section 35a may be formed at the same time as the main semiconductor element 15a and the gate electrode 10 of the current sensing section 37a, for example. The field insulating film 80 may be part of the interlayer insulating film 11 of the main semiconductor element 15a and the current sensing portion 37a. In this case, the p-type polysilicon layer 81 and the n-type polysilicon layer 82 of the temperature sensing portion 35a are formed after forming the interlayer insulating film 10 of the main semiconductor element 15a and the current sensing portion 37a.

Next, an anode electrode pad 35 and a cathode electrode pad 36 are formed in contact with the anode electrode 84 and the cathode electrode 85, respectively. The anode electrode pad 35 and the cathode electrode pad 36 may be formed together with the source electrode pad 15 to have the same laminated structure as the source electrode pad 15 .

Next, a polyimide film is formed to cover the anode electrode pad 35 and the cathode electrode pad 36 . Next, the polyimide film is selectively removed by photolithography and etching to form the first protective film 21 covering the anode electrode pad 35 and the cathode electrode pad 36, respectively, and the first protective film 21 is opened. .

Next, the plated film 16 is selectively formed on the anode electrode pad 35 and the cathode electrode pad 36 to form the second protective film 23 covering each boundary between the plated film 16 and the first protective film 21 . Next, external terminal electrodes 19 are formed on the plated film 16 with solder 17 interposed therebetween. As described above, the temperature sensing portion 35a is formed.

As described above, according to the silicon carbide semiconductor device according to the second embodiment, the low lifetime regions are provided at the four corners of the p-type base layer of the gate electrode pad portion, the temperature sensing portion, and the current sensing portion. It is As a result, concentration of carriers in the four corners of the p-type base layer can be suppressed, and the cut-off current can be increased.

In the above description of the present invention, the main surface of the silicon carbide substrate made of silicon carbide is the (0001) plane, and the MOS is formed on the (0001) plane. Various changes can be made to the semiconductor, the plane orientation of the main surface of the substrate, and the like.

Further, in the embodiments of the present invention, a trench type MOSFET has been described as an example, but the present invention is not limited to this, and can be applied to semiconductor devices of various configurations such as planar type MOSFETs and MOS type semiconductor devices such as IGBTs. Further, in each of the above-described embodiments, the case of using silicon carbide as a wide bandgap semiconductor has been described as an example. effect is obtained. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. It holds.

INDUSTRIAL APPLICABILITY As described above, the semiconductor device and the method for manufacturing a semiconductor device according to the present invention are useful for high-voltage semiconductor devices used in power converters, power supply devices for various industrial machines, and the like.

Reference Signs List 1, 101 n ⁺ -type silicon carbide substrate 1a effective region 2, 102 n-type silicon carbide epitaxial layer 2a first n-type silicon carbide epitaxial layer 2b second n-type silicon carbide epitaxial layer 3, 3g, 103 p-type base layer 3a highly functional region 4, 4g, 104 first p ⁺ -type base region 4a lower first p ⁺ -type base region 4b upper first p ⁺ -type base region 5, 105 second p ⁺ -type base region 6, 106 n-type high concentration region 6a lower n-type high concentration Region 6b Upper n-type high-concentration region 7, 107 n ⁺ -type source region 8, 108 p ⁺⁺ -type contact region 9, 109 Gate insulating films 10, 110 Gate electrodes 11, 111 Interlayer insulating films 12, 112 Insulating films 13, 113 Source electrodes 14, 114 Rear electrodes 15, 115 Source electrode pads 15a Main semiconductor elements 16, 116 Plated films 17, 117 Solders 18, 118 Trench 19, 119 External terminal electrodes 21, 121 First protective films 22, 122 Gate electrode pads 22a Gate electrode pad portions 23, 123 Second protective films 25, 125 First TiN films 26, 126 First Ti films 27, 127 Second TiN films 28, 128 Second Ti films 29, 129 Al alloy films 33, 133 Gate polysilicon electrode 34 Gate resistor 35 anode electrode pad 35a temperature sensing portion 36 cathode electrode pad 37 OC pad 37a current sensing portion 37b current sensing portion active regions 40, 140 active regions 41, 141 edge termination regions 50, 150 semiconductor chip 60 low lifetime region 80 field Insulating film 81 p-type polysilicon layer 82 n-type polysilicon layer 84 anode electrode 85 cathode electrode

Claims (6)

a first conductivity type semiconductor substrate;
a first semiconductor layer of a first conductivity type provided on the front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate;
a second conductivity type second semiconductor layer provided on the surface of the first semiconductor layer opposite to the semiconductor substrate;
a first conductivity type first semiconductor region selectively provided in a surface layer of the second semiconductor layer opposite to the semiconductor substrate;
a gate insulating film in contact with the second semiconductor layer;
a gate electrode provided on the surface of the gate insulating film opposite to the surface in contact with the second semiconductor layer;
a first electrode provided on the surface of the second semiconductor layer and the first semiconductor region;
a second electrode provided on the back surface of the semiconductor substrate;
and an active region through which a main current flows in an ON state, a gate electrode pad portion,
with
The gate electrode pad portion is
the semiconductor substrate;
the first semiconductor layer;
a third semiconductor layer of a second conductivity type provided on a surface of the first semiconductor layer opposite to the semiconductor substrate;
a gate electrode pad electrically connected to the gate electrode selectively provided via an interlayer insulating film on the surface of the third semiconductor layer opposite to the semiconductor substrate;
The semiconductor device according to claim 1 , wherein the third semiconductor layer has a rectangular planar shape , and the low lifetime regions are provided only at four corners of the third semiconductor layer . 2. The semiconductor device according to claim 1, wherein helium is implanted into said low lifetime region. 3. The semiconductor device according to claim 1, wherein the low lifetime region is provided at an interface in a depth direction between the third semiconductor layer and the first semiconductor layer. a current detection region having the MOS structure and having the semiconductor substrate and the first semiconductor layer in common with the active region;
a temperature detection region in which the semiconductor substrate and the first semiconductor layer are shared with the active region;
further comprising
In the current detection region and the temperature detection region, the second semiconductor layer is arranged at a predetermined distance from the second semiconductor layer in the active region,
The second semiconductor layer in the current detection region and the temperature detection region has a planar shape, and low lifetime regions are provided at four corners of the second semiconductor layer in the current detection region and the temperature detection region. 4. The semiconductor device according to any one of claims 1 to 3, characterized in that: the MOS structure further having a trench penetrating through the first semiconductor region and the second semiconductor layer and reaching the first semiconductor layer;
5. The semiconductor device according to claim 1, wherein said gate electrode is provided inside said trench via said gate insulating film. In a method for manufacturing a semiconductor device having an active region having a MOS structure through which a main current flows in an ON state and a gate electrode pad portion,
a first step of forming, on a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate;
a second step of forming a second conductivity type second semiconductor layer on the surface of the first semiconductor layer opposite to the semiconductor substrate;
a third step of selectively forming a first semiconductor region of a first conductivity type in a surface layer of the second semiconductor layer on the side opposite to the semiconductor substrate;
a fourth step of forming a third semiconductor layer of a second conductivity type provided on the surface of the first semiconductor layer opposite to the semiconductor substrate;
a fifth step of forming low lifetime regions only at four corners of the third semiconductor layer;
a sixth step of forming a gate insulating film in contact with the second semiconductor layer;
a seventh step of forming a gate electrode on the surface of the gate insulating film opposite to the surface in contact with the second semiconductor layer;
an eighth step of forming a first electrode on the surface of the second semiconductor layer and the first semiconductor region;
and a ninth step of forming a second electrode on the back surface of the semiconductor substrate,
In the first step, the semiconductor substrate of the gate electrode pad portion and the first semiconductor layer of the gate electrode pad portion are formed in common with the semiconductor substrate of the active region and the first semiconductor layer of the active region;
A method of manufacturing a semiconductor device, wherein in the fourth step, the third semiconductor layer is formed into a rectangular planar shape.

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