JP2015222743A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has high short-circuit resistance when the semiconductor device operates in a short-cut condition and which can achieve fast switching and high productivity.SOLUTION: A semiconductor device according to the present embodiment comprises a heat transfer member 3 bonded on a source electrode 6 via a bonding material 4. A region where the heat transfer member 3 is provided is defined as an element central region 1 and a region around the element central region 1 as an element peripheral region 2, a channel region 17 of a base layer 18 in the element peripheral region 2 is larger than the channel region 17 of the base layer 18 in the element central region 1.

Description

  The present invention relates to a semiconductor device, and more particularly to a technique for preventing element destruction due to overcurrent during a short circuit.

  The power switching element may operate in a short-circuit state due to a short-circuit accident or the like, that is, in a state where a load (inductance or the like) is not connected. When the semiconductor element is turned on in this state, a large overcurrent flows through the switching element. If this overcurrent continues to flow, the temperature of the device itself rises rapidly and the device is destroyed. The time from the start of the overcurrent flow to the breakdown is called short-circuit withstand capability and is one of the important indicators of the switching element.

  The switching element of Patent Document 1 is provided with a heat conducting member on the upper electrode, and when an overcurrent flows due to operation in a short circuit state, in the region on the back side of the heat conducting member in the semiconductor element, The heat generated by flowing flows diffuses through the heat conducting member. However, in a region other than the back surface side of the heat conducting member in the semiconductor element, it is difficult to diffuse the heat generated by the current flowing through the heat conducting member. Therefore, when the semiconductor element of Patent Document 1 operates in a short-circuited state, the region other than the back surface side of the heat conducting member becomes high temperature, and the short-circuit tolerance of the entire semiconductor device is reduced.

  In Patent Document 2, a heat conduction member is provided on the upper electrode of the semiconductor element, and in the element peripheral region other than the back surface side of the heat conduction member, the P-type impurity concentration is made higher than the element center region on the back surface side of the heat conduction member. By increasing the threshold voltage or by narrowing the trench width to increase the gate resistance, the on-state time is shortened. When this semiconductor element operates in a short-circuited state, the time for which the element peripheral region is turned on is shorter than that in the element central region, thereby reducing the energy density applied to the element peripheral region away from the heat conducting member. It becomes smaller than the region, and it is possible to suppress the temperature rise in the peripheral region of the element and suppress the decrease in the short-circuit resistance.

JP-A-2005-116702 JP 2013-115223 A

  When the semiconductor element of Patent Document 2 operates in a short-circuited state, the time in which the element peripheral region is turned on is shorter than that in the element central region, suppresses a temperature rise in the element peripheral region, and suppresses a decrease in short-circuit tolerance. Can do. However, in order to make the element peripheral region have different P-type impurity concentrations, it is necessary to separate the element central region and the P-type impurity region forming step for the element peripheral region, which increases the manufacturing process and decreases the productivity. Further, since there is a relation that the switching speed decreases when the gate resistance is increased, the method of increasing the gate resistance by narrowing the trench width decreases the switching speed and increases the switching loss. This is a particular problem with silicon carbide semiconductor elements that can operate at higher speeds than Si semiconductor elements.

  An object of the present specification is to provide a semiconductor device that has high short-circuit tolerance when the semiconductor device operates in a short-circuit state, is capable of high-speed switching, and has high productivity.

  A semiconductor device according to the present invention includes a semiconductor substrate, a drift layer formed on the semiconductor substrate, a plurality of base layers formed on a surface layer of the drift layer, and a surface layer of the plurality of base layers. A plurality of source regions each defining a surface layer of the base layer as a channel region, a gate oxide film formed on the channel region, a gate electrode formed on the gate oxide film, and a gate electrode A source electrode electrically connected to the source region and a heat conductive member bonded to the source electrode via a bonding material, and the region provided with the heat conductive member Is defined as the element central region, and the outer peripheral region of the element central region is defined as the element peripheral region. The channel region of the base layer in the element peripheral region is defined by the base layer in the element central region. Greater channel length than the Yaneru region.

  A semiconductor device according to the present invention includes a semiconductor substrate, a drift layer formed on the semiconductor substrate, a plurality of base layers formed on a surface layer of the drift layer, and a surface layer of the plurality of base layers. A plurality of source regions each defining a surface layer of the base layer as a channel region, a gate oxide film formed on the channel region, a gate electrode formed on the gate oxide film, and a gate electrode A source electrode electrically connected to the source region and a heat conductive member bonded to the source electrode via a bonding material, and the region provided with the heat conductive member Is defined as the element central region, and the outer peripheral region of the element central region is defined as the element peripheral region. The channel region of the base layer in the element peripheral region is defined by the base layer in the element central region. Greater channel length than the Yaneru region. Therefore, the current flowing at the time of a short circuit can be made smaller in the element peripheral region than in the element central region, heat generation is suppressed, and the short circuit tolerance is improved. In addition, a cell structure having a plurality of channel lengths can be easily formed without increasing the number of steps because it can be formed in the same step using a mask in which cells having different channel lengths are arranged. Further, adjusting the channel length does not increase the gate resistance.

1 is a cross-sectional view of a semiconductor device according to a first embodiment. 2 is a cross-sectional view of a short channel cell of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view of a long channel cell of the semiconductor device according to the first embodiment. FIG. 1 is a plan view of a semiconductor device according to a first embodiment. 2 is a cross-sectional view of the package of the semiconductor device according to the first embodiment. FIG. It is a figure which shows the channel length characteristic of the saturation current of MOSFET. 3 is a plan view showing a cell arrangement of the semiconductor device according to the first embodiment. FIG. 3 is a plan view showing a cell arrangement of the semiconductor device according to the first embodiment. FIG. FIG. 10 is a cross-sectional view of a package of a semiconductor device according to a modification of the first embodiment. FIG. 6 is a cross-sectional view of a semiconductor device according to a second embodiment. FIG. 6 is a plan view of a semiconductor device according to a second embodiment. FIG. 6 is a plan view showing a cell arrangement of a semiconductor device according to a second embodiment.

<A. Embodiment 1>
<A-1. Basic configuration>
FIG. 1 is a cross-sectional view of the semiconductor device 101 according to the first embodiment. Hereinafter, the semiconductor device 101 is described as a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) chip. The semiconductor device 101 is another semiconductor chip having an insulated gate structure such as an IGBT (Insulated Gate Bipolar Transistor). Also good. The semiconductor device 101 is classified into an element central region 1 on the central side of the semiconductor substrate 9 and an element peripheral region 2 on the outer peripheral side of the semiconductor substrate 9 surrounding the element central region. The cell structure formed in the element central region 1 is referred to as a short channel cell 12 and its sectional structure is shown in FIG. 2, and the cell structure formed in the element peripheral region 2 is called a long channel cell 11 and its sectional structure is shown in FIG. Respectively.

  The semiconductor device 101 includes a semiconductor substrate 9, a back electrode 10, a drift layer 8, a base layer 18, a source region 13, a base contact 19, a gate oxide film 16, a gate electrode 15, a breakdown voltage structure 7, an interlayer insulating film 14, and a source electrode 6. The protective film 5, the bonding material 4, and the heat conduction member 3 are provided. The semiconductor substrate 9 may use silicon, but if silicon carbide is used, a MOSFET capable of lower loss, higher speed operation, and higher temperature operation can be formed.

  A drift layer 8 is formed by epitaxial growth on the first main surface of the semiconductor substrate 9, and a back electrode 10 is formed on the second main surface. A plurality of base layers 18 are formed on the surface layer of the drift layer 8. A source region 13 is formed on the surface layer of each base layer 18. The base contact 19 penetrates from the front surface to the back surface of the source region 13 and is formed in contact with the base layer 18. The surface layer of the base layer 18 sandwiched between the source region 13 and the surface layer of the drift layer 8 becomes a channel region 17 in which an inversion layer is formed during the on-operation. A gate electrode 15 is formed on the base layer 18 on a region excluding a part of the source region 13 and the base contact 19 and on the drift layer 8 via a gate oxide film 16. Here, silicon oxide can be used for the gate oxide film 16, and polysilicon can be used for the gate electrode 15. A breakdown voltage structure 7 is formed at the element end of the drift layer 2 in order to maintain a breakdown voltage. The base layer 18, the source region 13, the base contact 19 and the breakdown voltage structure 7 are formed by ion implantation and activation annealing.

  An interlayer insulating film 14 having a contact hole on the surface is formed on the gate electrode 15. The source electrode 6 is a source electrode and is formed on the interlayer insulating film 14 and is insulated from the gate electrode 15 by the interlayer insulating film 14, while part of the source region 13 and the base contact 19 are formed through the opening of the interlayer insulating film 14. Make electrical contact. Here, silicon oxide can be used for the interlayer insulating film 14, and aluminum or copper can be used for the source electrode 6.

  In the element center region 1, the heat conducting member 3 is provided on the source electrode 6 via a bonding material 4 such as solder. The heat conducting member 3 is in electrical contact with the source electrode 6. In the element peripheral region 2, the protective film 5 is formed on the source electrode 6 where the heat conducting member 3 is not provided and on the interlayer insulating film 14 where the source electrode 6 is not provided. The protective film 5 is provided in order to avoid creeping discharge of the semiconductor device 101, and is therefore formed of an insulating resin such as polyimide. Since discharge in air occurs when the applied electric field exceeds 3 kV / mm, in order to avoid creeping discharge, the length of the protective film 5 from the end (chip end) of the semiconductor device 101 to the heat conducting member 3 is avoided. However, it is necessary to be at least the distance obtained by dividing the element breakdown voltage by 3 kV / mm. Therefore, the length of the protective film 5, in other words, the width of the element peripheral region 2 (the horizontal direction in FIG. 1) should be (element breakdown voltage / 3 kV) mm or more from the chip end. Since the heat conducting member 3 is joined to the source electrode 6 in the opening portion of the protective film 5, it is desirable that the opening area of the protective film 5 is large from the viewpoint of heat radiation from the source electrode 6 to the heat conducting member 3. However, as described above, in order to prevent creeping discharge, it is necessary to cover (element breakdown voltage / 3 kV) mm or more from the end of the chip with the protective film 5.

  The heat conducting member 3 is for absorbing the generated heat from the source electrode 6 and diffusing through the heat conducting member 3 when the MOSFET operates in a short circuit state and an overcurrent flows. Therefore, the thermal conductivity of the heat conducting member 3 is preferably higher than that of the protective film 5. As such a material, for example, a metal such as Cu, Ni, Al, or Mo, an alloy thereof, or a laminated structure thereof can be used. Further, it is desirable to increase the heat capacity of the heat conducting member 3 by making the thickness of the heat conducting member 3 larger than the thickness of the semiconductor substrate 9. As a joining method of the heat conducting member 3, for example, a Ni film can be formed on the source electrode 6 by plating, sputtering, vapor deposition, or the like, and the Ni film and the heat conducting member 3 can be joined with solder.

  FIG. 4 is a top view of the semiconductor device 101 (semiconductor chip) shown in FIG. 4 corresponds to FIG. 1. In the semiconductor device 101, a source electrode as the source electrode 6 and a gate pad 25 to which the gate electrode 15 is connected are formed. A breakdown voltage structure 7 is formed on the outermost peripheral portion of the semiconductor device 101 so as to surround the source electrode and the gate pad 25. The source electrode 6 may extend on a part of the breakdown voltage structure 7.

  As shown in FIG. 5, in the semiconductor device 101, the back electrode 10 is bonded to the base plate 21 by the bonding material 4. External terminals 22 are bonded to the base plate by the bonding material 4, whereby the back electrode 10 is electrically connected to the outside. In addition, wire bonding is performed on the heat conducting member 3, whereby the source electrode 6 is electrically connected to the outside. The semiconductor device 101 is sealed with a sealing resin 23 and stored in a package.

  The drift layer 8, the base layer 18, the source region 13, the base contact 19, the gate oxide film 16, and the gate electrode 15 together constitute one cell. As shown in FIG. 1, a plurality of the cells are arranged on the semiconductor substrate 9. 2 and 3, the channel length LC of the long channel cell 11 formed in the element peripheral region 2 is larger than the channel length LC of the short channel cell 12 formed in the element center region 1. These are the characteristics of the semiconductor device 101.

  FIG. 6 shows the channel length characteristics of the saturation current when the MOSFET is short-circuited. The horizontal axis of FIG. 6 indicates the channel length [μm], and the vertical axis indicates the saturation current [A]. As can be seen from FIG. 6, the saturation current decreases in proportion to the channel length, and the short-circuit resistance improves in proportion to the channel length. Therefore, as shown in FIGS. 2 and 3, in the element peripheral region 2 where heat cannot be radiated through the heat conducting member 3, the channel length is made larger than the element central region 1, thereby reducing the current value and generating heat. And the short circuit withstand capability is improved.

  It is necessary to increase the channel length so that the effect of increasing the short-circuit resistance by increasing the channel length of the element peripheral region 2 is larger than the effect of increasing the short-circuit resistance by the heat conducting member 3 in the element central region 1. By doing so, it is possible to suppress the current flowing through the element peripheral region 2 during the short-circuit operation.

  In addition, the configuration of the present embodiment in which the channel length is changed between the element peripheral region 2 and the element center region 1 can be formed in the same process using a mask in which cells having different channel lengths are arranged, so that the number of processes can be increased. Can be productive.

<A-2. Cell pitch>
Since the channel length LC in the element peripheral region 2 is made larger than the channel length LC in the element central region 1, the element central region is reduced in the element peripheral region 2 by reducing the interval between adjacent base layers 18, that is, the JFET length LJ. It is desirable to unify the cell pitches of 1 and element peripheral region 2. By unifying the cell pitches of both, as shown in FIG. 7 which is an enlarged view of the portion A in FIG. 4, the cell spacing is not increased at the corner portion that becomes the boundary between the element peripheral region 2 and the element central region 1. Both cells can be arranged. When the cell interval is widened, the electric field applied to the gate oxide film 16 is increased, so that the life of the gate oxide film 16 is shortened. However, the above configuration can avoid such a problem.

  Although FIG. 3 shows a configuration in which the JFET length LJ is reduced to adjust the cell pitch, the cell pitch may be adjusted by reducing the width of the source contact 20 or the base contact 19.

  Alternatively, as shown in FIG. 8 which is also an enlarged view of the portion A in FIG. 4, the cell pitch CP of the long channel cell 11 in the element peripheral region 2 is set to an integer multiple of the cell pitch CP of the short channel cell 12 (FIG. It can also be an example). FIG. 8 shows a case where the cell pitch CP of the long channel cell 11 and the cell pitch CP of the short channel cell 12 are 2: 1. In this case as well, both cells can be arranged without increasing the cell spacing at the corner portion that becomes the boundary between the element peripheral region 2 and the element central region 1. Therefore, it can be avoided that an excessive electric field is applied to the gate oxide film 16 and the lifetime is shortened.

  The cell pitch exemplified in FIG. 8 is adjusted by adjusting at least one of the JFET length LJ, the width of the source contact 20 and the width of the base contact 19. However, when the JFET length LJ is increased, the electric field applied to the gate oxide film 16 in the JFET portion increases and the life of the gate oxide film 16 is shortened. Therefore, the JFET length in the element peripheral region 2 is set to be equal to or less than the JFET length in the element center region 1.

<A-3. Modification>
In the above description, solder is used as the bonding material 4 for bonding the heat conducting member 3 to the source electrode 6. However, sintered silver bonding may be used instead of solder. According to sintered silver bonding, heat conductivity is better than solder bonding, so that heat generated at the time of a short circuit can be efficiently diffused to the heat conductive member 3, and the short circuit tolerance can be further improved.

  Further, FIG. 5 shows that a wire bond is bonded to the heat conducting member 3 to make an electrical connection with the outside, but the heat conducting member 3 and the external terminal 22 are joined to the bonding material 4 as shown in FIG. May be electrically connected to the outside by direct bonding.

<A-4. Effect>
The semiconductor device 101 according to the first embodiment of the present invention is, for example, a MOSFET, and the heat conducting member 3 is bonded onto the source electrode 6 via the bonding material 4. The region where the heat conducting member 3 is provided is defined as the element center region 1, and the outer peripheral region of the element center region 1 is defined as the element peripheral region 2. The channel region 17 of the base layer 18 in the element peripheral region 2 is defined as the element center region. The channel length is larger than the channel region 17 of the base layer 18 in the region 1. In the element peripheral region 2, heat can not be radiated through the heat conducting member 3, but by increasing the channel length as compared with the element central region 1, the current value can be reduced, heat generation can be suppressed, and the short circuit resistance can be improved. In addition, the structure having different channel lengths in the element peripheral region 2 and the element center region 1 can be formed in the same process using a mask in which cells having different channel lengths are arranged, and thus can be manufactured without increasing the number of processes. Good productivity. In addition, since the gate resistance is not increased, switching loss does not increase.

  In the semiconductor device 101, the distance between the adjacent base layers 18 (JFET length LJ) and the width of the source contact 20 so that the ratio of the cell pitch CP in the element peripheral region 2 to the cell pitch CP in the element center region 1 is an integer. Or at least one of the widths of the base contact 19 is determined. Thus, both cells can be arranged without increasing the cell spacing at the corner portion or the like that becomes the boundary between the element peripheral region 2 and the element center region 1. When the cell interval is widened, the electric field applied to the gate oxide film 16 is increased, so that the life of the gate oxide film 16 is shortened. However, the above configuration can avoid such a problem.

  Further, since the channel length of the channel region 17 in the element peripheral region 2 is larger than the channel length of the channel region 17 in the element central region 1, the distance between the adjacent base layers 18 in the element peripheral region 2 (JFET length LJ), the source At least one of the width of the contact 20 and the width of the base contact 19 may be made smaller than that in the element center region 1 so that the cell pitches of the element center region 1 and the element peripheral region 2 may be unified. Thus, both cells can be arranged without increasing the distance between the cells at the corner portion that becomes the boundary between the element peripheral region 2 and the element central region 1, and the lifetime of the gate oxide film 16 can be avoided.

  Moreover, the heat conductive member 3 consists of Cu, Ni, Al, Mo, these alloys, or these laminated structures. Further, the heat conducting member 3 is made thicker than the semiconductor substrate 9. With such a configuration, it is possible to dissipate heat generated by the overcurrent during the short-circuit operation by the heat conducting member 3.

  In addition, if sintered silver is used for the bonding material 4, heat conductivity is better than that of solder. Therefore, heat generated by an overcurrent during a short-circuit operation can be efficiently dissipated by the heat conductive member 3, and the short-circuit tolerance can be further increased. Can be improved.

  The heat conducting member 3 is electrically connected to the source electrode 6 and is electrically connected to the external electrode by a wire bond 24 made of aluminum, copper, an alloy thereof, or a laminated structure thereof. Alternatively, the heat conducting member 3 is electrically connected to the external electrode using the bonding material 4. With such a configuration, the source electrode 6 is electrically connected to the outside.

  Further, by using silicon carbide for the semiconductor substrate 9, a semiconductor device capable of operating at a lower loss, higher speed, and higher temperature than silicon can be obtained.

<B. Second Embodiment>
In the semiconductor device 101 according to the first embodiment, all the long channel cells 11 in the element peripheral region 2 have the same channel length. However, in the semiconductor device according to the second embodiment, the channel length is increased as the distance from the heat conducting member 3 increases in the element peripheral region 2. Other configurations are the same as those of the semiconductor device 101 according to the first embodiment, and the modified example described in the first embodiment can be applied to the second embodiment.

<B-1. Configuration>
FIG. 10 is a cross-sectional view of the semiconductor device 102 according to the second embodiment. FIG. 11 is a plan view of the semiconductor device 102, and a DD cross-sectional view of FIG. 11 corresponds to FIG. FIG. 12 is an enlarged view of part C in FIG. In the element peripheral region 2, the semiconductor device 102 includes a long channel cell 11A having a channel length larger than that of the short channel cell 12, and a long channel cell 11B having a channel length larger than that of the long channel cell 11A in the chip outer peripheral direction. In FIG. 10, one long channel cell 11A, 11B is shown in the same cross section, but the number is not limited to one.

  In FIG. 12, the cell pitch of the long channel cell 11B is set to twice the cell pitch of the long channel cell 11A. Two long channel cells 11A are arranged in the same cross-sectional direction. In the first embodiment, the cell pitches of the long channel cell 11 and the short channel cell 12 are unified or set to an integer ratio. However, the cell pitches of the long channel cells 11A and 11B are also unified or set to an integer ratio. It is desirable to do so.

  As described above, the feature of the semiconductor device 102 is that the cells are arranged in the element peripheral region 2 such that the channel length increases as the distance from the heat conducting member 3 increases. Therefore, the cells may be arranged so that the channel length is increased not only in the two stages of long channel cells 11A and 11B but also in multiple stages. If the channel length is uniform over the entire surface of the element peripheral region 2, a temperature gradient is generated in which the temperature increases in the direction away from the heat conducting member 3, that is, from the center of the chip toward the outer periphery during the short circuit operation of the MOSFET. However, by disposing the cell so that the channel length increases as the distance from the heat conducting member 3 increases, the temperature gradient is suppressed and the short-circuit resistance is further improved.

<B-2. Effect>
In the semiconductor device 102 according to the second embodiment, the channel length of the cell increases in the element peripheral region 2 as the distance from the heat conducting member 3 increases. With this configuration, it is possible to suppress the temperature gradient in which the temperature increases toward the direction away from the heat conducting member 3 during the short circuit operation of the MOSFET, and to increase the short circuit tolerance.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  DESCRIPTION OF SYMBOLS 1 Element center area | region, 2 Element periphery area | region, 3 Thermal conduction member, 4 Bonding material, 5 Protective film, 6 Source electrode, 7 Pressure | voltage resistant structure, 8 Drift layer, 9 Semiconductor substrate, 10 Back surface electrode, 11 Long channel cell, 12 Short Channel cell, 13 source region, 14 interlayer insulating film, 15 gate electrode, 16 gate oxide film, 17 channel region, 18 base layer, 19 base contact, 21 base plate, 22 external terminal, 23 sealing resin, 24 wire bond, 25 Gate pad, 101, 102 Semiconductor device.

Claims (11)

A semiconductor substrate;
A drift layer formed on the semiconductor substrate;
A plurality of base layers formed on a surface layer of the drift layer;
A plurality of source regions, each formed on a surface layer of the plurality of base layers, each defining a surface layer of the base layer between the drift layer and a channel region;
Gate oxide films respectively formed on the channel regions;
Gate electrodes respectively formed on the gate oxide film;
A source electrode formed on the gate electrode through an interlayer insulating film and electrically connected to the source region;
A heat conducting member bonded on the source electrode via a bonding material,
A region where the heat conducting member is provided is defined as an element central region, and an outer peripheral region of the element central region is defined as an element peripheral region.
The channel region of the base layer in the device peripheral region has a larger channel length than the channel region of the base layer in the device central region.
Semiconductor device. The distance between the adjacent base layers, the width of the source contact, or the width of the base contact is determined so that the ratio of the cell pitch in the element peripheral region and the cell pitch in the element center region is an integer.
The semiconductor device according to claim 1. Since the channel length of the channel region in the device peripheral region is larger than the channel length of the channel region in the device central region, the interval between the base layers adjacent to each other in the device peripheral region, the width of the source contact, or the base contact At least one of the widths of the element is smaller than that in the element center region, and the cell pitch of the element center region and the element peripheral region is unified.
The semiconductor device according to claim 2. In the element peripheral region, the channel length of the cell increases as the distance from the heat conducting member increases.
The semiconductor device according to claim 1. The heat conducting member is made of Cu, Ni, Al, Mo, alloys thereof, or a laminated structure thereof.
The semiconductor device according to claim 1. The heat conducting member is thicker than the semiconductor substrate;
The semiconductor device according to claim 1. The bonding material is sintered silver.
The semiconductor device according to claim 1. The heat conducting member is electrically connected to the source electrode, and is electrically connected to an external electrode by wire bonding made of aluminum, copper or an alloy thereof, or a laminated structure thereof.
The semiconductor device according to claim 1. The heat conducting member is electrically connected to the source electrode and electrically connected to an external electrode using a bonding material.
The semiconductor device according to claim 1. Silicon carbide is used for the semiconductor substrate;
The semiconductor device according to claim 1. The semiconductor device is a MOSFET;
The semiconductor device according to claim 1.

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