JP2016143846A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress peeling of an encapsulation resin on a semiconductor element peripheral part where peeling between the semiconductor element and the encapsulation resin is easy to occur during a heat cycle test, and obtain the semiconductor device having high reliability.SOLUTION: A semiconductor device comprises a semiconductor element 1; a mounting part for mounting the semiconductor element 1; and an encapsulation resin 6 for encapsulating the semiconductor element 1 and the mounting part, and the encapsulation resin 6 has an effective coefficient of thermal expansion of 4 to 12x10(1/K) in a region which comes into contact with the outer peripheral part of a surface opposing to a surface which comes into contact with the mounting part of the semiconductor element 1.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device in which a power semiconductor element is sealed with a resin, and more particularly to a semiconductor device on which a power semiconductor element using a compound semiconductor is mounted.

  A semiconductor device using a power semiconductor element uses a mold type in which the power semiconductor element is sealed with a thermosetting resin such as an epoxy resin, and a case type in which the power semiconductor element is sealed with a gel-like resin or an epoxy resin. In particular, mold-type semiconductor devices are small and excellent in reliability, and are easy to handle. Therefore, they are widely used for controlling air-conditioning equipment.

  In recent years, it is also used for power control of automobiles that perform motor control. Since the case type semiconductor device does not require a molding die for sealing, it is suitable for production of a small variety of products and is widely used for industrial purposes.

  Further, in the semiconductor device, the operating temperature of the power semiconductor element becomes high as the size and capacity are increased. The power semiconductor element is changed from Si (Silicon) to SiC (Silicon Carbide), so that it can be operated at high temperature. The SiC semiconductor element is said to have an operable temperature of 200 ° C. or more and 300 ° C.

  In a conventional semiconductor device, a wiring pattern of an insulating substrate on which a power semiconductor element is mounted is configured using a copper-containing material including copper and a metal having a smaller thermal expansion coefficient than copper, and the thermal expansion coefficient is Some have a thermal expansion coefficient smaller than that of copper. As a result, there has been provided a semiconductor device that can suppress cracks due to stress generated in the joint portion of the power semiconductor element and realize high reliability. (For example, Patent Document 1)

Japanese Unexamined Patent Publication No. 2012-253125 (page 4, FIG. 1)

  In the conventional semiconductor device, when the material of the semiconductor element is Si, it is effective for suppressing the stress of the semiconductor element joint portion and preventing the crack of the bonding material. However, when the material of the semiconductor element to be mounted is SiC, Also, the environment between the semiconductor element and the sealing resin is severe, and there is a problem that the insulation reliability of the semiconductor device is impaired.

  There are three main reasons why the insulation reliability is impaired by changing the material of the semiconductor element mounted on the semiconductor device from Si to SiC.

The first difference is due to the material properties of the semiconductor element. The thermal expansion coefficient of Si is 2.5 × 10 ⁻⁶ (1 / K) and the elastic modulus is 130 GPa, whereas the thermal expansion coefficient of SiC is 4.6 × 10 ⁻⁶ (1 / K) and the elastic modulus. The thermal stress generated at the bonding interface between the semiconductor element and the sealing resin depends on the structure of the semiconductor device and the thickness of the semiconductor element, but SiC is about 30 to 70 compared to Si. % Higher. Due to the increase in thermal stress, peeling at the bonding interface between the semiconductor element and the sealing resin and resin cracks occur, resulting in a decrease in insulation.

  The second is the adhesion between the sealing resin and the semiconductor element. A protective film polyimide layer for the purpose of electric field relaxation may be provided on one surface of the semiconductor element. However, there is a surface where Si or SiC is exposed at the outermost periphery of the semiconductor element, which is the outer periphery of the protective film polyimide layer. A natural oxide film is easily formed on the Si surface and adhesion to a resin such as an epoxy resin is advantageous. However, since the SiC surface is a relatively stable surface compared to Si, the natural oxide film is very Hard to generate. For this reason, in the adhesion between the element exposed surface without the protective film polyimide and the sealing resin, SiC has a lower adhesive strength than Si, and is easily peeled off against thermal stress in a temperature cycle or the like. For this reason, the SiC semiconductor element causes a decrease in insulation of the semiconductor device.

  The third is the difference in thermal stress generated by the operating temperature. The SiC semiconductor element can operate at a higher temperature than the Si semiconductor element, and is said to be both 200 ° C. and 300 ° C. or higher. Considering the heat resistance of the sealing resin that comes into contact with the semiconductor element, the semiconductor device can operate at a higher temperature when the SiC semiconductor element is mounted than when the Si semiconductor element is mounted. The temperature range for reliability evaluation is required to be wider than when the Si semiconductor element is mounted. For example, when the temperature cycle condition is −40 ° C. to 125 ° C. when the Si semiconductor element is mounted, for example, when −40 ° C. to 200 ° C. is required when the SiC semiconductor element is mounted, the evaluation temperature range ΔT is 165 ° C. to 240 ° C. It will increase to ° C. As a result, a semiconductor device on which an SiC semiconductor element is mounted is required to have a structure free from peeling and cracking against the generated thermal stress due to an increase in temperature cycle requirements.

  The present invention has been made to solve the above-described problems. By setting an effective thermal expansion coefficient of the sealing resin in the vicinity of the outer peripheral portion of the SiC semiconductor element, the present invention provides a sealing resin on the surface of the SiC semiconductor element. It is possible to obtain a semiconductor device that can suppress peeling and has improved reliability.

The semiconductor device according to the present invention includes a semiconductor element, a mounting portion on which the semiconductor element is mounted, and a sealing resin that seals the semiconductor element and the mounting portion. The effective thermal expansion coefficient in a region in contact with the outer peripheral portion of the surface opposite to the contact surface is 4 to 12 × 10 ⁻⁶ (1 / K).

In the present invention, since the effective thermal expansion coefficient of the sealing resin in the vicinity of the outer peripheral portion of the semiconductor element in which peeling between the semiconductor element and the sealing resin is likely to occur is 4 to 12 × 10 ⁻⁶ (1 / K), Separation from the sealing resin at the outer periphery of the semiconductor element during the temperature cycle can be suppressed, and high reliability can be ensured.

It is a cross-sectional structure schematic diagram of the semiconductor device of Embodiment 1 of this invention. It is the cross-sectional structure schematic diagram which expanded the semiconductor element edge part vicinity of the semiconductor device of Embodiment 1 of this invention. It is a cross-sectional structure schematic diagram which shows the peeling prevention object location of the semiconductor device of Embodiment 1 of this invention. It is a cross-sectional structure schematic diagram which shows the other peeling prevention object location of the semiconductor device of Embodiment 1 of this invention. It is a cross-sectional structure schematic diagram of the other semiconductor device of Embodiment 1 of this invention. It is a cross-sectional structure schematic diagram of the semiconductor device of Embodiment 2 of this invention. It is a cross-sectional structure schematic diagram of the semiconductor device of Embodiment 3 of this invention.

Embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably.

Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below with reference to the drawings. 1 is a schematic cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention. In FIG. 1, a semiconductor device 100 includes a semiconductor element 1, an insulating substrate 4 as a mounting portion, a metal base plate 5, a sealing resin 6, a bonding wire 7, and a lead frame 8.

  The semiconductor element 1 is, for example, a power control semiconductor element such as a MOSFET (Metal Oxide Field Effect Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor), or a power semiconductor element such as a freewheeling diode. In the first embodiment, the semiconductor device 100 includes a plurality (for example, two) of semiconductor elements 1, and the semiconductor element 1 includes two or more types (for example, two types) of semiconductors including a power control semiconductor element and a free wheel diode. It is an element. The semiconductor element 1 is formed of a wide band gap semiconductor material having a large band gap, and includes, for example, silicon carbide (SiC), a gallium nitride material, or diamond. Moreover, it does not need to be comprised only with a wide band gap semiconductor material, and what mixedly mounted the semiconductor element formed of silicon (Si) may be used. The elastic modulus of these materials is 430 GPa for silicon carbide, 200 GPa for gallium nitride, and 775 GPa for diamond.

  The semiconductor element 1 is mounted on one surface of the insulating substrate 4 by, for example, soldering or silver bonding (not shown), and the other surface of the insulating substrate 4 is made of, for example, copper molybdenum (CuMo). The metal base plate 5 is soldered or silver bonded (not shown).

The insulating substrate 4 includes a wiring pattern (electrode) 2 and a ceramic substrate 3. The insulating substrate 4 is not only insulated from the outside but also plays a role of radiating the heat generated from the semiconductor element 1. For example, a wiring pattern such as copper or aluminum is formed on both surfaces of ceramics such as alumina, aluminum nitride, and silicon nitride. 2 can be used. The wiring pattern 2 may be made of not only a single material such as copper or aluminum, but also a laminated structure or a wiring pattern 2 made of different materials on the front and back surfaces. Various combinations of thicknesses can be selected. The thermal expansion coefficient in the in-plane direction of the entire insulating substrate 4 changes depending on the selected ceramic type, the types of metal materials on both sides, and the combination of the thicknesses. The thermal expansion coefficient in the in-plane direction of the insulating substrate 4 can be measured by a thermomechanical measurement method or the like. Further, the effective thermal expansion coefficient of the surface of the wiring pattern 2 provided on both surfaces of the ceramic substrate 3 can be calculated by attaching a strain gauge to the surface of the wiring pattern 2 and measuring the amount of strain during the temperature cycle. . For example, in an insulating substrate 4 provided with 0.4 mm copper wiring pattern 2 on both sides of 0.32 mm thick silicon nitride, copper wiring pattern 2 is constrained by silicon nitride, and a strain gauge is actually used. The thermal expansion coefficient of the surface of the copper wiring pattern 2 is an average of 7.6 × 10 ⁻⁶ (1 / K) in the measurement range of −50 ° C. to 150 ° C. Considering that the inherent thermal expansion coefficient of copper is about 17 × 10 ⁻⁶ (1 / K), the effective thermal expansion coefficient of the copper wiring pattern 2 is reduced by being bonded to silicon nitride. .

  Further, dimples 16 (see FIG. 4) are provided on the surface of the wiring pattern 2 provided on the surface side of the insulating substrate 4 on which the semiconductor element 1 is mounted, in a location (region) other than the portion where the semiconductor element 1 is mounted. Thus, the adhesion between the sealing resin 6 and the wiring pattern 2 can be improved, and the peeling between the sealing resin 6 and the wiring pattern 2 can be suppressed.

One side of the metal base plate 5 is bonded to the insulating substrate 4 via, for example, a solder material or a silver bonding material (not shown), and the other surface is not covered with the sealing resin 6. It is exposed to the outside of the sealing resin 6. The material of the metal base plate 5 is not particularly limited, and copper (Cu), aluminum (Al), or the like can be used depending on conditions. However, depending on the structure of the insulating substrate 4 and the thermal expansion coefficient of the sealing resin 6, it is necessary to select a material having a small thermal expansion coefficient of the metal base plate 5. Molybdenum (Cu—Mo) or a clad material of copper and copper molybdenum can be used. By selecting these, the coefficient of thermal expansion as the metal base plate 5 is selected, for example, from 7 × 10 ⁻⁶ (1 / K) of Cu—Mo to around 24 × 10 ⁻⁶ (1 / K) of Al. It becomes possible to do.

  The sealing resin 6 is formed by transfer molding so as to seal the semiconductor element 1, the lead frame 8, the insulating substrate 4, the metal base plate 5, the bonding wire 7, and the like. The sealing resin 6 is formed of an epoxy resin filled with inorganic powder such as fused silica having a small thermal expansion coefficient or alumina having excellent thermal conductivity. The epoxy resin is not particularly limited, such as a general ortho-cresol novolak type or dicyclopentadiene type, although it depends on the heat dissipation of the power semiconductor device, the amount of heat generated during operation, and the operating temperature. For example, a highly heat-resistant resin using a naphthalene type or a polyfunctional type can be used by increasing the operating temperature of a semiconductor element using SiC or the like. Furthermore, when a semiconductor device used up to a high temperature region is assumed, a highly heat-resistant imide resin or isocyanate resin other than an epoxy resin may be used alone or in a mixed system with an epoxy resin.

  In addition, when thermal stress generated in a reliability test such as a temperature cycle is assumed, the thermal expansion coefficient of the sealing resin 6 is equal to or higher than the thermal expansion coefficient of the semiconductor element 1 within the range where the environmental temperature is assumed. It is desirable to keep it below the thermal expansion coefficient of the lead frame 8. When a temperature difference occurs due to a difference in thermal expansion coefficient, a difference in strain occurs at the contact surface, and stress is generated. Therefore, when the stress with the lead frame 8 or the semiconductor element 1 is assumed, it is desirable to employ the sealing resin 6 between the thermal expansion coefficients of both.

  For the electrical connection between the lead frame 8 and the semiconductor element 1, a bonding wire 7 may be used, or the semiconductor element 1 may be bonded to the opposite side of the surface where the semiconductor element 1 is bonded to the insulating substrate 4 with solder or silver. Also good.

By using the sealing resin 6 having such a thermal expansion coefficient range for the semiconductor device 100 including the insulating substrate 4 and the metal base plate 5, the outer peripheral portion of the surface on the side where the gate wiring of the semiconductor element 1 exists. The effective thermal expansion coefficient of the sealing resin 6 in contact with is 4 to 12 × 10 ⁻⁶ (1 / K), and this effect is obtained.

  Here, the effective thermal expansion coefficient is not the thermal expansion coefficient as the bulk of the sealing resin, but the effective thermal expansion coefficient when the sealing resin is bonded to the adherend and restrained. Point to. The sealing resin is constrained by bonding with various members of the semiconductor device. For example, in the vicinity of the bonding surface with a member having a thermal expansion coefficient smaller than that of the sealing resin, the bulk is actually bulky. The thermal expansion coefficient is smaller than the thermal expansion coefficient. The effective thermal expansion coefficient of the sealing resin in the vicinity of the bonding interface was calculated by a structural simulation simulating the structure of the semiconductor device, or a strain gauge was embedded inside the semiconductor device (module) to change the temperature of the semiconductor device. It is also possible to measure the effective thermal expansion coefficient by measuring the actual strain at times.

  The standard of the combination of the insulating substrate 4 and the metal base plate 5 is shown below. Assuming that each member is an elastic body, assuming that the elastic modulus of the semiconductor element 1, the insulating substrate 4 and the wiring pattern 2, and the metal base plate 5 is E, and the thickness is t, the total equivalent thermal expansion coefficient (effective thermal expansion coefficient) Can be expressed by the following equation.

ここで、Ｅは各材料の弾性率、αは各材料の熱膨張係数、ｔは厚さ、ｋは各部材を示す。実際には、各部材では塑性変形する領域もあるため、上式から求められる等価熱膨張係数と、ひずみゲージによって測定される表面の熱膨張係数を比較すると、ひずみゲージによって測定される熱膨張係数の方が２０〜４０％程度小さくなることがあるが、絶縁基板４および金属ベース板５の組み合わせの基準は、上式で求められたαｅの値が４〜１２の範囲である。

Here, E is the elastic modulus of each material, α is the thermal expansion coefficient of each material, t is the thickness, and k is each member. Actually, there are areas where plastic deformation occurs in each member, so comparing the equivalent thermal expansion coefficient obtained from the above equation with the thermal expansion coefficient of the surface measured by the strain gauge, the thermal expansion coefficient measured by the strain gauge However, the standard for the combination of the insulating substrate 4 and the metal base plate 5 is that the value of αe obtained by the above equation is in the range of 4-12.

  FIG. 2 is a schematic cross-sectional structure diagram enlarging the vicinity of the semiconductor element end portion of the semiconductor device according to the first embodiment of the present invention. In FIG. 2, polyimide 15 is disposed on the surface opposite to the surface in contact with the insulating substrate 4 of the semiconductor element 1 sealed with the sealing resin 6. The effective thermal expansion coefficient of the sealing resin 6 in the vicinity of the region 18 surrounded by the dotted line in the sealing resin 6 (in the vicinity of the outer peripheral portion opposite to the surface in contact with the insulating substrate 4) is set to the predetermined value as described above. By selecting the constituent members, stress generated due to the temperature cycle can be reduced, and peeling between the semiconductor element 1 and the sealing resin 6 during the temperature cycle can be suppressed.

FIG. 3 is a schematic cross-sectional structure diagram showing a part to be prevented from peeling of the semiconductor device according to the first embodiment of the present invention. In FIG. 3, there is a possibility that peeling occurs at the interface between the semiconductor element 1 and the sealing resin 6 in a region 19 surrounded by a dotted line during a temperature cycle. However, the stress generated due to the temperature cycle can be reduced by setting the effective thermal expansion coefficient of the sealing resin 6 to 4 to 12 × 10 ⁻⁶ (1 / K) as in the present invention. It becomes possible to suppress the peeling between the semiconductor element 1 and the sealing resin 6 during the temperature cycle.

FIG. 4 is a schematic cross-sectional structure diagram showing another delamination prevention target portion of the semiconductor device according to Embodiment 1 of the present invention. As a part to be prevented from peeling other than the area 19 shown in FIG. 3, peeling in the area 20 shown in FIG. In FIG. 4, dimples 16 are provided in the wiring pattern 2. In this case, an area 20 that is a bonding portion between the semiconductor element 1 and the wiring pattern 2 is conceivable as an area to be prevented from peeling off the sealing resin 6 during the temperature cycle. As shown in FIG. 4, by providing the dimples 16 in the wiring pattern 2, it is possible to suppress the peeling in the region 20 that is a joint portion between the semiconductor element 1 and the wiring pattern 2. Further, even when the dimples 16 are provided on the wiring pattern 2 as shown in FIG. 4, the sealing resin 6 is peeled off depending on the temperature cycle conditions, but the effective thermal expansion coefficient of the sealing resin 6 is 4. By setting it to ˜12 × 10 ⁻⁶ (1 / K), the stress generated due to the temperature cycle can be reduced, and the peeling between the semiconductor element 1 and the sealing resin 6 during the temperature cycle can be suppressed. In addition, it is possible to suppress peeling at the junction between the semiconductor element 1 and the wiring pattern 2.

FIG. 5 is a schematic sectional view of another semiconductor device according to the first embodiment of the present invention. In FIG. 5, the semiconductor device 200 includes a semiconductor element 1, an insulating substrate 4 as a mounting portion, a sealing resin 6, a bonding wire 7, and direct lead bonding (DLB) 9. The metal base plate 5 is eliminated from the semiconductor device 100 shown in FIG. 1, and the lead frame 8 is changed to the DLB 9. Also in the semiconductor device 200 having such a configuration, the stress generated due to the temperature cycle is reduced by setting the effective thermal expansion coefficient of the sealing resin 6 to 4 to 12 × 10 ⁻⁶ (1 / K). It can be reduced, and peeling between the semiconductor element 1 and the sealing resin 6 during the temperature cycle can be suppressed. 5 shows a configuration in which the metal base plate 5 is eliminated and the lead frame 8 is changed to the DLB 9, but the effective thermal expansion of the sealing resin 6 can be achieved even when only one of the configurations is changed. By setting the coefficient to 4 to 12 × 10 ⁻⁶ (1 / K), the stress generated due to the temperature cycle can be reduced, and the semiconductor element 1 and the sealing resin 6 are peeled off during the temperature cycle. Can be suppressed.

  Further, the use of DLB9 makes it possible to reduce the wiring inductance inside the semiconductor device 200, and the use of DLB9 improves the reliability due to the wiring.

In the semiconductor device configured as described above, since the effective thermal expansion coefficient of the sealing resin 6 is 4 to 12 × 10 ⁻⁶ (1 / K), the stress generated due to the temperature cycle is reduced. can do. As a result, peeling of the sealing resin 6 that occurs at the interface between the semiconductor element 1 and the sealing resin 6 can be prevented, and the insulation reliability of the semiconductor device can be improved.

Embodiment 2. FIG.
The second embodiment is different in that the insulating substrate 4 on which the semiconductor element 1 used in the first embodiment is mounted is changed to a heat spreader 10. Thus, even when it comprises using the heat spreader 10 which is a metal member as a mounting part of the semiconductor element 1, the effective thermal expansion coefficient of the sealing resin 6 shall be 4-12 * 10 < ^-6 > (1 / K). As a result, the stress generated due to the temperature cycle can be reduced. As a result, peeling of the sealing resin 6 that occurs at the interface between the semiconductor element 1 and the sealing resin 6 can be prevented, and the insulation reliability of the semiconductor device can be improved.

  A second embodiment of the present invention will be described below with reference to the drawings. 6 is a schematic sectional view of a semiconductor device according to the second embodiment of the present invention. In FIG. 6, the semiconductor device 300 includes a semiconductor element 1, a sealing resin 6, a bonding wire 7, a lead frame 8, a heat spreader 10 that is a metal member, an insulating sheet 11, and a metal foil 17.

  As described above, the difference from the first embodiment is the insulating structure. In the first embodiment, the insulation of the semiconductor device is ensured by the insulating substrate 4, whereas in the second embodiment, the semiconductor element 1 is mounted on the heat spreader 10 for the purpose of heat diffusion. When insulation is required for the semiconductor device, insulation is ensured by providing an insulating sheet 11 as shown in FIG. However, when an insulating structure is not required for the semiconductor device, the insulating sheet 11 (including the metal foil 17) is not necessarily provided.

  The combination of the heat spreader 10 and the insulating sheet 11 on which the semiconductor element 1 is mounted may be basically selected based on the concept described in the first embodiment.

Although the heat spreader 10 is a metal material, for example, a copper material having a thickness of 3 mm cannot be selected because αe in Formula 1 is 17 × 10 ⁻⁶ (1 / K) or more.

  When insulation is required for the semiconductor device, an insulating sheet as an insulating layer in which a copper foil as a metal foil 17 is attached to the surface (lower surface) opposite to the surface on which the semiconductor element 1 of the heat spreader 10 is mounted. 11 is provided. The insulating sheet 11 is formed of an epoxy resin filled with at least one kind of inorganic powder such as silica, alumina, boron nitride, aluminum nitride, etc. having excellent thermal conductivity, and the inorganic powder may be a single material or a combination of a plurality of materials. Moreover, the lower surface of the copper foil is exposed, and not only ensures heat dissipation, but also serves as a protective layer for preventing the insulating sheet 11 from being damaged by external contact. As long as this purpose is satisfied, the copper foil is not necessary, and a metal foil such as aluminum or a thick copper plate may be used.

  As the material of the heat spreader 10, for example, an alloy material having a smaller thermal expansion coefficient than copper can be used. For example, a material having a small thermal expansion coefficient such as copper molybdenum or a clad material of copper and copper molybdenum can be used. it can.

In the semiconductor device configured as described above, since the effective thermal expansion coefficient of the sealing resin 6 is 4 to 12 × 10 ⁻⁶ (1 / K), the stress generated due to the temperature cycle is reduced. can do. As a result, peeling of the sealing resin 6 that occurs at the interface between the semiconductor element 1 and the sealing resin 6 can be prevented, and the insulation reliability of the semiconductor device can be improved.

Embodiment 3 FIG.
The third embodiment is different in that the form of the semiconductor device used in the first embodiment is changed from a mold type to a case type. As described above, even when the semiconductor device is configured as a case type, the effective thermal expansion coefficient of the sealing resin 6 is set to 4 to 12 × 10 ⁻⁶ (1 / K). Can be reduced. As a result, peeling of the sealing resin 6 that occurs at the interface between the semiconductor element 1 and the sealing resin 6 can be prevented, and the insulation reliability of the semiconductor device can be improved.

  Embodiment 3 of the present invention will be described below with reference to the drawings. FIG. 7 is a schematic sectional view of a semiconductor device according to the third embodiment of the present invention. In FIG. 7, the semiconductor device 400 includes a semiconductor element 1, an insulating substrate 4, a metal base plate 5, a sealing resin 14, a bonding wire 7, a terminal 12, and a case member 13.

  A difference from the first embodiment is the sealing structure of the semiconductor device. In the first embodiment, the semiconductor device 100 is a so-called mold type semiconductor device that is sealed using a transfer molding machine. In the third embodiment, the sealing resin 14 that seals around the semiconductor element 1 does not have to be a sealing resin formed by transfer molding, and may be a so-called case type semiconductor device. The case type semiconductor device includes an insulating substrate 4 and a semiconductor element 1 in a case material 13 such as PPS, and is sealed in a case with a potting resin such as an epoxy resin as a sealing resin 14. It has become.

  In general, the sealing resin by potting is more restricted in viscosity than the sealing resin by transfer molding, and it is difficult to control to reduce the thermal expansion coefficient of the resin, but the equation (1) described in the first embodiment is used. By satisfying the conditions shown in the concept based on the above, even in a strict reliability test in a semiconductor device equipped with an SiC semiconductor element, the sealing resin / SiC semiconductor element is peeled off against thermal stress such as a temperature cycle. Generation of resin cracks can be suppressed, and a highly reliable semiconductor device can be obtained.

  In FIG. 7, the case material 13 is provided on the outer periphery of the metal base plate 5. However, the metal base plate 5 is not limited to a flat plate, and may be a metal base plate having a fin structure with irregularities. .

In the semiconductor device configured as described above, since the effective thermal expansion coefficient of the sealing resin 6 is 4 to 12 × 10 ⁻⁶ (1 / K), the stress generated due to the temperature cycle is reduced. can do. As a result, peeling of the sealing resin 6 that occurs at the interface between the semiconductor element 1 and the sealing resin 6 can be prevented, and the insulation reliability of the semiconductor device can be improved.

[Example]
Examples and comparative examples in the first embodiment will be described below. A comparative study was performed using the semiconductor device 100 shown in FIG. Table 1 shows the reliability test results of various semiconductor devices that were prototyped and evaluated.

[Example 1]
The configuration of the insulating substrate 4 was a silicon nitride substrate 3 in which copper wiring patterns 2 were provided on both sides of silicon nitride (Si ₃ N ₄ ). The thickness of the silicon wiring pattern was 0.32 mm, and the copper wiring pattern 2 was 0.3 mm on both sides. The SiC semiconductor element 1 was joined to one surface on which the copper wiring pattern 2 was provided. A dimple 16 for improving the adhesion with the sealing resin 6 is provided by etching in a portion (region) of the copper wiring pattern 2 on which the SiC semiconductor element 1 is not mounted. After the lead frame 8 and the insulating substrate 4 and the semiconductor element 1 were joined using the bonding wire 8, solder, or silver, the whole was sealed with a resin 6 so as to cover the semiconductor element 1 with a transfer mold apparatus. At this time, the copper wiring pattern 2 provided on the surface of the insulating substrate 4 opposite to the surface on which the semiconductor element 1 is mounted was molded so as to be exposed. The sealing resin 6 uses an epoxy resin filled with about 82% by weight of inorganic powder, and the thermal expansion coefficient of the sealing resin 6 is about 12 × 10 ⁻⁶ (1 / K) at room temperature. . Sealing resin 6 in the vicinity of the outer peripheral portion (about 0.1 mm) of the surface (the surface opposite to the surface in contact with the insulating substrate 4) provided with the gate wiring of the SiC semiconductor element 1 of the semiconductor device manufactured in this configuration. The effective thermal expansion coefficient is 7.1 × 10 ⁻⁶ (1 / K).

  Using this semiconductor device as a temperature cycle condition, a test of 1000 cycles from −40 ° C. to 200 ° C. was performed. After the temperature cycle test, the interface between the semiconductor element 1 and the sealing resin 6 and the interface between the wiring pattern 2 and the sealing resin 6 were observed with an ultrasonic flaw detector. As a result, no peeling occurred. It was confirmed that the electrical characteristics of 1 were good with almost no change from the initial stage.

[Example 2]
The second embodiment is a semiconductor device that has the same structure and process except that the configuration of the insulating substrate 4 is changed with respect to the contents of the first embodiment.

The configuration of the insulating substrate 4 was a silicon nitride substrate 3 in which copper wiring patterns 2 were provided on both sides of silicon nitride (Si ₃ N ₄ ). The structure of the thickness is to reduce the thermal expansion coefficient in the vicinity of the outer peripheral portion of the SiC semiconductor element 1 as compared with the first embodiment. Was 0.3 mm. The effective thermal expansion coefficient of the sealing resin 6 in the vicinity of the outer peripheral portion (about 0.1 mm) of the surface where the gate wiring of the SiC semiconductor element 1 of the semiconductor device manufactured in this configuration is provided is 5.9. × 10 ⁻⁶ (1 / K).

  Using this semiconductor device as a temperature cycle condition, a test of 1000 cycles from −40 ° C. to 200 ° C. was performed. After the temperature cycle test, the interface between the semiconductor element 1 and the sealing resin 6 and the interface between the wiring pattern 2 and the sealing resin 6 were observed with an ultrasonic flaw detector. As a result, no peeling occurred. It was confirmed that the electrical characteristics of 1 were good with almost no change from the initial stage.

[Example 3]
The third embodiment is a semiconductor device that has the same structure and process except that the configuration of the insulating substrate 4 is changed with respect to the contents of the first embodiment.

The configuration of the insulating substrate 4 was a silicon nitride substrate 3 in which copper wiring patterns 2 were provided on both surfaces of aluminum nitride (AlN). With respect to the structure of thickness, aluminum nitride was 0.64 mm and copper wiring pattern 2 was 0.3 mm on both sides for the purpose of improving heat dissipation of insulating substrate 4 as compared with Example 1. The effective thermal expansion coefficient of the sealing resin 6 in the vicinity of the outer peripheral portion (about 0.1 mm) of the surface where the gate wiring of the SiC semiconductor element 1 of the semiconductor device manufactured in this configuration is provided is 7.0. × 10 ⁻⁶ (1 / K).

  Using this semiconductor device as a temperature cycle condition, a test of 1000 cycles from -40 ° C to 200 ° C was performed. After the temperature cycle test, the interface between the semiconductor element 1 and the sealing resin 6 and the interface between the wiring pattern 2 and the sealing resin 6 were observed with an ultrasonic flaw detector. As a result, no peeling occurred. It was confirmed that the electrical characteristics of 1 were good with almost no change from the initial stage.

[Example 4]
The fourth embodiment is a semiconductor device that has the same structure and process except that the configuration of the insulating substrate 4 is changed with respect to the contents of the first embodiment.

The configuration of the insulating substrate 4 was a silicon nitride substrate 3 in which copper wiring patterns 2 were provided on both sides of silicon nitride (Si ₃ N ₄ ). The structure of the thickness was set such that silicon nitride was 0.32 mm and copper wiring pattern 2 on both sides was 1.0 mm for the purpose of improving heat dissipation of the insulating substrate as compared with Example 1. The effective thermal expansion coefficient of the sealing resin 6 in the vicinity of the outer peripheral portion (about 0.1 mm) of the surface where the gate wiring of the SiC semiconductor element 1 of the semiconductor device manufactured in this configuration is provided is 10.7. × 10 ⁻⁶ (1 / K).

  Using this semiconductor device as a temperature cycle condition, a test of 1000 cycles from −40 ° C. to 200 ° C. was performed. After the temperature cycle test, the interface between the semiconductor element 1 and the sealing resin 6 and the interface between the wiring pattern 2 and the sealing resin 6 were observed with an ultrasonic flaw detector. As a result, no peeling occurred. It was confirmed that the electrical characteristics of 1 were good with almost no change from the initial stage.

[Example 5]
The fifth embodiment is a semiconductor device that has the same structure and process except that the configuration of the insulating substrate 4 is changed with respect to the contents of the first embodiment.

The configuration of the insulating substrate 4 was a silicon nitride substrate 3 provided with a wiring pattern 2 in which copper and aluminum were laminated on both sides of silicon nitride (Si ₃ N ₄ ). The structure of the thickness is that 0.44 mm of aluminum wiring layers are provided on both sides with respect to 0.64 mm of silicon nitride for the purpose of reducing thermal stress on the silicon nitride plate 3 as compared with Example 1. It was assumed that a copper wiring layer was provided on both sides by 0.8 mm. The effective thermal expansion coefficient of the sealing resin 6 in the vicinity of the outer peripheral portion (about 0.1 mm) of the surface where the gate wiring of the SiC semiconductor element 1 of the semiconductor device manufactured in this configuration is provided is 9.9. × 10 ⁻⁶ (1 / K).

  Using this semiconductor device as a temperature cycle condition, a test of 1000 cycles from -40 ° C to 200 ° C was performed. After the temperature cycle test, the interface between the semiconductor element 1 and the sealing resin 6 and the interface between the wiring pattern 2 and the sealing resin 6 were observed with an ultrasonic flaw detector. As a result, no peeling occurred. It was confirmed that the electrical characteristics of 1 were good with almost no change from the initial stage.

[Comparative Example 1]
The present comparative example 1 is a semiconductor device that has the same structure and process except that the configuration of the insulating substrate 4 is changed with respect to the contents of the first embodiment.

The configuration of the insulating substrate 4 was a silicon nitride substrate 4 in which copper wiring patterns 2 were provided on both sides of silicon nitride (Si ₃ N ₄ ). The structure of the thickness is 1.0 mm for silicon nitride and 0.1 mm for copper wiring pattern 2 on both sides for the purpose of reducing stress applied to the silicon nitride plate 3 of the insulating substrate 4 as compared with the first embodiment. did. The effective thermal expansion coefficient of the sealing resin 6 in the vicinity of the outer peripheral portion (about 0.1 mm) of the surface where the gate wiring of the SiC semiconductor element 1 of the semiconductor device manufactured in this configuration is provided is 3.9. × 10 ⁻⁶ (1 / K).

Using this semiconductor device as a temperature cycle condition, a test of 1000 cycles from −40 ° C. to 200 ° C. was performed. After the temperature cycle test, the presence or absence of peeling at each interface was evaluated using an ultrasonic flaw detector. As a result, no peeling occurred at the interface between the semiconductor element 1 and the sealing resin 6, but the wiring pattern 2 and the sealing resin 6 Peeling occurred at the interface. For this reason, the reliability test was not cleared when the insulating substrate 4 having a small thermal expansion coefficient such that the thermal expansion coefficient of the corresponding part was smaller than 4 × 10 ⁻⁶ (1 / K) was applied.

[Comparative Example 2]
The present comparative example 2 is a semiconductor device that has the same structure and process except that the configuration of the insulating substrate 4 is changed with respect to the contents of the first embodiment.

The configuration of the insulating substrate 4 was a silicon nitride substrate 3 provided with a wiring pattern 2 in which copper and aluminum were laminated on both sides of silicon nitride (Si ₃ N ₄ ). The thickness of the silicon nitride plate 3 is 0.32 mm and the aluminum wiring layer is 0.5 mm on both sides for the purpose of reducing thermal stress on the silicon nitride plate 3 and improving heat dissipation compared to the first embodiment. Further, it was assumed that 1.0 mm of a copper wiring layer was provided on both sides. The effective thermal expansion coefficient of the sealing resin 6 in the vicinity of the outer peripheral portion (about 0.1 mm) of the surface of the semiconductor device 1 manufactured with this configuration where the gate wiring of the SiC semiconductor element 1 is provided is 12.4. × 10 ⁻⁶ (1 / K).

Using this semiconductor device as a temperature cycle condition, a test of 1000 cycles from −40 ° C. to 200 ° C. was performed. After the temperature cycle test, as a result of evaluating the presence or absence of peeling at each interface using an ultrasonic flaw detector, no peeling occurred at the interface between the copper wiring pattern 2 and the sealing resin 6, but the surface of the semiconductor element 1 was sealed off. Peeling occurred at the interface with the stop resin 6. For this reason, the reliability test was not cleared when the insulating substrate 4 having a large coefficient of thermal expansion was applied such that the coefficient of thermal expansion of the corresponding part was larger than 12 × 10 ⁻⁶ (1 / K).

[Example 6]
In the sixth embodiment, the metal base plate 5 is further bonded to the surface of the insulating substrate 4 on which the semiconductor element 1 is not mounted, and nothing is bonded to the metal base plate 5 with respect to the contents of the comparative example 2. The semiconductor device is formed by the same structure and process except that the structure is exposed to the outside of the semiconductor device.

The added metal base plate 5 is copper molybdenum (CuMo), and is composed of 30 wt% copper and 70 wt% molybdenum as a composition ratio. The thermal expansion coefficient of the metal base plate 5 is about 7.0 × 10 ⁻⁶ (1 / K). The effective thermal expansion coefficient of the sealing resin 6 in the vicinity of the outer peripheral portion (about 0.1 mm) of the surface where the gate wiring of the SiC semiconductor element 1 of the semiconductor device manufactured in this configuration is provided is 10.8. × 10 ⁻⁶ (1 / K). By providing this metal base plate 5, the thermal expansion coefficient of the sealing resin 6 in the vicinity of the SiC semiconductor element 1 can be reduced while maintaining the thermal stress reduction and heat dissipation intended for application in Comparative Example 2 to some extent. And reliability can be ensured.

  Using this semiconductor device as a temperature cycle condition, a test of 1000 cycles from -40 ° C to 200 ° C was performed. After the temperature cycle test, the interface between the semiconductor element 1 and the sealing resin 6 and the interface between the wiring pattern 2 and the sealing resin 6 were observed with an ultrasonic flaw detector. As a result, no peeling occurred. It was confirmed that the electrical characteristics of 1 were good with almost no change from the initial stage.

[Example 7]
In the present embodiment, the metal base plate 5 is further bonded to the surface of the insulating substrate 4 on which the semiconductor element 1 is not mounted, and the surface of the metal base plate 5 on which nothing is bonded. The semiconductor device has the same structure and process except that the structure is exposed to the outside of the semiconductor device.

The added metal base plate 5 is copper molybdenum (CuMo), and is composed of 30 wt% copper and 70 wt% molybdenum as a composition ratio. The thermal expansion coefficient of the metal base plate 5 is about 7.0 × 10 ⁻⁶ (1 / K). The effective thermal expansion coefficient of the sealing resin 6 in the vicinity of the outer peripheral part (about 0.1 mm) of the surface of the semiconductor device 1 manufactured with this configuration where the gate wiring of the SiC semiconductor element 1 is provided is 6.3. × 10 ⁻⁶ (1 / K). By providing the metal base plate 5, it is possible to reduce the warp of the semiconductor device while ensuring the reliability in the second embodiment.

  Using this semiconductor device as a temperature cycle condition, a test of 1000 cycles from −40 ° C. to 200 ° C. was performed. After the temperature cycle test, the interface between the semiconductor element 1 and the sealing resin 6 and the interface between the wiring pattern 2 and the sealing resin 6 were observed with an ultrasonic flaw detector. As a result, no peeling occurred. It was confirmed that the electrical characteristics of 1 were good with almost no change from the initial stage.

In Example 1 to Example 7 and Comparative Example 1 to Comparative Example 2, the reliability result varies depending on the combination of the insulating substrate 4 and the metal base plate 5. Examples 1 to 7 are examples of combinations, and the combinations are limited as long as the thermal expansion coefficient of the sealing resin in the corresponding part is 4 to 12 × 10 ⁻⁶ (1 / K) by combination. Is not to be done.

  Examples and comparative examples in Embodiment 2 are shown below. Table 2 shows the reliability test results of various semiconductor devices that were prototyped and evaluated.

[Example 8]
As the heat spreader 10, copper molybdenum (CuMo) composed of 30% by weight of copper and 70% by weight of molybdenum was used as a composition ratio. The thermal expansion coefficient of the heat spreader 10 is about 7.0 × 10 ⁻⁶ (1 / K). The thickness of the heat spreader 10 was 3 mm, and a 200 μm thick insulating sheet 11 having a copper foil 17 of about 100 μm provided on one side was bonded to a surface not provided with a copper foil. The semiconductor element 1 is mounted on the surface of the heat spreader 10 on which the insulating sheet 11 is not provided, and transfer molding is performed so that the whole is covered with the sealing resin 6 so that the copper foil 17 is exposed. Resin-sealed by an apparatus.

The insulating sheet 11 is an epoxy resin filled with boron nitride of about 50 to 60% by volume, has a thermal conductivity of about 12 W / (m · K), and a battle expansion coefficient of about 14 × 10 ⁻⁶ ( 1 / K) was used. As in Example 1, the sealing resin 6 is an epoxy resin filled with about 82% by weight of inorganic powder, and the thermal expansion coefficient of the sealing resin is about 12 × 10 ⁻⁶ (1 / K). The effective thermal expansion coefficient of the sealing resin 6 in the vicinity of the outer peripheral portion (about 0.1 mm) of the surface where the gate wiring of the SiC semiconductor element 1 of the semiconductor device manufactured in this configuration is provided is 6.7. × 10 ⁻⁶ (1 / K).

  Using this semiconductor device as a temperature cycle condition, a test of 1000 cycles from −40 ° C. to 200 ° C. was performed. After the temperature cycle test, the interface between the semiconductor element 1 and the sealing resin 6 and the interface between the wiring pattern 2 and the sealing resin 6 were observed with an ultrasonic flaw detector. As a result, no peeling occurred. It was confirmed that the electrical characteristics of 1 were good with almost no change from the initial stage.

[Comparative Example 3]
The third comparative example is a semiconductor device that has the same structure and process except that the material of the heat spreader 10 is changed with respect to the contents of the eighth embodiment.

Copper was used as the heat spreader 10. The thermal expansion coefficient of the heat spreader 10 is about 17.0 × 10 ⁻⁶ (1 / K). The thickness was 3 mm as in Example 8.

The effective thermal expansion coefficient of the sealing resin 6 in the vicinity of the outer peripheral portion (about 0.1 mm) of the surface where the gate wiring of the SiC semiconductor element 1 of the semiconductor device manufactured in this configuration is provided is 14.2. × 10 ⁻⁶ (1 / K).

Using this semiconductor device as a temperature cycle condition, a test of 1000 cycles from −40 ° C. to 200 ° C. was performed. After the temperature cycle test, as a result of evaluating the presence or absence of peeling at each interface using an ultrasonic flaw detector, no peeling occurred at the interface between the copper wiring pattern 2 and the sealing resin 6, but the surface of the semiconductor element 1 was sealed off. Peeling occurred at the interface with the stop resin 6. For this reason, the reliability test was not cleared when the material was applied as the heat spreader 10 with a material having a large thermal expansion coefficient such that the thermal expansion coefficient of the corresponding part was larger than 12 × 10 ⁻⁶ (1 / K).

  DESCRIPTION OF SYMBOLS 1 Semiconductor element, 2 wiring pattern, 3 ceramic substrate, 4 insulating substrate, 5 metal base board, 6 sealing resin, 7 bonding wire, 8 lead frame, 9 DLB, 10 heat spreader, 11 insulating sheet, 12 terminal, 13 case material , 14 sealing resin (gel), 15 polyimide, 16 dimples, 17 metal foil, 18 effective thermal expansion coefficient measurement position, 19, 20 peeling prevention target location, 100, 200, 300, 400 semiconductor device.

Claims (9)

A semiconductor element;
A mounting portion for mounting the semiconductor element;
A sealing resin for sealing the semiconductor element and the mounting portion;
The semiconductor is characterized in that the sealing resin has an effective thermal expansion coefficient of 4 to 12 × 10 ⁻⁶ (1 / K) in a region in contact with the outer peripheral portion of the surface opposite to the surface in contact with the mounting portion of the semiconductor element. apparatus. The semiconductor device according to claim 1, wherein the mounting portion is an insulating substrate. The semiconductor device according to claim 1, wherein the mounting portion is a metal member. The semiconductor device according to claim 2, wherein the insulating substrate is formed using aluminum nitride or silicon nitride. The semiconductor device according to claim 4, wherein a metal base plate is bonded to an opposite surface of the insulating substrate on which the semiconductor element is mounted. The semiconductor device according to claim 3, wherein the metal member is a heat spreader having a thermal expansion coefficient larger than that of copper molybdenum and smaller than that of copper. The semiconductor device according to claim 6, wherein an insulating sheet is provided on a surface opposite to the surface on which the semiconductor element is mounted of the heat spreader. 8. The semiconductor device according to claim 1, wherein the semiconductor element has an elastic modulus of 130 GPa or more and 775 GPa or less. The semiconductor device according to claim 1, wherein a material of the semiconductor element is silicon carbide.

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