JP2019016738A - Semiconductor device - Google Patents

Abstract

To provide an art to reduce loss of a vertical semiconductor element included in a semiconductor device and an art suitable for inhibiting cracks of the semiconductor substrate included in the semiconductor device.SOLUTION: A semiconductor device comprises: a semiconductor substrate having an active region and a peripheral region arranged around the active region; a vertical semiconductor element provided in the active region and capable of applying electric current to a gap between a surface and a rear face of the semiconductor substrate; a recess provided on the rear face and in the active region; and a metal layer arranged in the recess, in which a rear face of the metal layer is covered with a material capable of being solder jointed.SELECTED DRAWING: Figure 2

Description

  The technology disclosed in this specification relates to a semiconductor device.

  In order to reduce the loss of a semiconductor device, a technique for thinning a semiconductor substrate is widely known. Patent Document 1 discloses a technique for thinning a semiconductor wafer. A metal layer or a resin layer reaching from the upper surface to the lower surface of the semiconductor wafer is provided on the periphery of the semiconductor wafer. When a crack is generated from the outer peripheral edge to the inner peripheral side of the semiconductor wafer, it is possible to suppress the crack from being extended by the metal layer or the resin layer.

JP 2011-159838 A

  2. Description of the Related Art A semiconductor device including a vertical semiconductor element capable of flowing a current between a front surface and a back surface of a semiconductor substrate is known. In the vertical semiconductor element, the loss can be reduced by thinning the semiconductor substrate. On the other hand, when the semiconductor substrate is thinned, there is a problem that the strength of the semiconductor substrate is lowered. With the technique of Patent Document 1, it is possible to suppress the progress of cracks in the state of the semiconductor wafer. However, the technique disclosed in Patent Document 1 does not take into consideration after the semiconductor wafer is separated into semiconductor devices. For this reason, in each semiconductor device separated from the semiconductor wafer, there is a problem that the semiconductor substrate is easily broken. The present specification provides a technique for reducing the loss of a vertical semiconductor element included in a semiconductor device and appropriately suppressing cracks in a semiconductor substrate included in the semiconductor device.

  A semiconductor device disclosed in this specification includes a semiconductor substrate having an active region and a peripheral region disposed around the active region. In the active region, a vertical semiconductor element capable of passing a current between the front surface and the back surface of the semiconductor substrate is provided. On the back surface, a recess is provided in the active region. A metal layer is disposed in the recess. The back surface of the metal layer is covered with a solderable material.

  In this semiconductor device, a recess is provided on the back surface of the semiconductor substrate in the active region. For this reason, in the part in which the recessed part is provided, the thickness of the semiconductor substrate in an active region is thinner than the thickness of the semiconductor substrate in a peripheral region. When the vertical semiconductor element operates, a current flows in the thickness direction of the semiconductor substrate in the active region. In addition, the metal layer arrange | positioned in a recessed part functions as an electrode electrically connected with an active region. Since the semiconductor substrate is thin in the active region where current flows, loss of the semiconductor element can be reduced. Moreover, since the thickness of the semiconductor substrate in the peripheral region is thick, the strength of the semiconductor substrate can be ensured. Furthermore, the strength of the semiconductor substrate can be further improved by the metal layer disposed in the recess. Therefore, even if stress is applied in the direction in which the semiconductor substrate is bent, the semiconductor substrate is unlikely to crack. Thus, in this semiconductor device, the loss of the semiconductor element can be reduced and the strength of the semiconductor substrate can be ensured.

1 is a longitudinal sectional view of a semiconductor module 10. FIG. The partial expanded sectional view of FIG. FIG. 3 is a plan view of a semiconductor substrate 22. FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor module 10. FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor module 10. FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor module 10.

  The semiconductor module 10 of the embodiment shown in FIG. 1 includes an upper lead frame 12, a copper block 16, a semiconductor device 19, a metal layer 24, a lower lead frame 30, and a resin layer 32. The semiconductor device 19 includes a semiconductor substrate 22, an upper electrode layer 20, a lower electrode layer 26, and a metal layer 24. In the present embodiment, the semiconductor substrate 22 is made of silicon carbide (SiC). An upper electrode layer 20 is provided on the surface of the semiconductor substrate 22. A metal layer 24 and a lower electrode layer 26 are provided on the back surface of the semiconductor substrate 22. The lower electrode layer 26 covers the back surfaces of the semiconductor substrate 22 and the metal layer 24. The upper electrode layer 20 is connected to the back surface of the copper block 16 via the solder layer 18. The surface of the copper block 16 is connected to the back surface of the upper lead frame 12 through the solder layer 14. The lower electrode layer 26 is connected to the surface of the lower lead frame 30 via the solder layer 28. The upper lead frame 12 and the lower lead frame 30 function as electrode plates for energizing the semiconductor substrate 22 and also function as heat dissipation plates for radiating heat from the semiconductor substrate 22. The side surface of the laminate composed of the upper lead frame 12, the copper block 16, the semiconductor device 19 and the lower lead frame 30 is covered with a resin layer 32.

  FIG. 2 is an enlarged cross-sectional view including the back surface of the semiconductor substrate 22 of FIG. In FIG. 2, it should be noted that the configuration above the upper electrode layer 20, the configuration below the solder layer 28, and the resin layer 32 in FIG. 1 are omitted. FIG. 3 is a plan view of the semiconductor substrate 22.

  As shown in FIGS. 2 and 3, the semiconductor substrate 22 includes an active region 50 and a peripheral region 60 arranged around the active region 50. Although not shown, a plurality of semiconductor elements are formed in the active region 50. The semiconductor element is a vertical semiconductor element capable of passing a current between the front surface 22a (that is, the upper electrode layer 20) and the rear surface 22b (lower electrode layer 26) of the semiconductor substrate 22. The structure of the vertical semiconductor element formed in the active region 50 is not particularly limited. For example, switching such as IGBT (Insulated Gate Bipolar Transistor) or MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is used. An element is mentioned. As shown in FIG. 3, the peripheral region 60 is provided between the active region 50 and the outer peripheral end surface of the semiconductor substrate 22. The distance d2 (see FIG. 3) from the outer peripheral end surface of the semiconductor substrate 22 to the active region 50 is not particularly limited, but is, for example, 1000 μm or less. The active region 50 is not formed in the peripheral region 60. That is, when the semiconductor module 10 is energized, the main current flows between the front surface 22 a and the back surface 22 b of the semiconductor substrate 22 in the active region 50, and less current flows in the peripheral region 60.

  A recess 40 is provided in the active region 50 on the back surface 22 b of the semiconductor substrate 22. In the present embodiment, a step is formed on the back surface 22 b of the semiconductor substrate 22 at the boundary between the active region 50 and the peripheral region 60 by the recesses 40 provided in the entire active region 50. That is, the thickness of the semiconductor substrate 22 in the active region 50 is thinner than the thickness of the semiconductor substrate 22 in the peripheral region 60. The depth of the recess 40 (the distance between the position of the back surface 22b of the semiconductor substrate 22 in the active region 50 and the position of the back surface 22b of the semiconductor substrate 22 in the peripheral region 60 in the thickness direction of the semiconductor substrate 22) d1 ( Although not particularly limited, for example, it is 1 μm or more.

  A metal layer 24 is disposed in the recess 40. The metal layer 24 is filled in the recess 40 without a gap. The metal layer 24 is made of a material having a high thermal conductivity or a material having a high electrical conductivity. Specifically, the metal layer 24 is made of, for example, copper (Cu), aluminum (Al), nickel (Ni), or the like.

  A range extending from the back surface of the metal layer 24 to the back surface 22 b of the semiconductor substrate 22 in the peripheral region 60 is covered with the lower electrode layer 26. The lower electrode layer 26 covers the entire back surface of the metal layer 24 and the entire back surface 22 b of the semiconductor substrate 22 in the peripheral region 60. The lower electrode layer 26 is made of a solderable material. Specifically, the lower electrode layer 26 is made of, for example, Cu, Ni, zinc (Zn), lead (Pb), or the like. Although the thickness of the lower electrode layer 26 is not specifically limited, For example, it is 100 nm or more. The lower electrode layer 26 is an example of a “solderable material”.

  In the semiconductor device 19 of the present embodiment, a recess 40 is provided on the back surface 22 b of the semiconductor substrate 22 in the active region 50. For this reason, the thickness of the semiconductor substrate 22 in the active region 50 is thinner than the thickness of the semiconductor substrate 22 in the peripheral region 60 in the portion where the recess 40 is provided. When the vertical semiconductor element operates, a main current flows in the thickness direction of the semiconductor substrate 22 in the active region 50. The metal layer 24 disposed in the recess 40 functions as an electrode that is electrically connected to the active region 50. Since the semiconductor substrate 22 is thin in the active region 50 where the main current flows, the loss of the semiconductor element formed in the active region 50 can be reduced.

  Moreover, since the thickness of the semiconductor substrate 22 in the peripheral region 60 is thick, the strength of the semiconductor substrate 22 can be ensured. Furthermore, the strength of the semiconductor substrate 22 can be further improved by the metal layer 24 disposed in the recess 40. Therefore, even if stress is applied in the direction in which the semiconductor substrate 22 is bent, the semiconductor substrate 22 is unlikely to crack. As described above, in the semiconductor device 19, the loss of the semiconductor elements formed in the active region 50 can be reduced and the strength of the semiconductor substrate 22 can be ensured.

  Next, a method for manufacturing the semiconductor module 10 of the embodiment will be described. First, as shown in FIG. 4, a semiconductor substrate 22 having an active region 50 having an element structure and a peripheral region 60 disposed around the active region 50 is prepared. At this time, the thickness of the semiconductor substrate 22 is, for example, 200 μm. Then, as shown in FIG. 5, a recess 40 is formed on the back surface 22 b of the semiconductor substrate 22. The recess 40 is formed by masking the back surface 22 b of the peripheral region 60 of the semiconductor substrate 22 and etching the back surface 22 b in the active region 50.

  Next, as shown in FIG. 6, the back surface 22b of the semiconductor substrate 22 in the peripheral region 60 is masked, and the metal layer 24 is formed in the recess 40 by sputtering. Next, the lower electrode layer 26 is formed by sputtering so as to cover the back surface of the metal layer 24 and the back surface 22b of the peripheral region 60 of the semiconductor substrate 22 (see FIG. 2). Thereafter, as shown in FIG. 1, the upper electrode layer 20 is formed by sputtering. Next, the upper lead frame 12, the copper block 16, the semiconductor substrate 22, and the lower lead frame 30 are laminated via the solder layers 14, 18, and 28, and the laminated body is heated in a reflow furnace. Then, the solder layers 14, 18, and 28 are once melted and then solidified. As a result, the upper lead frame 12, the copper block 16, the semiconductor substrate 22, and the lower lead frame 30 are joined together. Then, the semiconductor module 10 shown in FIG. 1 is completed by covering the periphery of the laminate with the resin layer 32.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10: Semiconductor module 12: Upper lead frame 14: Solder layer 16: Copper block 18: Solder layer 19: Semiconductor device 20: Upper electrode layer 22: Semiconductor substrate 22a: Front surface 22b: Back surface 24: Metal layer 26: Lower electrode layer 28 : Solder layer 30: Lower lead frame 32: Resin layer 40: Recess 50: Active region 60: Peripheral region

Claims (1)

Comprising a semiconductor substrate having an active region and a peripheral region disposed around the active region;
In the active region, a vertical semiconductor element capable of flowing a current between the front surface and the back surface of the semiconductor substrate is provided,
The back surface is provided with a recess in the active region,
A metal layer is disposed in the recess,
The back surface of the metal layer is covered with a solderable material,
Semiconductor device.

Images