JP6299568B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a semiconductor element is bonded on a lead frame.

  Patent Document 1 describes that the surface of a lead frame made of a nickel-based alloy material is covered with a lower resistance copper plating layer, and a semiconductor chip is bonded to the lead frame via the copper plating layer. . The copper plating layer is formed thicker than the skin depth, and is a region where a high-frequency current flows. Patent Document 2 describes mounting a semiconductor chip on a substrate using an alloy bonding material in order to obtain good reliability in a high temperature environment.

Japanese Patent Laying-Open No. 2005-086057 JP 2013-038330 A

  However, a bonding material containing a magnetic metal such as nickel is used to bond a semiconductor chip such as a power semiconductor element in a state of being stacked on a lead frame. Therefore, the self-inductance parasitic on the joint formed from the joint material has a large value proportional to the relative permeability. When a high frequency current component flows by switching the power semiconductor element, a large surge voltage based on the product of the self-inductance and the time change rate of the high frequency current component is generated from the junction.

  The present invention provides a semiconductor device capable of reducing inductance parasitic to a circuit due to the presence of a joining portion while having a configuration in which semiconductor elements are joined in a state of being stacked on a lead frame. It is.

A first aspect of the present invention is a semiconductor device in which semiconductor elements are stacked on a lead frame, wherein the semiconductor element and the lead frame are joined to each other, and the semiconductor element and the lead frame in the joined part are joined covering only the surface of all sides not, and a, and a plating layer made of a low magnetic material than the material of the joint.

  According to the first invention, the high-frequency current component generated with the operation of the semiconductor element flows through the plating layer formed on the joint due to the skin effect. Since the plating layer is made of a material having a lower magnetic property than the material of the bonding portion, the self-inductance of the plating layer is smaller than the self-inductance of the bonding portion. Therefore, even if a high-frequency current component flows through the plating layer, a surge voltage is hardly generated. Thus, by providing the plating layer, the parasitic inductance generated due to the presence of the junction hardly affects the circuit.

  According to the present invention, there is provided a semiconductor device capable of reducing inductance parasitic to a circuit due to the presence of a joining portion while having a configuration in which semiconductor elements are joined in a state of being stacked on a lead frame. can do.

It is a figure which shows the structure of the semiconductor device which concerns on embodiment of this invention, Comprising: (a) is sectional drawing, (b) is a partial top view FIGS. 2A and 2B are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIGS. 6A and 6B are diagrams illustrating a semiconductor device according to a modification of the embodiment of the present invention, where FIG. 5A is a cross-sectional view illustrating a configuration of the semiconductor device, and FIG.

  Hereinafter, embodiments will be described in detail with reference to FIGS. 1 to 3.

[Configuration of semiconductor device]
FIG. 1 shows a configuration of a semiconductor device 1 according to the present embodiment. The semiconductor device 1 includes four stacked bodies including semiconductor elements. The semiconductor device 1 is a module that constitutes a pair of upper and lower arms provided in an inverter device of a vehicle, for example. As semiconductor elements, IGBT (Insulated Gate Bipolar Transistor) 10a, IGBT 10b, freewheeling diode 11a, and freewheeling diode 11b, which are power semiconductor elements processed into a chip, are mounted. The upper arm includes a stacked body 1A including the IGBT 10a and a stacked body including the free-wheeling diode 11a. The lower arm has a stacked body 1B including the IGBT 10b and a stacked body including the free-wheeling diode 11b.

  FIG. 1A shows a cross-sectional view of the semiconductor device 1 cut along a plane including the stacking direction and passing through the stacked body 1A and the stacked body 1B. FIG. 1B is a partial plan view of the semiconductor device 1 when viewed from a state where the stacked portion above each semiconductor element (above the line XX ′) is removed. . In the plan view, illustration of a mold resin 20 to be described later is omitted.

  The laminated body 1A has a configuration in which a lead frame La1, a joint portion Ba1, an IGBT 10a, a joint portion Ba2, a lead frame La2, a joint portion Ba3, and a lead frame La3 are laminated in this order. The laminated body 1B has a configuration in which a lead frame Lb1, a joint Bb1, an IGBT 10b, a joint Bb2, a lead frame Lb2, a joint Bb3, and a lead frame Lb3 are laminated in this order. Further, an extended lead La30 formed by extending the lead frame La3 of the laminated body 1A to the laminated body 1B side and an extended lead Lb10 formed by extending the lead frame Lb1 of the laminated body 1B to the laminated body 1A side are between each other. Are connected so as to sandwich the joint Bc.

  In addition, the semiconductor device 1 includes a plating layer WD that covers the side surfaces of the respective joints. In addition, the semiconductor device 1 includes a mold resin 20 that seals the entire connection structure between the stacked body 1A and the stacked body 1B and the plating layer WD.

  Each joint part joins to-be-joined bodies (semiconductor elements and lead frames) arranged on both sides in the stacking direction of the joint part. The joining portion Ba1 joins the lead frame La1 and the collector electrode of the semiconductor element 10a. The junction Ba2 joins the emitter electrode of the semiconductor element 10a and the lead frame La2. The joining portion Ba3 joins the lead frame La2 and the lead frame La3. The lead frame La2 connects the emitter electrode of the IGBT 10a and the anode electrode of the reflux diode 11a. The joint Bb1 joins the lead frame Lb1 and the collector electrode of the semiconductor element 10b. The junction Bb2 joins the emitter electrode of the semiconductor element 10b and the lead frame Lb2. The joint Bb3 joins the lead frame Lb2 and the lead frame Lb3. The lead frame Lb2 connects the emitter electrode of the IGBT 10b and the anode electrode of the reflux diode 11b.

  Similar to the stacked bodies 1A and 1B, the stacked body including the freewheeling diode 11a and the stacked body including the freewheeling diode 11b have a configuration in which the lead frame and the semiconductor element are bonded at the joint. Moreover, the plating layer WD which covers the side surface of each junction part is provided. The multilayer body including the free-wheeling diode 11a shares the multilayer body 1A and the lead frame La1 on the base surface 20z. The multilayer body including the free-wheeling diode 11b shares the multilayer body 1B and the lead frame Lb1 on the base surface 20z where the base of each multilayer body is located.

  Further, a lead frame La11, a lead frame Lb11, and a lead frame Lb31 are provided on the base surface 20z. The lead frame La11 is a lead formed by drawing the lead frame La1 to the outside of the mold resin 20, and the lead frame Lb11 is a lead formed by drawing the lead frame Lb1 to the outside of the mold resin 20. The lead frame Lb31 is a lead that is connected to the lead frame Lb3 beyond the stacking step and leads the lead frame Lb3 to the outside of the mold resin 20.

  A positive power supply voltage is applied to the lead frame La11, and a negative power supply voltage is applied to the lead frame Lb31. Further, an output to the load of the inverter device is drawn from the lead frame Lb11. Further, the semiconductor device 1 is provided with a lead pin 31A and a lead pin 31B which are drawn out from the mold resin 20 to the outside. Wire bonding is performed in the mold resin 20 between the IGBT 10a and the lead pin 31A and between the IGBT 10b and the lead pin 31B. The lead pin 31A and the lead pin 31B are used for transmission of a gate drive voltage and a temperature sensor signal.

  Each lead frame is made of, for example, copper. Each joint is formed from, for example, a nickel-based joint material. The plating layer WD is made of a material having a lower magnetic property than the material of the joint, that is, a material having a lower magnetic permeability than the material of the joint. The plating layer WD is made of a low magnetic metal having high conductivity, such as copper, silver, or gold. Each plating layer WD is in contact with the object to be joined on both sides in the stacking direction of the plating layer WD.

  When the IGBT is switched at high speed, a high-frequency current component flows in the circuit. The high frequency current component flows near the surface of the conductor due to the skin effect. The degree of the skin effect is expressed by the so-called skin depth at which the current has a predetermined attenuation compared to the magnitude on the surface. The skin depth decreases as the current frequency increases. For example, in the case of a copper conductor, the value is 8.57 mm at 60 Hz, 0.66 mm at 10 kHz, and 21 μm at 10 MHz. In the inverter device and the converter device, the switching speed is generally on the order of MHz or more. Therefore, if the plating layer WD is formed of copper to a thickness of about 10 μm that is employed in a normal copper plating process, almost all of the high-frequency current component that is biased to the surface side due to the skin effect flows through the plating layer WD.

[Method for Manufacturing Semiconductor Device]
Next, FIG. 2 shows a method for manufacturing the semiconductor device 1.

  First, as shown in FIG. 2A, each laminate described with reference to FIG. 1 is formed by pressure-bonding a bonding material between the objects to be bonded. Next, as shown in FIG. 2B, the plating layer WD is formed by plating the side surface, which is the exposed surface of each joint. At this time, a plating material having an ionization tendency smaller than the material of the bonding material and having an ionization tendency equal to or higher than the material of the lead frame is selected so that each lead frame is not plated. For example, when the material of the bonding material is nickel and the material of the lead frame is copper, copper is selected as the plating material. In addition, the plating material does not deposit on the semiconductor (silicon, silicon carbide) of the semiconductor element. In addition, when there are parts that can be plated such as guard ring electrodes on the semiconductor element and these parts are not to be plated, the part is protected by, for example, an oxide film or an organic film (for example, polyimide) during the plating process. do it.

  Then, wire bonding is performed between the IGBT 10a and the lead pin 31A and between the IGBT 10b and the lead pin 31B in the configuration formed in the process of FIG. By sealing each laminated body with the mold resin 20 after wire bonding, the semiconductor device 1 shown in FIG. 1A is obtained. In the sealing step, a primer or the like may be applied on the plating layer WD in order to enhance the adhesion between the plating layer WD and the mold resin 20.

[Effects of the embodiment, etc.]
According to the present embodiment, the high-frequency current component generated with the operation of the semiconductor element flows through the plating layer WD formed on the joint due to the skin effect. Since the plating layer WD is made of a material having a lower magnetic property than the material of the bonding portion, the self-inductance of the plating layer WD is smaller than the self-inductance of the bonding portion. For example, since the permeability of copper is about 1/180 of the permeability of nickel, the self-inductance proportional to the permeability is much smaller than that of nickel if the conductor dimensions are the same. Therefore, even if a high-frequency current component flows through the plating layer WD, a surge voltage is hardly generated. Thus, by providing the plating layer, the parasitic inductance generated due to the presence of the junction hardly affects the circuit. Also, efficient material consumption is possible by covering only necessary portions with a plating material of low magnetic material by a technique called plating.

[Modification]
FIG. 3 shows the configuration and manufacturing method of the semiconductor device 2 according to a modification of the present embodiment. The same members as those of the semiconductor device 1 are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 3A, the semiconductor device 2 includes a stacked body 1A 'and a stacked body 1B'. In the laminated body 1A ′, the lead frames La1, La2, and La3 of the laminated body 1A described in FIG. 1 are sequentially replaced with lead frames La1 ′, La2 ′, and La3 ′ whose surfaces are plated with nickel. It is a configuration. In the laminated body 1B ′, the lead frames Lb1, Lb2, and Lb3 of the laminated body 1B described in FIG. 1 are sequentially replaced with lead frames Lb1 ′, Lb2 ′, and Lb3 ′ whose surfaces are plated with nickel. It is a configuration. The lead frame of the laminated body including the reflux diode is similarly nickel-plated.

  In addition, the semiconductor device 2 includes a plating layer WE on the surface that is not involved in the bonding of each bonding portion and each lead frame. The surface that is not related to the bonding of the bonding portion is the same side surface as that of the semiconductor device 1 of FIG. That is, the semiconductor device 2 has a configuration in which a plating layer is added to the surface of the semiconductor device 1 that is not related to the joining of the lead frame. The plating layer WE is made of a material having a lower magnetic property than the material of the joint. The plating layer WE is made of a low magnetic metal having a high conductivity such as copper, silver, or gold.

  Next, a method for manufacturing the semiconductor device 2 will be described with reference to FIG. First, each laminated body is formed by a step of pressure-bonding a bonding material between bonded objects. Next, the plating layer WE is formed by plating the exposed surfaces of each joint and each lead frame. At this time, a plating material having an ionization tendency smaller than the material of the bonding material and the surface material of the lead frame is selected. Since the material of the surface of the lead frame is nickel, for example, when the material of the bonding material is nickel, copper, silver, or gold is selected as the plating material.

  Then, as described above, the semiconductor device 2 of FIG. 3A is obtained by sealing each laminated body with the mold resin 20 after wire bonding. In the sealing step, a primer or the like may be applied on the plating layer WE in order to enhance the adhesion between the plating layer WE and the mold resin 20.

  According to this modification, when a lead frame that is pre-plated with a magnetic material such as nickel is used, the high-frequency current component flows through the plating layer WE with a small self-inductance on the surface of the lead frame. Therefore, generation | occurrence | production of a surge voltage can be suppressed with the effect by the plating layer WE which covers a junction part.

  The embodiment has been described above. In the above, an example is shown in which four laminated bodies are provided so as to be adapted to the upper and lower combinations of the inverter arms, but it is sufficient that one or more laminated bodies are provided.

  The present invention can be applied to mounting of a semiconductor chip such as a power semiconductor.

1, 2 Semiconductor devices 1A, 1B, 1A ′, 1B ′ Stack 10a, 10b IGBT
20 Mold resin 20z Base surface 31A, 31B Lead pins 11a, 11b Reflux diodes Ba1, Ba2, Ba3, Bb1, Bb2, Bb3, Bc
Junction La1, La2, La3, Lb1, Lb2, Lb3, La1 ′, La2 ′, La3 ′, Lb1 ′, Lb2 ′, Lb3 ′, La11, Lb11, Lb31
Lead frame La30, Lb10 Stretched lead WD, WE Plating layer

Claims (1)

A semiconductor device in which semiconductor elements are stacked on a lead frame,
A joint for joining the semiconductor element and the lead frame;
A plating layer that covers only the surfaces of all the side surfaces that are not bonded to the semiconductor element and the lead frame of the bonding portion, and that is made of a material having a lower magnetic property than the material of the bonding portion. A semiconductor device.

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