JP2019212808A - Manufacturing method of semiconductor device - Google Patents

Abstract

To accurately control the spread of a solder on a conductor member.SOLUTION: A manufacturing method of a semiconductor device discloses in this specification includes a laser irradiation step of irradiating a laser to a first region of a metal film formed on a conductor member, and a soldering step of soldering a semiconductor element to a second region of the conductor member. In the laser irradiation step, a third region having lower solder wettability than the second region is formed adjacent to the second region due to adhesion of a scattered matter from the first region. Thus, in the soldering step, the third region adjacent to the second region suppresses the spread of the solder from the second region to the third region.SELECTED DRAWING: Figure 1

Description

  The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.

  Patent Document 1 discloses a semiconductor device. The semiconductor device includes a semiconductor element and a conductor member connected to the semiconductor element. In this semiconductor device, the semiconductor element and the conductor member are joined via a solder layer.

JP 2012-146760 A

  In general, in a soldering process of a semiconductor device, the semiconductor element and the conductor member are joined to each other by temporarily melting the solder disposed between the semiconductor element and the conductor member. At this time, a so-called fillet shape (a flared shape) is formed at the end of the solder layer, and this fillet angle (an angle of the fillet-shaped end) depends on the wet spread of the molten solder. Therefore, in order to control the fillet angle of the solder layer, it is necessary to control the wetting and spreading of the solder in the semiconductor element or conductor member.

  In particular, when the fillet angle of the solder layer on the semiconductor element side is unintentionally increased (90 degrees or more), the solder layer is thick on the semiconductor element along the outer peripheral edge of the solder layer. Usually, the outer peripheral edge of the solder layer is formed along the outer peripheral edge of the electrode of the semiconductor element, and there are multiple points where two or more different materials (for example, the electrode material and the protective film material) contact each other Exists. If the solder layer is thick on such multiple points of the semiconductor element, a large stress may locally act on the semiconductor element from the solder layer when the semiconductor device is used. In order to avoid such a problem, it is necessary to limit the fillet angle of the solder layer on the semiconductor element side. For that purpose, it is necessary to accurately control the wetting and spreading of the solder in the conductor member. The present specification provides a technique that can accurately control the wetting and spreading of solder in a conductor member.

  A semiconductor device manufacturing method disclosed in this specification includes a laser irradiation step of irradiating a first region of a metal film formed on a conductor member with a laser, and soldering for soldering a semiconductor element to the second region of the conductor member. A process. In the laser irradiation step, a third region having a lower solder wettability than the second region is formed adjacent to the second region due to adhesion of scattered matter from the first region. As a result, in the soldering process, the third region adjacent to the second region suppresses the spread of the solder from the second region to the third region.

  In the manufacturing method described above, the laser is irradiated to the first region of the metal film formed on the conductor member. By this laser irradiation, the first region of the metal film is roughened (that is, a fine uneven shape is formed), and the solder wettability is lowered. At this time, also in the third region adjacent to the first region, the solder wettability simultaneously decreases due to the adhesion of scattered matter from the first region. Therefore, in order to accurately control the wetting and spreading of the solder, it is necessary to determine the first region to be irradiated with laser in consideration of the formation of such a third region. In this regard, in the manufacturing method disclosed in this specification, the third region to which the scattered matter adheres with laser irradiation is formed adjacent to the second region to which the semiconductor element is subsequently soldered. Then, the first region for laser irradiation is determined. Thereby, when the semiconductor element is soldered to the second region, the third region adjacent to the second region suppresses the wetting and spreading of the solder from the second region to the third region. According to such a configuration, it is possible to accurately control the wetting and spreading of the solder in the conductor member.

Sectional drawing which shows the internal structure of the semiconductor device 10 of an Example. The enlarged view of the II section in FIG. FIG. 6 is a bottom perspective view of the upper heat sink 22. The bottom view which shows the laser irradiation area | region of the upper side heat sink. FIG. 4 is a top perspective view of the lower heat sink 24. FIG. 6 is a top view showing a laser irradiation region of the lower heat sink 24. A comparative example in the case where the fillet angle of the solder layer 42 is 90 degrees or more is shown. The schematic diagram which shows a 1st soldering process. The schematic diagram which shows a 2nd soldering process.

  With reference to the drawings, a semiconductor device 10 of an embodiment and a manufacturing method thereof will be described. As shown in FIG. 1, the semiconductor device 10 includes a first semiconductor element 20, a second semiconductor element 40, an upper radiator plate 22, a lower radiator plate 24, and a sealing body 12. The first semiconductor element 20 and the second semiconductor element 40 are sealed inside the sealing body 12. Although the sealing body 12 is not specifically limited, For example, it is comprised with thermosetting resins, such as an epoxy resin.

  The first semiconductor element 20 has a front electrode 20a and a back electrode 20b. The front electrode 20 a is located on the upper surface of the first semiconductor element 20, and the rear electrode 20 b is located on the lower surface of the first semiconductor element 20. The first semiconductor element 20 is a vertical semiconductor element having a pair of upper and lower electrodes 20a and 20b. The second semiconductor element 40 also has a front electrode 40a and a back electrode 40b. The front electrode 40 a is located on the lower surface of the second semiconductor element 40, and the rear electrode 40 b is located on the upper surface of the second semiconductor element 40. The second semiconductor element 40 is a vertical semiconductor element having a pair of upper and lower electrodes 40a and 40b. Although it does not specifically limit to the material which comprises the electrodes 20a and 20b of the 1st semiconductor element 20, and the electrodes 40a and 40b of the 2nd semiconductor element 40, For example, an aluminum type or another metal is employable. Although it is an example, the 1st semiconductor element 20 and the 2nd semiconductor element 40 are inserted between the upper side heat sink 22 and the lower side heat sink 24 in the posture turned upside down mutually.

  The first semiconductor element 20 and the second semiconductor element 40 in the present embodiment are the same type of semiconductor elements. Specifically, the first semiconductor element 20 and the second semiconductor element 40 are RC-IGBT (Reverse Conducting IGBT) elements including an IGBT (Insulated Gate Bipolar Transistor) and a diode. is there. However, each of the first semiconductor element 20 and the second semiconductor element 40 is not limited to the RC-IGBT element, and may be another power semiconductor element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) element. Good. Alternatively, each of the first semiconductor element 20 and the second semiconductor element 40 may be replaced with two or more semiconductor elements such as a diode element and an IGBT element (or a MOSFET element). Specific configurations of the first semiconductor element 20 and the second semiconductor element 40 are not particularly limited, and various semiconductor elements can be employed. In this case, the first semiconductor element 20 and the second semiconductor element 40 may be different semiconductor elements. Each of the first semiconductor element 20 and the second semiconductor element 40 can be configured using various semiconductor materials such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN).

  As shown in FIG. 2, the first semiconductor element 20 includes a protective film 50 on the upper surface (surface electrode 20 a side). The protective film 50 is a resin material having an insulating property, and is made of, for example, polyimide. The protective film 50 has a function of maintaining the withstand voltage of the first semiconductor element 20 and a function of preventing foreign matter from coming into contact with the first semiconductor element 20. The protective film 50 extends in a frame shape along the outer peripheral edge of the first semiconductor element 20 and surrounds the surface electrode 20a. The same applies to the second semiconductor element 40, and a protective film is provided on the lower surface (surface electrode 40 a side), and the surface electrode 40 a is surrounded by the protective film.

  The semiconductor device 10 further includes an upper radiator plate 22 and a lower radiator plate 24. As shown in FIGS. 1 and 3, the upper radiator plate 22 includes an insulating substrate 30, a first inner conductor layer 26, a second inner conductor layer 28, and an outer conductor layer 32. The first inner conductor layer 26 is located on one side of the insulating substrate 30 and is electrically connected to the surface electrode 20 a of the first semiconductor element 20 via the solder layer 42. The second inner conductor layer 28 is located on one side of the insulating substrate 30 and is electrically connected to the back electrode 40 b of the second semiconductor element 40 through the solder layer 46. The outer conductor layer 32 is located on the other side of the insulating substrate 30. The first inner conductor layer 26 and the outer conductor layer 32 and the second inner conductor layer 28 and the outer conductor layer 32 are insulated from each other by the insulating substrate 30. Metal films 27 and 29 are formed on the surfaces of the first inner conductor layer 26 and the second inner conductor layer 28. The metal films 27 and 29 are made of, for example, a material containing nickel as a main component (including pure nickel), and can be formed by a sputtering method as an example.

  As shown in FIG. 4, each inner conductor layer 26, 28 has a first region A1, a second region A2, and a third region A3. The first region A1 is a region irradiated with a laser and is a region where the metal films 27 and 29 are roughened and oxidized. The second region A2 is a region joined to the semiconductor elements 20 and 40 via the solder layers 42 and 46. The third region A3 is located between the first region A1 and the second region A2, and is adjacent to the second region A2. 3rd area | region A3 is an area | region where the scattering material (for example, nickel oxide) from 1st area | region A1 adhered in the laser irradiation process with respect to 1st area | region A1. The first region A1 and the third region A3 have a relatively low solder wettability compared to the second region A2, and are provided to suppress the spread of the solder in the soldering process described later. Yes.

  As shown in FIGS. 1 and 5, the lower heat sink 24 includes an insulating substrate 36, an inner conductor layer 34, and an outer conductor layer 38. The inner conductor layer 34 is located on one side of the insulating substrate 36, is connected to the back electrode 20 b of the first semiconductor element 20 via the solder layer 44, and is a surface electrode of the second semiconductor element 40 via the solder layer 48. 40a is electrically connected to each other. The outer conductor layer 38 is located on the other side of the insulating substrate 36. The inner conductor layer 34 and the outer conductor layer 38 are insulated from each other by the insulating substrate 36. A metal film 35 is formed on the surface of the inner conductor layer 34. The metal film 35 is made of, for example, a material containing nickel as a main component (including pure nickel), and can be formed by a sputtering method as an example.

  As shown in FIG. 6, the second inner conductor layer 34 of the lower radiator plate 24 also has a first region A1, a second region A2, and a third region A3. The first region A1 is a region irradiated with a laser, and is a region where the metal film 35 is roughened and oxidized. The second region A2 is a region joined to the semiconductor elements 20 and 40 via the solder layers 44 and 48. The third region A3 is located between the first region A1 and the second region A2, and is adjacent to the second region A2. 3rd area | region A3 is an area | region where the scattering material (for example, nickel oxide) from 1st area | region A1 adhered in the laser irradiation process with respect to 1st area | region A1. Also in the lower heat sink 24, the first region A1 and the third region A3 have relatively low solder wettability compared to the second region A2, and the solder wets and spreads in the soldering process described later. It is provided to suppress this.

  As an example, a DBC (Direct Bonded Copper) substrate can be employed for the upper heat sink 22 and the lower heat sink 24 in the present embodiment. The insulating substrates 30 and 36 of the upper radiator plate 22 and the lower radiator plate 24 are made of ceramic such as aluminum oxide, silicon nitride, aluminum nitride, or the like. The inner conductor layers 26, 28, 34 and the outer conductor layers 32, 38 of the upper heat sink 22 and the lower heat sink 24 are made of copper. The upper radiator plate 22 and the lower radiator plate 24 are examples of conductor members in the technology disclosed in this specification. The upper radiator plate 22 and the lower radiator plate 24 are not limited to the DBC substrate. The inner conductor layers 26, 28, 34 and the outer conductor layers 32, 38 are not limited to copper, and may be composed of other metals. And also about the junction structure between the insulating substrate 30 of the upper radiator plate 22 and each conductor layer 26, 28, 32 and between the insulating substrate 36 of the lower radiator plate 24 and each conductor layer 34, 38, There is no particular limitation. The upper radiator plate 22 and the lower radiator plate 24 may be, for example, a DBA (Direct Bonded Aluminum) substrate, or may be a conductor plate without the insulating substrates 30 and 36.

  The outer conductor layer 32 of the upper radiator plate 22 is exposed on the upper surface 12 a of the sealing body 12. Accordingly, the upper heat sink 22 not only constitutes a part of the semiconductor device 10 but also functions as a heat sink that releases the heat of the first semiconductor element 20 and the second semiconductor element 40 to the outside. Similarly, the outer conductor layer 38 of the lower heat radiating plate 24 is exposed on the lower surface 12 b of the sealing body 12. Thereby, the lower heat sink 24 not only constitutes a part of the electric circuit of the semiconductor device 10, but also functions as a heat sink that releases the heat of the first semiconductor element 20 and the second semiconductor element 40 to the outside. . As described above, the semiconductor device 10 according to the present embodiment has a double-sided cooling structure in which the outer conductor layer 32 of the upper radiator plate 22 and the outer conductor layer 38 of the lower radiator plate 24 are exposed on both surfaces 12a and 12b of the sealing body 12. Have However, the semiconductor device 10 is not limited to the double-sided cooling structure, and has a single-sided cooling structure in which the outer conductor layer 32 of the upper radiator plate 22 or the outer conductor layer 38 of the lower radiator plate 24 is exposed from the sealing body 12. Also good.

  As shown in FIG. 2, on the upper surface of the first semiconductor element 20, the outer peripheral edge of the solder layer 42 is in contact with both the surface electrode 20 a and the protective film 50. Multiple points of contact are formed. Since the plurality of materials forming the multiple points have different linear expansion coefficients, when the semiconductor device 10 operates and generates heat, the amounts of thermal expansion generated in them also differ from each other. Therefore, a large stress is likely to act on the multiple points. In particular, if the solder layer 42 is thick on the multiple points, a large stress may locally act on the first semiconductor element 20 from the solder layer 42. In order to avoid such a problem, the semiconductor device 10 of this embodiment is designed so that the fillet angle on the first semiconductor element 20 side of the solder layer 42 is less than 90 degrees. Similarly, on the lower surface (front electrode 40a side) of the second semiconductor element 40, the fillet angle on the second semiconductor element 40 side of the solder layer 48 is designed to be less than 90 degrees.

  On the other hand, for example, as shown in FIG. 7, it is assumed that the fillet angle of the solder layer 42 on the first semiconductor element 20 side is 90 degrees or more. In this case, the solder layer 42 exists thickly on the first semiconductor element 20 along the outer peripheral edge of the solder layer 42. As described above, at the position of the outer peripheral edge of the solder layer 42, there are multiple points where two or more different materials come into contact with each other. Therefore, when the fillet angle is 90 degrees or more, the solder layer 42 exists thickly on the multiple points, and a large stress may be locally applied from the solder layer 42 to the first semiconductor element 20. Therefore, the fillet angle of the solder layer 42 (and the solder layer 48) is preferably less than 90 degrees.

  In addition, if the fillet angle of the solder layer 42 on the first semiconductor element 20 side is less than 90 degrees, it is advantageous in terms of insulation between the first semiconductor element 20 and the first inner conductor layer 26. For example, when the fillet angle of the solder layer 42 exceeds 90 degrees, the solder layer 42 protrudes above the protective film 50 of the first semiconductor element 20. The region where the protective film 50 of the first semiconductor element 20 is provided, that is, the peripheral region of the first semiconductor element 20 is a breakdown voltage holding region, and when the first semiconductor element 20 is turned off, its potential is relatively low. Can be expensive. When the solder layer 42 protrudes from such a withstand voltage holding region, the spatial distance between the withstand voltage holding region and the solder layer 42 is shortened, and the insulation between them is lowered. On the other hand, if the fillet angle of the solder layer 42 is less than 90 degrees, a spatial distance between the pressure-resistant holding region and the solder layer 42 is ensured, so that the insulation between the two is avoided. be able to.

  Next, a method for manufacturing the semiconductor device 10 will be described with reference to FIGS. This manufacturing method includes a laser irradiation process, a first soldering process, and a second soldering process. In the laser irradiation step, the upper heat radiating plate 22 and the lower heat radiating plate 24 are prepared, and the inner conductor layers 26, 28, and 34 are irradiated with laser. As described above, the laser is applied to the first region A1 of the inner conductor layers 26, 28, and 34 (see FIGS. 4 and 6). Thereby, the first region A1 is roughened (that is, a fine uneven shape is formed), and the solder wettability in the first region A1 is lowered. At this time, also in the third region A3 close to the first region A1, the solder wettability simultaneously decreases due to the scattered matter from the first region A1 resulting from the laser irradiation. In order to accurately control the wetting and spreading of the solder in the soldering process described later, the first region A1 to be irradiated with the laser is determined in consideration of the formation of the third region A3. There is a need.

  In this regard, in the manufacturing method of the present embodiment, the third region A3 to which scattered matter adheres with laser irradiation is formed adjacent to the second region A2 to which the semiconductor elements 20 and 40 are soldered thereafter. As described above, the first region A1 to be irradiated with laser is determined. Thereby, when the semiconductor elements 20 and 40 are soldered to the second region A2, the third region A3 adjacent to the second region A2 spreads the solder from the second region A2 to the third region A3. It is suppressed. According to such a configuration, it is possible to accurately control the wetting and spreading of the solder in the inner conductor layers 26, 28, and 34, and to ensure that the aforementioned fillet angle of the solder layers 42 and 48 is less than 90 degrees. That is, for the solder layer 42 between the first inner conductor layer 26 of the upper radiator plate 22 and the first semiconductor element 20, the second region A2 where the solder layer 42 is in contact with the first inner conductor layer 26 is defined as a solder layer. 42 can be disposed inside the region in contact with the first semiconductor element 20. With respect to the solder layer 48 between the inner conductor layer 34 of the lower heat sink 24 and the second semiconductor element 40, the solder layer 48 is in the second region A2 in contact with the inner conductor layer 34, and the solder layer 48 is in the second semiconductor. It can be arranged inside a region in contact with the element 40.

  Next, as shown in FIG. 8, a first soldering step is performed. In the first soldering step, the first semiconductor element 20 and the second semiconductor element 40 are soldered to the two second regions A2 of the inner conductor layer 34 of the lower heat sink 24. Specifically, the back electrode 20b of the first semiconductor element 20 is soldered to one second region A2, and the surface electrode 40a of the second semiconductor element 40 is soldered to the other second region A2. The specific method of the first soldering process is not particularly limited. In the present embodiment, solder 44 is disposed between the first semiconductor element 20 and the inner conductor layer 34, solder 48 is disposed between the second semiconductor element 40 and the inner conductor layer 34, and the solder 44, 48 is temporarily melted in a reflow oven. The melted solders 44 and 48 are suppressed from spreading from the second region A2 to the third region A3 by the third region A3 adjacent to the second region A2. In addition, since the solders 44 and 48 constitute the solder layers 44 and 48 described above, the same reference numerals are given here.

  Next, as shown in FIG. 9, a second soldering step is performed. In the second soldering step, the inner conductor layers 26 and 28 of the upper radiator plate 22 are soldered to the first semiconductor element 20 and the second semiconductor element 40, respectively. Specifically, the surface electrode 20a of the first semiconductor element 20 is soldered to the second region A2 of the first inner conductor layer 26, and the back surface of the second semiconductor element 40 is bonded to the second region A2 of the second inner conductor layer 28. The electrode 40b is soldered. The specific method of the second soldering process is not particularly limited. In this embodiment, the solder 42 is disposed between the first semiconductor element 20 and the first inner conductor layer 26, and the solder 46 is disposed between the second semiconductor element 40 and the second inner conductor layer 28. The solders 42 and 46 are temporarily melted in a reflow furnace. The melted solders 42 and 46 are prevented from spreading from the second region A2 to the third region A3 by the third region A3 adjacent to the second region A2. In addition, since the solders 42 and 46 comprise the solder layers 42 and 46 mentioned above, the same code | symbol is attached | subjected here.

  As described above, the manufacturing method of the present embodiment includes a laser irradiation step of irradiating the first region (A1) of the metal film (27, 29, 35) formed on the conductor member (22, 24) with a laser, A soldering step of soldering the semiconductor elements (20, 40) to the second region (A2) of the conductor member. In the laser irradiation step, the third region (A3) having lower solder wettability than the second region (A2) is formed adjacent to the second region due to adhesion of scattered matter from the first region (A1). . Thereby, in the soldering step, the wetting and spreading of the solder (42, 44, 46, 48) from the second region to the third region is suppressed by the third region adjacent to the second region.

  As described above, each of the first regions A1 of the metal films 27, 29, and 35 formed on the inner conductor layers 26, 28, and 34 of the heat sinks 22 and 24 of the present embodiment is roughened in the laser irradiation process. It has become. In other words, fine irregularities are formed in the first region A1 of the metal films 27, 29, and 35 by laser irradiation. This fine uneven shape improves the adhesion between the upper radiator plate 22 and the lower radiator plate 24 and the sealing body 12 by an anchor effect.

  Several specific examples have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations.

10: Semiconductor device 12: Sealing body 20, 40: Semiconductor element 20a, 40a: Front electrode 20b, 40b: Back electrode 22: Upper radiator plate 24: Lower radiator plate 26: First inner conductor layer 27 of the upper radiator plate , 29, 35: metal film 28: second inner conductor layer 30 of the upper radiator plate 30: insulating substrate 32 of the upper radiator plate: outer conductor layer 34 of the upper radiator plate: inner conductor layer 36 of the lower radiator plate: lower radiation Insulating substrate 38 of plate: Outer conductor layer 42, 44, 46, 48 of lower heat sink: Solder (layer)
50: Protective film A1: First region A2: Second region A3: Third region

Claims (1)

A laser irradiation step of irradiating the first region of the metal film formed on the conductor member with a laser;
A soldering step of soldering a semiconductor element to the second region of the conductor member;
With
In the laser irradiation step, a third region having lower solder wettability than the second region is formed adjacent to the second region due to adhesion of scattered matter from the first region,
In the soldering step, the third region adjacent to the second region suppresses the spread of solder from the second region to the third region.
A method for manufacturing a semiconductor device.

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