JP7106891B2 - semiconductor equipment - Google Patents

Description

The technology disclosed in this specification relates to a semiconductor device.

Patent Document 1 discloses a semiconductor device. This semiconductor device includes a semiconductor element, and an upper heatsink and a lower heatsink facing each other with the semiconductor element interposed therebetween. The upper heatsink is formed by bonding a laminate including a semiconductor element and a lower heatsink via a solder layer. The upper heat sink is provided with solder absorption grooves along the perimeter of the solder joint areas where the solder layers contact. This solder absorption groove accommodates excess solder of the solder layer during soldering between the upper heat sink and the laminate.

Japanese Patent Application Laid-Open No. 2007-103909

As exemplified in the above-described upper heat sink and laminate, when soldering two members, if a solder absorption groove is provided along the periphery of the solder joint area, excess solder can be absorbed into the solder absorption groove. can be accommodated in However, since there are individual differences in the amount of surplus solder, for example, when the amount of surplus solder is relatively small, the surplus solder is accommodated only in some sections of the solder absorption grooves. In this case, part of the peripheral edge of the solder joint area is positioned inside the solder absorption groove, and the other part is positioned outside the solder absorption groove. fillet shape) can be very different. Here, when the solder melts between the two members, an adsorption force caused by the surface tension of the melted solder acts between the two members. The magnitude of this attraction force changes according to the contact angle of the solder. Therefore, in a state in which excessive solder is contained only in a portion of the solder absorbing groove, the adsorption force acting between the two members is unevenly generated. As a result, the relative positions and attitudes of the two members change, possibly degrading the dimensional accuracy of the semiconductor device. In particular, if the contact angles of the solder (that is, the attraction force generated) are different between the two sides facing each other in the peripheral edge of the solder joint area, the relative positions and postures of the two members are likely to change, and the size of the semiconductor device is affected. Accuracy tends to be significantly degraded. This specification provides a technique capable of suppressing the occurrence of such events and improving the dimensional accuracy of a semiconductor device.

A semiconductor device disclosed in this specification includes a first member and a second member bonded to the first member via a solder layer. The first member is provided with a solder absorbing groove containing excess solder of the solder layer. When the range in contact with the solder layer of the first member is defined as a solder joint area, of the peripheral edge of the solder joint area, two sides that face each other in the first direction are located in the solder absorption groove and face each other in the second direction. The other two sides are located outside the solder absorption groove.

In the semiconductor device described above, of the peripheral edge of the solder joint area, two opposing sides are positioned within the solder absorbing groove, and the other two opposing sides are positioned outside the solder absorbing groove. According to such a configuration, when the two members are soldered, the positions where the excess solder is accommodated in the solder absorption grooves are limited to the two opposite sides of the solder joint area. Therefore, even if the amount of surplus solder fluctuates to a certain extent, the surplus solder is uniformly accommodated in the solder absorption grooves on the two sides, and the contact angles of the solder are substantially equal. On the other hand, the other two opposite sides of the solder joint area are located outside the solder absorption grooves, so that the contact angles of the solder are substantially equal. Since the contact angles of the solder are substantially equal on each of the two opposing sides of the solder joint area, changes in the relative positions and postures of the two members are suppressed, and the dimensional accuracy of the semiconductor device is improved.

1 is a plan view of a semiconductor device 10 of an embodiment; FIG. 2 is a plan view showing the internal structure of the semiconductor device 10; FIG. FIG. 2 is a cross-sectional view showing the internal structure taken along line III-III of FIG. 1; FIG. 2 is a cross-sectional view showing the internal structure taken along line IV-IV of FIG. 1; FIG. 4 is a bottom view of the first upper heat sink 22 and schematically shows a state in which it is in contact with the solder layers 23 and 50; A step of simultaneously soldering the laminate having the first conductor spacer 24 and the second joint portion 46c of the second lower heat sink 46 onto the first upper heat sink 22 is shown. It is a bottom view of the modification of the 1st upper side heat sink 22, and shows typically the state contacting the solder layer 23. FIG. It is a bottom view of the modification of the 1st upper side heat sink 22, and shows typically the state contacting the solder layer 23. FIG.

In one embodiment of the present technology, the semiconductor device may further include a third member bonded to the first member via a second solder layer. In this case, when the range in contact with the second solder layer of the first member is defined as the second solder joint area, at least part of the second solder joint area is positioned in the first direction with respect to the first solder joint area. do it. In soldering the first member and the second member, for example, when the amount of surplus solder is extremely small, the surplus solder is uniformly distributed to the solder absorption grooves on two sides of the solder joint area facing the first direction. They may not be accommodated. In this case, the adsorption force caused by the surface tension of the solder acts unevenly between the two sides facing each other in the first direction, possibly changing the relative positions and postures of the two members. At this time, if the third member is soldered to the second solder joint area of the first member at the same time, the adsorption force caused by the surface tension of the solder also acts on the second solder joint area. Since the second solder-bonding area is positioned in the first direction with respect to the first solder-bonding area, the adsorption force of the solder acting on the second solder-bonding area has the effect of changing the position and orientation of the first member. can be effectively suppressed.

A semiconductor device 10 of an embodiment will be described with reference to the drawings. The semiconductor device 10 of this embodiment can be used in power conversion circuits such as converters and inverters in electric vehicles such as electric vehicles, hybrid vehicles, and fuel cell vehicles. However, the application of the semiconductor device 10 is not particularly limited. The semiconductor device 10 can be widely used in various devices and circuits.

As shown in FIGS. 1 to 4, the semiconductor device 10 includes a first semiconductor element 20, a second semiconductor element 40, a sealing body 12, and a plurality of external connection terminals 14, 15, 16, 18, and 19. Prepare. The first semiconductor element 20 and the second semiconductor element 40 are sealed inside the sealing body 12 . Although not particularly limited, the sealing body 12 is made of a thermosetting resin such as an epoxy resin, for example. Each of the external connection terminals 14 , 15 , 16 , 18 , 19 extends from the outside to the inside of the sealing body 12 and connects the first semiconductor element 20 and the second semiconductor element 40 inside the sealing body 12 . It is electrically connected to at least one. As an example, the plurality of external connection terminals 14, 15, 16, 18, and 19 include a P terminal 14, an N terminal 15, and an O terminal 16 for electric power, and a plurality of first signal terminals 18 for signals. and a plurality of second signal terminals 19 .

The first semiconductor element 20 has an upper surface electrode 20a and a lower surface electrode 20b. The upper electrode 20 a is located on the upper surface of the first semiconductor element 20 , and the lower electrode 20 b is located on the lower surface of the first semiconductor element 20 . The first semiconductor element 20 is a vertical semiconductor element having a pair of upper and lower electrodes 20a and 20b. Similarly, the second semiconductor element 40 has an upper surface electrode 40a and a lower surface electrode 40b. The upper electrode 40 a is located on the upper surface of the second semiconductor element 40 , and the lower electrode 40 b is located on the lower surface of the second semiconductor element 40 . That is, the second semiconductor element 40 is also a vertical semiconductor element having a pair of upper and lower electrodes 40a and 40b. The first semiconductor element 20 and the second semiconductor element 40 in this embodiment are semiconductor elements of the same type, and more specifically, are RC-IGBT (Reverse Conducting IGBT) elements incorporating an IGBT (Insulated Gate Bipolar Transistor) and a diode. be.

However, each of the first semiconductor element 20 and the second semiconductor element 40 is not limited to an RC-IGBT element, and may be another power semiconductor element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) element. good. Alternatively, each of the first semiconductor element 20 and the second semiconductor element 40 may be replaced with two or more semiconductor elements such as a diode element and an IGBT element (or MOSFET element). The specific configurations of the first semiconductor element 20 and the second semiconductor element 40 are not particularly limited, and various semiconductor elements can be employed. In this case, the first semiconductor device 20 and the second semiconductor device 40 may be different semiconductor devices. Also, each of the first semiconductor element 20 and the second semiconductor element 40 can be configured using various semiconductor materials such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). The material forming the upper surface electrode 20a and the lower surface electrode 20b of the first semiconductor element 20 is not particularly limited, but aluminum-based or other metals, for example, can be used. Similarly, the material forming the upper surface electrode 40a and the lower surface electrode 40b of the second semiconductor element 40 is not particularly limited, but aluminum-based or other metals, for example, can be used.

The semiconductor device 10 further includes a first upper heat sink 22 , a first conductor spacer 24 and a first lower heat sink 26 . The first conductor spacer 24 is made of a conductive material such as copper or other metal. The first conductor spacer 24 is generally a plate-shaped or block-shaped member and has an upper surface 24a and a lower surface 24b located on the opposite side of the upper surface 24a. A first conductor spacer 24 is located within the encapsulant 12 . The upper surface 24 a of the first conductor spacer 24 is bonded to the first upper heat sink 22 via the solder layer 23 . The lower surface 24b of the first conductor spacer 24 is joined to the upper surface electrode 20a of the first semiconductor element 20 via the solder layer 25. As shown in FIG. That is, the first conductor spacer 24 is electrically connected to the first semiconductor element 20 . The first conductor spacer 24 secures space when connecting the first signal terminal 18 to the first semiconductor element 20, although it is not absolutely necessary. The first conductor spacer 24 is an example of the second member in the technology disclosed in this specification.

The first upper heatsink 22 and the first lower heatsink 26 are made of a material with excellent thermal conductivity, such as copper, aluminum, or other metals. The first upper radiator plate 22 is generally a rectangular parallelepiped or plate-shaped member, and has an upper surface 22a and a lower surface 22b located on the opposite side of the upper surface 22a. The upper surface 22 a of the first upper heat sink 22 is exposed to the outside at the upper surface 12 a of the sealing body 12 . The lower surface 22b of the first upper heat sink 22 is joined to the upper surface 24a of the first conductor spacer 24 via a solder layer 23. As shown in FIG. That is, the first upper radiator plate 22 is electrically and thermally connected to the first semiconductor element 20 via the first conductor spacers 24 . Thereby, the first upper heat radiation plate 22 not only constitutes a part of the electric circuit of the semiconductor device 10, but also functions as a heat radiation plate for radiating the heat of the first semiconductor element 20 to the outside. Here, the first upper radiator plate 22 is an example of the first member in the technology disclosed in this specification.

The first lower radiator plate 26 is generally a rectangular parallelepiped or plate-shaped member, and has an upper surface 26a and a lower surface 26b located on the opposite side of the upper surface 26a. A lower surface 26 b of the first lower heat sink 26 is exposed to the outside at the lower surface 12 b of the sealing body 12 . Also, the upper surface 26 a of the first lower heat sink 26 is joined to the lower surface electrode 20 b of the first semiconductor element 20 via a solder layer 27 . That is, the first lower radiator plate 26 is electrically and thermally connected to the first semiconductor element 20 . As a result, the first lower radiator plate 26 not only constitutes a part of the electric circuit of the semiconductor device 10, but also functions as a radiator plate for radiating the heat of the first semiconductor element 20 to the outside. Thus, the semiconductor device 10 of this embodiment has a double-sided cooling structure in which the first upper heat sink 22 and the first lower heat sink 26 are exposed on both surfaces 12 a and 12 b of the sealing body 12 .

The semiconductor device 10 further includes a second upper heat sink 42 , a second conductor spacer 44 , and a second lower heat sink 46 . The second conductor spacer 44 is made of a conductive material such as copper or other metal. The second conductor spacer 44 is generally a plate-shaped or block-shaped member and has an upper surface 44a and a lower surface 44b located on the opposite side of the upper surface 44a. A second conductor spacer 44 is located within the encapsulant 12 . The upper surface 44 a of the second conductor spacer 44 is joined to the second upper heat sink 42 via the solder layer 43 . The lower surface 44b of the second conductor spacer 44 is joined to the upper surface electrode 40a of the second semiconductor element 40 via the solder layer 45. As shown in FIG. That is, the second conductor spacer 44 is electrically connected to the second semiconductor element 40 . The second conductor spacer 44 secures a space when connecting the second signal terminal 19 to the second semiconductor element 40, although it is not necessarily required.

The second upper heatsink 42 and the second lower heatsink 46 are made of a material with excellent thermal conductivity, such as copper, aluminum, or other metals. The second upper radiator plate 42 is generally a rectangular parallelepiped or plate-shaped member, and has an upper surface 42a and a lower surface 42b located on the opposite side of the upper surface 42a. The upper surface 42 a of the second upper heat sink 42 is exposed to the outside at the upper surface 12 a of the sealing body 12 . The lower surface 42b of the second upper heat sink 42 is joined to the upper surface 44a of the second conductor spacer 44 via a solder layer 43. As shown in FIG. That is, the second upper radiator plate 42 is electrically and thermally connected to the second semiconductor element 40 via the second conductor spacers 44 . Thereby, the second upper heat radiation plate 42 not only constitutes a part of the electric circuit of the semiconductor device 10, but also functions as a heat radiation plate for radiating the heat of the second semiconductor element 40 to the outside.

The second lower radiator plate 46 is a generally rectangular parallelepiped or plate-shaped member, and has an upper surface 46a and a lower surface 46b located on the opposite side of the upper surface 46a. The lower surface 46 b of the second lower heat sink 46 is exposed to the outside at the lower surface 12 b of the sealing body 12 . Also, the upper surface 46 a of the second lower heat sink 46 is joined to the lower surface electrode 40 b of the second semiconductor element 40 via a solder layer 47 . That is, the second lower radiator plate 46 is electrically and thermally connected to the second semiconductor element 40 . As a result, the second lower radiator plate 46 not only constitutes a part of the electric circuit of the semiconductor device 10, but also functions as a radiator plate for radiating the heat of the second semiconductor element 40 to the outside. Thus, the semiconductor device 10 of this embodiment has a double-sided cooling structure in which the second upper heat sink 42 and the second lower heat sink 46 are exposed on both surfaces 12 a and 12 b of the sealing body 12 . The second lower radiator plate 46 is connected to the first upper radiator plate 22 via a first joint portion 22c and a second joint portion 46c, which will be described later. The second lower radiator plate 46 is an example of the third member in the technology disclosed in this specification.

As described above, the semiconductor device 10 has the P terminal 14, the N terminal 15 and the O terminal 16 as external connection terminals. The P terminal 14, N terminal 15 and O terminal 16 in this embodiment are made of copper. However, the P terminal 14, the N terminal 15 and the O terminal 16 are not limited to copper, and may be made of other conductors. The P terminal 14 is connected to the upper surface 26 a of the first lower heat sink 26 inside the sealing body 12 . The N terminal 15 is connected to the lower surface 42 b of the second upper heat sink 42 inside the sealing body 12 . The O terminal 16 is connected to the upper surface 46 a of the second lower heat sink 46 . As an example, the P terminal 14 and the O terminal 16 are formed integrally with the first lower heat radiation plate 26 and the second lower heat radiation plate 46, respectively. However, one or both of the P terminal 14 and the O terminal 16 may be joined to the first lower radiator plate 26 and the second lower radiator plate 46, respectively, by welding, for example. The N terminal 15 is soldered to the joint portion 42c of the second upper heat sink 42, as will be described later. The semiconductor device 10 also includes a plurality of first signal terminals 18 and a plurality of second signal terminals 19 as external connection terminals. The plurality of signal terminals 18 and 19 in this embodiment are connected to the first semiconductor element 20 and the second semiconductor element 40 by bonding wires 18a and 19a, respectively.

As shown in FIGS. 2, 3, and 5, the first upper heat sink 22 of the semiconductor device 10 further has a first joint portion 22c made of a conductor. Similarly, the second lower radiator plate 46 further has a second joint portion 46c made of a conductor. The first joint portion 22 c and the second joint portion 46 c are located inside the sealing body 12 . The first joint portion 22c of the first upper heat radiation plate 22 is joined to the second joint portion 46c of the second lower heat radiation plate 46 with a solder layer 50 interposed therebetween. That is, the first joint portion 22 c and the second joint portion 46 c electrically connect the first upper heat radiation plate 22 and the second lower heat radiation plate 46 . Thereby, the first semiconductor element 20 and the second semiconductor element 40 are connected in series via the first joint portion 22c and the second joint portion 46c. The first joint portion 22c and the second joint portion 46c can be made of copper, for example. The first joint portion 22c and the first upper radiator plate 22 may be formed integrally or may be joined together. The method of joining in this case is not particularly limited, and joining may be performed by welding, for example. Similarly, the second joint portion 46c and the second lower radiator plate 46 may be formed integrally or may be joined together. The joining method in this case is also not particularly limited, and may be joined by welding, for example.

Solder absorbing grooves 22 d are provided on the lower surface 22 b of the first upper heat sink 22 so as to surround the solder layer 23 . The solder absorption groove 22d accommodates excess solder when soldering the first conductor spacer 24 and the first upper heat sink 22, and prevents the solder from spreading to an unintended range. Similarly, a solder absorbing groove 42 d is provided on the lower surface 42 b of the second upper heat sink 42 so as to surround the solder layer 43 . When soldering the second conductor spacer 44 and the second upper radiator plate 42 together, the solder absorption grooves 42d accommodate excess solder and prevent it from wetting and spreading to an unintended range. Although it is an example, in the semiconductor device 10 of the present embodiment, members having the same shape are employed for the first upper heat radiation plate 22 and the second upper heat radiation plate 42 .

In the first upper heat sink 22, the first joint portion 22c is also provided with solder absorption grooves 22e. The solder absorption groove 22e is provided so as to surround the solder layer 50 located between the second joint portion 46c. The solder absorbing groove 22e accommodates excess solder when soldering the first joint portion 22c and the second joint portion 46c, and prevents the solder from spreading to an unintended extent. Similarly, the joint portion 42c of the second upper heat sink 42 is also provided with a solder absorbing groove 42e. This solder absorbing groove 42e is provided so as to surround a solder layer (not shown) located between the N terminal 15 and the solder absorbing groove 42e. The solder absorption groove 42e accommodates excess solder when soldering the joint portion 42c of the second upper heat sink 42 and the N terminal 15, and prevents the excess solder from spreading to an unintended extent.

Next, the joint structure between the first upper heat sink 22 and the first conductor spacer 24 will be described with reference to FIGS. 3 to 6. FIG. As shown in FIG. 5, of the lower surface 22b of the first upper heat sink 22, the area in contact with the solder layer 23 interposed between the first conductor spacers 24 is here referred to as the first solder joint area S1. called. As described above, the lower surface 22b of the first upper radiator plate 22 is provided with the solder absorbing grooves 22d so as to surround the solder layer 23. As shown in FIG. In the present embodiment, two sides 52 and 56 of the periphery of the first solder joint area S1 that face each other in the first direction D1 are located in the solder absorption groove 22d, and the other two sides that face each other in the second direction D2 are positioned within the solder absorption groove 22d. Sides 54 and 58 are positioned outside solder absorption groove 22d. As an example, the first direction D1 and the second direction D2 are orthogonal to each other.

According to the above-described configuration, as shown in FIG. 6, when the first upper heat radiation plate 22 and the first conductor spacer 24 are soldered, the position where excess solder is accommodated in the solder absorption grooves 22d is the first solder. It is limited to two opposing sides 52 and 56 (first direction D1) of the joint area S1. By limiting the position at which surplus solder flows into the solder absorption grooves 22d to a part of the periphery of the first solder joint area S1, even if the amount of surplus solder fluctuates to a certain degree, In the two sides 52 and 56 of , excess solder is evenly accommodated in the solder absorbing grooves 22d, and the contact angles of the solder 23 are also substantially equal (see FIG. 3). On the other hand, the other two opposing sides 54 and 58 (second direction D2) of the first solder joint area S1 are positioned outside the solder absorption grooves 22d, respectively, so that the contact angles of the solder 23 are substantially equal ( See Figure 4). Since the contact angles of the solder 23 are substantially equal on each of the two opposing sides (52 and 56, 54 and 58) of the first solder joint area S1, the contact angle between the first upper heat sink 22 and the first conductor spacer 24 is Changes in relative position and posture are suppressed, and the dimensional accuracy of the semiconductor device 10 is improved. Since the solder 23 in the manufacturing stage forms the solder layer 23 of the semiconductor device 10 described above, the same reference numerals are given here. Also, as shown in FIG. 6, when soldering the first upper heat sink 22 and the first conductor spacer 24, a jig J may be used as necessary.

As described above, the first semiconductor element 20 of this embodiment is an RC-IGBT element, but instead of the RC-IGBT element, two or more semiconductor elements such as a diode element and an IGBT element (or MOSFET element) may be substituted. may be In this case, since two or more elements (or two or more conductor spacers) are soldered to the first upper heat sink 22 at the same time, the position and orientation of the first upper heat sink 22 may change during the soldering. is relatively stable. In other words, as in the semiconductor device 10 of this embodiment, if the structure is such that a single element (or a single conductor spacer) is soldered to the first upper heat sink 22, during the soldering The position and orientation of the first upper radiator plate 22 are likely to change. Therefore, the technology disclosed in this specification can be suitably employed in a structure in which a single element or other member (for example, a single conductor spacer) is soldered to the first upper heat sink 22. can be done. Regarding this point, the same applies to the second semiconductor element 40 and the second upper heat radiation plate 42 .

In the semiconductor device 10 of this embodiment, the second joint portion 46 c of the second lower heat sink 46 is joined to the first upper heat sink 22 via the solder layer 50 in addition to the first conductor spacer 24 . there is As shown in FIG. 5, the area of the lower surface 22b of the first upper heat sink 22 that is in contact with the solder layer 50 is referred to as a second solder joint area S2. In this case, part of the second solder joint area S2 is located in the first direction D1 with respect to the first solder joint area S1. As shown in FIG. 6, when soldering the first conductor spacer 24 to the first upper heat sink 22 in the manufacturing stage of the semiconductor device 10, the second joint portion 46c of the second lower heat sink 46 is 1 is soldered to the upper heat sink 22 .

In soldering between the first upper heat sink 22 and the first conductor spacer 24, for example, when the amount of surplus solder is extremely small, two sides 52 of the first solder joint area S1 facing the first direction D1, At 56, excess solder may not be evenly accommodated in solder absorbing grooves 22d. In this case, the adsorption force caused by the surface tension of the solder 23 acts unevenly between the two sides 52 and 56 facing each other in the first direction D1, changing the position and orientation of the first upper heat sink 22. There is a risk. At this time, when the second joint portion 46c is soldered to the second solder joint area S2 of the first upper heat radiation plate 22 at the same time, the solder 50 also adheres to the second solder joint area S2 due to the surface tension of the solder 50. force acts. Since the second solder-joint area S2 is located in the first direction D1 with respect to the first solder-joint area S1, the attraction force of the solder 50 acting on the second solder-joint area S2 is can effectively suppress changes in the position and posture of Since the solder 50 in the manufacturing stage forms the solder layer 50 of the semiconductor device 10 described above, the same reference numerals are used here.

The embodiment of the solder absorption grooves 22d provided on the lower surface 22b of the first upper heat sink 22 in the technology disclosed in this specification can be changed in various ways. Modifications of the first upper radiator plate 22 will be described with reference to FIGS. 7 and 8. FIG. As shown in FIG. 7, the lower surface 122b of the first upper heat sink 122 may be provided with two opposing solder absorption grooves 122d along the periphery of the first solder joint area S1. That is, the solder absorbing groove 122d does not have to be formed in an annular shape. In this case, two opposing sides 152 and 156 of the peripheral edge of the first solder joint area S1 are positioned within the solder absorbing groove 122d, and the other two opposing sides 154 and 158 are positioned outside the solder absorbing groove 122d. . According to such a configuration, when the first upper heat radiation plate 122 and the first conductor spacer 24 are soldered, the position where excess solder is accommodated in the solder absorption grooves 122d faces the first solder joint area S1. It is limited to two sides 152,156.

Alternatively, as shown in FIG. 8, the width or cross-sectional area of the solder absorption groove 222d is made different between two sections facing each other in the first direction D1 and two sections facing each other in the second direction D2. may In the modification shown in FIG. 8, the width of the two sections facing in the second direction D2 is sufficiently smaller than the width of the two sections facing in the first direction D1. As a result, the cross-sectional areas of the two sections facing each other in the second direction D2 are reduced to such an extent that the surplus solder cannot be accommodated. As an example, the width of two sections facing each other in the second direction D2 can be 0.5 mm or less. According to such a configuration, when the first upper heat radiation plate 222 and the first conductor spacer 24 are soldered, the two sides 254 and 258 facing each other in the second direction D2 of the first solder joint area S1 are soldered together. It is positioned outside of the absorption groove 222d. On the other hand, the two sides 252 and 256 facing each other in the first direction D1 are held at the positions of the solder absorbing grooves 222d. That is, also in this modification, the two sides 252 and 256 of the peripheral edge of the first solder joint area S1 that face each other in the first direction D1 are located in the solder absorbing groove 222d and face each other in the second direction D2. The other two sides 254, 258 are located outside the solder absorption grooves 222d. Note that the solder absorption groove 222d does not necessarily have to be formed in an annular shape, and may be divided into the four sections described above, for example.

Although several specific examples have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness alone or in various combinations.

10: Semiconductor device 12: Sealing body 14: P terminal 15: N terminal 16: O terminals 18, 19: Signal terminals 20, 40: Semiconductor elements 22, 122, 222: First upper heat sinks 22c, 42c, 46c: Joints 22d, 42d, 122d, 222d: Solder absorption grooves 22e, 42e of upper heat sink: Solder absorption grooves 23, 25, 27, 50 of joints: Solder (layer)
24, 44: Conductor spacer 26: First lower heat sink 42: Second upper heat sink 46: Second lower heat sink D1: First direction D2: Second direction S1, S2: Soldering area

Claims (2)

a first member;
A second member joined to the first member via a solder layer,
The first member is provided with a solder absorption groove that accommodates surplus solder of the solder layer,
When the range in contact with the solder layer of the first member is the solder joint area,
The solder absorption groove annularly surrounds at least a portion of the solder joint area,
Of the peripheral edge of the solder joint area, two sides facing each other in the first direction are positioned within the solder absorption groove, and other two sides facing each other in the second direction are positioned outside the solder absorption groove,
semiconductor equipment. 2. The semiconductor device according to claim 1, wherein said other two sides facing each other in said second direction are located within a range surrounded by said solder absorption groove.

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