JP2017054855A - Semiconductor device, and semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board, a semiconductor device, and a semiconductor package having a high cooling performance.SOLUTION: A semiconductor device according to an embodiment comprises: a first wiring board that has a first insulation substrate configured by a ceramic material and on whose one principal surface a first wiring layer is formed, and a base plate arranged at the other side of the first insulation substrate and having a projection that protrudes outward from an outer peripheral edge of the insulation substrate; a semiconductor chip arranged on the first wiring layer and that has an electrode electrically connected with the first wiring layer; and a second wiring board that has a second insulation substrate arranged at one side of the first wiring layer while interposing the semiconductor chip and configured by a ceramic material, and a second wiring layer formed on a surface at the semiconductor chip side of the second insulation substrate and electrically connected with the semiconductor chip.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device and a semiconductor package.

  The semiconductor package includes, for example, a semiconductor circuit substrate and a sealing member that seals the semiconductor circuit substrate. The semiconductor circuit board is, for example, a conductive base material including an insulating base material such as ceramic or resin and a metal foil fixed on both sides or one side of the insulating base material, and a semiconductor fixed to one conductive base material with solder or the like. A circuit including a chip and the like.

  For example, a power semiconductor chip such as an insulated gate bipolar transistor (IGBT) generates heat by switching. Therefore, the semiconductor circuit board is cooled by being fixed in contact with the heat sink via a diffusion plate that diffuses heat.

  In recent years, when power semiconductors switch at high speeds under high voltage and large current, the amount of heat generated is increased by switching at high speeds under large currents. Therefore, heat dissipation and cooling performance are improved for semiconductor circuits including power semiconductors. Is desired.

  In addition, with the practical application of hybrid cars and electric vehicles, power semiconductor packages are desired to be reduced in size, weight, and cost.

JP 2002-329938 A JP 2002-315358 A

  The cooling performance of the semiconductor circuit board depends on the thermal resistance (package thermal resistance) between the semiconductor element and the cooling surface and the thermal resistance (heat transfer) between the cooling surface and the cooling medium.

  For example, if the configuration interposed between the semiconductor element and the cooling surface is reduced, the package thermal resistance can be reduced, which is advantageous for improving the cooling performance. In a general semiconductor module cooling method, a module heat sink and a heat sink are adhered and bonded together by silicon grease or the like. In such a configuration, since there are many intervening materials and there is a material having a large thermal resistance called silicon grease, it is difficult to obtain high cooling performance.

  Embodiments of the present invention have been made in view of the above circumstances, and an object thereof is to provide a semiconductor device and a semiconductor package with high cooling performance.

  A semiconductor device according to an embodiment includes a first insulating substrate made of a ceramic material and having a first wiring layer formed on one main surface, and an outer peripheral edge of the insulating substrate disposed on the other side of the first insulating substrate. A first wiring board comprising a base plate having a projecting portion projecting outward, and a semiconductor chip having an electrode disposed on the first wiring layer and electrically connected to the first wiring layer; A second insulating substrate disposed on one side of the first wiring layer with the semiconductor chip interposed therebetween and made of a ceramic material; and formed on a surface of the second insulating substrate on the semiconductor chip side. And a second wiring board that is electrically connected to the second wiring layer.

1 is a perspective view illustrating a configuration of a semiconductor package according to a first embodiment. The perspective view which shows the structure of the 2nd wiring board of the same semiconductor package. Sectional drawing which shows the structure of the semiconductor package. The bottom view of the semiconductor package. The perspective view of the semiconductor package. Explanatory drawing which shows the manufacturing process of the semiconductor package. Sectional drawing which shows the structure of the semiconductor package which concerns on 2nd Embodiment. Explanatory drawing which shows the structure of the semiconductor package. Explanatory drawing which shows a part of the semiconductor package.

[First Embodiment]
Hereinafter, the semiconductor device 1 and the semiconductor package 100 of the embodiment will be described with reference to FIGS. 1 to 4. In each figure, the structure is appropriately enlarged, reduced, or omitted for explanation.

  FIG. 1 is a perspective view of a semiconductor package 100 including the semiconductor device 1 according to the first embodiment as viewed from above, and FIG. 2 is a perspective view showing a configuration of a second wiring board 30. FIG. 3 is an explanatory view showing a cross section of the semiconductor package 100. 4 is a bottom view of the semiconductor package 100, and FIG. 5 is a perspective view of the semiconductor package 100 as viewed from below. FIG. 6 is an explanatory view showing a manufacturing process of the semiconductor package 100. In FIG. 1, the sealing structure 36 is omitted.

  As shown in FIGS. 1 to 4, the semiconductor device 1 includes a first wiring board 10 as a first wiring board, a semiconductor chip group 20 as a semiconductor element provided on the first wiring board 10, and a semiconductor chip. A second wiring board 30 disposed on the opposite side of the first wiring board 10 across the group 20 and a sealing structure portion 36 for sealing the semiconductor chip group 20 are provided.

  The semiconductor package 100 according to the present embodiment includes the semiconductor device 1 and a cooling structure unit 40 provided on the other side of the first wiring substrate 10 of the semiconductor device 1.

  The first wiring substrate 10 includes a first insulating substrate 11, a first wiring layer 12 formed on one main surface of the first insulating substrate 11, and a base plate 13 provided on the other side of the first insulating substrate 11. It is equipped with.

  The first insulating substrate 11 is formed of a ceramic material, and is configured in a rectangular plate shape having a first surface 11a on one side on which the semiconductor chip group 20 is mounted and a second surface 11b on the other side. Yes.

The first insulating substrate 11 is formed by sintering a powdery material into a sheet. In the present embodiment, the first insulating substrate 11 is formed of a ceramic sheet such as silicon nitride (SiN) or alumina (Al ₂ O ₃ ), for example. A plurality of sheets can be stacked and formed. For example, silicon nitride has high strength and a low coefficient of linear expansion, so that it is difficult to deform even in a high temperature environment. Silicon nitride has a higher thermal conductivity than alumina or resin. The first insulating substrate 11 is made of ceramic. For this reason, it is hard to corrode, and since it has high hardness and strength, it has sufficient resistance to an increase in the flow rate of the cooling medium and a boiling phenomenon.

  For example, the thickness of the insulating substrate 11, that is, the dimension in the Z direction is configured to be about 0.3 mm to 1 mm. In this embodiment, it is 0.5 mm or less.

  The first wiring layer 12 which is the first wiring layer is a wiring layer formed by patterning a conductive material such as copper or aluminum used for circuit wiring. For example, in the first wiring layer 12, for example, a copper pad is directly bonded to the first insulating substrate 11 by so-called DBC bonding, or a copper pad is welded on the first insulating substrate 11. The first wiring layer 12 may constitute a part of a circuit including the semiconductor chip group 20, and may include a connection pad to which a lead terminal 15 that supplies current from the outside is connected.

  The first wiring layer 12 transfers heat generated in the semiconductor chip group 20 in the direction of the substrate surface of the first insulating substrate 11, that is, in the direction orthogonal to the stacking direction of the semiconductor chip group 20 and the first insulating substrate 11. It also functions as a heat spreader.

  As shown in FIG. 1, in the embodiment, the first wiring layer 12 has a collector pattern 12b. The collector pattern 12b is formed in an L shape corresponding to a predetermined region including the lower surfaces of the chips 21 and 22 and the collector terminal 18b.

  A semiconductor chip group 20 is arranged on the collector pattern 12b. A bonding wire 16 connected to the lead terminal 15 that is a signal pin is bonded to the edge of the collector pattern 12b on the one end side in the Y direction. A collector terminal 18b is connected to the edge of the collector pattern 12b on the other end side in the Y direction.

  The lead terminal 15, the emitter terminal 18a, and the collector terminal 18b are connection members configured in a strip shape from a conductive material, and electrically connect a plurality of electrodes and terminals.

  For example, in the manufacturing process, the lead terminal 15, the emitter terminal 18 a, and the collector terminal 18 b are disposed as a part of the lead frame 50 disposed on the outer periphery of the wiring substrate 10. The lead frame 50 includes an emitter terminal 18 a, a collector terminal 18 b, a lead terminal 15, and a rectangular frame portion that is disposed outward from the outer periphery of the base plate 13. The lead frame 50 is cut in the manufacturing process and removed leaving the portions of the lead terminal 15 and the terminals 18a and 18b.

  The base plate 13 is configured in a plate shape with, for example, a metal material that is a conductive material, and one main surface thereof is bonded to the first insulating substrate 11. For example, in the embodiment, the base plate 13 is made of a copper plate.

  For example, the thickness of the base plate 13, that is, the dimension in the Z direction is configured to be about 3 mm to 5 mm. The base plate 13 is directly bonded to the first insulating substrate 11 by DBC (Direct Plated Copper) bonding.

  The base plate 13 includes a protruding portion 13 c that protrudes outward from the outer peripheral edge of the first insulating substrate 11 at the outer peripheral portion thereof. That is, the base plate 13 has the first insulating substrate 11 disposed at the central portion on the upper surface thereof. The outer peripheral portion of the base plate 13 protrudes outward from the outer peripheral edge of the first insulating substrate 11 to form a protruding portion 13 c that is exposed without being covered by the first insulating substrate 11.

  A cutout portion 13 d that is recessed toward the center in the surface direction of the insulating substrate is formed at a predetermined location on the outer peripheral portion of the base plate 13. The bottom of the notch 13 d is located closer to the center than the first insulating substrate 11. The notch 13d is disposed at a portion where various terminals such as a signal connection lead terminal 15, an emitter terminal 18a, and a collector terminal 18b are arranged, and these terminals 15, 18a, 18b are prevented from contacting the base plate 13. doing.

  In FIG. 1, the base plate 13 is formed with notches 13d at two locations on both end edges in the Y direction, and protruding portions 13c are formed at the remaining portions.

  The protruding portion 13c serves as a holding allowance for the mold 60 during molding, for example. Further, the protruding portion 13c functions as an attachment portion for fixing the cooling structure portion 40.

  Specifically, a mounting hole 13e penetrating in the Z direction, which is the thickness direction, is formed in the protruding portion 13c. The cooling structure 40 is attached to the base plate 13 by a fastening member 19 such as a screw in the attachment hole 13e.

  The emitter terminal 18 a is partially bent and extends upward, that is, toward the second wiring substrate 30, and the tip portion is positioned above the frame portion of the lead frame 50. This tip portion is bonded to the second wiring layer 32 of the second wiring board 30 placed on the semiconductor chip group 20 in the assembling process.

  The collector terminal 18 b is partially bent and extends downward, and the tip portion is located below the frame portion of the lead frame 50. This tip portion is bonded to the collector first wiring layer 12 on the first wiring substrate 10.

  The semiconductor chip group 20 is bonded to the first wiring layer 12 on the first wiring substrate 10 by, for example, solder. The semiconductor chip group 20 can use various semiconductor chips used for electric circuits such as semiconductor switches such as IGBTs, FETs (Field-Effect Transistors), GTOs (Gate-Turn-Off Thyristors), transistors, and diodes.

  For example, in the present embodiment, as the semiconductor chip 20, an IGBT chip 21 and an FRD (Fast Recovery Diode) chip 22 that are switching elements are arranged side by side in the X direction on an insulating substrate. The outer shape of the IGBT chip 21 and the FRD chip 22 is configured in a rectangular plate shape, for example.

  The IGBT chip 21 and the FRD chip 22 have a collector electrode and an emitter electrode as electrodes on both main surfaces, respectively. For example, in the embodiment, an emitter electrode is formed on the upper surface and a collector electrode is formed on the lower surface.

  The emitter electrode of the FRD chip 22 and the emitter electrode of the IGBT chip 21 are electrically connected by the second wiring board 30.

  The collector electrodes arranged on the lower surfaces of the IGBT chip 21 and the FRD chip 22 are joined to the collector first wiring layer 12 on the wiring board 10.

  The second wiring substrate 30 includes a second insulating substrate 31, a second wiring layer 32 formed on the other main surface of the second insulating substrate 31, and a conductive portion formed at a predetermined location on the second wiring layer 32. As an emitter pad 33, a spacer 34 that defines a distance from the substrate 10, and a third wiring layer 35 formed on one main surface of the second insulating substrate 31. The second wiring board 30 is joined to the first wiring board 10 via solder or the like with the semiconductor chip group 20 in between.

  The second insulating substrate 31 is formed of a ceramic material in the same manner as the first insulating substrate 11 and has a rectangular plate shape. For example, the thickness of the second insulating substrate 31, that is, the dimension in the Z direction is configured to be about 0.3 to 0.5 mm.

  Similar to the first wiring layer 12, the second wiring layer 32 is a wiring layer formed by patterning a conductive material such as copper or aluminum used for circuit wiring. In the second wiring layer 32, for example, a copper pad is directly bonded to the second insulating substrate 31 by so-called DBC bonding. The second wiring layer 32 may constitute a part of a circuit including the semiconductor chip group 20 and may include a connection pad to which a lead terminal 15 that supplies current from the outside is connected. The thickness of the second wiring layer 32, that is, the dimension in the Z direction is configured to be about 0.3 to 0.5 mm.

  The second wiring layer 32 diffuses the heat generated in the semiconductor chip group 20 in the direction of the substrate surface of the second insulating substrate 31, that is, in the direction orthogonal to the direction in which the semiconductor chip group 20 and the second insulating substrate 31 are stacked. It also functions as a heat spreader.

  In the embodiment, the second wiring layer 32 is an emitter pattern for connecting an emitter electrode. As shown in FIGS. 1 to 3, the second wiring layer 32 is connected to the semiconductor chip group 20 via the emitter pad 33. The emitter terminal 18 a connected to the lead frame 50 is connected to the edge of the second wiring layer 32 on the other end side in the Y direction.

  The plurality of emitter pads 33 are each formed in a plate shape having a predetermined thickness from a conductive material such as copper. The emitter pads 33 are respectively disposed at predetermined locations facing the upper surfaces of the IGBT chip 21 and the FRD chip 22. Each emitter pad 33, 33 is bonded to an emitter electrode formed on the upper surface of the IGBT chip 21 and the FRD chip 22 via a bonding agent such as solder. The emitter pad 33 has a thickness of about 1 to 1.5 mm, for example.

  The spacer 34 is formed of a ceramic material that is an insulating material, for example, similarly to the second insulating substrate 31, and has a predetermined thickness obtained by adding the thickness dimension of the emitter pad 33 and the thickness dimension of the IGBT chip 21 or the FRD chip 22. It is configured as a square plate having a thickness. For example, the spacer 34 abuts on the upper surface of the wiring board 11 when the second wiring board 30 is bonded onto the first wiring board 10 on which the semiconductor chip group 20 is mounted, so that the first wiring board 10 and the second wiring board are contacted. It maintains a constant distance from 30 and performs a positioning function for arranging them in parallel.

  The third wiring layer 35 is formed on the first surface 31a of the second insulating substrate 31 in a layered shape having a predetermined thickness from a conductive material such as copper. The third wiring layer 35 is ground as necessary, and the main surface on one side thereof is exposed to the outside from the sealing structure portion 36.

  The cooling structure 40 includes a cooling jacket 41 disposed to face the base plate 13 and a rectifying guide 42 formed integrally with the second surface 13 b of the base plate 13.

  The rectifying guide 42 includes a plurality of rectifying units 42 a configured on the second surface 13 b of the base plate 13. The rectifying unit 42a is configured in various shapes such as a fin shape, a column shape, a pin shape, and a wall shape.

  The cooling jacket 41 includes a case portion 41a having a rectangular recess that forms a flow path that is a gap through which the cooling medium passes, and a plurality of attachment portions provided on the outer periphery of the case portion 41a. 41b, an inflow port 41c and an outflow port 41d for communicating the inside and outside of the case portion 41a.

  A ring groove in which the O-ring 43 is disposed is formed on the outer peripheral edge of the cooling jacket 41. The cooling jacket 41 is covered with the case portion 41a on the second surface 13b of the base plate 13 so as to cover the rectifying portion 42a, and the attachment portion 41b is attached to the base plate 13 with a fastening member such as a screw. A predetermined flow path that is sealed by an O-ring 43 disposed in the ring groove 41e is formed on the second surface 13b side.

  The sealing structure 36 is an insulator formed of, for example, resin. The sealing structure portion 36 covers and seals the chips 21 and 22, the first wiring layer 12, the second wiring substrate 30, and the like of the semiconductor package 100 by, for example, molding or potting. The sealing structure portion 36 seals at least the semiconductor chip group 20 to prevent the semiconductor chip group 20 from coming into contact with water or air, and avoids deterioration of the semiconductor chip group 20. The sealing structure portion 36 may be disposed so as to expose a part of the wiring pattern 12.

  In the present embodiment, the sealing structure portion 36 exposes one surface of the third wiring layer 35 of the second wiring substrate 30. For example, the sealing structure 36 is ground as necessary to expose the third wiring layer 35.

  In the semiconductor device 1 and the semiconductor package 100, the cooling structure 40 is cooled by the coolant flowing through the flow path formed in the cooling structure 40. The refrigerant flowing through the flow path is, for example, water, ethylene glycol or the like.

  A manufacturing process of the semiconductor package 100 configured as described above will be described.

  First, the wiring board 10 manufactured by the DBC process is prepared. The manufacturing process of the wiring substrate 10 includes, for example, directly bonding the insulating substrate 11 formed in a plate shape from a ceramic material on the base plate 13 formed in a predetermined shape having the fin-like rectifying portion 41a on the lower surface by DBC bonding. Then, the wiring pattern 12 is formed on the insulating substrate 11.

  The wiring substrate 10 may be manufactured by forming the wiring pattern 12 on the ceramic insulating substrate 11 in advance and then bonding the insulating substrate 11 directly on the base plate 13. Alternatively, the conductive substrate may be used as a pattern forming step. May be joined directly.

  On the other hand, the second insulating substrate 31 configured in a plate shape from a ceramic material is prepared, the third wiring layer 35 is formed on the first surface 31a, and the second wiring layer 32 is formed on the second surface 31b. Form. Further, the emitter pad 33 and the spacer 34 are DBC bonded onto the second wiring layer 32 to form the second wiring substrate 30.

  The wiring board 10 is placed on a jig for reflow conveyance. The conveyance jig includes a guide pin for positioning inserted into a hole provided in the base plate 13, for example.

  As shown in FIG. 1, the second wiring board 30 is placed on the first wiring board 10 and joined by soldering. Specifically, the solder sheet, the semiconductor chip 20, and the lead frame 50 are arranged on a predetermined position on the wiring pattern 12 of the wiring board 10, and the solder sheet and the second wiring board 30 are arranged to face each other. Then, it is put into a hydrogen / formic acid reflow furnace and soldered. The spacers 34 of the second wiring substrate 30 are disposed on the collector pattern 12 and the emitter pads 33 are disposed on the upper surface of the semiconductor chip group 20 so as to face each other. Further, the emitter terminal 18 a is joined to the second wiring layer 32.

  At this time, the spacer 34 abuts on the collector pattern 12 so that the first wiring board 10 and the second wiring board 30 are arranged in parallel with a predetermined constant interval.

  Then, by holding the lead frame 50 using a jig for fixing the frame and bonding a Cu ribbon or a bonding wire for electrode connection, the gate signal, temperature sense, and emitter sense of the plurality of semiconductor chips 20, The lead terminals 15 are connected to each other.

  Next, the wiring board 10 on which the semiconductor chip 20 is mounted is removed from the conveyance jig together with the lead frame 50, and is set in a mold 60 of a mold processing apparatus, for example, as shown in FIG. A stop structure 36 is formed. The mold 60 includes a plurality of molds 61 and 62 that seal the outer periphery of the wiring board 10. An internal space having a predetermined shape corresponding to the shape of the wiring substrate 10 and the sealing structure portion 36 formed on the wiring substrate 10 is formed between the plurality of molds. In addition, the plurality of molds constituting the mold 60 are arranged such that terminals 15, 18 a, and 18 b are arranged on the outer edge portion of the mold 60 with the mold 60 closed, and the periphery thereof is sealed. have. The wiring board 10 is set on a jig 63 for avoiding mechanical interference with the rectifying unit 42a. The wiring substrate 10 is arranged in the inner space of the mold 60, and the mold 60 is closed and molded to form the sealing structure portion 36 in a state where a part of the terminals 15, 18a, 18b is exposed. The chip 20 and the wiring pattern 12 are covered and sealed. The sealing structure 36 may be formed by other processes such as a potting process in addition to the molding process.

  When forming the sealing structure portion 36, it is possible to easily perform positioning and processing by pressing the protruding portion 13c with a processing device jig. Then, unnecessary portions on the outer periphery of the lead frame 50 are cut with a mold, whereby the semiconductor device 1 is completed.

  Further, the cooling jacket 41 is placed on the second surface 13 b of the base plate 13, the fastening member 19 is fastened at the mounting portion 41 b, and the semiconductor package 100 is completed by fixing to the base plate 13.

  The semiconductor device 1 configured as described above includes the solder, the first wiring layer 12, the first wiring layer between the semiconductor chip group 20 that is a heat source and the cooling surface of the cooling structure 40 that contacts the cooling medium. An insulating substrate 11 and a base plate 13 are provided.

  Therefore, the heat generated in the semiconductor chip group 20 is transferred to the first wiring layer 12 and further transferred to the cooling structure 40 via the first insulating substrate 11 and the base plate 13 and cooled by the cooling medium. Further, when a lead is connected to the first wiring layer 12, heat is generated at a connection portion between the lead and the first wiring layer 12 due to a current flowing from the lead to the first wiring layer 12. The heat generated between the lead and the first wiring layer 12 is transferred to the first wiring layer 12 and further transferred to the cooling structure 40 via the first insulating substrate 11 and cooled by the cooling medium. .

  The semiconductor device 1 and the semiconductor package 100 of the present embodiment are configured to include the semiconductor chip group 20, the first wiring layer 12, and the sealing structure portion 36 on the first wiring substrate 10. Compared to a configuration having a large number of solder joints, it is possible to achieve a reduction in size, weight, and cost. Further, since the first insulating substrate 11 is made of a ceramic material, a high breakdown voltage can be ensured, and performance suitable for mounting a power semiconductor element can be secured.

  Further, the base plate 13 bonded to the first insulating substrate 11 has a protruding portion 13c that projects outward from the first insulating substrate 11, so that the assemblability is good. That is, it is possible to provide a holding allowance in the molding process, and it is possible to provide an attachment function with other structures, so that the assemblability is good.

Further, according to the present embodiment, the emitter electrodes on the upper surfaces of the chips 21 and 22 of the semiconductor chip group 20 that is a heat source are the emitter pad 33, the second wiring layer 32, the second insulating substrate 31, and the third wiring layer. The heat is radiated to the outside through 35. Thus, since the semiconductor package 100 can also radiate heat from the second wiring board 30 side arranged on the upper surface of the semiconductor chip group 20, high heat radiation performance can be secured.
[Second Embodiment]
Hereinafter, the first wiring board 10, the semiconductor device 2, and the semiconductor package 200 according to the second embodiment will be described with reference to FIGS. FIG. 6 is a plan view showing the configuration of the semiconductor package 200 according to the second embodiment, and FIG. 7 is a side view showing the configuration of the semiconductor package 200. FIG. 8 is a perspective view showing a part of the semiconductor package 200.

  The semiconductor package 200 according to the second embodiment has a so-called 6-in-1 structure, and includes six semiconductor chip groups 20 </ b> A each including two IGBT chips 21 and two FRD chips 22 on one first wiring substrate 10. Have one. Since the rest is the same as that of the semiconductor package 100 according to the first embodiment, in the semiconductor package 200 according to the second embodiment, the same components as those of the semiconductor package 100 are denoted by the same reference numerals, and redundant description is omitted. To do.

  As shown in FIGS. 6 to 8, the semiconductor package 200 of the present embodiment includes the semiconductor device 2 and a cooling structure unit 40 provided on the other side of the first wiring substrate 10 of the semiconductor device 2. The

  The first wiring substrate 10 of the semiconductor device 2 is provided with a first insulating substrate 11 on a base plate 13.

  The base plate 13 has a rectangular shape that is long in one direction along the X axis in the drawing, and includes a plurality of cutout portions 13d on the outer periphery thereof.

  The first insulating substrate 11 is formed in a rectangular shape that is smaller than the base plate 13 and long in one direction along the X axis in the drawing. A plurality of collector patterns 12 b and a plurality of emitter patterns 12 a are formed on the first insulating substrate 11 as the first wiring layer 12.

  Further, the semiconductor package 100 according to the present embodiment includes an electrode bridge 17 made of a conductive material such as copper as a connection member for connecting a plurality of spaced electrodes, terminals, or wiring patterns.

  In the present embodiment, six sets of chip sets 20A each including two IGBT chips 21 and two FRD chips 22 are arranged side by side in the X direction. Two adjacent chip sets 20A each correspond to one phase, and three-phase groups corresponding to the U-phase, V-phase, and W-phase are arranged side by side in the X direction.

  The first wiring layer 12 has six rectangular collector patterns 12b arranged in the X direction. Two IGBT chips 21 and two FRD chips 22 are arranged on each collector pattern 12b. The collector pattern 12b is continuously formed along the X direction on one end side in the Y direction of the semiconductor device 2, and is formed at a predetermined position between the adjacent rectangular collector patterns 12b.

  Two IGBT chips 21 and two FRD chips 22 are arranged on each of the six collector patterns 12b of the first wiring board 10.

  Each IGBT chip 21 and FRD chip 22 have a collector electrode and an emitter electrode as electrodes on both main surfaces, respectively. For example, in the embodiment, an emitter electrode is formed on the upper surface and a collector electrode is formed on the lower surface.

  The emitter electrode of the FRD chip 22 and the emitter electrode of the IGBT chip 21 are electrically connected by the emitter pad 33 and the second wiring layer 32.

  The collector electrode is electrically connected by a collector pattern 12b formed on the lower side of the chip.

  A second wiring substrate 30 is provided on the opposite side of the six collector patterns 12b in the Z direction across the semiconductor chip group 20A.

  Similar to the first embodiment, the second wiring substrate 30 includes a second insulating substrate 31, a second wiring layer 32 formed on one main surface of the second insulating substrate 31, and the second wiring layer 32. An emitter pad 33 formed at a predetermined location and a third wiring layer 35 are provided.

  The second wiring board 30 is bonded to the first wiring board 10 on which the semiconductor chip group 20 is mounted via solder or the like. Here, six locations are arranged corresponding to each collector pattern 12b.

  The second insulating substrate 31 is formed of a ceramic material and is configured in a rectangular plate shape having a pair of opposed main surfaces. A third wiring layer 35 is formed on one main surface of the second insulating substrate 31, and a second wiring layer 32 is formed on the other main surface.

  In the embodiment, the second wiring layer 32 is an emitter pattern for connecting an emitter electrode. The second wiring layer 32 is connected to the semiconductor chip group 20 via the emitter pad 33.

  The plurality of emitter pads 33 are each formed in a plate shape having a predetermined thickness from a conductive material such as copper. The emitter pads 33 are respectively disposed at predetermined locations facing the upper surfaces of the plurality of IGBT chips 21 and the FRD chips 22.

  In this embodiment, an example in which the spacer 34 is not provided is shown, but the present invention is not limited to this, and a columnar member that becomes the spacer 34 may be provided at an appropriate position as necessary. .

  On the first insulating substrate 11, emitter patterns 12a are arranged at predetermined positions on the side of the rectangular collector pattern 12b arranged side by side and mounting the semiconductor chip group 20 on one end side in the Y direction of each collector pattern 12b. Is formed.

  A lead frame 50 is provided on the outer periphery of the semiconductor package 200. The lead frame 50 is a rectangular frame that is outside the outer periphery of the base plate 13 and surrounds the first wiring board 10.

  The lead frame 50 includes a plurality of lead terminals 15 extending in the Y direction toward the collector pattern 12b of the first wiring layer 12 disposed on the inner side of the frame portion on one end side in the Y direction. The lead terminal 15 is connected to the collector pattern 12 b through the bonding wire 16.

An emitter terminal 18a and a collector terminal 18b connected to the emitter pattern 12a and the collector pattern 12b of the first wiring layer 12 are provided on the frame portion on one end side in the X direction of the lead frame 50, respectively.
The lead frame 50 is cut in the manufacturing process leaving the portions of the various terminals 15, 18a, 18b.

  Further, in the semiconductor package 200, an emitter bridge 17a, which is an emitter connection member, and a collector bridge 17b, which is a collector connection member, are disposed at predetermined positions. The emitter bridge 17a electrically connects the plurality of emitter patterns 12a and the plurality of second wiring layers 32. The collector bridge 17b electrically connects the plurality of collector patterns 12b.

  The lead terminal 15, the emitter bridge 17a, the collector bridge 17b, the emitter terminal 18a, and the collector terminal 18b are formed in a band shape or a pin shape from a conductive material, and electrically connect a plurality of electrodes and terminals.

  The cooling structure portion 40 includes a case portion 41a that covers the second surface 13b of the base plate 13 via a predetermined flow path. The flow path is a space through which the cooling medium passes.

  The sealing structure 36 is an insulator formed of, for example, resin. The sealing structure portion 36 covers and seals the semiconductor chip group 20 of the semiconductor package, the first wiring layer 12, and the like by, for example, molding or potting.

  In the semiconductor device 2 and the semiconductor package 200, the cooling structure 40 is cooled by the coolant flowing through the flow path formed in the cooling structure 40. The refrigerant flowing through the flow path is, for example, water, ethylene glycol or the like.

  Also in the semiconductor device 2 and the semiconductor package 200 of the present embodiment, the same effects as those of the semiconductor device 1 and the semiconductor package 100 according to the first embodiment can be obtained. Furthermore, since the semiconductor device 2 and the semiconductor package 100 according to the present embodiment use the common cooling jacket 41 for the plurality of chip sets 20A, the cooling structure is simple, and the flow rate of the refrigerant can be secured, thereby improving the heat dissipation efficiency. To do.

  Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the components without departing from the scope of the invention in the implementation stage.

  For example, the cooling structure 40 may be omitted. Even in that case, the same effects as those of the first wiring substrate 10 and the semiconductor package of the first embodiment described above can be obtained.

  In the said embodiment, although the semiconductor packages 100 and 200 provided with the cooling structure part 40 on the other side of the 1st wiring board were illustrated, it is not restricted to this. For example, as another embodiment, the cooling structure 40 may be provided on one side of the second wiring board 30. In this case, higher heat radiation performance can be ensured by cooling the third wiring layer exposed from the sealing structure portion 36.

  Moreover, the structure of the cooling structure 40 is not limited to the above embodiment. For example, other shapes such as a plurality of columnar portions and a plurality of wall-shaped portions may be used. Further, it is also possible to define the flow path by arranging a rubber member that elastically contacts and faces the rectifying part 42a formed on the wiring board 10 side, for example, on the bottom surface of the case part 41a.

  In the first embodiment and the second embodiment, the sealing structure 36 may be disposed so as to cover the semiconductor chip group 20 by exposing a part of the first wiring layer 12. Even in such a case, the same effects as those of the first and second embodiments described above can be obtained.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1, 2 ... Semiconductor device, 10 ... 1st wiring board, 11 ... 1st insulated substrate, 12 ... 1st wiring layer, 12a ... Emitter pattern, 12b ... Collector pattern, 13 ... Base plate, 13c ... Projection part, 13d ... Notch , 13e: mounting hole, 15: lead terminal (connecting member), 16: bonding wire (connecting member), 17a: emitter bridge (connecting member), 18a: emitter terminal (connecting member), 18b: collector terminal (connecting member) , 19 ... Fastening member, 20 ... Semiconductor chip group, 21 ... IGBT chip (semiconductor chip), 22 ... FRD chip (semiconductor chip), 30 ... Second wiring board, 31 ... Second insulating board, 32 ... Second wiring Layer 33 emitter pad (conductive pad) 34 spacer 3 35 wiring layer 36 sealing structure 40 cooling structure 41 cooling jacket DOO, 41a ... case body, 42a ... rectifying unit, 50 ... lead frames, 100, 200 ... semiconductor package.

Claims (8)

A first insulating substrate made of a ceramic material and having a first wiring layer formed on one main surface, and disposed on the other side of the first insulating substrate, and protrudes outward from an outer peripheral edge of the first insulating substrate. A first wiring board comprising a base plate having a protruding portion that
A semiconductor chip having an electrode disposed on the first wiring layer and electrically connected to the first wiring layer;
A second insulating substrate disposed on one side of the first wiring layer across the semiconductor chip and made of a ceramic material; and formed on a surface of the second insulating substrate on the semiconductor chip side, the semiconductor chip A second wiring board comprising: a second wiring layer electrically connected to the second wiring layer;
A semiconductor device comprising: A conductive portion disposed between the second wiring layer and the semiconductor chip; and a third wiring layer formed on one main surface of the second insulating substrate,
The semiconductor device according to claim 1, wherein the sealing structure part exposes at least a part of the third wiring layer.   The semiconductor device according to claim 1, further comprising a spacer made of an insulating material between the second wiring layer and the first wiring layer. The base plate is made of a metal material and directly bonded to the insulating substrate,
4. The projecting portion according to claim 1, wherein at least a part of the base plate projects outward from the insulating substrate in a plane direction intersecting a stacking direction of the insulating substrate and the base plate. A semiconductor device according to any one of the above. On the first wiring board, a plurality of chip sets each including the plurality of semiconductor chips are provided,
Each of the semiconductor chips has an emitter electrode and a collector electrode on both main surfaces,
A plurality of the second wiring boards are arranged corresponding to each of a plurality of semiconductor chip sets,
The first wiring layer includes a wiring pattern electrically connected to one of the collector electrode or the emitter electrode,
5. The semiconductor device according to claim 1, wherein the second wiring layer includes a wiring pattern electrically connected to the other of the collector electrode or the emitter electrode.   The semiconductor device according to claim 1, further comprising a sealing structure portion that seals the semiconductor chip. A semiconductor device according to any one of claims 1 to 6;
A cooling structure provided on the other side of the base plate.   The semiconductor package according to claim 7, further comprising a cooling jacket that is disposed to face the other surface of the base plate, forms a flow path between the cooling structure and the base plate, and is attached to the protruding portion.