JP2013105884A - Semiconductor module - Google Patents

Semiconductor module Download PDF

Info

Publication number
JP2013105884A
JP2013105884A JP2011248682A JP2011248682A JP2013105884A JP 2013105884 A JP2013105884 A JP 2013105884A JP 2011248682 A JP2011248682 A JP 2011248682A JP 2011248682 A JP2011248682 A JP 2011248682A JP 2013105884 A JP2013105884 A JP 2013105884A
Authority
JP
Japan
Prior art keywords
semiconductor module
insulating member
semiconductor
covers
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011248682A
Other languages
Japanese (ja)
Other versions
JP5845835B2 (en
Inventor
Takashi Kurihara
貴史 栗原
Takahisa Kaneko
高久 金子
Masahiro Hirano
雅弘 平野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2011248682A priority Critical patent/JP5845835B2/en
Publication of JP2013105884A publication Critical patent/JP2013105884A/en
Application granted granted Critical
Publication of JP5845835B2 publication Critical patent/JP5845835B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13062Junction field-effect transistor [JFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13063Metal-Semiconductor Field-Effect Transistor [MESFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor module which can inhibit detachment of an insulating member than in the past even when a temperature difference occurs.SOLUTION: A semiconductor module 10 comprises: a plurality of semiconductor elements 16; a heat radiation part 15 radiating heat generated in each semiconductor element 16; and an insulating member 14 covering at least the semiconductor elements 16. The insulating member 14 covers an entire surface of the semiconductor module or covers around a plurality of surfaces around the semiconductor module 10. According to this configuration, the insulating member 14 covers an entire surface of the semiconductor module 10 or covers a plurality of surfaces around the semiconductor module 10. Detachment of the insulating member 14 can be inhibited than in the past even when stress due to a linear expansion coefficient difference caused on the basis of a temperature difference occurring between the heat radiation part 15 and the insulating member 14.

Description

本発明は、複数の半導体素子、放熱部、絶縁部材を備える半導体モジュールに関する。   The present invention relates to a semiconductor module including a plurality of semiconductor elements, a heat radiating portion, and an insulating member.

従来では、放熱効率に優れ、高い形状精度を有する半導体冷却ユニットに関する技術の一例が開示されている(例えば特許文献1を参照)。この半導体冷却ユニットは、同文献の段落番号[0020]および図1の記載を参照すると、半導体素子(11)を挟むように相互に対面する2枚の電極板(15)を有し、各電極板(15)に対して絶縁層(30)を介在させて冷却チューブ(20)を接合する構成である。   Conventionally, an example of a technique related to a semiconductor cooling unit having excellent heat radiation efficiency and high shape accuracy has been disclosed (see, for example, Patent Document 1). This semiconductor cooling unit has two electrode plates (15) facing each other so as to sandwich the semiconductor element (11) with reference to paragraph number [0020] and the description of FIG. The cooling tube (20) is joined to the plate (15) with an insulating layer (30) interposed.

特開2005−093593号公報Japanese Patent Laid-Open No. 2005-093593

しかし、特許文献1で開示された半導体冷却ユニットの構成によれば、各電極板(15)の全面に対して絶縁層(30)を接着させ、絶縁層(30)の全面に対して冷却チューブ(20)を接着させている。一般的に電極板(15)と冷却チューブ(20)との間には大きな温度差が生じるので、絶縁層(30)には線膨張係数差による応力が少なからず発生する。当該応力が接着力を上回る場合には、絶縁層(30)の一部(多くは端面)から剥離が発生するという問題があった。   However, according to the configuration of the semiconductor cooling unit disclosed in Patent Document 1, the insulating layer (30) is bonded to the entire surface of each electrode plate (15), and the cooling tube is bonded to the entire surface of the insulating layer (30). (20) is adhered. In general, since a large temperature difference is generated between the electrode plate (15) and the cooling tube (20), a stress due to a difference in coefficient of linear expansion is generated in the insulating layer (30). When the stress exceeds the adhesive force, there is a problem that peeling occurs from a part (mostly end face) of the insulating layer (30).

本発明はこのような点に鑑みてなしたものであり、温度差が生じても従来よりは絶縁部材の剥離を抑止することができる半導体モジュールを提供することを目的とする。   The present invention has been made in view of such a point, and an object of the present invention is to provide a semiconductor module that can suppress peeling of an insulating member more than ever even if a temperature difference occurs.

上記課題を解決するためになされた請求項1に記載の発明は、複数の半導体素子と、各前記半導体素子で生じる熱を放出する放熱部と、少なくとも前記半導体素子を覆う絶縁部材とを備える半導体モジュールにおいて、前記絶縁部材は、前記半導体モジュールの全表面を覆うか、または、複数面を周回して覆うことを特徴とする。   The invention according to claim 1, which has been made in order to solve the above-described problem, includes a plurality of semiconductor elements, a heat radiation part that releases heat generated in each of the semiconductor elements, and an insulating member that covers at least the semiconductor elements. In the module, the insulating member covers the entire surface of the semiconductor module or covers around a plurality of surfaces.

この構成によれば、絶縁部材は半導体モジュールの全表面を覆うか、または、複数面を周回して覆う。放熱部と絶縁部材との間に生じる温度差に基づく線膨張係数差による応力が発生しても、従来よりは絶縁部材の剥離を抑止することができる。なお周回して覆う場合には、周回数を問わない。   According to this configuration, the insulating member covers the entire surface of the semiconductor module or covers around a plurality of surfaces. Even if a stress due to a difference in linear expansion coefficient based on a temperature difference generated between the heat dissipating part and the insulating member is generated, peeling of the insulating member can be suppressed as compared with the conventional case. In addition, when covering around, it does not ask | require the number of times of circulation.

なお「半導体素子」は、通電に伴って発熱する任意の半導体素子が該当する。例えば、半導体チップ、FET(具体的にはMOSFET,JFET,MESFET等)、IGBT、GTO、パワートランジスタ、ダイオード、サイリスタなどが該当する。「放熱部」は、半導体素子で生じる熱を放出可能な任意の部材を適用でき、材質・材料・形状等を問わない。「絶縁部材」は、熱伝導性があり、電気的絶縁性を有すれば任意の部材を適用でき、材質や材料等を問わない。   The “semiconductor element” corresponds to any semiconductor element that generates heat when energized. For example, semiconductor chips, FETs (specifically MOSFETs, JFETs, MESFETs, etc.), IGBTs, GTOs, power transistors, diodes, thyristors, etc. are applicable. As the “heat dissipating part”, any member capable of releasing heat generated in the semiconductor element can be applied, and any material, material, shape, etc. can be used. As the “insulating member”, any member can be applied as long as it has thermal conductivity and electrical insulation, and any material or material can be used.

請求項2に記載の発明は、前記絶縁部材は、前記半導体モジュールの複数面を周回して覆う場合、前記外部装置と電気的な接続を行う接続部材を有する面を除いた全ての面を覆うことを特徴とする。この構成によれば、半導体モジュールの表面のうちで接続部材を有する面を除いた全ての面(以下では単に「非接続面」と呼ぶ。)を周回して絶縁部材で覆う。放熱部と絶縁部材との間に生じる温度差に基づく線膨張係数差による応力が発生しても、絶縁部材の剥離をより確実に抑止することができる。なお「接続部材」は、外部装置との間で電気的な接続を行える導電性の部材であれば任意であり、半導体モジュールの表面から突出しているか、当該表面に露出しているかを問わない。例えば、端子、リード、ピン、バスバー等が該当する。   According to a second aspect of the present invention, when the insulating member wraps around and covers a plurality of surfaces of the semiconductor module, the insulating member covers all surfaces except for a surface having a connecting member that performs electrical connection with the external device. It is characterized by that. According to this configuration, all the surfaces of the surface of the semiconductor module except the surface having the connection member (hereinafter simply referred to as “non-connection surface”) go around and are covered with the insulating member. Even if a stress due to a difference in linear expansion coefficient based on a temperature difference generated between the heat dissipating part and the insulating member occurs, the peeling of the insulating member can be more reliably suppressed. The “connecting member” is arbitrary as long as it is a conductive member that can be electrically connected to an external device, regardless of whether it protrudes from the surface of the semiconductor module or is exposed on the surface. For example, a terminal, a lead, a pin, a bus bar, and the like are applicable.

請求項3に記載の発明は、前記絶縁部材は、前記半導体モジュールにおける前記放熱部を備えない面で少なくとも一部を重ねる重畳部位を有し、前記重畳部位を一体化させることを特徴とする。この構成によれば、絶縁部材の重畳部位を一体化させる。放熱部と絶縁部材との間に生じる温度差に基づく線膨張係数差による応力が発生しても、重畳部位が絶縁部材の剥離をより確実に抑止することができる。なお、重畳部位の固定手段は任意である。例えば、接着剤を用いて重畳部位を着ける接着や、重畳部位を溶かして着ける溶着、重畳部位を圧縮して着ける圧着などが該当する。   The invention according to claim 3 is characterized in that the insulating member has an overlapping portion that overlaps at least a part of the surface of the semiconductor module that does not include the heat dissipation portion, and integrates the overlapping portions. According to this configuration, the overlapping portions of the insulating member are integrated. Even if a stress due to a difference in linear expansion coefficient based on a temperature difference generated between the heat radiating portion and the insulating member is generated, the overlapping portion can more reliably suppress the peeling of the insulating member. In addition, the fixing means for the overlapping portion is arbitrary. For example, the adhesion which attaches an overlapping part using an adhesive, the welding which melts and overlaps an overlapping part, and the crimping | compression which compresses and attaches an overlapping part correspond.

請求項4に記載の発明は、前記重畳部位の一体化は、接着および溶着のうちで一方または双方で行うことを特徴とする。この構成によれば、重畳部位は接着および溶着のうちで一方または双方で確実に一体化されるので、重畳部位が絶縁部材の剥離をより確実に抑止することができる。   The invention according to claim 4 is characterized in that the overlapping portion is integrated by one or both of adhesion and welding. According to this configuration, since the overlapping portion is reliably integrated with one or both of adhesion and welding, the overlapping portion can more reliably suppress peeling of the insulating member.

請求項5に記載の発明は、前記絶縁部材は、前記半導体素子に対向する面とは反対側の面に導体部材を有することを特徴とする。この構成によれば、導体部材は放熱部と同様に放熱作用がある。絶縁部材が受ける熱で線膨張係数差によって応力が生じても導体部材から放熱するので、絶縁部材の剥離をより確実に抑止することができる。なお「導体部材」は絶縁部材よりも熱伝導率が高い材質や材料等であれば任意である。例えば、銅(Cu)やアルミニウム(Al)等が該当する。導体部材の形状は問わない。すなわち、絶縁部材と関連する形状(例えば同一形状や類似形状等)で形成してもよく、絶縁部材とは無関係な形状で形成してもよい。   The invention according to claim 5 is characterized in that the insulating member has a conductor member on a surface opposite to a surface facing the semiconductor element. According to this configuration, the conductor member has a heat radiation action like the heat radiation portion. Since heat is radiated from the conductor member even if stress is generated due to the difference in the linear expansion coefficient due to the heat received by the insulating member, peeling of the insulating member can be more reliably suppressed. The “conductor member” is arbitrary as long as it is a material or material having a higher thermal conductivity than the insulating member. For example, copper (Cu), aluminum (Al), etc. correspond. The shape of the conductor member does not matter. That is, it may be formed in a shape related to the insulating member (for example, the same shape or a similar shape), or may be formed in a shape unrelated to the insulating member.

請求項6に記載の発明は、前記導体部材は、予め前記絶縁部材と一体成形されることを特徴とする。この構成によれば、絶縁部材と導体部材とが予め一体成形されているので、あとは半導体素子や放熱部を覆えばよい。絶縁部材と導体部材との接着や接合等を行う工程が不要になるので、半導体モジュールの製造に要する時間を短縮することができる。   The invention according to claim 6 is characterized in that the conductor member is integrally formed with the insulating member in advance. According to this configuration, since the insulating member and the conductor member are integrally formed in advance, the semiconductor element and the heat radiating portion may be covered thereafter. Since a process for bonding, bonding, and the like between the insulating member and the conductor member becomes unnecessary, the time required for manufacturing the semiconductor module can be shortened.

請求項7に記載の発明は、前記絶縁部材は、絶縁フィルムまたは絶縁シートであることを特徴とする。この構成によれば、絶縁部材として用いる絶縁フィルムや絶縁シートは一般的に厚みが薄いので、半導体モジュール全体の体格を小さく抑えることができる。   The invention described in claim 7 is characterized in that the insulating member is an insulating film or an insulating sheet. According to this configuration, since the insulating film or the insulating sheet used as the insulating member is generally thin, the physique of the entire semiconductor module can be kept small.

半導体モジュールの第1構成例を模式的に示す図である。It is a figure which shows typically the 1st structural example of a semiconductor module. 半導体モジュールの第2構成例を模式的に示す図である。It is a figure which shows typically the 2nd structural example of a semiconductor module. 半導体モジュールの第3構成例を模式的に示す図である。It is a figure which shows typically the 3rd structural example of a semiconductor module. 半導体モジュールの第4構成例を模式的に示す図である。It is a figure which shows typically the 4th structural example of a semiconductor module. 半導体モジュールの第5構成例を模式的に示す図である。It is a figure which shows typically the 5th structural example of a semiconductor module. 半導体モジュールの第6構成例を模式的に示す図である。It is a figure which shows typically the 6th structural example of a semiconductor module. 半導体モジュールの第7構成例を模式的に示す図である。It is a figure which shows typically the 7th structural example of a semiconductor module. 半導体モジュールの第8構成例を模式的に示す図である。It is a figure which shows typically the 8th structural example of a semiconductor module. 半導体モジュールで発生する熱を吸収する熱吸収部材(冷却装置)の構成例を模式的に示す斜視図である。It is a perspective view which shows typically the structural example of the heat absorption member (cooling device) which absorbs the heat which generate | occur | produces in a semiconductor module. 半導体モジュールで発生する熱を吸収する熱吸収部材(冷却フィン)の構成例を模式的に示す断面図である。It is sectional drawing which shows typically the structural example of the heat absorption member (cooling fin) which absorbs the heat which generate | occur | produces in a semiconductor module.

以下、本発明を実施するための形態について、図面に基づいて説明する。なお、特に明示しない限り、「接続する」という場合には電気的に接続することを意味する。各図は、本発明を説明するために必要な要素を図示し、実際の全要素を図示しているとは限らない。上下左右等の方向を言う場合には、図面の記載を基準とする。   Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. Note that unless otherwise specified, “connecting” means electrically connecting. Each figure shows elements necessary for explaining the present invention, and does not necessarily show all actual elements. When referring to directions such as up, down, left and right, the description in the drawings is used as a reference.

〔実施の形態1〕
実施の形態1は、2つの半導体素子を備える半導体モジュール(いわゆる両面モジュール)の第1構成例であって、図1を参照しながら説明する。図1(A)には平面図で示し、図1(B)には図1(A)に示すIB−IB矢視の断面図を示す。なお、図1(A)で双方を破線で示す放熱部15と半導体素子16とは、図1(B)に示すように平面上は同一形状である。いずれも各要素の存在を明示にするため、便宜的に相似形状で示しているに過ぎない(図2以降についても同様である)。
[Embodiment 1]
The first embodiment is a first configuration example of a semiconductor module (so-called double-sided module) including two semiconductor elements, and will be described with reference to FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along the arrow IB-IB shown in FIG. Note that the heat radiation portion 15 and the semiconductor element 16, both of which are indicated by broken lines in FIG. 1A, have the same shape on a plane as shown in FIG. 1B. In any case, in order to clarify the existence of each element, they are merely shown in a similar shape for convenience (the same applies to FIG. 2 and subsequent figures).

図1(A)および図1(B)に示す半導体モジュール10は「半導体素子パッケージ」とも呼ばれ、樹脂封止部11、2つの放熱部15、2つの半導体素子16などを有する。樹脂封止部11は、各放熱部15および各半導体素子16を封止して所定形状(例えば直方体等のような多面体)に形成するための封止体である。この封止体は、半導体素子16を封止可能な絶縁材料であれば任意である。例えば、エポキシ樹脂(EP)やフェノール樹脂(PF)等のような各種の樹脂、当該樹脂を主成分としてシリカ充填材等を加えた熱硬化性成形材料、レジン・モールド等のような耐熱樹脂、金属酸化物(例えばアルミナ等)や無機化合物(例えば窒化ケイ素等)などを含むセラミックスなどが該当する。   The semiconductor module 10 shown in FIGS. 1A and 1B is also referred to as a “semiconductor element package”, and includes a resin sealing portion 11, two heat radiation portions 15, two semiconductor elements 16, and the like. The resin sealing portion 11 is a sealing body for sealing each heat radiating portion 15 and each semiconductor element 16 to form a predetermined shape (for example, a polyhedron such as a rectangular parallelepiped). The sealing body is arbitrary as long as it is an insulating material capable of sealing the semiconductor element 16. For example, various resins such as epoxy resin (EP) and phenol resin (PF), thermosetting molding materials in which the resin is the main component and silica filler is added, heat resistant resins such as resin molds, This includes ceramics containing a metal oxide (for example, alumina) or an inorganic compound (for example, silicon nitride).

放熱部15は、半導体素子16で生じる熱を放出可能な任意の部材を適用でき、材質・材料・形状等を問わない。本形態の放熱部15は、半導体素子16と直接または間接に接して放熱する機能を担い、熱伝導率が高い材料(例えば銅板等のような金属板)で形成したものを用いる。各放熱部15は、各半導体素子16の発熱面(図示する上面や下面)に対向して配置される。放熱部15の形状は任意であり、図示するような平板状でもよく、半導体素子16の形状や発熱量等に応じて曲面状でもよい。板厚についても均一であると不均一であるとを問わない。   Any member capable of releasing heat generated in the semiconductor element 16 can be applied to the heat radiating portion 15, and any material, material, shape, etc. can be used. The heat radiating portion 15 of this embodiment has a function of directly or indirectly contacting the semiconductor element 16 and radiating heat, and is formed of a material having a high thermal conductivity (for example, a metal plate such as a copper plate). Each heat radiating portion 15 is disposed so as to face the heat generating surface (the upper surface and the lower surface in the drawing) of each semiconductor element 16. The shape of the heat radiating portion 15 is arbitrary, and may be a flat plate shape as illustrated, or may be a curved surface shape according to the shape of the semiconductor element 16, the heat generation amount, or the like. It does not matter whether the plate thickness is uniform or non-uniform.

2つの半導体素子16は、それぞれが目的とする処理を行う電気回路が半導体で形成されている。インバータやコンバータ等の電力変換装置に用いる場合には、一方の半導体素子16を上アーム側に用い、他方の半導体素子16を下アーム側に用いる。各半導体素子16は、半導体チップ、スイッチング素子、当該スイッチング素子を駆動する駆動回路、還流用ダイオードなどが該当する。スイッチング素子は、例えばFET(具体的にはMOSFET,JFET,MESFET等)、IGBT、GTO、パワートランジスタ、ダイオード、サイリスタなどが該当する。各半導体素子16は、端子12,17との間でワイヤボンディング等によって予め接続される(図示せず)。   Each of the two semiconductor elements 16 is formed of a semiconductor in an electric circuit that performs a target process. When used in a power conversion device such as an inverter or a converter, one semiconductor element 16 is used on the upper arm side, and the other semiconductor element 16 is used on the lower arm side. Each semiconductor element 16 corresponds to a semiconductor chip, a switching element, a driving circuit for driving the switching element, a freewheeling diode, or the like. Examples of the switching element include an FET (specifically, MOSFET, JFET, MESFET, etc.), IGBT, GTO, power transistor, diode, thyristor, and the like. Each semiconductor element 16 is connected in advance between the terminals 12 and 17 by wire bonding or the like (not shown).

端子12,17はそれぞれが「接続部材」に相当し、信号や電力の入出力を行う外部装置を接続する。図1(A)の構成例では、端子12を上面側に設け、端子17を下面側に設けている。なお、端子をどの面に設けるのかは任意であり、端子数を幾つに設定するのかも任意である。端子12に接続する外部装置の一例としては、例えば各半導体素子16へ個別に信号を入力するコントローラ(例えばECUやコンピュータ等)が該当する。端子17に接続する外部装置の一例としては、回転電機(例えば発電機,電動機,電動発電機等)や電力系統等が該当する。図1(A)の構成例では端子17が3つあるので、各端子は三相(U相,V相,W相)の電力を出力する端子に対応する。よって、接続する外部装置の相数に応じて端子17の数も異なってくる。   Each of the terminals 12 and 17 corresponds to a “connection member”, and is connected to an external device that inputs and outputs signals and power. In the configuration example of FIG. 1A, the terminal 12 is provided on the upper surface side, and the terminal 17 is provided on the lower surface side. It should be noted that on which surface the terminals are provided is arbitrary, and how many terminals are set is also arbitrary. An example of an external device connected to the terminal 12 is a controller (for example, an ECU or a computer) that individually inputs a signal to each semiconductor element 16. As an example of the external device connected to the terminal 17, a rotating electrical machine (for example, a generator, a motor, a motor generator, etc.), a power system, and the like are applicable. Since there are three terminals 17 in the configuration example of FIG. 1A, each terminal corresponds to a terminal that outputs three-phase (U-phase, V-phase, W-phase) power. Therefore, the number of terminals 17 varies depending on the number of phases of external devices to be connected.

絶縁部材14は、熱伝導性があり、電気的絶縁性を有すれば任意の部材を適用でき、材質や材料等を問わない。本形態の絶縁部材14は、絶縁性の樹脂で形成される絶縁フィルムを用い、接着・溶着・一体成形等によって固定される。図1(B)に示すように、半導体モジュール10の複数面(本例では非接続面の4面)を周回し、放熱部15を介して半導体素子16を覆う。図1(B)の構成例では1周(1層)で形成しているが、2周(2層)以上の数周(数層)で形成してもよい。   The insulating member 14 is thermally conductive, and any member can be applied as long as it has electrical insulation, regardless of material or material. The insulating member 14 of this embodiment uses an insulating film formed of an insulating resin, and is fixed by adhesion, welding, integral molding, or the like. As shown in FIG. 1B, the semiconductor element 10 is circulated around a plurality of surfaces of the semiconductor module 10 (in this example, four non-connection surfaces), and the semiconductor element 16 is covered via the heat dissipation portion 15. In the configuration example of FIG. 1B, it is formed with one turn (one layer), but it may be formed with two or more turns (two layers) or more.

導体部材13は、絶縁部材14を通じて放熱部15から伝わる熱を外部に逃がす機能を担い、半導体素子16に対向する面とは反対側の面(すなわち絶縁部材14の外面)に備えられる。本形態の導体部材13は、一面(図1(B)の上面または下面)における2つの放熱部15の合計面積よりも広い面積で形成され、接着や溶着等によって予め絶縁部材14と一体成形される。この導体部材13は、絶縁部材14よりも熱伝導率が高い材質や材料等であれば任意である。例えば銅(Cu)やアルミニウム(Al)等が該当する。なお、絶縁部材14と導体部材13との厚みについては、同一でもよく異なってもよい。   The conductor member 13 has a function of radiating heat transmitted from the heat radiation part 15 through the insulating member 14 to the outside, and is provided on a surface opposite to the surface facing the semiconductor element 16 (that is, the outer surface of the insulating member 14). The conductor member 13 of this embodiment is formed in an area wider than the total area of the two heat dissipating portions 15 on one surface (the upper surface or the lower surface in FIG. 1B), and is integrally formed with the insulating member 14 in advance by bonding or welding. The The conductor member 13 is optional as long as it is a material or material having a higher thermal conductivity than the insulating member 14. For example, copper (Cu), aluminum (Al), and the like are applicable. The thicknesses of the insulating member 14 and the conductor member 13 may be the same or different.

上述した実施の形態1によれば、以下に示す各効果を得ることができる。まず請求項1に対応し、半導体モジュール10において、絶縁部材14は、半導体モジュール10の複数面を周回して覆う構成とした(図1を参照)。この構成によれば、放熱部15と絶縁部材14との間に生じる温度差に基づく線膨張係数差による応力が発生しても、従来よりは絶縁部材14の剥離を抑止することができる。   According to the first embodiment described above, the following effects can be obtained. First, corresponding to claim 1, in the semiconductor module 10, the insulating member 14 is configured to surround and cover a plurality of surfaces of the semiconductor module 10 (see FIG. 1). According to this configuration, even if a stress due to a difference in linear expansion coefficient based on a temperature difference generated between the heat radiating portion 15 and the insulating member 14 is generated, it is possible to suppress the peeling of the insulating member 14 as compared with the related art.

請求項2に対応し、絶縁部材14は、半導体モジュール10の複数面を周回して覆う場合、端子12,17(接続部材)を有する面を除いた全ての面、すなわち非接続面を覆う構成とした(図1を参照)。この構成によれば、放熱部15と絶縁部材14との間に生じる温度差に基づく線膨張係数差による応力が発生しても、絶縁部材14の剥離をより確実に抑止することができる。   Corresponding to claim 2, when the insulating member 14 wraps around a plurality of surfaces of the semiconductor module 10, the insulating member 14 covers all surfaces except the surfaces having the terminals 12 and 17 (connection members), that is, the non-connection surfaces. (See FIG. 1). According to this configuration, even if a stress due to a difference in linear expansion coefficient based on a temperature difference generated between the heat radiating portion 15 and the insulating member 14 occurs, the peeling of the insulating member 14 can be more reliably suppressed.

請求項5に対応し、絶縁部材14は、半導体素子16に対向する面とは反対側の面に導体部材13を有する構成とした(図1を参照)。この構成によれば、絶縁部材14が受ける熱で線膨張係数差によって応力が生じても導体部材13から放熱するので、絶縁部材14の剥離をより確実に抑止することができる。   Corresponding to claim 5, the insulating member 14 has a conductor member 13 on the surface opposite to the surface facing the semiconductor element 16 (see FIG. 1). According to this configuration, since heat is radiated from the conductor member 13 even if stress is generated due to the difference in linear expansion coefficient due to the heat received by the insulating member 14, peeling of the insulating member 14 can be more reliably suppressed.

請求項6に対応し、導体部材13は、予め絶縁部材14と一体成形される構成とした(図1を参照)。この構成によれば、絶縁部材14と導体部材13とが予め一体成形されているので、あとは半導体素子16や放熱部15を覆えばよい。絶縁部材14と導体部材13との接着や接合を行う工程が不要になるので、半導体モジュール10の製造に要する時間を短縮することができる。   Corresponding to claim 6, the conductor member 13 is previously formed integrally with the insulating member 14 (see FIG. 1). According to this configuration, since the insulating member 14 and the conductor member 13 are integrally formed in advance, the semiconductor element 16 and the heat radiating portion 15 may be covered thereafter. Since the process of bonding or joining the insulating member 14 and the conductor member 13 is not required, the time required for manufacturing the semiconductor module 10 can be shortened.

請求項7に対応し、絶縁部材14は絶縁フィルムである構成とした(図1を参照)。この構成によれば、絶縁部材14として用いる絶縁フィルムは一般的に厚みが薄いので、半導体モジュール10全体の体格を小さく抑えることができる。なお、絶縁フィルムに代えて絶縁シートを用いる場合でも同様の作用効果を得ることができる。   Corresponding to claim 7, the insulating member 14 is an insulating film (see FIG. 1). According to this configuration, since the insulating film used as the insulating member 14 is generally thin, the overall size of the semiconductor module 10 can be kept small. Even when an insulating sheet is used instead of the insulating film, the same effect can be obtained.

〔実施の形態2〕
実施の形態2は、実施の形態1と同様に2つの半導体素子を備える半導体モジュールの第2構成例であって、図2を参照しながら説明する。図2(A)には平面図で示し、図2(B)には図2(A)に示すIIB−IIB矢視の断面図を示す。図示および説明を簡単にするために、実施の形態2では実施の形態1と異なる点について説明する。よって実施の形態1で用いた要素と同一の要素には同一の符号を付して説明を省略する。
[Embodiment 2]
The second embodiment is a second configuration example of a semiconductor module including two semiconductor elements as in the first embodiment, and will be described with reference to FIG. 2A is a plan view, and FIG. 2B is a cross-sectional view taken along the line IIB-IIB shown in FIG. In order to simplify the illustration and description, the second embodiment will be described with respect to differences from the first embodiment. Therefore, the same elements as those used in Embodiment 1 are denoted by the same reference numerals, and description thereof is omitted.

実施の形態2が実施の形態1と異なるのは、絶縁部材14の構成である。実施の形態1では半導体モジュール10の複数面(本例では非接続面の4面)を周回する構成であるのに対して(図1(B)を参照)、実施の形態2では絶縁部材14に重畳部位をさらに有する点で相違する。図2(A)や図2(B)の楕円内に示す重畳部位18を有する。この重畳部位18は、絶縁部材14の少なくとも一部を重ねて一体化する部位である。重畳部位18の配置は、半導体モジュール10における放熱部15を備えない面(例えば図2の側面等)に限らず、放熱部15を備える面であっても当該放熱部15から所定距離(例えば5[mm]や10[mm]等)だけ離れた部位などであってもよい。   The second embodiment differs from the first embodiment in the configuration of the insulating member 14. In the first embodiment, the semiconductor module 10 is configured to circulate on a plurality of surfaces (four unconnected surfaces in this example) (see FIG. 1B), whereas in the second embodiment, the insulating member 14 is provided. Is different in that it further has a superimposed portion. It has the superimposition part 18 shown in the ellipse of FIG. 2 (A) and FIG. 2 (B). The overlapping portion 18 is a portion where at least a part of the insulating member 14 is overlapped and integrated. The arrangement of the overlapping portion 18 is not limited to a surface (for example, the side surface in FIG. 2) of the semiconductor module 10 that does not include the heat radiating portion 15, but also a surface that includes the heat radiating portion 15. [mm], 10 [mm], etc.)

重畳部位18(特に接触面)の固定手段は任意である。例えば、接着剤を用いて重畳部位18を着ける接着、および、重畳部位18を溶かして着ける溶着のうちで一方または双方が該当する。接着や溶着以外では、重畳部位18を圧縮して着ける圧着などが該当する。これらのうちで二以上の固定手段を任意に選択して行ってもよい。   The fixing means for the overlapping portion 18 (particularly the contact surface) is arbitrary. For example, one or both of the bonding that attaches the overlapping portion 18 using an adhesive and the welding that melts and attaches the overlapping portion 18 correspond to this. Other than adhesion and welding, crimping that compresses and attaches the overlapped portion 18 is applicable. Of these, two or more fixing means may be arbitrarily selected and performed.

上述した実施の形態2によれば、以下に示す各効果を得ることができる。重畳部位18を除く半導体モジュール10の構成は実施の形態1と同様であるので、請求項1,2,5,6に対応する効果も実施の形態1と同様である。   According to the second embodiment described above, the following effects can be obtained. Since the configuration of the semiconductor module 10 excluding the overlapping portion 18 is the same as that of the first embodiment, the effect corresponding to claims 1, 2, 5, and 6 is the same as that of the first embodiment.

請求項3に対応し、絶縁部材14は、半導体モジュール10における放熱部15を備えない面で少なくとも一部を重ねる重畳部位18を有し、重畳部位18を一体化させる構成とした(図2を参照)。この構成によれば、放熱部15と絶縁部材14との間に生じる温度差に基づく線膨張係数差による応力が発生しても、重畳部位18が絶縁部材14の剥離をより確実に抑止することができる。   Corresponding to claim 3, the insulating member 14 has a superposition part 18 that overlaps at least a part of the surface of the semiconductor module 10 that does not include the heat radiating part 15, and is configured to integrate the superposition part 18 (see FIG. 2). reference). According to this configuration, even when a stress due to a difference in linear expansion coefficient based on a temperature difference generated between the heat radiating portion 15 and the insulating member 14 occurs, the overlapping portion 18 more reliably suppresses the peeling of the insulating member 14. Can do.

請求項4に対応し、重畳部位18の一体化は、接着および溶着のうちで一方または双方で行う構成とした(図2を参照)。この構成によれば、重畳部位18は接着および溶着のうちで一方または双方で確実に一体化されるので、重畳部位18が絶縁部材14の剥離をより確実に抑止することができる。   Corresponding to claim 4, the overlapping portion 18 is integrated by one or both of adhesion and welding (see FIG. 2). According to this configuration, since the overlapping portion 18 is reliably integrated with one or both of adhesion and welding, the overlapping portion 18 can more reliably suppress peeling of the insulating member 14.

〔実施の形態3〕
実施の形態3は、実施の形態1と同様に2つの半導体素子を備える半導体モジュールの第3構成例であって、図3を参照しながら説明する。図3(A)には平面図で示し、図3(B)には図3(A)に示すIIIB−IIIB矢視の断面図を示す。図示および説明を簡単にするために、実施の形態3では実施の形態1と異なる点について説明する。よって実施の形態1で用いた要素と同一の要素には同一の符号を付して説明を省略する。
[Embodiment 3]
The third embodiment is a third configuration example of a semiconductor module including two semiconductor elements as in the first embodiment, and will be described with reference to FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along arrow IIIB-IIIB shown in FIG. In order to simplify the illustration and description, the third embodiment will be described with respect to differences from the first embodiment. Therefore, the same elements as those used in Embodiment 1 are denoted by the same reference numerals, and description thereof is omitted.

実施の形態3が実施の形態1と異なるのは、導体部材13の構成である。実施の形態1では各導体部材13が2つの放熱部15の合計面積よりも広い面積で形成する構成であるのに対して(図1を参照)、実施の形態3では絶縁部材14と同様に半導体モジュール10の複数面(本例では非接続面の4面)を周回する点で相違する。すなわち、絶縁部材14と導体部材13とを同一形状に形成して覆う。「同一形状」には、所定の許容範囲内(例えば±X[mm]や±Y[%]の範囲内;XとYは定数である。)で異なる形状を含む。特に導体部材13を絶縁部材14と予め一体成形すれば、放熱部15を介して半導体素子16を覆うだけでよく、半導体モジュール10の製造に要する時間を短縮することができる。   The third embodiment differs from the first embodiment in the configuration of the conductor member 13. In the first embodiment, each conductor member 13 is formed to have a larger area than the total area of the two heat radiating portions 15 (see FIG. 1), whereas in the third embodiment, similarly to the insulating member 14. The semiconductor module 10 is different in that it circulates around a plurality of surfaces (in this example, four non-connection surfaces). That is, the insulating member 14 and the conductor member 13 are formed in the same shape and covered. The “same shape” includes different shapes within a predetermined allowable range (for example, within a range of ± X [mm] or ± Y [%]; X and Y are constants). In particular, if the conductor member 13 is integrally formed with the insulating member 14 in advance, it is only necessary to cover the semiconductor element 16 via the heat radiating portion 15, and the time required for manufacturing the semiconductor module 10 can be shortened.

上述した実施の形態3によれば、導体部材13の構成が相違するに過ぎないので、実施の形態1と同様の作用効果を得ることができる。   According to the third embodiment described above, since the configuration of the conductor member 13 is only different, the same effect as that of the first embodiment can be obtained.

〔実施の形態4〕
実施の形態4は、実施の形態1と同様に2つの半導体素子を備える半導体モジュールの第4構成例であって、図4を参照しながら説明する。図4(A)には平面図で示し、図4(B)には図4(A)に示すIVB−IVB矢視の断面図を示す。図示および説明を簡単にするために、実施の形態4では実施の形態1と異なる点について説明する。よって実施の形態1で用いた要素と同一の要素には同一の符号を付して説明を省略する。
[Embodiment 4]
The fourth embodiment is a fourth configuration example of a semiconductor module including two semiconductor elements as in the first embodiment, and will be described with reference to FIG. 4A is a plan view, and FIG. 4B is a cross-sectional view taken along the arrow IVB-IVB shown in FIG. 4A. In order to simplify the illustration and description, the fourth embodiment will be described with respect to differences from the first embodiment. Therefore, the same elements as those used in Embodiment 1 are denoted by the same reference numerals, and description thereof is omitted.

実施の形態4が実施の形態1と異なるのは、絶縁部材14の構成である。実施の形態1では半導体モジュール10の複数面(本例では非接続面の4面)を周回する構成であるのに対して(図1を参照)、実施の形態4では半導体モジュール10における端子12,17を除いた全表面を覆う点で相違する。「半導体モジュール10の全表面を覆う」とは、少なくとも半導体素子16の全表面を覆うことを意味し、現実的には樹脂封止部11の全表面を覆う形態である。以下の説明においても同様の意図で用いる。通常は一体成形が可能な成形機(例えば射出成形機や圧縮成形機等)によって絶縁部材14の形成を行うが、成形機以外の加工機によって絶縁部材14の形成を行ってもよい。   The fourth embodiment differs from the first embodiment in the configuration of the insulating member 14. In the first embodiment, the semiconductor module 10 is configured to circulate around a plurality of surfaces (four non-connection surfaces in this example) (see FIG. 1), whereas in the fourth embodiment, the terminals 12 of the semiconductor module 10 are provided. , 17 except that it covers the entire surface. “Covering the entire surface of the semiconductor module 10” means covering at least the entire surface of the semiconductor element 16, and is actually a form of covering the entire surface of the resin sealing portion 11. In the following description, the same intention is used. Normally, the insulating member 14 is formed by a molding machine capable of integral molding (for example, an injection molding machine, a compression molding machine, etc.), but the insulating member 14 may be formed by a processing machine other than the molding machine.

導体部材13は、実施の形態1と同様に2つの放熱部15の合計面積よりも広い面積で形成し、全表面を覆った絶縁部材14に対して接着や溶着等によって固定する。なお絶縁部材14と同様にして、半導体モジュール10における端子12,17を除いた全表面を導体部材13で覆う構成としてもよい。ただし、導体部材13は導電性であるので、端子12,17との間で非接触かつ所要の絶縁抵抗を確保する隙間を設ける必要がある。   The conductor member 13 is formed in a larger area than the total area of the two heat dissipating parts 15 as in the first embodiment, and is fixed to the insulating member 14 covering the entire surface by adhesion or welding. In the same manner as the insulating member 14, the entire surface of the semiconductor module 10 except for the terminals 12 and 17 may be covered with the conductor member 13. However, since the conductor member 13 is conductive, it is necessary to provide a gap between the terminals 12 and 17 that ensures non-contact and a required insulation resistance.

上述した実施の形態4によれば、請求項1に対応し、半導体モジュール10において、絶縁部材14は、半導体モジュール10の全表面を覆う構成とした(図4を参照)。この構成によれば、放熱部15と絶縁部材14との間に生じる温度差に基づく線膨張係数差による応力が発生しても、従来よりは絶縁部材14の剥離を抑止することができる。なお請求項2,5,6,7については、絶縁部材14の構成が相違するに過ぎないので、実施の形態1と同様の作用効果を得ることができる。   According to the fourth embodiment described above, corresponding to claim 1, in the semiconductor module 10, the insulating member 14 is configured to cover the entire surface of the semiconductor module 10 (see FIG. 4). According to this configuration, even if a stress due to a difference in linear expansion coefficient based on a temperature difference generated between the heat radiating portion 15 and the insulating member 14 is generated, it is possible to suppress the peeling of the insulating member 14 as compared with the related art. In the second, fifth, sixth, and seventh aspects, since only the configuration of the insulating member 14 is different, the same effect as the first embodiment can be obtained.

〔他の実施の形態〕
以上では本発明を実施するための形態について実施の形態1〜4に従って説明したが、本発明は当該形態に何ら限定されるものではない。言い換えれば、本発明の要旨を逸脱しない範囲内において、種々なる形態で実施することもできる。例えば、次に示す各形態を実現してもよい。
[Other Embodiments]
In the above, although the form for implementing this invention was demonstrated according to Embodiment 1-4, this invention is not limited to the said form at all. In other words, various forms can be implemented without departing from the scope of the present invention. For example, the following forms may be realized.

上述した実施の形態1〜4では、半導体モジュール10内に備える半導体素子16の素子数を2とした(図1〜図4を参照)。この形態に代えて、所定数で半導体素子16を備える半導体モジュール10に適用することも可能である。例えば実施の形態1に対応する構成として、一列にタイル状に並べて3つの半導体素子16を備える半導体モジュール10の構成例を図5に示し、二行二列のタイル状に並べて4つの半導体素子16を備える半導体モジュール10の構成例を図6に示す。具体的には、図5(A)には平面図を示し、図5(B)には図5(A)に示すVB−VB矢視の断面図を示し、図6には平面図を示す、なお、図6に示すIB−IB矢視の断面図は図1(B)と同様の構成になる。半導体素子16の素子数に関する「所定数」は1以上で任意に設定可能であるが、現実的には数個〜十数個程度になる。図示しないが、実施の形態2〜4に示す半導体モジュール10についても、図5や図6と同様の構成とすることも可能である。いずれの形態にせよ、半導体素子16の素子数が相違するに過ぎないので、実施の形態1〜4に示す各請求項に対応して同様の作用効果を得ることができる。   In the first to fourth embodiments described above, the number of the semiconductor elements 16 provided in the semiconductor module 10 is set to two (see FIGS. 1 to 4). Instead of this form, it is also possible to apply to a semiconductor module 10 including a predetermined number of semiconductor elements 16. For example, as a configuration corresponding to the first embodiment, a configuration example of the semiconductor module 10 including three semiconductor elements 16 arranged in a tile in one column is illustrated in FIG. 5, and four semiconductor elements 16 are arranged in a tile in two rows and two columns. FIG. 6 shows a configuration example of the semiconductor module 10 including the above. Specifically, FIG. 5A shows a plan view, FIG. 5B shows a cross-sectional view taken along arrow VB-VB shown in FIG. 5A, and FIG. 6 shows a plan view. Note that the cross-sectional view taken along the arrow IB-IB shown in FIG. 6 has the same configuration as that in FIG. The “predetermined number” relating to the number of elements of the semiconductor element 16 can be arbitrarily set to 1 or more, but in reality, it is about several to a dozen. Although not shown, the semiconductor module 10 shown in the second to fourth embodiments can have the same configuration as that shown in FIGS. In any form, since the number of elements of the semiconductor element 16 is only different, the same effect can be obtained corresponding to each claim shown in the first to fourth embodiments.

上述した実施の形態1〜4では、両面モジュールとしての半導体モジュール10を適用した(図1〜図4を参照)。この形態に代えて、片面モジュールとしての半導体モジュール10に適用することも可能である。例えば図7には、実施の形態1に示す半導体モジュール10に対応する片面モジュールの構成例を示す。図7(A)には平面図で示し、図7(B)には図7(A)に示すVIIB−VIIB矢視の断面図を示す。実施の形態1で用いた要素と同一の要素には同一の符号を付して説明を省略する。   In the first to fourth embodiments described above, the semiconductor module 10 as a double-sided module is applied (see FIGS. 1 to 4). It can replace with this form and can also apply to the semiconductor module 10 as a single-sided module. For example, FIG. 7 shows a configuration example of a single-sided module corresponding to the semiconductor module 10 shown in the first embodiment. 7A is a plan view, and FIG. 7B is a cross-sectional view taken along the arrow VIIB-VIIB shown in FIG. 7A. The same elements as those used in Embodiment 1 are denoted by the same reference numerals, and description thereof is omitted.

片面モジュールとしての半導体モジュール10は、実施の形態1に示す両面モジュールとしての半導体モジュール10と比べて、放熱部15の数が相違する。実施の形態1では各半導体素子16の両面側に対応して4つ備えるのに対して、図7の構成例では各半導体素子16の片面側に対応して2つ備える。絶縁部材14や導体部材13の構成は実施の形態1と同等である(図1を参照)。図示しないが、実施の形態2〜4に示す半導体モジュール10についても、図7と同様の構成とすることも可能である。いずれの形態にせよ、放熱部15の数が実施の形態1〜4と相違するに過ぎないので、実施の形態1〜4に示す各請求項に対応して同様の作用効果を得ることができる。   The semiconductor module 10 as a single-sided module is different from the semiconductor module 10 as a double-sided module shown in Embodiment 1 in the number of heat radiation portions 15. In the first embodiment, four semiconductor devices 16 are provided corresponding to both sides of each semiconductor element 16, whereas in the configuration example of FIG. 7, two semiconductor devices 16 are provided corresponding to one side. The configuration of the insulating member 14 and the conductor member 13 is the same as that of the first embodiment (see FIG. 1). Although not shown, the semiconductor module 10 shown in the second to fourth embodiments can also have the same configuration as that in FIG. In any form, since the number of the heat radiating portions 15 is only different from the first to fourth embodiments, the same effects can be obtained corresponding to the claims shown in the first to fourth embodiments. .

上述した実施の形態1〜4では、絶縁部材14を用いて、半導体モジュール10の全表面を覆うか(図4を参照)、または、複数面を周回して覆う構成とした(図1,図2,図3,図5を参照)。言い換えれば、絶縁部材14の被覆面積は導体部材13の被覆面積よりも広くなるように構成した。ここに言う「被覆面積」は半導体モジュール10を覆う面積を意味する。この形態に代えて、導体部材13の被覆面積が絶縁部材14の被覆面積よりも広く形成し、半導体モジュール10の全表面を覆うか(図4を参照)、または、複数面を周回して覆う構成としてもよい。   In the above-described first to fourth embodiments, the insulating member 14 is used to cover the entire surface of the semiconductor module 10 (see FIG. 4) or to wrap around a plurality of surfaces (FIGS. 1 and 1). 2, see FIGS. 3 and 5). In other words, the covering area of the insulating member 14 is configured to be larger than the covering area of the conductor member 13. Here, “covered area” means an area covering the semiconductor module 10. Instead of this form, the covering area of the conductor member 13 is formed wider than the covering area of the insulating member 14 and covers the entire surface of the semiconductor module 10 (see FIG. 4) or covers around a plurality of surfaces. It is good also as a structure.

例えば図8(A)および図8(B)には、複数面を周回して覆う構成である実施の形態1(図1)とは逆に、一面(図8(B)の上面または下面)における2つの放熱部15の合計面積よりも広い面積で絶縁部材14を形成し、半導体モジュール10の複数面(図8では非接続面の4面)を周回して半導体モジュール10を覆う構成を示す。図8(A)には平面図で示し、図8(B)には図8(A)に示すVIIIB−VIIIB矢視の断面図を示す。角部は、図8(B)に実線で示すような階段形状としてもよく、二点鎖線で示すように丸めてもよい。図示しないが、実施の形態2〜4に示す半導体モジュール10についても、図8と同様の構成とすることも可能である。なお、絶縁部材14と導体部材13とを同一形状(同等の被覆面積)に形成して覆う構成は実施の形態3(図3)に示す通りであり、実施の形態1,2,4も同様に適用することも可能である。いずれの形態にせよ、絶縁部材14と導体部材13とにかかる被覆面積が相違するに過ぎないので、実施の形態1〜4に示す各請求項に対応して同様の作用効果を得ることができる。   For example, in FIGS. 8A and 8B, one surface (upper surface or lower surface in FIG. 8B) is opposite to Embodiment 1 (FIG. 1), which is configured to wrap around a plurality of surfaces. The structure which forms the insulating member 14 in an area wider than the total area of the two heat radiating parts 15 and covers the semiconductor module 10 by circling a plurality of surfaces of the semiconductor module 10 (four unconnected surfaces in FIG. 8) is shown. . 8A is a plan view, and FIG. 8B is a cross-sectional view taken along arrow VIIIB-VIIIB shown in FIG. 8A. The corner may have a staircase shape as shown by a solid line in FIG. 8B, or may be rounded as shown by a two-dot chain line. Although not shown, the semiconductor module 10 shown in the second to fourth embodiments can have the same configuration as that in FIG. In addition, the structure which forms and covers the insulating member 14 and the conductor member 13 in the same shape (equivalent covering area) is as shown in the third embodiment (FIG. 3), and the same applies to the first, second and fourth embodiments. It is also possible to apply to. In any form, since the covering areas for the insulating member 14 and the conductor member 13 are different from each other, the same function and effect can be obtained corresponding to each claim shown in the first to fourth embodiments. .

上述した実施の形態1〜4では、半導体素子16で発生した熱は、絶縁部材14を介して導体部材13に伝え、導体部材13から外部に放出する構成とした(図1〜図4を参照)。この形態に代えて、導体部材13に伝わる熱を積極的に吸収する熱吸収部材20を備える構成としてもよい。熱吸収部材20の構成例を図9と図10に示す。以下では、図9と図10に示す各構成例について説明する。   In the first to fourth embodiments described above, the heat generated in the semiconductor element 16 is transmitted to the conductor member 13 via the insulating member 14 and discharged to the outside from the conductor member 13 (see FIGS. 1 to 4). ). It may replace with this form and it is good also as a structure provided with the heat absorption member 20 which absorbs the heat transmitted to the conductor member 13 positively. The structural example of the heat absorption member 20 is shown in FIG. 9 and FIG. Below, each structural example shown in FIG. 9 and FIG. 10 is demonstrated.

図9の斜視図に示す熱吸収部材20は、複数の冷却体21aと複数の管路21bとで構成される冷却装置21である。冷却体21aの相互間にそれぞれ半導体モジュール10を矢印Dinで示すように配置し、冷却体21aの表面と導体部材13の表面とを接触させる。接触面積の広さに応じて熱交換が行われる。図9の構成例では冷却体21aが5つあるので、4つの半導体モジュール10からなる半導体モジュール群10G(具体的には半導体素子16)を冷却することができる。2つの管路21bのうちで、一方は流体(例えば水,空気,油等)を流入する流入路であり、他方は当該流体を流出させる流出路である。冷却装置21を用いることで絶縁部材14や導体部材13を積極的に冷却できる。   The heat absorbing member 20 shown in the perspective view of FIG. 9 is a cooling device 21 including a plurality of cooling bodies 21a and a plurality of pipe lines 21b. The semiconductor modules 10 are arranged between the cooling bodies 21a as indicated by arrows Din, and the surface of the cooling body 21a and the surface of the conductor member 13 are brought into contact with each other. Heat exchange is performed according to the size of the contact area. In the configuration example of FIG. 9, since there are five cooling bodies 21a, the semiconductor module group 10G (specifically, the semiconductor element 16) including the four semiconductor modules 10 can be cooled. Of the two pipe lines 21b, one is an inflow path through which fluid (for example, water, air, oil, etc.) flows, and the other is an outflow path through which the fluid flows out. By using the cooling device 21, the insulating member 14 and the conductor member 13 can be actively cooled.

図10の断面図に示す熱吸収部材20は、金属等で形成される冷却フィン22である。この冷却フィン22は、図示するように、複数の導体部材13と接合や接着等させる。冷却フィン22を用いる場合でも、絶縁部材14や導体部材13を積極的に冷却できる。   The heat absorbing member 20 shown in the cross-sectional view of FIG. 10 is a cooling fin 22 formed of metal or the like. As shown in the figure, the cooling fins 22 are bonded to or bonded to the plurality of conductor members 13. Even when the cooling fins 22 are used, the insulating member 14 and the conductor member 13 can be actively cooled.

上述した実施の形態1〜4では、接続部材として端子12,17を適用した(図1〜図4を参照)。この形態に代えて、端子12,17のうちで一方または双方に他の接続部材を適用してもよい。他の接続部材は、例えばリード、ピン、バスバー等が該当する。外部装置の接続に用いる接続部材の相違に過ぎないので、上述した実施の形態1〜4と同様の作用効果を得ることができる。   In Embodiment 1-4 mentioned above, the terminals 12 and 17 were applied as a connection member (refer FIGS. 1-4). Instead of this form, another connecting member may be applied to one or both of the terminals 12 and 17. Other connection members correspond to, for example, leads, pins, bus bars, and the like. Since only the connection member used for the connection of the external device is different, it is possible to obtain the same effects as those of the first to fourth embodiments.

10 半導体モジュール
11 樹脂封止部
12,17 端子(接続部材)
13 導体部材
14 絶縁部材
14a 第1絶縁部材
14b 第2絶縁部材
15 放熱部
16 半導体素子
18 重畳部位
20 熱吸収部材
21 冷却装置
22 冷却フィン
10 Semiconductor module 11 Resin sealing part 12, 17 Terminal (connection member)
DESCRIPTION OF SYMBOLS 13 Conductive member 14 Insulating member 14a 1st insulating member 14b 2nd insulating member 15 Heat radiation part 16 Semiconductor element 18 Overlapping part 20 Heat absorption member 21 Cooling device 22 Cooling fin

Claims (7)

複数の半導体素子と、各前記半導体素子で生じる熱を放出する放熱部と、少なくとも前記半導体素子を覆う絶縁部材とを備える半導体モジュールにおいて、
前記絶縁部材は、前記半導体モジュールの全表面を覆うか、または、複数面を周回して覆うことを特徴とする半導体モジュール。
In a semiconductor module comprising a plurality of semiconductor elements, a heat dissipation part that releases heat generated in each of the semiconductor elements, and an insulating member that covers at least the semiconductor elements,
The insulating member covers the entire surface of the semiconductor module or covers a plurality of surfaces around the semiconductor module.
前記絶縁部材は、前記半導体モジュールの複数面を周回して覆う場合、前記外部装置と電気的な接続を行う接続部材を有する面を除いた全ての面を覆うことを特徴とする請求項1に記載の半導体モジュール。   The said insulating member covers all the surfaces except the surface which has a connection member which makes an electrical connection with the said external device, when it wraps around and covers the several surface of the said semiconductor module. The semiconductor module as described. 前記絶縁部材は、前記半導体モジュールにおける前記放熱部を備えない面で少なくとも一部を重ねる重畳部位を有し、前記重畳部位を一体化させることを特徴とする請求項1または2に記載の半導体モジュール。   3. The semiconductor module according to claim 1, wherein the insulating member has an overlapping portion that overlaps at least a part on a surface of the semiconductor module that does not include the heat dissipation portion, and integrates the overlapping portion. . 前記重畳部位の一体化は、接着および溶着のうちで一方または双方で行うことを特徴とする請求項3に記載の半導体モジュール。   The semiconductor module according to claim 3, wherein the integration of the overlapping portions is performed by one or both of adhesion and welding. 前記絶縁部材は、前記半導体素子に対向する面とは反対側の面に導体部材を有することを特徴とする請求項1から4のいずれか一項に記載の半導体モジュール。   5. The semiconductor module according to claim 1, wherein the insulating member has a conductor member on a surface opposite to a surface facing the semiconductor element. 6. 前記導体部材は、予め前記絶縁部材と一体成形されることを特徴とする請求項5に記載の半導体モジュール。   The semiconductor module according to claim 5, wherein the conductor member is integrally formed with the insulating member in advance. 前記絶縁部材は、絶縁フィルムまたは絶縁シートであることを特徴とする請求項1から6のいずれか一項に記載の半導体モジュール。   The semiconductor module according to claim 1, wherein the insulating member is an insulating film or an insulating sheet.
JP2011248682A 2011-11-14 2011-11-14 Semiconductor module Active JP5845835B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011248682A JP5845835B2 (en) 2011-11-14 2011-11-14 Semiconductor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011248682A JP5845835B2 (en) 2011-11-14 2011-11-14 Semiconductor module

Publications (2)

Publication Number Publication Date
JP2013105884A true JP2013105884A (en) 2013-05-30
JP5845835B2 JP5845835B2 (en) 2016-01-20

Family

ID=48625226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011248682A Active JP5845835B2 (en) 2011-11-14 2011-11-14 Semiconductor module

Country Status (1)

Country Link
JP (1) JP5845835B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015053362A (en) * 2013-09-06 2015-03-19 株式会社日本自動車部品総合研究所 Lamination unit
WO2015186470A1 (en) * 2014-06-03 2015-12-10 日立オートモティブシステムズ株式会社 Semiconductor module, method for manufacturing semiconductor module, and electronic control device
KR20160062447A (en) * 2014-11-25 2016-06-02 현대모비스 주식회사 Film capacitor module of inverter for vehicle
JP2016127196A (en) * 2015-01-07 2016-07-11 株式会社ソシオネクスト Electronic device and method of manufacturing electronic device
JP7024900B1 (en) 2021-02-19 2022-02-24 富士電機株式会社 Semiconductor device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05235240A (en) * 1992-02-25 1993-09-10 Mitsubishi Electric Corp Method for mounting board of surface mounting type package and method for cooling printed board
WO1999019908A1 (en) * 1997-10-14 1999-04-22 Matsushita Electric Industrial Co., Ltd. Thermal conductive unit and thermal connection structure using same
JP2001308245A (en) * 2000-04-25 2001-11-02 Denso Corp Refrigerant cooling type both-face cooling semiconductor device
JP2005175130A (en) * 2003-12-10 2005-06-30 Toyota Motor Corp Semiconductor module, semiconductor device and load driver
JP2006128260A (en) * 2004-10-27 2006-05-18 Toyota Motor Corp Semiconductor device and semiconductor device having cooler
JP2007115816A (en) * 2005-10-19 2007-05-10 Shin Etsu Chem Co Ltd Mounting method of cover for heat generating electronic parts, and cover
JP2011159862A (en) * 2010-02-02 2011-08-18 Toyota Motor Corp Cooling device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05235240A (en) * 1992-02-25 1993-09-10 Mitsubishi Electric Corp Method for mounting board of surface mounting type package and method for cooling printed board
WO1999019908A1 (en) * 1997-10-14 1999-04-22 Matsushita Electric Industrial Co., Ltd. Thermal conductive unit and thermal connection structure using same
JP2001308245A (en) * 2000-04-25 2001-11-02 Denso Corp Refrigerant cooling type both-face cooling semiconductor device
JP2005175130A (en) * 2003-12-10 2005-06-30 Toyota Motor Corp Semiconductor module, semiconductor device and load driver
JP2006128260A (en) * 2004-10-27 2006-05-18 Toyota Motor Corp Semiconductor device and semiconductor device having cooler
JP2007115816A (en) * 2005-10-19 2007-05-10 Shin Etsu Chem Co Ltd Mounting method of cover for heat generating electronic parts, and cover
JP2011159862A (en) * 2010-02-02 2011-08-18 Toyota Motor Corp Cooling device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015053362A (en) * 2013-09-06 2015-03-19 株式会社日本自動車部品総合研究所 Lamination unit
WO2015186470A1 (en) * 2014-06-03 2015-12-10 日立オートモティブシステムズ株式会社 Semiconductor module, method for manufacturing semiconductor module, and electronic control device
KR20160062447A (en) * 2014-11-25 2016-06-02 현대모비스 주식회사 Film capacitor module of inverter for vehicle
KR102326063B1 (en) * 2014-11-25 2021-11-12 현대모비스 주식회사 Film capacitor module of inverter for vehicle
JP2016127196A (en) * 2015-01-07 2016-07-11 株式会社ソシオネクスト Electronic device and method of manufacturing electronic device
JP7024900B1 (en) 2021-02-19 2022-02-24 富士電機株式会社 Semiconductor device
JP2022127145A (en) * 2021-02-19 2022-08-31 富士電機株式会社 Semiconductor device

Also Published As

Publication number Publication date
JP5845835B2 (en) 2016-01-20

Similar Documents

Publication Publication Date Title
US10778113B2 (en) Intelligent power module, electric vehicle, and hybrid car
US9351423B2 (en) Semiconductor device and semiconductor device connection structure
JP5273101B2 (en) Semiconductor module and manufacturing method thereof
WO2016079995A1 (en) Semiconductor device and power module
JP7284566B2 (en) semiconductor equipment
CN108735692B (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
EP3026701B1 (en) Power module and manufacturing method thereof
WO2018043535A1 (en) Power module, power module with drive circuit, industrial equipment, electric automobile and hybrid car
CN110506330B (en) Power electronic module and electric power converter comprising the same
JP5845835B2 (en) Semiconductor module
JP2013105882A (en) Semiconductor module
WO2015198411A1 (en) Power-module device, power conversion device, and method for manufacturing power-module device
JP4531087B2 (en) Power semiconductor device
JP2015099846A (en) Semiconductor device, and method of manufacturing the same
JP2004040899A (en) Semiconductor module and power converter
WO2020184053A1 (en) Semiconductor device
ES2898791T3 (en) power module
JP2012248700A (en) Semiconductor device
JP3673776B2 (en) Semiconductor module and power conversion device
JP6503909B2 (en) Semiconductor device
JP7163583B2 (en) semiconductor equipment
WO2013065462A1 (en) Semiconductor device and manufacturing method therefor
JP2017054842A (en) Wiring board, semiconductor device, and semiconductor package
WO2018047485A1 (en) Power module and inverter device
JP2017011028A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20131218

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150127

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20150130

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150324

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20151027

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20151109

R151 Written notification of patent or utility model registration

Ref document number: 5845835

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250