JP2017011028A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can inhibit heat transfer between semiconductor chips while improving connection reliability of a first semiconductor chip having small Young's modulus.SOLUTION: A semiconductor device comprises: a first semiconductor chip 13; a second semiconductor chip 14 formed by a material having a Young's modulus larger than that of the first semiconductor chip; a heat sink 15 in which the first semiconductor chip and the second semiconductor chip are arranged alongside in an X direction on one surface 15a and heat of the first semiconductor chip and the second semiconductor chip is transferred; and an encapsulation resin body 19 for integrally encapsulating the first semiconductor chip, the second semiconductor chip and the one surface of the heat sink. The heat sink has a through hole 15c formed on a position in the X direction between a first region 15d which is an arrangement region of the first semiconductor chip and a second region 15e which is an arrangement region of the second semiconductor chip. The encapsulation resin body has a coating part 19e for coating the one surface and a filling part 19f which continues from the coating part to be filled in the through hole.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a semiconductor device in which a first semiconductor chip and a second semiconductor chip formed using materials having different Young's moduli are arranged on the same surface of a heat dissipation member and sealed with a sealing resin body.

  For example, Patent Document 1 discloses a semiconductor device in which a first semiconductor chip and a second semiconductor chip formed using materials having different Young's moduli are arranged on the same surface of a heat dissipation member. In this semiconductor device, the first semiconductor chip made of Si and the second semiconductor chip made of SiC are arranged on the same surface of the heat dissipation member.

JP 2013-87763 A

  The semiconductor device as described above usually further includes a sealing resin body. Then, at least one surface of the first semiconductor chip, the second semiconductor chip, and the heat dissipation member is integrally sealed with the sealing resin body.

  The second semiconductor chip is formed using a material having a higher Young's modulus than the first semiconductor chip, and is less likely to deform (hard) than the first semiconductor chip. For this reason, in the resin-encapsulated semiconductor device, the resin is easily peeled around the second semiconductor chip due to a change in temperature of the use environment. Since the first semiconductor chip and the second semiconductor chip are arranged on the same surface of the heat dissipation member, the resin peeling that occurs around the second semiconductor chip is caused by the interface between the sealing resin body and one surface of the heat dissipation member. There is a risk of progressing to one semiconductor chip side. That is, there is a possibility that the connection reliability of the first semiconductor chip with respect to the heat dissipation member is lowered.

  Further, the first semiconductor chip and the second semiconductor chip are disposed on the same surface of the heat dissipation member, and for example, heat generated by the first semiconductor chip is transmitted to the second semiconductor chip via the heat dissipation member. As described above, when the heat of one semiconductor chip is transferred to the other semiconductor chip, the other semiconductor chip becomes high temperature, and there is a possibility that the element characteristics are deteriorated.

  In view of the above problems, an object of the present invention is to provide a semiconductor device capable of suppressing heat transfer between semiconductor chips while improving connection reliability of a first semiconductor chip having a low Young's modulus.

  The invention disclosed herein employs the following technical means to achieve the above object. Note that the reference numerals in parentheses described in the claims and in this section indicate a corresponding relationship with specific means described in the embodiments described later as one aspect, and limit the technical scope of the invention. Not what you want.

  One of the disclosed inventions is a semiconductor device, which includes a first semiconductor chip (13), a second semiconductor chip (14) formed using a material having a Young's modulus larger than that of the first semiconductor chip, 15a, 16a, 22a) and a back surface (15b, 16b, 22b) opposite to each other in the thickness direction, the first semiconductor chip and the second semiconductor chip are arranged side by side on the one surface, and the first semiconductor A heat radiation member (15, 16, 22) to which heat generated by the chip and the second semiconductor chip is transmitted, and a sealing resin that integrally seals at least one surface of the first semiconductor chip, the second semiconductor chip, and the heat radiation member A body (19).

The heat dissipating member has, as one surface, a first region (15d, 16d, 22d) that is an arrangement region of the first semiconductor chip, and a second region (15e, 16e, 22e) that is an arrangement region of the second semiconductor chip. And through holes (15c, 16c, 22c) formed between the first region and the second region in the arrangement direction of the first semiconductor chip and the second semiconductor chip. Have
The sealing resin body is characterized by having a one surface covering portion (19e) that covers one surface and a filling portion (19f) that is connected to the one surface covering portion and is filled in the through hole.

  In the present invention, the heat dissipation member has a through hole at a position between the first region and the second region in the arrangement direction. And the sealing resin body is arrange | positioned in the through-hole. Therefore, even if resin peeling occurs around the second semiconductor chip due to the high Young's modulus, the resin peeling progresses at the interface between the filling portion and the wall surface of the through hole. For this reason, compared with the structure which does not have the conventional through-hole, the path | route of resin peeling from a 2nd semiconductor chip to a 1st semiconductor chip is long. Moreover, since the filling part which is a part of sealing resin body is arrange | positioned in a through-hole, the contact area of a sealing resin body and a thermal radiation member is large compared with the past. Further, the filling portion is provided extending in the thickness direction from the one surface side covering portion, and functions as an anchor. As described above, the semiconductor device of the present invention can suppress the resin peeling from progressing toward the first semiconductor chip even if the resin peeling occurs around the second semiconductor chip. That is, the connection reliability of the first semiconductor chip with respect to the heat dissipation member can be improved as compared with the conventional case.

  Moreover, the through-hole penetrates over one surface and the back surface of the heat radiating member, and there is no heat radiating member in the through-hole forming portion. Therefore, the semiconductor device of the present invention can suppress heat transfer between the first semiconductor chip and the second semiconductor chip.

  One of the other disclosed inventions is characterized in that the first semiconductor chip and the second semiconductor chip are driven in parallel, and the amount of heat generated by the driving is larger in the first semiconductor chip than in the second semiconductor chip.

  With the above-described through-hole, it is possible to suppress the heat generated by the first semiconductor chip from being transmitted to the second semiconductor chip through the heat dissipation member. Therefore, the semiconductor device of the present invention can suppress the deterioration of the characteristics of the elements formed on the second semiconductor chip due to the heat transfer of the second semiconductor chip. Moreover, since it can suppress that resin peeling progresses to the 1st semiconductor chip side among the 1st semiconductor chip and 2nd semiconductor chip which are driven in parallel, fail-safe property can also be improved.

It is a figure which shows schematic structure of the power converter device with which the semiconductor device of 1st Embodiment is applied. It is a top view which shows schematic structure of a semiconductor device. In a semiconductor device, it is the top view which omitted the sealing resin body. It is a top view which shows the position of the through-hole in a heat sink. It is sectional drawing which follows the VV line of FIG. It is sectional drawing which follows the VI-VI line of FIG. It is a top view which shows a 1st modification. It is a top view which shows the 2nd modification. It is sectional drawing which shows a 3rd modification. In the semiconductor device concerning a 2nd embodiment, it is a top view showing the position of the penetration hole in a heat sink. In the semiconductor device concerning a 2nd embodiment, it is a sectional view showing the circumference of a penetration hole. In the semiconductor device concerning a 3rd embodiment, it is a sectional view showing the circumference of a penetration hole. It is sectional drawing which shows a 4th modification. It is sectional drawing which shows a 5th modification.

  Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, common or related elements are given the same reference numerals. Moreover, the thickness direction of a heat sink is shown as a Z direction. An arrangement direction of the first semiconductor chip and the second semiconductor chip that are orthogonal to the Z direction and constitute the same arm is indicated as an X direction. A direction perpendicular to both the Z direction and the X direction is referred to as a Y direction. The XY plane defined by the X direction and the Y direction described above is a plane orthogonal to the Z direction, and unless otherwise specified, the shape along the XY plane is a planar shape.

(First embodiment)
First, an example of a power conversion device to which a semiconductor device is applied will be described with reference to FIG.

  A power conversion device 1 shown in FIG. 1 is configured to convert a DC voltage supplied from a DC power source 2 into a three-phase AC and output it to a three-phase AC motor 3. Such a power converter 1 is mounted on, for example, an electric vehicle (EV) or a hybrid vehicle (HV). The power conversion device 1 can also convert the electric power generated by the motor 3 into direct current and charge the battery as the direct current power source 2. For this reason, the motor 3 is also referred to as a motor generator. Reference numeral 4 shown in FIG. 1 is a smoothing capacitor.

  The power converter 1 has a three-phase inverter. The three-phase inverter is a three-phase circuit provided between a high potential power line 5 connected to the positive electrode (high potential side) of the DC power source 2 and a low potential power line 6 connected to the negative electrode (low potential side). Has upper and lower arms. The upper and lower arms of each phase are each constituted by a semiconductor device 10. That is, in the present embodiment, the semiconductor device 10 constitutes the upper and lower arms for one phase.

  The semiconductor device 10 includes two IGBTs 11 and two MOSFETs 12. The two IGBTs 11 are connected in series between the high potential power line 5 and the low potential power line 6. A MOSFET 12 is connected to each IGBT 11 in parallel. Note that a reflux FWD (not shown) is connected to the IGBT 11 in reverse parallel and can be refluxed by the FWD. The MOSFET 12 has a parasitic diode (not shown), and current is circulated by the parasitic diode.

  In the present embodiment, an n-channel IGBT 11 and an n-channel MOSFET 12 are employed. The cathode electrode of the FWD is shared with the collector electrode of the IGBT 11, and the anode electrode is shared with the emitter electrode. The cathode electrode of the parasitic diode is shared with the drain electrode of the MOSFET 12, and the anode electrode is shared with the source electrode.

  In the semiconductor device 10, the collector electrode of the IGBT 11 on the upper arm (high side) side is electrically connected to the high potential power supply line 5, and the emitter electrode is connected to the output line 7 to the motor 3. On the other hand, the collector electrode of the IGBT 11 on the lower arm (low side) side is connected to the output line 7, and the emitter electrode is electrically connected to the low potential power supply line 6. The drain electrode of the MOSFET 12 on the upper arm side is electrically connected to the collector electrode of the IGBT 11 on the upper arm side, that is, the high-potential power line 5, and the source electrode is the emitter electrode of the IGBT 11 on the upper arm side, that is, the output line. 7 is connected. On the other hand, the drain electrode of the MOSFET 12 on the lower arm side is electrically connected to the collector electrode and the output line 7 of the IGBT 11 on the lower arm side, and the source electrode is the emitter electrode of the IGBT 11 on the lower arm side, that is, the low-potential power line 6. And are electrically connected.

  In addition to the above-described three-phase inverter, the power conversion device 1 is used as a boost converter that boosts a DC voltage supplied from the DC power supply 2, an IGBT 11 and a MOSFET 12 that constitute a three-phase inverter, and a switching element that constitutes a boost converter. A drive circuit that outputs a drive signal and a control unit that outputs a control signal to the drive circuit may be included.

  As described above, the configuration in which the IGBT 11 and the MOSFET 12 are connected in parallel is well known. The saturation voltage at the time of ON is smaller in the MOSFET 12 in the small current region and smaller in the IGBT 11 in the large current region. For example, ON / OFF of the IGBT 11 and the MOSFET 12 is controlled so that a current flows through the MOSFET 12 in the small current region and a current flows through the IGBT 11 in the large current region. By such control, on-loss can be reduced. Further, since the turn-off loss is only the loss of the MOSFET 12 having excellent switching performance, the tail current is reduced and the turn-off loss can be reduced.

  Next, a schematic configuration of the semiconductor device 10 will be described with reference to FIGS. FIG. 3 is a view in which the sealing resin body is omitted from FIG. 6 strictly shows the structure of the upper arm side, but the structure of the first semiconductor chip 13 and the second semiconductor chip 14 is shown because the lower arm side has the same structure.

  As shown in FIGS. 2 to 6, the semiconductor device 10 includes a first semiconductor chip 13, a second semiconductor chip 14, heat sinks 15 and 16, terminals 17 and 18, and a sealing resin body 19. ing. In addition, the semiconductor device 10 of the present embodiment includes a high potential power terminal 20, a low potential power terminal 21, an output terminal 22, and a signal terminal 23 as terminals for external connection. Hereinafter, the high potential power supply terminal 20 is also referred to as a P terminal 20. Similarly, the low potential power supply terminal 21 is also referred to as an N terminal 21, and the output terminal 22 is also referred to as an O terminal 22. These P terminal 20, N terminal 21, and O terminal 22 are also referred to as terminals 20, 21, and 22. The heat sink 15 corresponds to a first heat sink, and the heat sink 16 corresponds to a second heat sink.

  The first semiconductor chip 13 is formed by forming an IGBT 11 and an FWD connected in reverse parallel to the IGBT 11 on a semiconductor substrate. That is, RC (Reverse Conducting) -IGBT is formed in the first semiconductor chip 13. The IGBT 11 and the FWD have a so-called vertical structure so that a current flows in the thickness direction of the first semiconductor chip 13, that is, the Z direction.

  In the present embodiment, the first semiconductor chip 13 includes the first semiconductor chip 131 in which the upper-arm IGBT 11 and FWD are formed, and the first semiconductor chip 132 in which the lower-arm IGBT 11 and FWD are formed. doing. A collector electrode is formed on one surface side of the first semiconductor chip 13, and an emitter electrode is formed on the surface opposite to the collector electrode formation surface. The collector electrode is formed on almost the entire surface facing the heat sink 15. A plurality of pads including a pad electrically connected to the gate electrode is provided in a peripheral region different from the active region where the emitter electrode is formed on the emitter electrode forming surface.

  The first semiconductor chips 131 and 132 have substantially the same planar shape and have substantially the same size. The first semiconductor chips 131 and 132 are both substantially rectangular in plan. Further, the first semiconductor chips 131 and 132 are positioned at substantially the same height in the Z direction as shown in FIG. 5, and are arranged side by side in the X direction as indicated by broken lines in FIGS. .

  In the present embodiment, the first semiconductor chip 13 (131, 132) is formed using Si (silicon). Thus, the first semiconductor chip 13 is formed by forming the IGBT 11 and the FWD on the semiconductor substrate made of Si.

  The second semiconductor chip 14 is formed by forming a MOSFET 12 on a semiconductor substrate formed using a semiconductor material having a Young's modulus greater than that of the first semiconductor chip 13. The MOSFET 12 has a so-called vertical structure so that a current flows in the thickness direction of the second semiconductor chip 14, that is, the Z direction.

  In the present embodiment, the second semiconductor chip 14 includes a second semiconductor chip 141 in which the upper arm side MOSFET 12 is formed, and a second semiconductor chip 142 in which the lower arm side MOSFET 12 is formed. A drain electrode is formed on one surface side of the second semiconductor chip 14, and a source electrode is formed on the surface opposite to the drain electrode formation surface. The drain electrode is formed on almost the entire surface facing the heat sink 15. The drain electrode formation surface of the second semiconductor chip 14 is on the same side as the collector electrode formation surface of the first semiconductor chip 13 in the Z direction. A plurality of pads including a pad electrically connected to the gate electrode is provided in a peripheral region different from the active region where the source electrode is formed on the source electrode formation surface.

  The second semiconductor chips 141 and 142 have substantially the same planar shape and have substantially the same size. The second semiconductor chips 141 and 142 are both substantially rectangular in plan, and the size thereof is smaller than that of the first semiconductor chip 13 as indicated by broken lines in FIGS. Although not shown, the second semiconductor chips 141 and 142 are located at substantially the same height in the Z direction and are arranged side by side in the X direction.

  Further, as shown in FIG. 6, the second semiconductor chip 14 is positioned at substantially the same height in the Z direction as the first semiconductor chip 13 disposed on the one surface 15 a of the same heat sink 15 and is aligned in the X direction. Is arranged in. Specifically, the second semiconductor chip 141 is located at substantially the same height as the first semiconductor chip 131 in the Z direction and is arranged side by side in the X direction. Further, the second semiconductor chip 142 is located at substantially the same height as the first semiconductor chip 132 in the Z direction, and is arranged side by side in the X direction. 2, the first semiconductor chip 131, the second semiconductor chip 141, the first semiconductor chip 132, and the second semiconductor chip 142 are arranged in this order in the X direction.

  In the present embodiment, the second semiconductor chip 14 is formed using SiC (silicon carbide). As described above, the second semiconductor chip 14 includes the MOSFET 12 formed on the semiconductor substrate made of SiC. Hereinafter, the first semiconductor chip 13 and the second semiconductor chip 14 are also referred to as semiconductor chips 13 and 14. As described above, the IGBT 11 is formed on the first semiconductor chip 13, the MOSFET 12 is formed on the second semiconductor chip 14, and the first semiconductor chip 13 and the second semiconductor chip 14 are driven in parallel. Further, since the current is controlled to flow through the IGBT 11 in the large current region, the amount of heat generated by the driving is larger in the first semiconductor chip 13 than in the second semiconductor chip 14.

  In the Z direction, heat sinks 15 are arranged on the collector electrode formation surface side of the first semiconductor chip 13 and the drain electrode formation surface side of the second semiconductor chip 14. On the other hand, heat sinks 16 are disposed on the emitter electrode forming surface side of the first semiconductor chip 13 and the source electrode forming surface side of the second semiconductor chip 14. As described above, in the present embodiment, the heat sinks 15 and 16 are the heat sinks 151 and 161 sandwiching the first semiconductor chip 131 and the second semiconductor chip 141 on the upper arm side, and the first semiconductor chip 132 on the lower arm side. And heat sinks 152 and 162 sandwiching the second semiconductor chip 142 therebetween. That is, the heat sink 15 includes heat sinks 151 and 152, and the heat sink 16 includes heat sinks 161 and 162. In the present embodiment, the heat sink 15 (151 and 152) corresponds to a heat radiating member.

  The heat sinks 151 and 161 corresponding to the upper arm are respectively disposed so as to include the first semiconductor chip 131 and the second semiconductor chip 141 on the upper arm side in a projection view from the Z direction. The heat sinks 152 and 162 corresponding to the lower arm are respectively disposed so as to include the first semiconductor chip 132 and the second semiconductor chip 142 on the lower arm side in a projected view from the Z direction. In the present embodiment, each of the heat sinks 151, 152, 161, 162 has a substantially rectangular planar shape.

  These heat sinks 15 and 16 function to dissipate heat generated by the corresponding semiconductor chips 13 and 14 to the outside of the semiconductor device 10. In this embodiment, in addition to the heat dissipation function, the function of electrical connection, that is, the function of wiring is also achieved. For this reason, the heat sinks 15 and 16 are formed using metal materials, such as copper, in order to ensure heat conductivity and electrical conductivity.

  On the one surface 15 a of the heat sink 15, the first semiconductor chip 13 and the second semiconductor chip 14 are disposed. 4 and 5, a solder 24 is interposed between the heat sink 15 and the collector electrode of the first semiconductor chip 13, and the heat sink 15 and the collector electrode are thermally and electrically connected by the solder 24. It is connected to the. As shown in FIG. 6, solder 25 is interposed between one surface 15a of the heat sink 15 and the drain electrode of the second semiconductor chip 14, and the heat sink 15 and the drain electrode are thermally and electrically connected by the solder 25. It is connected to the.

  Specifically, the upper arm side first semiconductor chip 131 and second semiconductor chip 141 are arranged on one surface 15 a of the heat sink 151. The solder 24 is interposed between the heat sink 151 and the collector electrode of the first semiconductor chip 131, and the heat sink 151 and the collector electrode of the first semiconductor chip 131 are thermally and electrically connected by the solder 24. Yes. Further, solder 25 is interposed between the heat sink 151 and the drain electrode of the second semiconductor chip 141, and the heat sink 151 and the drain electrode of the second semiconductor chip 141 are thermally and electrically connected by the solder 25. Yes.

  Similarly, on the one surface 15 a of the heat sink 152, the first semiconductor chip 132 and the second semiconductor chip 142 on the lower arm side are arranged. The solder 24 is interposed between the heat sink 152 and the collector electrode of the first semiconductor chip 132, and the heat sink 152 and the collector electrode of the first semiconductor chip 132 are thermally and electrically connected by the solder 24. Yes. Further, solder 25 is interposed between the heat sink 152 and the drain electrode of the second semiconductor chip 142, and the heat sink 152 and the drain electrode of the second semiconductor chip 142 are thermally and electrically connected by the solder 25. Yes.

  In addition, the back surface 15b opposite to the one surface 15a in each heat sink 15 (151, 152) is exposed from the first surface 19a of the sealing resin body 19 in the Z direction. In the present embodiment, the back surface 15b and the first surface 19a are substantially flush.

  Of the heat sink 15, the heat sink 152 on the lower arm side has a joint portion 152 a as shown in FIGS. 3 to 5. The joint portion 152 a is provided thinner than the other portion (main body portion) of the heat sink 152. In addition, the joint portion 152a is extended from the part of the side surface of the heat sink 152 on the heat sink 151 side to the heat sink 161 side with two bent portions. That is, it extends in the X direction and also in the Z direction.

  Further, a P terminal 20 is connected to the heat sink 151 on the upper arm side as shown in FIGS. The P terminal 20 is electrically connected to the above-described high potential power supply line 5. The P terminal 20 may be provided integrally with the heat sink 15 or may be provided as a separate member from the heat sink 15 and connected to the heat sink 15. The P terminal 20 extends in the Y direction and protrudes from the side surface 19c of the sealing resin body 19 as shown in FIG.

  The O terminal 22 is connected to the heat sink 152 on the lower arm side as shown in FIGS. The O terminal 22 is electrically connected to the output line 7 described above. The O terminal 22 may be provided integrally with the heat sink 152, provided as a separate member from the heat sink 152, and connected to the heat sink 152. The O terminal 22 extends in the Y direction and protrudes from the same side surface 19 c as the P terminal 20 in the sealing resin body 19. The O terminal 22 may be connected to the heat sink 161 on the upper arm side. The heat sinks 152 and 161 may have two O terminals 22 connected to each other.

  On the other hand, a heat sink 16 is disposed on the emitter electrode formation surface of the first semiconductor chip 13 and the source electrode formation surface side of the second semiconductor chip 14. A terminal 17 is interposed between the first semiconductor chip 13 and the heat sink 16 as shown in FIGS. A terminal 18 is interposed between the second semiconductor chip 14 and the heat sink 16 as shown in FIG.

  The terminal 17 secures a height for connecting the signal terminal 23 and the pad of the first semiconductor chip 13 by the bonding wire 26. The terminal 17 is formed using at least a metal material in order to ensure thermal conductivity and electrical conductivity in order to thermally and electrically relay the emitter electrode of the first semiconductor chip 13 and the heat sink 16. The terminal 17 is disposed opposite to the emitter electrode on the emitter electrode forming surface of the first semiconductor chip 13 and is electrically connected to the emitter electrode via the solder 27.

  Similarly, the terminal 18 ensures a height for connecting the signal terminal 23 and the pad of the second semiconductor chip 14 by the bonding wire 26. The terminal 18 is formed using at least a metal material in order to ensure thermal conductivity and electrical conductivity in order to thermally and electrically relay the source electrode of the second semiconductor chip 14 and the heat sink 16. The terminal 18 is disposed opposite the source electrode formation surface of the second semiconductor chip 14 and is electrically connected to the source electrode via the solder 28.

  The heat sink 16 is provided so that most of the heat sink 16 overlaps the corresponding heat sink 15 in a projection view from the Z direction. Specifically, the heat sink 161 on the upper arm side is provided so as to overlap the heat sink 151, and the heat sink 162 on the lower arm side is provided so as to overlap the heat sink 152. The heat sink 16 is disposed opposite to the surfaces of the terminals 17 and 18 opposite to the semiconductor chips 13 and 14.

  As shown in FIGS. 5 and 6, solder 29 is interposed between one surface 16 a of the heat sink 16 and the terminal 17, and the heat sink 16 and the terminal 17 are thermally and electrically connected by the solder 29. . As shown in FIG. 6, solder 30 is interposed between one surface 16 a of the heat sink 16 and the terminal 18, and the heat sink 16 and the terminal 18 are thermally and electrically connected by the solder 30.

  Specifically, the terminal 17 is interposed between the one surface 16 a of the heat sink 161 and the first semiconductor chip 131 on the upper arm side, and the emitter electrode of the first semiconductor chip 131 and the terminal 17 are connected by the solder 27. Yes. Further, the terminal 17 and the heat sink 161 are connected by solder 29. On the other hand, the terminal 18 is interposed between the one surface 16 a of the heat sink 161 and the second semiconductor chip 141 on the upper arm side, and the source electrode of the second semiconductor chip 141 and the terminal 17 are connected by solder 28. Further, the terminal 18 and the heat sink 161 are connected by the solder 30. As described above, the first semiconductor chip 131 and the second semiconductor chip 141 are arranged on the one surface 16 a of the heat sink 161.

  Similarly, the terminal 17 is interposed between the one surface 16 a of the heat sink 162 and the first semiconductor chip 132 on the lower arm side, and the emitter electrode 13 b of the first semiconductor chip 132 and the terminal 17 are connected by solder 27. Further, the terminal 17 and the heat sink 162 are connected by solder 29. On the other hand, the terminal 18 is interposed between the one surface 16 a of the heat sink 162 and the second semiconductor chip 142 on the lower arm side, and the source electrode 14 b of the second semiconductor chip 142 and the terminal 17 are connected by the solder 28. Further, the terminal 18 and the heat sink 162 are connected by the solder 30. Thus, the first semiconductor chip 132 and the second semiconductor chip 142 are arranged on the one surface 16a of the heat sink 162.

  Note that the back surface 16 b opposite to the one surface 16 a is exposed from the second surface 19 b of the sealing resin body 19. The second surface 19b is a surface opposite to the first surface 19a. In the present embodiment, the back surface 16b and the second surface 19b are substantially flush.

  The heat sink 161 on the upper arm side of the heat sink 16 has a joint portion 161a. The joint portion 161 a is provided thinner than the other portion (main body portion) of the heat sink 161. Further, the joint portion 161 a extends in the X direction from a part of the side surface of the heat sink 161 on the heat sink 162 side. The distal end portion of the joint portion 161 a and the distal end portion of the joint portion 152 a face each other in the Z direction and are electrically connected via the solder 31.

  Further, the heat sink 162 on the lower arm side has a joint portion 162a. The joint portion 162a is provided thinner than other portions (main body portions) of the heat sink 162. The joint portion 162a extends in the X direction from a part of the side surface of the heat sink 162 on the heat sink 161 side. The N terminal 21 is electrically connected to the joint portion 162a via solder (not shown).

  The N terminal 21 is electrically connected to the low potential power line 6 described above. The N terminal 21 is electrically connected to the joint 162 a of the heat sink 162, extends in the Y direction, and protrudes to the outside from the side surface 19 c of the sealing resin body 19. Thus, the N terminal 21 protrudes from the same side surface 19 c as the P terminal 20 and the O terminal 22. In addition, the protrusion part from the sealing resin body 19 in these terminals 20, 21, and 22 is arrange | positioned in the mutually same position in the Z direction. In the Y direction, the P terminal 20, the N terminal 21, and the O terminal 22 are arranged in this order.

  The signal terminal 23 is electrically connected to the pads of the corresponding semiconductor chips 13 and 14 via bonding wires 26. The signal terminal 23 extends in the Y direction, and protrudes to the outside from the side surface 19 d opposite to the side surface 19 c among the side surfaces of the sealing resin body 19.

  The sealing resin body 19 integrally seals the semiconductor chips 13 and 14, a part of the heat sinks 15 and 16, the terminals 17 and 18, and the terminals 20, 21, 22 and 23. The sealing resin body 19 is made of, for example, an epoxy resin and is molded by a transfer mold method. As shown in FIG. 2, the sealing resin body 19 has a substantially rectangular plane shape, and the P terminal 20, the N terminal 21, and the O terminal 22, which are main terminals, are drawn from a side surface 19 c substantially parallel to the X direction. It is. Further, the signal terminal 23 is drawn out from the side surface 19d opposite to the side surface 19c.

  The semiconductor device 10 configured as described above is a so-called 4-in-1 package including two first semiconductor chips 13 (131, 132) and two second semiconductor chips 14 (141, 142). Further, heat sinks 15 and 16 exist on both sides in the Z direction of the semiconductor chips 13 and 14 so that heat of the semiconductor chips 13 and 14 can be dissipated to both sides.

  Further, on the upper arm side, the arrangement in the Z direction is, from the first surface 19a side, the heat sink 15 (151), solders 24 and 25, the first semiconductor chip 13 (131) and the second semiconductor chip 14 ( 141), solders 27 and 28, terminals 17 and 18, solders 29 and 30, and heat sink 16 (161). On the other hand, in the portion constituting the lower arm, the arrangement in the Z direction is the heat sink 15 (152), the solders 24 and 25, the first semiconductor chip 13 (132) on the lower arm side, and the second semiconductor from the first surface 19a side. Chip 14 (142), solders 27 and 28, terminals 17 and 18, solders 29 and 30, and heat sink 16 (162) are arranged in this order. That is, the arrangement in the Z direction is the same between the upper arm and the lower arm.

  Next, based on FIG.4 and FIG.6, the detailed structure of the heat sink 15 which is a heat radiating member, and the sealing structure by the sealing resin body 19 are demonstrated. In FIG. 4, on the one surface 15 a of the heat sink 15, a first region 15 d that is an arrangement region of the first semiconductor chip 13 and a second region 15 e that is an arrangement region of the second semiconductor chip 14 are indicated by broken lines. Further, a facing region 15f between the first region 15d and the second region 15e is also indicated by a broken line.

  As shown in FIGS. 4 and 6, the heat sink 15 (151 and 152) has a through hole 15c. The first semiconductor chip 13 (131, 132) and the second semiconductor chip 14 (141, 142) are disposed on one surface 15a of the heat sink 15. On one surface 15a, the arrangement area of each first semiconductor chip 13 is indicated as a first area 15d, and the arrangement area of each second semiconductor chip 14 is indicated as a second area 15e. The first region 15d indicates a portion where the first semiconductor chip 13 is disposed on the one surface 15a, that is, a portion where the solder 24 is joined. The second region 15e indicates a portion where the second semiconductor chip 14 is disposed on the one surface 15a, that is, a portion where the solder 25 is bonded.

  The collector electrode of the first semiconductor chip 13 is formed on almost the entire surface facing the heat sink 15. The drain electrode of the second semiconductor chip 14 is formed on almost the entire surface facing the heat sink 15. For this reason, the first region 15d substantially coincides with the first semiconductor chip 13 in the projection view from the Z direction, and the first region 15d has a substantially rectangular planar shape. Similarly, in the projection view from the Z direction, the second region 15e substantially coincides with the second semiconductor chip 14, and the second region 15e has a substantially rectangular planar shape. The first region 15d and the second region 15e are provided side by side in the X direction. The first region 15d and the second region 15e have two sets of opposite sides as the outer periphery having a substantially rectangular shape in plan view. Two sides forming one set are substantially parallel to the X direction, and two sides forming the other set are substantially parallel to the Y direction.

  The through hole 15c penetrates through the one surface 15a and the back surface 15b of the heat sink 15. The through hole 15c is formed at a position between the first region 15d and the second region 15e in the X direction. The X coordinate of the through hole 15c is a coordinate between the X coordinate of the first region 15d and the X coordinate of the second region 15e. Specifically, the X coordinate of the through hole 15c is the X coordinate of the opposite side (hereinafter referred to as the first opposite side) of the first region 15d with the second region 15e and the first region 15d of the second region 15e. This is a coordinate between the X coordinates of the opposing side (hereinafter referred to as the second opposing side). The through-hole 15c is formed at a position between the shortest portions of the facing distance between the first region 15d and the second region 15e in the X direction that is the arrangement direction.

  In particular, in the present embodiment, the through hole 15c is formed at a position near the second semiconductor chip 14 in the X direction. In other words, the through hole 15c is formed at a position closer to the second region 15e than to the first region 15d.

  The through hole 15c is formed in a facing region 15f between the first region 15d and the second region 15e. The opposing region 15f is a virtual straight line connecting the first opposing side of the first region 15d, the second opposing side of the second region 15e, and the end portions of the first opposing side and the second opposing side on the P terminal 20 side. And an imaginary straight line connecting ends opposite to the P terminal 20 on the first opposing side and the second opposing side. In the present embodiment, the plurality of through holes 15c are formed so as to straddle the opposing region 15f in the Y direction. Specifically, five through holes 15c are formed in the heat sinks 151 and 152, respectively. The five through holes 15c are formed at a predetermined pitch along the Y direction. Of the five through holes 15c, three are formed in the opposing region 15f, and the remaining two are formed outside the opposing region 15f.

  As shown in FIG. 6, the sealing resin body 19 includes a covering portion 19 e that covers one surface 15 a of the heat sink 15 that is a heat radiating member, and a filling portion 19 f that is filled in the through hole 15 c. The covering portion 19e is disposed on the one surface 15a so as to close the through hole 15c, and is in close contact with the one surface 15a. The covering portion 19e corresponds to a one-side covering portion.

  The filling portion 19f is arranged from the opening end on the one surface 15a side to the opening end on the back surface 15b side with respect to the through hole 15c. The filling portion 19f is in close contact with the wall surface of the through hole 15c. The end on the back surface 15b side of the filling portion 19f is substantially flush with the back surface 15b. The filling portion 19f is continuous with the covering portion 19e and is formed integrally with the covering portion 19e. The filling portion 19f extends from the covering portion 19e on the side opposite to the heat sink 16 in the Z direction.

  Next, the effect of the semiconductor device 10 will be described.

  As described above, the second semiconductor chip 14 is formed using a semiconductor material having a Young's modulus greater than that of the first semiconductor chip 13, and is less likely to deform (hard) than the first semiconductor chip 13. For this reason, peeling is likely to occur in the periphery of the second semiconductor chip 14, for example, in the outer peripheral portion of the second semiconductor chip 14, in the sealing resin body 19 due to a temperature change in the use environment.

  On the other hand, in the present embodiment, the heat sink 15 has a through hole 15c at a position between the first region 15d and the second region 15e in the X direction. And the sealing resin body 19 is filled in the through-hole 15c, and the filling part 19f is formed. Even if resin peeling occurs around the second semiconductor chip 14, the resin peeling progresses at the interface between the filling portion 19 f and the wall surface of the through hole 15 c, so that the second semiconductor chip is compared with the configuration having no through hole. The progress path of the resin peeling from 14 to the first semiconductor chip 13 is long.

  Moreover, the filling part 19f which is a part of the sealing resin body 19 is disposed in the through-hole 15c, and the contact area between the sealing resin body 19 and the heat sink 15 is larger than the conventional one. Furthermore, the filling portion 19f extends from the covering portion 19e in the Z direction, and an anchor effect can be expected.

  As described above, the semiconductor device 10 according to the present embodiment can suppress the resin peeling from progressing toward the first semiconductor chip 13 even when the resin peeling occurs around the second semiconductor chip 14. That is, the connection reliability of the first semiconductor chip 13 with respect to the heat sink 15 can be improved as compared with the conventional case.

  Further, the through hole 15c penetrates over the one surface 15a and the back surface 15b of the heat sink 15, and the heat sink 15 does not exist in the through hole forming portion. Therefore, in addition to the above effects, the semiconductor device 10 according to the present embodiment can suppress heat transfer between the first semiconductor chip 13 and the second semiconductor chip 14.

  In particular, in the present embodiment, the IGBT 11 formed on the first semiconductor chip 13 and the MOSFET 12 formed on the second semiconductor chip 14 are driven in parallel. Further, since the current is controlled to flow through the IGBT 11 in the large current region, the amount of heat generated by the driving is larger in the first semiconductor chip 13 than in the second semiconductor chip 14. However, by providing the above-described configuration, the semiconductor device 10 of this embodiment can suppress the heat of the first semiconductor chip 13 from being transmitted to the second semiconductor chip 14 via the heat sink 15. Therefore, it is possible to suppress the deterioration of the characteristics of the MOSFET 12 formed on the second semiconductor chip 14 due to the high temperature of the second semiconductor chip 14 due to heat transfer. In particular, the characteristics of SiC greatly vary depending on the operating temperature range, and the conduction resistance is higher in the high temperature region than in the normal temperature region. That is, the loss increases. However, since heat transfer to the second semiconductor chip 14 made of SiC is suppressed, it is possible to suppress deterioration of characteristics.

  In addition, of the first semiconductor chip 13 and the second semiconductor chip 14 that are driven in parallel, it is possible to suppress the resin peeling from progressing to the first semiconductor chip 13 side. Even if the second semiconductor chip 14 side becomes defective due to the resin peeling and the MOSFET 12 cannot be driven, the IGBT 11 on the first semiconductor chip 13 side which is the main element can be driven. Thereby, for example, retreat travel is possible. Therefore, fail-safe property can also be improved.

  In the present embodiment, the through hole 15 c is formed at a position closer to the second semiconductor chip 14 than the first semiconductor chip 13 in the X direction. That is, the through hole 15 c is formed at a position away from the first semiconductor chip 13 in the X direction. Since the through hole 15 c does not exist around the first semiconductor chip 13 and the heat sink 15 exists, the semiconductor device 10 of this embodiment can also improve the heat dissipation from the first semiconductor chip 13 to the heat sink 15. .

  The resin peeling from the second semiconductor chip 14 toward the first semiconductor chip 13 progresses in the heat sink 15 via a position between the first region 15d and the second region 15e. In particular, there is a high possibility of passing through the opposing region 15f between the first region 15d and the second region 15e. Further, heat conduction between the first semiconductor chip 13 and the second semiconductor chip 14 also passes through a portion between the first region 15d and the second region 15e in the X direction. This heat conduction mainly passes through the opposing region 15f between the first region 15d and the second region 15e. In this embodiment, since the through-hole 15c is provided in the opposing area | region 15f, it can suppress effectively that resin peeling progresses to the 1st semiconductor chip 13 side. In addition, heat transfer between the first semiconductor chip 13 and the second semiconductor chip 14 can be effectively suppressed. In particular, in the present embodiment, the through hole 15c is formed so as to straddle the opposing region 15f. That is, the through-hole 15c is formed so as to block the separation progress and heat conduction in the facing region 15f. For this reason, the progress of the resin peeling toward the first semiconductor chip 13 and the heat transfer between the first semiconductor chip 13 and the second semiconductor chip 14 can be effectively suppressed.

  In the present embodiment, an example in which the plurality of through holes 15c are formed so as to straddle the opposing region 15f is shown. However, as shown in the first modification of FIG. 7, one through hole 15c may be formed so as to straddle the opposing region 15f. The through-hole 15c extends in the Y direction and straddles the opposing region 15f in the Y direction. As described above, the through-hole 15c is not discontinuous and may straddle the opposing region 15f continuously. FIG. 7 corresponds to FIG.

  The arrangement of the through holes 15c is not limited to the arrangement straddling the facing region 15f described above. For example, as shown in the second modification of FIG. 8, a configuration in which the through hole 15c is formed only in the facing region 15f can also be employed. Although not shown in the drawings, a configuration in which the through hole 15c is formed only at the position between the first region 15d and the second region 15e in the X direction and outside the opposing region 15f may be employed. it can. Furthermore, a configuration in which the through hole 15c is formed at an intermediate position between the first region 15d and the second region 15e in the X direction can be adopted, or a configuration in which the through hole 15c is formed at a position close to the first region 15d. It can also be adopted. FIG. 8 corresponds to FIG.

  As described above, the first semiconductor chip 13 and the second semiconductor chip 14 are also disposed on the one surface 16 a of the heat sink 16 via the corresponding terminals 17 and 18. In the case of a double-sided heat dissipation structure in which the heat sinks 15 and 16 are disposed on both sides in the Z direction of the first semiconductor chip 13 and the second semiconductor chip 14, the through hole may be formed in at least one of the heat sinks 15 and 16. The heat sinks 15 and 16 in which the through holes are formed correspond to heat radiating members.

  For example, in the third modification shown in FIG. 9, the through hole 16 c is formed not only in the heat sink 15 but also in the heat sink 16. The arrangement of the through holes 16c is the same as that of the through holes 15c. That is, the through hole 16c is formed at a position between the first region 16d and the second region 16e in the X direction. The first region 16d indicates a portion where the first semiconductor chip 13 is disposed on the one surface 16a of the heat sink 16, that is, a portion where the solder 29 is bonded. The second region 16e indicates a portion where the second semiconductor chip 14 is disposed on the one surface 16a, that is, a portion where the solder 30 is joined. In addition, although illustration is abbreviate | omitted, the structure by which the through-hole 16c was formed only in the heat sink 16 is also employable. However, as shown in this embodiment, in the configuration in which the semiconductor device 10 includes the terminals 17 and 18, the heat sink 15 is closer to the first semiconductor chip 13 and the second semiconductor chip 14 in the Z direction. The structure in which the through-hole 15c is formed in 15 is preferable. FIG. 9 corresponds to FIG.

(Second Embodiment)
This embodiment can refer to the preceding embodiment. For this reason, the description of the parts common to the semiconductor device 10 shown in the previous embodiment is omitted.

  In this embodiment, as shown in FIGS. 10 and 11, the through hole 15c is formed in the heat sink 15 (151 and 152) so as to surround the second semiconductor chip 14, that is, the second region 15e. 10 corresponds to FIG. 4, and FIG. 11 corresponds to FIG.

  As shown in FIG. 10, a plurality of through holes 15c are formed so as to surround the second region 15e at the same pitch. That is, the through hole 15c discontinuously surrounds the second region 15e. Part of the plurality of through holes 15c is formed at a position between the first region 15d and the second region 15e in the X direction. A part of the plurality of through holes 15c is formed in the facing region 15f. And the filling part 19f is arrange | positioned at each through-hole 15c.

  According to the above configuration, it is possible to block the separation progress path and the heat conduction path almost entirely around the second semiconductor chip 14. For this reason, the progress of the resin peeling toward the first semiconductor chip 13 and the heat transfer between the first semiconductor chip 13 and the second semiconductor chip 14 can be effectively suppressed. For example, no matter where the resin peeling occurs around the second semiconductor chip 14, the resin peeling progresses toward the first semiconductor chip 13 by any of the through holes 15 c formed around the second semiconductor chip 14. Can be suppressed.

  In the present embodiment, the example in which the through holes 15c surround the second semiconductor chip 14 discontinuously is shown. However, for example, a through hole 15c formed in a C shape so as to surround the second semiconductor chip 14 may be employed. In this case, the through hole 15c continuously surrounds the second semiconductor chip 14.

  The above configuration is not limited to the through hole 15c, but can also be applied to the through hole 16c of the heat sink 16.

(Third embodiment)
This embodiment can refer to the preceding embodiment. For this reason, the description of the parts common to the semiconductor device 10 shown in the previous embodiment is omitted.

  As shown in FIG. 12, in this embodiment, the sealing resin body 19 further includes a covering portion 19g that is continuous with the filling portion 19f and covers the back surfaces 15b and 16b of the heat sinks 15 and 16. This covering portion 19g corresponds to the back surface covering portion.

  In FIG. 12, both heat sinks 15 and 16 have through holes 15c and 16c. The covering portion 19 e is in close contact with the one surface 15 a of the heat sink 15 and the one surface 16 a of the heat sink 16. The covering portion 19 e is a portion between the heat sinks 15 and 16. The covering portion 19g is disposed on the back surface 15b of the heat sink 15 so as to close the through hole 15c, and is in close contact with the entire back surface 15b. The covering portion 19g is also disposed on the back surface 16b of the heat sink 16 so as to close the through hole 16c, and is in close contact with the entire back surface 16b.

  The covering portion 19e is connected to one end of the filling portion 19f filled in the through hole 15c, and the covering portion 19g on the back surface 15b side is connected to the other end. Similarly, the covering portion 19e is connected to one end of the filling portion 19f filled in the through hole 16c, and the covering portion 19g on the back surface 16b side is connected to the other end. In this way, the filling part 19f connects the covering parts 19e and 19g.

  According to the above configuration, the contact area between the sealing resin body 19 and the heat sink 15 and the contact area between the sealing resin body 19 and the heat sink 16 can be increased. Thereby, progress of resin peeling can be suppressed. Further, in the sealing resin body 19, the covering portions 19e and 19g connected by the filling portion 19f sandwich the heat sinks 15 and 16, respectively. For this reason, not only the X direction but also the progress of the resin peeling and the resin peeling due to the stress in the Z direction can be effectively suppressed.

  When the semiconductor device 10 is cooled by transferring the heat of the first semiconductor chip 13 and the second semiconductor chip 14 to a cooler (not shown), the heat sinks 15 and 16 and the cooler are electrically connected by the covering portion 19g. It can also be separated. According to this, compared with the structure which uses an insulating plate in order to electrically isolate heat sinks 15 and 16 and a cooler, the number of parts can also be reduced.

  In the present embodiment, an example in which the covering portion 19g is provided on the heat sinks 15 and 16 has been described. However, when the heat sink 15 has the through hole 15c, the covering portion 19g may be provided on the back surface 15b side. Moreover, what is necessary is just to provide the coating | coated part 19g in the back surface 16b side, when the heat sink 16 has the through-hole 16c.

  The covering portion 19g is not limited to the configuration in which the covering portion 19g is in close contact with the entire back surface 15b, 16b. The covering portion 19g only needs to be connected to the filling portion 19f and be in close contact with at least the periphery of the openings of the back surfaces 15b and 16b.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  The configuration of the semiconductor device 10 is not limited to the above example. Although an example having upper and lower arms for one phase has been shown, upper and lower arms for three phases may be provided. Further, only one set of the upper and lower arms, that is, the first semiconductor chip 13 and the second semiconductor chip 14 may be provided.

  As the semiconductor device 10 having the double-sided heat dissipation structure, a configuration without the terminals 17 and 18 can be adopted.

  The back surfaces 15 b and 16 b of the heat sinks 15 and 16 having no through holes may be covered with the sealing resin body 19. For example, when the through hole 15 c is formed only in the heat sink 15, the back surface 16 b of the heat sink 16 in which no through hole is formed may be covered with the sealing resin body 19. In this case, you may cover the back surface 15b of the heat sink 15 in which the through-hole 15c was formed with the sealing resin body.

  As the semiconductor device 10, an example in which the heat sinks 15 and 16 are arranged on both sides of the semiconductor chips 13 and 14 has been shown. However, the present invention can also be applied to a semiconductor device in which a heat sink is disposed only on one side of the semiconductor chips 13 and 14.

  For example, in the fourth modification shown in FIG. 13, the semiconductor device 10 includes a first semiconductor chip 13, a second semiconductor chip 14, a heat sink 15, and terminals 17 and 18. The difference from the first embodiment (see FIG. 6) is that the semiconductor device 10 does not include the heat sink 16, and the O terminal 22 is connected to the terminals 17 and 18 via the bonding wires 32. In the case of the lower arm side, the N terminal 21 is used instead of the O terminal 22. And the through-hole 15c is formed in the heat sink 15, and the filling part 19f is arrange | positioned at this through-hole 15c.

  In FIG. 13, the semiconductor device 10 includes the terminals 17 and 18, but a configuration without the terminals 17 and 18 can also be employed. In FIG. 13, the back surface 15 b is exposed from the sealing resin body 19, but a configuration covered with the sealing resin body 19 can also be adopted.

  Further, in the fifth modified example shown in FIG. 14, unlike the above-described FIG. 13, the O terminal 22 is connected to the terminals 17 and 18 via the solders 29 and 30. That is, the first semiconductor chip 13 and the second semiconductor chip 14 are disposed on the one surface 22 a of the O terminal 22. The O terminal 22 is formed with a through hole 22c penetrating over one surface 22a and a back surface 22b opposite to the one surface 22a. The through holes 22c are arranged similarly to the through holes 15c. The one surface 22a includes a first region 22d, which is a region where the first semiconductor chip 13 is disposed, and a second region 22e, which is a region where the second semiconductor chip 14 is disposed. The through hole 22c is formed at a position between the first region 22d and the second region 22e in the X direction. A filling portion 19f is disposed in the through hole 22c. Moreover, in FIG. 14, the sealing resin body 19 has the coating | coated part 19g arrange | positioned on the back surface 22b so that the through-hole 22c may be plugged up. The covering portion 19g is continuous with the filling portion 19f. In this configuration, the heat sink 15 and the O terminal 22 correspond to a heat radiating member.

  In FIG. 14, the back surface 15 b is exposed from the sealing resin body 19, but a configuration covered with the sealing resin body 19 can also be employed.

  Although the example in which the first semiconductor chip 13 is made of Si and the second semiconductor chip 14 is made of SiC is shown, the present invention is not limited to this. The second semiconductor chip 14 may be formed using a semiconductor material having a Young's modulus larger than that of the first semiconductor chip 13.

DESCRIPTION OF SYMBOLS 1 ... Power converter device, 2 ... DC power supply, 3 ... Motor, 4 ... Smoothing capacitor, 5 ... High potential power supply line, 6 ... Low potential power supply line, 7 ... Output line, 10 ... Semiconductor device, 11 ... IGBT, 12 ... MOSFET, 13, 131, 132 ... first semiconductor chip, 14, 141, 142 ... second semiconductor chip, 15, 16, 151, 152, 161, 162 ... heat sink, 15a, 16a ... one side, 15b, 16b ... back side, 15c, 16c ... through hole, 15d, 16d ... first region, 15e, 16e ... second region, 15e, 16e ... through hole, 15f ... opposing region, 152a, 161a, 162a ... joint portion, 17, 18 ... terminal, DESCRIPTION OF SYMBOLS 19 ... Sealing resin body, 19a ... 1st surface, 19b ... 2nd surface, 19c, 19d ... Side surface, 19e, 19g ... Covering part, 19f ... Filling part, 20 ... High potential Source terminal 21 ... Low-potential power terminal 22 ... Output terminal 22a ... One side 22b ... Back side 22c ... Through hole 22d ... First region 22e ... Second region 23 ... Signal terminal 24, 25, 27 , 28, 29, 30, 31 ... solder, 26, 32 ... bonding wire

Claims (9)

A first semiconductor chip (13);
A second semiconductor chip (14) formed using a material having a Young's modulus greater than that of the first semiconductor chip;
It has one surface (15a, 16a, 22a) and a back surface (15b, 16b, 22b) opposite to the one surface in the thickness direction, and the first semiconductor chip and the second semiconductor chip are arranged on the one surface. A heat dissipating member (15, 16, 22) arranged to transmit heat generated by the first semiconductor chip and the second semiconductor chip;
A sealing resin body (19) for integrally sealing at least one surface of the first semiconductor chip, the second semiconductor chip, and the heat dissipation member;
A semiconductor device comprising:
The heat radiating member has, as one surface, a first region (15d, 16d, 22d) that is an arrangement region of the first semiconductor chip and a second region (15e, 16e, 22e) that is an arrangement region of the second semiconductor chip. And penetrating across the one surface and the back surface, and formed at a position between the first region and the second region in the alignment direction of the first semiconductor chip and the second semiconductor chip. With holes (15c, 16c, 22c),
The sealing resin body includes a one-surface covering portion (19e) that covers the one surface, and a filling portion (19f) that is connected to the one-surface covering portion and is filled in the through hole. apparatus. The first semiconductor chip and the second semiconductor chip are driven in parallel;
2. The semiconductor device according to claim 1, wherein the amount of heat generated by driving is greater in the first semiconductor chip than in the second semiconductor chip.   The semiconductor device according to claim 2, wherein the through hole is formed in a position closer to the second semiconductor chip than the first semiconductor chip in the arrangement direction.   4. The semiconductor device according to claim 1, wherein the through-hole is formed in a facing region (15 f) between the first region and the second region.   The semiconductor device according to claim 4, wherein the through hole is formed so as to straddle the opposing region continuously or discontinuously.   The semiconductor device according to claim 5, wherein the through hole is formed so as to surround the second region.   The semiconductor device according to claim 1, wherein the sealing resin body further includes a back surface covering portion (19 g) that is continuous with the filling portion and covers the back surface. The first semiconductor chip is made of silicon;
The semiconductor device according to claim 1, wherein the second semiconductor chip is made of silicon carbide. The first heat sink and a second heat sink in which the first semiconductor chip and the second semiconductor chip are disposed between the first heat sink and the first heat sink in the thickness direction. In the semiconductor device described in
At least one of the first heat sink and the second heat sink is the heat radiating member.

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