JP2019067950A - Semiconductor device manufacturing method - Google Patents

Abstract

To inhibit deterioration in location accuracy of external connection terminals in a manufacturing process of a semiconductor device having an insulating substrate.SOLUTION: A semiconductor device manufacturing method disclosed in the present specification comprises the steps of: preparing an insulating substrate where metal layers are provided on both surfaces of an insulation layer; preparing a lead frame where a plurality of external connection terminals are provided; bonding one metal layer of the insulating substrate and the lead frame; and arranging a semiconductor element on the one metal layer of the insulating substrate.SELECTED DRAWING: Figure 7

Description

  The technology disclosed herein relates to a method of manufacturing a semiconductor device having an insulating substrate.

  In recent years, in the field of power semiconductors, it is expected that the amount of heat generation inside the semiconductor device will increase due to the improvement of the allowable power of the semiconductor element by adoption of silicon carbide or the like. Therefore, further improvement of the heat resistance performance is required in the semiconductor device, and it is conceivable to adopt an insulating substrate as one of the methods. The term "insulating substrate" as used herein means a substrate in which metal layers are provided on both sides of the insulating layer. Patent Document 1 discloses a semiconductor device having such an insulating substrate.

JP 2012-146760 A

  In the manufacturing process of the semiconductor device described above, it is necessary to bond a plurality of external connection terminals for electrically connecting the semiconductor element to the outside to the metal layer of the insulating substrate and the semiconductor element. In such a case, since the plurality of external connection terminals are respectively joined, the positional accuracy of the external connection terminals may vary, which may deteriorate the assemblability of the semiconductor device. On the other hand, a manufacturing method is also conceivable in which, first, a lead frame in which the external connection terminal and the metal layer constituting the insulating substrate are integrated is manufactured, and then the insulating layer is joined on the metal layer. However, according to such a manufacturing method, although it is necessary to perform high-temperature treatment when bonding the insulating layer, the external connection terminal may be softened by the high temperature, and as a result, the positional accuracy between the external connection terminals is poor. May be The present specification provides a technique that can suppress deterioration in the positional accuracy of external connection terminals in the process of manufacturing a semiconductor device having an insulating substrate.

  In the method of manufacturing a semiconductor device disclosed in the present specification, a step of preparing an insulating substrate in which metal layers are provided on both sides of an insulating layer, a step of preparing a lead frame in which a plurality of external connection terminals are provided, The method includes the steps of bonding one metal layer of the insulating substrate and the lead frame, and disposing the semiconductor element on the one metal layer of the insulating substrate.

  In this manufacturing method, first, an insulating substrate in which metal layers are provided on both surfaces of an insulating layer and a lead frame in which a plurality of external connection terminals are provided are respectively prepared. Then, they are integrated by joining one metal layer of the insulating substrate and the lead frame to each other. According to such a manufacturing method, since the plurality of external connection terminals provided in the lead frame are simultaneously positioned with respect to the insulating substrate, the positional accuracy between the external connection terminals can be maintained as it is. In addition, since the insulating substrate and the lead frame can be individually prepared, even if high temperature processing is required in the process of preparing the insulating substrate, the positional accuracy of the external connection terminal is not deteriorated thereby.

The top view of the semiconductor device 10 of an Example is shown. The internal structure of the semiconductor device 10 of an Example is shown. Sectional drawing in the III-III line in FIG. 1 is shown. Sectional drawing in the IV-IV line in FIG. 1 is shown. FIG. 7 is a view for explaining one manufacturing step of the semiconductor device 10, and shows the prepared first lower insulating substrate 26 and the second lower insulating substrate 46; FIG. 7 is a view for explaining one manufacturing step of the semiconductor device 10, and shows the prepared lead frame 4; FIG. FIG. 7 is a view for explaining one manufacturing process of the semiconductor device 10, and shows the lead frame 4 joined to the first lower insulating substrate 26 and the second lower insulating substrate 46. FIG. 17 is a view for explaining one manufacturing step of the semiconductor device 10, in which the first semiconductor element 20, the second semiconductor element 40 and the like are assembled on the first lower insulating substrate 26 and the second lower insulating substrate 46. Indicates FIG. 18 is a view for explaining one manufacturing step of the semiconductor device 10, and showing a state in which the first upper insulating substrate 22 and the second upper insulating substrate 42 are assembled. FIG. 10 is a view for explaining one manufacturing step of the semiconductor device 10, and shows a state in which unnecessary portions of the molded sealing body 12 and the lead frame 4 are removed. The lead frame 4a of the modification which further includes the coupling 60 is shown. The semiconductor device 10a which employ | adopted the lead frame 4a of the modification is shown.

  The semiconductor device 10 of the embodiment will be described with reference to the drawings. The semiconductor device 10 of the present embodiment can be used, for example, in a power conversion circuit such as a converter or an inverter in an electric vehicle such as an electric vehicle, a hybrid vehicle, or a fuel cell vehicle. However, the application of the semiconductor device 10 is not particularly limited. The semiconductor device 10 can be widely adopted in various devices and circuits.

  As shown in FIG. 1, FIG. 2, FIG. 3 and FIG. 4, the semiconductor device 10 includes the first semiconductor element 20, the second semiconductor element 40, the sealing body 12, and the plurality of external connection terminals 14, 15, 16, 18 and 19 are provided. The first semiconductor element 20 and the second semiconductor element 40 are sealed inside the sealing body 12. Although the sealing body 12 is not particularly limited, it is made of, for example, a thermosetting resin such as an epoxy resin. The respective external connection terminals 14, 15, 16, 18, 19 extend from the outside to the inside of the sealing body 12, and the first semiconductor element 20 and the second semiconductor element 40 in the sealing body 12. It is electrically connected to at least one of them. In one example, the plurality of external connection terminals 14, 15, 16, 18, 19 include a P terminal 14 for power, an N terminal 15 and an O terminal 16, and a plurality of first signal terminals 18 for signals. And a plurality of second signal terminals 19 are included.

  The first semiconductor element 20 has an upper surface electrode 20a and a lower surface electrode 20b. The upper surface electrode 20 a is located on the upper surface of the first semiconductor element 20, and the lower surface electrode 20 b is located on the lower surface of the first semiconductor element 20. The first semiconductor element 20 is a vertical semiconductor element having a pair of upper and lower electrodes 20a and 20b. Similarly, the second semiconductor element 40 has an upper surface electrode 40a and a lower surface electrode 40b. The upper surface electrode 40 a is located on the upper surface of the second semiconductor element 40, and the lower surface electrode 40 b is located on the lower surface of the second semiconductor element 40. That is, the second semiconductor element 40 is also a vertical semiconductor element having a pair of upper and lower electrodes 40a and 40b. The first semiconductor element 20 and the second semiconductor element 40 in the present embodiment are semiconductor elements of the same type, and more specifically, an RC-IGBT (Reverse Conducting IGBT) element incorporating an IGBT (Insulated Gate Bipolar Transistor) and a diode. is there.

  However, each of the first semiconductor element 20 and the second semiconductor element 40 is not limited to the RC-IGBT element, and may be another power semiconductor element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) element, for example. Good. Alternatively, each of the first semiconductor element 20 and the second semiconductor element 40 may be replaced with two or more semiconductor elements such as a diode element and an IGBT element (or MOSFET element). The specific configurations of the first semiconductor element 20 and the second semiconductor element 40 are not particularly limited, and various semiconductor elements can be employed. In this case, the first semiconductor element 20 and the second semiconductor element 40 may be semiconductor elements different from each other. In addition, each of the first semiconductor element 20 and the second semiconductor element 40 can be configured using various semiconductor materials such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN), for example.

  The semiconductor device 10 further includes a first upper insulating substrate 22, a first conductor spacer 24, and a first lower insulating substrate 26. The first upper insulating substrate 22 has an insulating layer 28, an inner metal layer 30 provided on one side of the insulating layer 28, and an outer metal layer 32 provided on the other side of the insulating layer 28. The inner metal layer 30 and the outer metal layer 32 are mutually insulated by the insulating layer 28. The inner metal layer 30 of the first upper insulating substrate 22 is electrically connected to the upper surface electrode 20 a of the first semiconductor element 20 via the first conductor spacer 24. Although not particularly limited, in the present embodiment, soldering is employed for this connection, and between the first upper insulating substrate 22 and the first conductor spacer 24, and between the first conductor spacer 24 and the first semiconductor element 20. The solder layers 23 and 25 are respectively formed between them.

  Although this is an example, the first upper insulating substrate 22 in the present embodiment is a DBC substrate. The insulating layer 28 is made of, for example, a ceramic such as aluminum oxide, silicon nitride, or aluminum nitride, and the inner metal layer 30 and the outer metal layer 32 are each made of copper. However, the first upper insulating substrate 22 is not limited to the DBC substrate. The insulating layer 28 is not limited to ceramic, and may be made of another insulator. The inner metal layer 30 and the outer metal layer 32 are not limited to copper, and may be made of other metals. Also, the bonding structure between the insulating layer 28 and the metal layers 30 and 32 is not particularly limited. Moreover, the 1st conductor spacer 24 in a present Example is comprised with the copper- molybdenum alloy. However, the first conductor spacer 24 is also not limited to the copper-molybdenum alloy, and may be made of another conductor such as pure copper or another copper alloy.

  The first lower insulating substrate 26 has an insulating layer 34, an inner metal layer 36 provided on one side of the insulating layer 34, and an outer metal layer 38 provided on the other side of the insulating layer 34. The inner metal layer 36 and the outer metal layer 38 are mutually insulated by the insulating layer 34. The inner metal layer 36 of the first lower insulating substrate 26 is electrically connected to the lower surface electrode 20 b of the first semiconductor element 20. Although not particularly limited, in the present embodiment, soldering is adopted for this connection, and a solder layer 27 is formed between the first semiconductor element 20 and the first lower insulating substrate 26.

  Although this is an example, the first lower insulating substrate 26 in the present embodiment is a DBC substrate. The insulating layer 34 is made of, for example, a ceramic such as aluminum oxide, silicon nitride, or aluminum nitride, and each of the inner metal layer 36 and the outer metal layer 38 is made of copper. However, the first lower insulating substrate 26 is not limited to the DBC substrate. The insulating layer 34 is not limited to ceramic, and may be made of another insulator. The inner metal layer 36 and the outer metal layer 38 are not limited to copper, and may be made of other metals. Also, the bonding structure between the insulating layer 34 and each of the metal layers 36 and 38 is not particularly limited.

  The outer metal layer 32 of the first upper insulating substrate 22 is exposed to the upper surface 12 a of the sealing body 12. Thus, the first upper insulating substrate 22 not only forms part of the electric circuit of the semiconductor device 10, but also functions as a heat dissipation plate that mainly dissipates the heat of the first semiconductor element 20 to the outside. Similarly, the outer metal layer 38 of the first lower insulating substrate 26 is exposed to the lower surface 12 b of the sealing body 12. As a result, the first lower insulating substrate 26 not only forms part of the electric circuit of the semiconductor device 10 but also functions as a heat sink which mainly dissipates the heat of the first semiconductor element 20 to the outside. As described above, the semiconductor device 10 of this embodiment has a double-sided cooling structure in which the outer metal layers 32 and 38 are exposed on the upper and lower surfaces 12 a and 12 b of the sealing body 12.

  The semiconductor device 10 further includes a second upper insulating substrate 42, a second conductor spacer 44, and a second lower insulating substrate 46. The second upper insulating substrate 42 has an insulating layer 48, an inner metal layer 50 provided on one side of the insulating layer 48, and an outer metal layer 52 provided on the other side of the insulating layer 48. The inner metal layer 50 and the outer metal layer 52 are mutually insulated by the insulating layer 48. The inner metal layer 50 of the second upper insulating substrate 42 is electrically connected to the upper surface electrode 40 a of the second semiconductor element 40 via the second conductor spacer 44. Although not particularly limited, in the present embodiment, soldering is employed for this connection, and between the second upper insulating substrate 42 and the second conductor spacer 44, and between the second conductor spacer 44 and the second semiconductor element 40. The solder layers 43 and 45 are respectively formed between them.

  Although this is an example, the second upper insulating substrate 42 in the present embodiment is a DBC substrate. The insulating layer 48 is made of, for example, a ceramic such as aluminum oxide, silicon nitride, or aluminum nitride, and each of the inner metal layer 50 and the outer metal layer 52 is made of copper. However, the second upper insulating substrate 42 is not limited to the DBC substrate. The insulating layer 48 is not limited to ceramic, and may be made of another insulator. The inner metal layer 50 and the outer metal layer 52 are not limited to copper, and may be made of other metals. Also, the bonding structure between the insulating layer 48 and each of the metal layers 50 and 52 is not particularly limited. Moreover, the 2nd conductor spacer 44 in a present Example is comprised with the copper- molybdenum alloy. However, the second conductor spacer 44 is not limited to a copper-molybdenum alloy, and may be made of another conductor such as pure copper or another copper alloy.

  The second lower insulating substrate 46 includes an insulating layer 54, an inner metal layer 56 provided on one side of the insulating layer 54, and an outer metal layer 58 provided on the other side of the insulating layer 54. Inner metal layer 56 and outer metal layer 58 are insulated from each other by insulating layer 54. The inner metal layer 56 of the second lower insulating substrate 46 is electrically connected to the lower surface electrode 40 b of the second semiconductor element 40. Although not particularly limited, in the present embodiment, soldering is employed for this connection, and a solder layer 47 is formed between the second semiconductor element 40 and the first lower insulating substrate 46.

  Although this is an example, the second lower insulating substrate 46 in the present embodiment is a DBC substrate. The insulating layer 54 is made of, for example, a ceramic such as aluminum oxide, silicon nitride, or aluminum nitride, and each of the inner metal layer 56 and the outer metal layer 58 is made of copper. However, the second lower insulating substrate 46 is not limited to the DBC substrate. The insulating layer 54 is not limited to ceramic, and may be made of other insulators. The inner metal layer 56 and the outer metal layer 58 are not limited to copper but may be made of other metals. Also, the bonding structure between the insulating layer 54 and each of the metal layers 56 and 58 is not particularly limited.

  The outer metal layer 52 of the second upper insulating substrate 42 is exposed to the upper surface 12 a of the sealing body 12. Thus, the second upper insulating substrate 42 not only forms part of the electric circuit of the semiconductor device 10, but also functions as a heat dissipation plate that mainly dissipates the heat of the second semiconductor element 40 to the outside. Similarly, the outer metal layer 58 of the second lower insulating substrate 46 is exposed to the lower surface 12 b of the sealing body 12. Thus, the second lower insulating substrate 46 not only forms part of the electric circuit of the semiconductor device 10, but also functions as a heat sink that mainly dissipates the heat of the second semiconductor element 40 to the outside. As described above, the semiconductor device 10 of the present embodiment also has a double-sided cooling structure in which the outer metal layers 32 and 38 are exposed to the upper and lower surfaces 12 a and 12 b of the sealing body 12.

  The semiconductor device 10 further includes a joint 60 made of a conductor. The joint 60 is located inside the sealing body 12 and electrically connected between the inner metal layer 30 of the first upper insulating substrate 22 and the inner metal layer 56 of the second lower insulating substrate 46. There is. Thus, the first semiconductor element 20 and the second semiconductor element 40 are connected in series via the joint 60. In one example, the joint 60 of the present embodiment is made of copper and is joined to the inner metal layer 30 of the first upper insulating substrate 22 via the solder layer 62 and the second lower insulating substrate 46. The inner metal layer 56 is joined by welding.

  As described above, the semiconductor device 10 includes the P terminal 14, the N terminal 15, and the O terminal 16 as external connection terminals. The P terminal 14, the N terminal 15 and the O terminal 16 in the present embodiment are made of copper. However, the P terminal 14, the N terminal 15 and the O terminal 16 are not limited to copper, and may be made of other conductors. The P terminal 14 is bonded to the inner metal layer 36 of the first lower insulating substrate 26 in the inside of the sealing body 12. The N terminal 15 is bonded to the inner metal layer 50 of the second upper insulating substrate 42 inside the sealing body 12. The O terminal 16 is bonded to the inner metal layer 56 of the second lower insulating substrate 46. In one example, the P terminal 14 and the O terminal 16 are joined to the inner metal layer 36 of the first lower insulating substrate 26 and the inner metal layer 56 of the second lower insulating substrate 46 by welding, respectively. In addition, the range WL shown in the drawings of the present specification indicates a welding point by welding.

  The plurality of first signal terminals 18 are connected to the first semiconductor element 20 via the bonding wires 18a, and the plurality of second signal terminals 19 are connected to the second semiconductor element 40 via the bonding wires 19a. There is. The number and specific configuration of the first signal terminal 18 and the second signal terminal 19 are not particularly limited. In addition, the semiconductor device 10 does not necessarily have to include the first signal terminal 18 and the second signal terminal 19.

  Next, a method of manufacturing the semiconductor device 10 will be described with reference to FIGS. First, as shown in FIG. 5, the first lower insulating substrate 26 and the second lower insulating substrate 46 are prepared. Further, as shown in FIG. 6, the lead frame 4 is prepared. The lead frame 4 is provided with a P terminal 14, an N terminal 15 and an O terminal 16, a plurality of first signal terminals 18 and a plurality of second signal terminals 19. As described above, these terminals 14, 15, 16, 18, 19 are external connection terminals of the semiconductor device 10. The lead frame 4 can be comprised of copper or other conductor.

  Next, as shown in FIG. 7, the lead frame 4 is bonded to the first lower insulating substrate 26 and the second lower insulating substrate 46. This bonding can be performed, for example, by laser welding. By this process, the first lower insulating substrate 26 and the second lower insulating substrate 46 are integrated with the lead frame 4. In one example, in the present embodiment, the two lower insulating substrates 26 and the lead frame 4 are integrated by laser welding at four locations. However, the number, area, and shape of the bonding points can be changed as appropriate. In addition to the bonding of the lead frame 4, a member constituting the joint 60 is prepared and bonded to the inner metal layer 56 of the second lower insulating substrate 46. The joint 60 may be provided in advance on the inner metal layer 56 of the second lower insulating substrate 46.

  In the above process, the plurality of external connection terminals 14, 15, 16, 18, 19 provided on the lead frame 4 are simultaneously positioned with respect to the insulating substrates 26, 46. That is, the positional accuracy of the external connection terminals 14, 15, 16, 18, 19 in the lead frame 4 is maintained as it is with respect to the insulating substrates 26, 46. Therefore, the plurality of external connection terminals 14, 15, 16, 18, 19 can be accurately disposed on the insulating substrates 26, 46. Further, since the insulating substrates 26 and 46 and the lead frame 4 can be separately prepared, even if high temperature processing is required in the process of preparing the insulating substrates 26 and 46, the external connection terminals 14 and 15, The positional accuracy of 16, 18, 19 does not deteriorate.

  Next, as shown in FIG. 8, assembly of the first semiconductor element 20 and the second semiconductor element 40 is performed. Specifically, the first semiconductor element 20 is soldered on the inner metal layer 36 of the first lower insulating substrate 26, and the second semiconductor element 40 is on the inner metal layer 56 of the second lower insulating substrate 46. Soldered to Further, the first conductor spacer 24 is soldered on the first semiconductor element 20, and the second conductor spacer 44 is soldered on the second semiconductor element 40. The soldering at these multiple points may be performed simultaneously by a single reflow process, or may be divided into two or more steps. Then, the plurality of first signal terminals 18 are connected to the first semiconductor element 20 by the bonding wires 18 a, and the plurality of second signal terminals 19 are connected to the second semiconductor element 40 by the bonding wires 19 a.

  Next, as shown in FIG. 9, the first upper insulating substrate 22 and the second upper insulating substrate 42 are assembled. Specifically, the first upper insulating substrate 22 is soldered on the first conductor spacer 24, and the second upper insulating substrate 42 is soldered on the second conductor spacer 44. At this time, the first upper insulating substrate 22 is also soldered to the joint 60. The second upper insulating substrate 42 is also soldered to the N terminal 15. The soldering at these multiple points may be performed simultaneously by a single reflow process, or may be divided into two or more steps.

  Finally, as shown in FIG. 10, molding of the sealing body 12 is performed. As one example, the molding of the sealing body 12 can be performed by insert molding using an epoxy resin. After molding of the sealing body 12, the surface of the sealing body 12 is cut as necessary to form the respective outer metal layers 32, 52 of the upper insulating substrates 22, 42 and the lower insulating substrates 26, 46. The outer metal layers 38, 58 are exposed. Next, the semiconductor device 10 is completed by removing the unnecessary part (broken line part) of the lead frame 4.

  As described above, the manufacturing method disclosed herein comprises insulating substrates (26, 46) provided with metal layers (36, 38, 56, 58) on both sides of insulating layers (34, 54). A step of preparing, a step of preparing a lead frame (4) provided with a plurality of external connection terminals (14, 15, 16, 18, 19), one metal layer (36, 56) of the insulating substrate and a lead And a step of bonding the frame (4) and a step of disposing the semiconductor element (20, 40) on the one metal layer of the insulating substrate. According to such a manufacturing method, since the plurality of external connection terminals provided on the lead frame are simultaneously positioned with respect to the insulating substrate, the positional accuracy of the external connection terminals in the lead frame can be maintained as it is. it can. In addition, since the insulating substrate and the lead frame can be individually prepared, even if high temperature processing is required in the process of preparing the insulating substrate, the positional accuracy of the external connection terminal is not deteriorated thereby.

  As another embodiment, the lead frame 4 may further be provided with a joint 60. In this case, for example, as shown in FIG. 11, a lead frame 4a further having a joint 60 can be used. In the lead frame 4a, the joint 60 is connected to the other part of the lead frame 4a via the tie bar 60a. The position and posture of the joint 60 can be appropriately adjusted by the shape of the tie bar 60a. Here, when such a lead frame 4 a is used, as shown in FIG. 12, in the completed semiconductor device 10 a, a part of the remaining tie bar 60 a is exposed on the surface of the sealing body 12. Since the tie bar 60a is electrically connected to the O terminal 16 for power, it is necessary to electrically isolate the first signal terminal 18 and the second signal terminal 19 for adjacent signals. . In this regard, in the semiconductor device 10a shown in FIG. 12, the groove 13 for extending the creeping distance between the tie bar 60a and the first signal terminal 18 and between the tie bar 60a and the second signal terminal 19 is provided. It is formed. The design items such as the position, number, and shape of the grooves 13 can be appropriately set according to the required insulation.

  Although some specific examples have been described above in detail, these are merely examples and do not limit the scope of the claims. The art set forth in the claims includes various variations and modifications of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness singly or in various combinations.

4, 4a: lead frame 10, 10a: semiconductor device 12: sealing body 13: groove 14 of sealing body: P terminal 15: N terminal 16: O terminal 18: first signal terminal 19: second signal terminal 20, 40: first semiconductor element 22, 42: upper insulating substrate 24, 44: conductor spacer 26, 46: lower insulating substrate 28, 48: insulating layer 30 of upper insulating substrate 30: inner metal layer 32 of upper insulating substrate: upper insulating Outer metal layer 34 of substrate: insulating layer 36 of lower insulating substrate: inner metal layer 38 of lower insulating substrate: outer metal layer 60 of lower insulating substrate 60: joint 60a: tie bar WL: junction by welding

Claims (1)

Preparing an insulating substrate having a metal layer provided on each side of the insulating layer;
Preparing a lead frame provided with a plurality of external connection terminals;
Bonding one of the metal layers of the insulating substrate and the lead frame;
Placing a semiconductor element on the one metal layer of the insulating substrate;
And a method of manufacturing a semiconductor device.

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