JP2015023226A - Wide gap semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wide gap semiconductor device which resolves a problem of heat stress caused by wire bonding while maintaining the flexibility of a terminal shape etc.SOLUTION: The invention includes: a device module (101) disposed on a metal pattern 112; a signal terminal 105 disposed on the metal pattern; electrode wiring (104) which is arranged in the metal pattern and the device module; an enclosure case 109 which houses a base plate 102; and a sealing resin (110) filling the enclosure case. A metal wire serving as the electrode wiring does not exist in the enclosure case 109 which excludes the interior of the device module.

Description

  The present invention relates to a wide gap semiconductor device, and more particularly to high reliability and versatility of a power semiconductor device.

  Conventionally, there is a highly reliable semiconductor power module configured by a combination of DLB (direct lead bond) bonding of main wiring and transfer mold sealing technology (Patent Document 1). Examples of the power module include a MOSFET (metal-oxide-semiconductor field-effect transistor) or an IGBT (Insulated Gate Bipolar Transistor). Si is mainly used as the chip of the semiconductor power module.

  On the other hand, an insulating substrate is soldered on a metal base plate, and further a power device chip is soldered on the upper surface of the insulating substrate, and wiring connection is made from the upper surface of the chip to the case electrode via aluminum wire bonding. There is a power module configured by this (Patent Document 2). In addition, said insulating substrate joins a copper plate on both surfaces of a ceramic. Si is mainly used as the chip of the power module.

JP 2012-74543 A JP 2002-76257 A

  As described above, there is a structure obtained by combining the DLB bonding of the main wiring and the transfer mold sealing technique as a means for improving the thermal stress or the like of the wire bonding.

  The method of using aluminum wire bond as a means to extract current from the power device is a proven method that has been implemented in the past, but when the wire bond is directly joined to the heat generating part of the power device, power device switching Thermal stress due to repeated operations appears as a fatigue life as it is (see Patent Document 2). For this reason, if priority is given to long life, it is necessary to set the maximum temperature Tj (max) of the joint portion low, resulting in a problem that the apparatus is enlarged and the manufacturing cost is increased.

  When combining DLB bonding and transfer mold sealing technology as in Patent Document 1 above, the above-mentioned problems caused by thermal stress can be solved, but the initial investment amount increases due to the necessity of preparing a mold or the like. . In addition, there is a limitation on the degree of freedom of the terminal shape and dimensions, and there is a problem that a very expensive cost is required to apply to a wide variety or a small amount of product group.

  The present invention has been made to solve the above problems, and provides a wide gap semiconductor device capable of solving the problem of thermal stress due to wire bonding while maintaining the flexibility of the terminal shape and the like. Objective.

  A wide gap semiconductor device according to an aspect of the present invention includes a base plate, an insulating substrate disposed on the base plate and having a metal pattern formed on a surface thereof, and at least one device module disposed on the metal pattern. A signal terminal disposed on the metal pattern, an electrode wiring wired to the metal pattern and the device module, an enclosing case for housing the base plate, and filling the enclosing case. The device module includes a metal frame, a wide gap semiconductor transistor disposed on the metal frame, a wide gap semiconductor diode disposed on the metal frame, and the wide gap semiconductor transistor. Arranged on the upper surface and the upper surface of the wide gap semiconductor diode, respectively An electrode block connected to the electrode wiring, a separated metal frame connected to the signal terminal and spaced apart from the metal frame, a metal wire connecting the wide gap semiconductor transistor and the separated metal frame, The electrode block, the metal frame, and the spaced metal frame are partially exposed to cover the metal frame, the wide gap semiconductor transistor, the wide gap semiconductor diode, the electrode block, the spaced metal frame, and the metal wire. A metal resin as the electrode wiring does not exist in the outer case except for the inside of the device module.

  According to the above aspect of the present invention, the metal wire is used in the device module to maintain the flexibility of the terminal shape and the like, and the electrode wiring that does not use the wire bonding outside the device module is caused by the wire bonding. The maximum temperature limit can be removed.

It is sectional drawing which shows the whole structure of the SiC semiconductor device regarding embodiment. It is a figure for demonstrating the assembly procedure of the SiC semiconductor device regarding embodiment. It is a figure for demonstrating the assembly procedure of the SiC semiconductor device regarding embodiment. It is a figure for demonstrating the assembly procedure of the SiC semiconductor device regarding embodiment. It is a figure for demonstrating the assembly procedure of the SiC semiconductor device regarding embodiment. It is a figure for demonstrating the assembly procedure of the SiC semiconductor device regarding embodiment. It is a figure for demonstrating the assembly procedure of the SiC semiconductor device regarding embodiment. It is a figure for demonstrating the assembly procedure of the SiC semiconductor device regarding embodiment. It is a figure for demonstrating the assembly procedure of the SiC semiconductor device regarding embodiment. It is sectional drawing which shows the material structure of 1 arm module regarding embodiment. It is a figure for demonstrating the assembly procedure of the module for inverters regarding embodiment. It is a figure for demonstrating the assembly procedure of the module for inverters regarding embodiment. It is a figure for demonstrating the assembly procedure of the module for inverters regarding embodiment. It is a figure for demonstrating the assembly procedure of the module for inverters regarding embodiment. It is a figure for demonstrating the assembly procedure of the module for inverters regarding embodiment. It is a figure for demonstrating the assembly procedure of the module for inverters regarding embodiment. It is a figure for demonstrating the assembly procedure of the module for inverters regarding embodiment. It is a figure for demonstrating the assembly procedure of the module for inverters regarding embodiment. It is a figure for demonstrating the assembly procedure of the module for inverters regarding embodiment. It is a figure for demonstrating the assembly procedure of the module for inverters regarding embodiment. It is a figure for demonstrating the assembly procedure of the module for inverters regarding embodiment. It is a figure which shows the SiC semiconductor device at the time of employ | adopting the wire harness regarding embodiment. It is a figure which shows the power device module which made the bending direction of the space | interval metal frame regarding embodiment reverse (upward). It is a perspective view showing the state before the printed circuit board mounting of the SiC semiconductor device concerning an embodiment. It is a perspective view which shows the state after the printed circuit board mounting of the SiC semiconductor device regarding embodiment. It is sectional drawing which shows the whole structure of the Si semiconductor device regarding a base technology.

  Hereinafter, embodiments will be described with reference to the accompanying drawings.

<Embodiment>
<Configuration>
FIG. 1 is a cross-sectional view showing the overall structure of the SiC semiconductor device according to this embodiment.

  Here, the SiC is a kind of wide gap semiconductor. The wide gap semiconductor generally refers to a semiconductor having a forbidden band width of about 2 eV or more, and includes a group III nitride represented by GaN, a group II nitride represented by ZnO, a group II chalcogenide represented by ZnSe, and SiC and the like are known. In this embodiment, the case where SiC is used will be described. However, other wide gap semiconductors can be similarly applied.

As shown in FIG. 1, the SiC semiconductor device includes a power device module 101, a base plate 102, an insulating substrate 103 made of Si ₃ N ₄ or the like, a main electrode wiring 104, a signal terminal 105, a printed circuit board 106, a signal terminal 107, and solder. 108, an outer case 109, a silicone gel 110 as a sealing resin, and a lid 111.

  A plurality of insulating substrates 103 are arranged on the base plate 102 via solder 108. For example, metal patterns 112 such as copper plates are formed on both surfaces of each insulating substrate 103 made of ceramic or the like.

  On each metal pattern 112, the power device module 101 is disposed via the solder 108. Further, on each metal pattern 112, the main electrode wiring 104 and the signal terminal 105 are arranged via the solder 108.

  The main electrode wiring 104 is wired on the power device module 101 and extends to the upper surface of the outer casing 109. The main electrode wiring 104 is made of, for example, copper. The signal terminal 105 is connected to the signal terminal 107 via the printed circuit board 106.

  The structure including the power device module 101 is accommodated in an outer case 109, and the outer case 109 is filled with a silicone gel 110. Further, the lid 111 is disposed on the silicone gel 110, but the signal terminal 107 is provided so as to protrude onto the lid 111.

<Manufacturing method>
Next, an assembly procedure of one arm module (power device module 101 shown in FIG. 1) will be described with reference to FIGS.

  First, a different thickness frame 1 which is a metal frame having a different thickness for each region is prepared (FIG. 2). As the material of the different thickness frame 1, for example, copper can be used. Next, for example, n-Ag bonding material 2 (n-Ag paste) is printed on the different thickness frame 1 (FIG. 3).

  Next, one SiC chip 3 for MOSFET and one SiC chip 4 for SBD are mounted on the region where the n-Ag bonding material 2 is printed (FIG. 4).

  Subsequently, for example, n-Ag bonding material 2 (n-Ag paste) is also printed on the anode electrode and the source electrode of each chip (FIG. 5).

  Furthermore, the electrode block 5 is mounted on the region where the n-Ag bonding material 2 is printed (FIG. 6). And an electrode is joined by a heating and pressurization.

  Subsequently, the gate, source, and other signal system of the SiC chip 3 of the MOSFET are connected by wire bonding (ball bonding method) using the Au wire 6 (or Cu wire) (FIG. 7). For example, the MOSFET SiC chip 3 and a later-described spaced metal frame 1 b are connected via an Au wire 6.

  Subsequently, after the element region is sealed with the mold resin 7 (FIG. 8), one arm module (power device module 101) is formed by tie bar cutting and lead forming (FIG. 9).

  FIG. 10 is a cross-sectional view showing a material configuration of one arm module (power device module 101) according to this embodiment.

  As shown in FIG. 10, one MOSFET chip 3 and one SBD SiC chip 4 are mounted on the metal frame 1 a of the different thickness frame 1 via the n-Ag bonding material 2, respectively. Has been.

  In addition, electrode blocks 5 serving as source electrodes or anode electrodes are respectively disposed on the upper surfaces of the SiC chip 3 and the SiC chip 4. If the height of the upper surface of each electrode block 5 is formed to be equal, the wiring of the main electrode wiring 104 is facilitated. Each electrode block 5 is connected to the main electrode wiring 104.

  An Au wire 6 is wired from above the SiC chip 3, and the Au wire 6 is connected to a separated metal frame 1 b of the different thickness frame 1 that is separated from the metal frame 1 a. The Au wire 6 is a thinner wire than usual, specifically, it is about φ50 μm to about φ200 to φ400 μm. The separated metal frame 1 b is connected to the signal terminal 105 through the metal pattern 112 on the insulating substrate 103.

  The entire module is covered with a mold resin 7 (for example, epoxy resin). Specifically, the mold resin 7 exposes the electrode block 5, the metal frame 1a, and the separated metal frame 1b, and the metal frame 1a, the SiC chip 3, the SiC chip 4, the electrode block 5, the separated metal frame 1b, and the Au wire. The wire 6 is covered.

  Further, in the enclosing case 109 except for the power device module 101, a metal wire as the main electrode wiring 104 is not provided.

  The non-insulated one-arm module (power device module 101) shown in FIGS. 2 to 10 is transfer-molded and sealed in the outer case 109 to complete the SiC semiconductor device according to this embodiment.

  The SiC chip 3 for MOSFET and the SiC chip 4 for SBD in the power device module 101 use a sintered metal such as n-Ag as a bonding material on both upper and lower surfaces. With this configuration, the maximum junction temperature of the element can be increased. Therefore, it is possible to prevent remelting when soldering.

  Fine wire bonding of Au wire or Cu wire is performed on the gate and source signal terminal wiring of the MOSFET. In this way, the required area of the SiC chip can be reduced.

  Next, an assembling procedure of the inverter module on which six 1-arm modules are mounted will be described with reference to FIGS.

  First, the base plate 102 is prepared (FIG. 11), and solder 108 (solder paste) is printed on the base plate 102 (FIG. 12).

  Further, the insulating substrate 103 having the upper surface printed with the solder 108 is mounted on the printed solder 108 (FIG. 13). Note that metal patterns 112 are formed on both surfaces of the insulating substrate 103.

  Subsequently, the one-arm module (power device module 101) formed in FIG. 9 is mounted corresponding to the position on the insulating substrate 103 where the solder 108 is formed (FIG. 14).

  Subsequently, the solder 108 is dispensed (or printed in advance on the electrode portion) on the electrode portion on the upper surface of the one-arm module (power device module 101), and the signal terminal 105 is mounted on the base plate 102 (FIG. 15). Further, the main electrode wiring 104 is mounted on one arm module (power device module 101) (FIG. 16).

  Thereafter, heating (atmosphere furnace) is performed to complete soldering. Note that the solder paste can be soldered in a reducing atmosphere by mounting a plate-like solder.

  Subsequently, the outer case 109 provided with the nut for the main electrode and the signal terminal for external extraction is bonded and fixed (FIG. 17).

  Next, each signal terminal 105 is connected by the printed circuit board 106 (or wire harness) (FIG. 18). Then, the main electrode wiring 104 is bent and placed on the nut of the outer casing 109 so that wiring is possible (FIG. 19).

  Subsequently, silicone gel 110 is injected as a secondary sealing resin and cured (cured) (FIG. 20). Finally, the lid 111 is attached (FIG. 21).

  FIG. 22 is a diagram showing a SiC semiconductor device in which the printed circuit board 106 is not used for wiring of the signal terminals 105 and a wire harness 205 is employed instead. However, illustration of the P side is omitted. With this configuration, the package shape restriction can be greatly relaxed. Specifically, the printed circuit board and the external connection connector can be omitted by making the shape of the signal terminal 105 into a shape in which the sealing resin does not enter. As a result, the SiC semiconductor device can be manufactured at low cost.

  FIG. 23 is a diagram showing the power device module 101a in which the bending direction of the separated metal frame 1b in the portion exposed from the power device module is opposite (the direction toward the upper side of the insulating substrate 103). With such a configuration, the signal input terminal block for arranging the signal terminal 105 can be omitted, and the material cost and assembly processing cost can be reduced. In addition, the assembly process can be simplified.

  FIG. 24 is a perspective view showing a state of the SiC semiconductor device before the printed circuit board 106 is mounted. FIG. 25 is a perspective view showing a state after mounting the printed circuit board 106 of the SiC semiconductor device.

  FIG. 26 is a cross-sectional view showing the overall structure of the Si semiconductor device related to the base technology.

  As shown in FIG. 26, the Si semiconductor device is integrally formed into an IGBT or FWD (Free Wheeling Diode) Si chip 3a and Si chip 4a, a base plate 102, an insulating substrate 103 (metal pattern 112 on both sides), and a case. Main electrode wiring 104b, main current compatible aluminum wire 104a, signal wiring aluminum wire 105a, signal terminal 107a integrally formed in the case, solder 108, enclosing case 109, silicone gel 110 as sealing resin, and lid 111 It has.

  In the structure shown in FIG. 26, the metal pattern 112 on the insulating substrate 103 and the signal terminal 107a formed integrally with the surrounding case 109 are connected by wire bonding via the aluminum wire 105a.

  In FIG. 26, the aluminum wire 104a is made of a thicker wire than the aluminum wire 105a. However, in the case of such a structure, since it is necessary to prepare a plurality of types of wires, the production efficiency is not good. On the other hand, when all the aluminum wires have the same thickness as that of the aluminum wire 104a, the gate pad area increases, and particularly when the chip material is expensive, the manufacturing cost increases. It will be.

  In the configuration shown in FIG. 1, the terminals of the source and anode main electrode wirings 104 are exposed on the upper surface of the outer casing 109, so that the power device module 101 and the like are mounted on the metal pattern 112 and then the substrate. The main wiring can be performed without requiring an area. Further, since the main electrode wiring 104 is used, it is not necessary to set the maximum temperature Tj of the joint due to heat generation low.

  Compared to the case shown in FIG. 26 in which the Si chip is directly mounted on the metal pattern 112 of the insulating substrate 103, the apparatus becomes larger for forming the mold resin 7, but the wiring routing pattern and the wire bonding area The pattern can be omitted, and the module package as a whole is not increased in size (floor area reduction effect by three-dimensional wiring).

  Further, since the wire bonding is performed only in the power device module 101, only a thin metal wire can be used, and the required gate pad area can be reduced. Moreover, the area | region which must implement | achieve the environment which can perform wire bonding can also be limited. Furthermore, since wire bonding is used, restrictions such as dimensions are reduced.

<Modification>
By using ultrasonic bonding (UltraSonics bonding) for the connection between the main electrode wiring 104 and the metal pattern 112 on the insulating substrate 103 and the connection between the main electrode wiring 104 and the power device module 101, assembly is facilitated. It is possible to simplify the mounting of components for soldering, especially the simultaneous mounting of one arm module, main electrode wiring, and solder in multiple layers. In addition, mounting can be performed with the main electrode wiring 104 bent in advance, and dimensional accuracy can be further improved.

  When a liquid epoxy resin is used instead of the silicone gel 110 as the secondary sealing resin and the epoxy resin is hardened and sealed, the lid 111 can be omitted.

<Effect>
According to this embodiment, the wide gap semiconductor device includes a base plate 102, an insulating substrate 103, at least one device module (power device module 101), a signal terminal 105, and electrode wiring (main electrode wiring 104). The outer casing 109 and the sealing resin (silicone gel 110) are provided.

  The insulating substrate 103 is disposed on the base plate 102, and a metal pattern 112 is formed on the surface. The power device module 101 is disposed on the metal pattern 112. The signal terminal 105 is disposed on the metal pattern 112. The main electrode wiring 104 is wired to the metal pattern 112 and the power device module 101. The enclosing case 109 accommodates the base plate 102. The silicone gel 110 is filled in the outer case 109.

  Further, the power device module 101 includes a metal frame 1a, a wide gap semiconductor transistor (SiC chip 3 for MOSFET), a wide gap semiconductor diode (SiC chip 4 for SBD), an electrode block 5, and a separated metal frame 1b. And a metal wire (Au wire 6) and a mold resin 7.

  SiC chip 3 and SiC chip 4 are arranged on metal frame 1a. The electrode block 5 is arranged on each of the upper surface of the SiC chip 3 and the upper surface of the SiC chip 4 and is connected to the main electrode wiring 104. The separated metal frame 1b is connected to the signal terminal 105 and is separated from the metal frame 1a. The Au wire 6 connects the SiC chip 3 and the separated metal frame 1b.

  The mold resin 7 partially exposes the electrode block 5, the metal frame 1a, and the separated metal frame 1b, and the metal frame 1a, the SiC chip 3, the SiC chip 4, the electrode block 5, the separated metal frame 1b, and the Au wire 6 Covering.

  In addition, no metal wire as the main electrode wiring 104 exists in the outer case 109 excluding the power device module 101.

  According to such a configuration, by using the Au wire 6 in the power device module 101, while maintaining the degree of freedom of the terminal shape and the like, the electrode wiring outside the power device module 101 does not use wire bonding. The maximum temperature limitation due to wire bonding can be eliminated. Moreover, since the frame structure is adopted in the power device module 101, the wire bonding process of the Au wire 6 can be performed by general-purpose equipment. Further, by performing wire bonding only in the power device module 101, the work after the power device module 101 is mounted becomes easy.

  Further, by using the Au wire 6 which is a thin wire in the power device module 101, the gate pad area can be reduced.

  Moreover, high heat resistance is realizable by making the power device module 101 into a non-insulation type module and using the ceramic etc. as the insulated substrate 103.

  Further, outside the power device module 101, by using a simple configuration using the main electrode wiring 104, it is possible to reduce the number of wiring steps and the wiring resistance. Therefore, high performance can be realized by reducing power loss.

  In the said embodiment, although the material of each component, material, the conditions of implementation, etc. are described, these are illustrations and are not restricted to what was described.

  In the present invention, any component in the present embodiment can be modified or omitted within the scope of the invention.

  1 different thickness frame, 1a metal frame, 1b spaced metal frame, 2 n-Ag bonding material, 3,4 SiC chip, 3a, 4a Si chip, 5 electrode block, 6 Au wire wire, 7 mold resin, 101, 101a power Device module, 102 Base plate, 103 Insulating substrate, 104, 104b Main electrode wiring, 104a, 105a Aluminum wire, 105, 107, 107a Signal terminal, 106 Printed circuit board, 108 Solder, 109 Outer case, 110 Silicone gel, 111 Lid 112 metal pattern, 205 wire harness.

Claims (7)

A base plate,
An insulating substrate disposed on the base plate and having a metal pattern formed on the surface;
At least one device module disposed on the metal pattern;
A signal terminal disposed on the metal pattern;
An electrode wiring wired to the metal pattern and the device module;
An outer case for housing the base plate;
A sealing resin filled in the outer case,
The device module is
A metal frame,
A wide gap semiconductor transistor disposed on the metal frame;
A wide gap semiconductor diode disposed on the metal frame;
An electrode block disposed on each of the upper surface of the wide gap semiconductor transistor and the upper surface of the wide gap semiconductor diode and connected to the electrode wiring;
A spaced metal frame connected to the signal terminal and spaced apart from the metal frame;
A metal wire connecting the wide gap semiconductor transistor and the spaced metal frame;
The electrode block, the metal frame, and the spaced metal frame are partially exposed to cover the metal frame, the wide gap semiconductor transistor, the wide gap semiconductor diode, the electrode block, the spaced metal frame, and the metal wire. With mold resin,
In the outer case excluding the inside of the device module, there is no metal wire as the electrode wiring,
Wide gap semiconductor device. The upper surfaces of the electrode blocks disposed on the upper surface of the wide gap semiconductor transistor and the upper surface of the wide gap semiconductor diode have the same height.
The wide gap semiconductor device according to claim 1. The spaced apart metal frame of the portion exposed from the mold resin is bent in a direction toward the upper side of the insulating substrate,
The wide gap semiconductor device according to claim 1. The sealing resin contains a silicone gel,
The wide gap semiconductor device according to claim 1. The sealing resin is formed by solidifying a liquid epoxy resin,
The wide gap semiconductor device according to claim 1. The electrode wiring is wired by ultrasonic bonding to the metal pattern and the device module,
The wide gap semiconductor device according to claim 1. The signal terminal is connected to a wire harness,
The wide gap semiconductor device according to claim 1.

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