JP7069848B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP7069848B2
JP7069848B2 JP2018039958A JP2018039958A JP7069848B2 JP 7069848 B2 JP7069848 B2 JP 7069848B2 JP 2018039958 A JP2018039958 A JP 2018039958A JP 2018039958 A JP2018039958 A JP 2018039958A JP 7069848 B2 JP7069848 B2 JP 7069848B2
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heat sink
terminal
semiconductor element
semiconductor device
joint portion
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JP2019153756A (en
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真悟 岩崎
美由紀 木戸
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本明細書が開示する技術は、半導体装置に関する。 The techniques disclosed herein relate to semiconductor devices.

特許文献１に、半導体装置が開示されている。この半導体装置は、半導体素子と、半導体素子に接続された放熱板と、放熱板に接合材を介して接合された電力端子と、を備える。 Patent Document 1 discloses a semiconductor device. This semiconductor device includes a semiconductor element, a heat radiating plate connected to the semiconductor element, and a power terminal bonded to the heat radiating plate via a joining material.

特開２０１５－１３０４６５号公報JP-A-2015-130465

上記のような半導体装置では、電力端子が、接合材（例えば、はんだ又は導電性接着剤）に接触する接合エリアと、それに隣接する非接合エリアと、を有する。接合エリアと非接合エリアとの境界は、設計上定められており、半導体装置の製造段階では、流動性を有する接合材が、意図せず広範囲に広がることを防止する必要がある。 In a semiconductor device as described above, the power terminal has a bonding area in contact with a bonding material (for example, solder or a conductive adhesive) and a non-bonding area adjacent thereto. The boundary between the bonded area and the non-bonded area is defined by design, and it is necessary to prevent the bonded material having fluidity from unintentionally spreading over a wide area at the manufacturing stage of the semiconductor device.

本明細書に開示される半導体装置は、半導体素子と、前記半導体素子に接続された放熱板と、前記放熱板に接合材を介して接合された電力端子と、を備える。前記電力端子は、前記接合材に接触する接合エリアとそれに隣接する非接合エリアとの境界において、前記電力端子の厚み方向に屈曲する屈曲部が形成されている。 The semiconductor device disclosed in the present specification includes a semiconductor element, a heat sink connected to the semiconductor element, and a power terminal bonded to the heat sink via a bonding material. The power terminal is formed with a bent portion that bends in the thickness direction of the power terminal at a boundary between a joining area in contact with the joining material and a non-joining area adjacent to the joining area.

上記の構成によると、電力端子は、接合材に接触する接合エリアと、それに隣接する非接合エリアとの境界に、屈曲部を有する。この屈曲部は、接合部分の厚み方向に屈曲しているので、半導体装置の製造段階では、流動性を有する接合材が、屈曲部を超えて広がることが抑制される。これにより、接合エリアと非接合エリアとの意図された境界を越えて、接合材が過剰に広がることが防止され得る。 According to the above configuration, the power terminal has a bent portion at the boundary between the joining area in contact with the joining material and the non-joining area adjacent thereto. Since this bent portion is bent in the thickness direction of the joined portion, it is suppressed that the joining material having fluidity spreads beyond the bent portion at the manufacturing stage of the semiconductor device. This can prevent the joining material from spreading excessively beyond the intended boundary between the joining area and the non-joining area.

また、電力端子の屈曲部は、半導体装置の製造段階において曲げ加工などにより、容易に形成することができる。即ち、電力端子のうち接合エリアが占めるエリアを容易に変更することができる。このため、接合エリアを、放熱板の形状といった他の設計要件に容易に対応させることができ、それによって、放熱板と電力端子との間の接合面積を最大化させることができる。 Further, the bent portion of the power terminal can be easily formed by bending or the like at the manufacturing stage of the semiconductor device. That is, the area occupied by the junction area among the power terminals can be easily changed. Therefore, the joint area can be easily adapted to other design requirements such as the shape of the heat sink, thereby maximizing the joint area between the heat sink and the power terminal.

半導体装置１０の平面図。Top view of the semiconductor device 10. 半導体装置１０の内部構造を示す平面図。The plan view which shows the internal structure of the semiconductor device 10. 図１のIII－III線における内部構造を示す断面図。The cross-sectional view which shows the internal structure in line III-III of FIG. 図２のIV部を拡大して示す拡大図。An enlarged view showing the IV part of FIG. 2 in an enlarged manner. 図４のV－Vにおける断面図。FIG. 4 is a cross-sectional view taken along the line VV of FIG.

図面を参照して、実施例の半導体装置１０について説明する。本実施例の半導体装置１０は、例えば電気自動車、ハイブリッド車、燃料電池車といった電動自動車において、コンバータやインバータといった電力変換回路に用いることができる。但し、半導体装置１０の用途は特に限定されない。半導体装置１０は、様々な装置や回路に広く採用することができる。 The semiconductor device 10 of the embodiment will be described with reference to the drawings. The semiconductor device 10 of this embodiment can be used for a power conversion circuit such as a converter or an inverter in an electric vehicle such as an electric vehicle, a hybrid vehicle, or a fuel cell vehicle. However, the use of the semiconductor device 10 is not particularly limited. The semiconductor device 10 can be widely adopted in various devices and circuits.

図１、図２、図３に示すように、半導体装置１０は、第１半導体素子２０と、第２半導体素子４０と、封止体１２と、複数の外部接続端子１４、１５、１６、１８、１９と、を備える。第１半導体素子２０と第２半導体素子４０は、封止体１２の内部に封止されている。封止体１２は、特に限定されないが、例えばエポキシ樹脂といった熱硬化性樹脂で構成されている。各々の外部接続端子１４、１５、１６、１８、１９は、封止体１２の外部から内部に亘って延びており、封止体１２の内部で第１半導体素子２０及び第２半導体素子４０の少なくとも一方に電気的に接続されている。一例ではあるが、複数の外部接続端子１４、１５、１６、１８、１９には、電力用であるＰ端子１４、Ｎ端子１５及びＯ端子１６と、信号用である複数の第１信号端子１８及び複数の第２信号端子１９が含まれる。 As shown in FIGS. 1, 2, and 3, the semiconductor device 10 includes a first semiconductor element 20, a second semiconductor element 40, a sealant 12, and a plurality of external connection terminals 14, 15, 16, and 18. , 19, and. The first semiconductor element 20 and the second semiconductor element 40 are sealed inside the sealing body 12. The sealing body 12 is not particularly limited, but is made of a thermosetting resin such as an epoxy resin. Each of the external connection terminals 14, 15, 16, 18, and 19 extends from the outside to the inside of the sealing body 12, and inside the sealing body 12, the first semiconductor element 20 and the second semiconductor element 40 It is electrically connected to at least one of them. As an example, the plurality of external connection terminals 14, 15, 16, 18, and 19 include a P terminal 14, an N terminal 15 and an O terminal 16 for electric power, and a plurality of first signal terminals 18 for signals. And a plurality of second signal terminals 19.

図３に示すように、第１半導体素子２０は、上面電極２０ａと、下面電極２０ｂと、を有する。上面電極２０ａは、第１半導体素子２０の上面に位置しており、下面電極２０ｂは、第１半導体素子２０の下面に位置している。第１半導体素子２０は、上下一対の電極２０ａ、２０ｂを有する縦型の半導体素子である。同様に、第２半導体素子４０は、上面電極４０ａと下面電極４０ｂとを有する。上面電極４０ａは第２半導体素子４０の上面に位置しており、下面電極４０ｂは第２半導体素子４０の下面に位置する。即ち、第２半導体素子４０についても、上下一対の電極４０ａ、４０ｂを有する縦型の半導体素子である。本実施例における第１半導体素子２０と第２半導体素子４０は、互いに同種の半導体素子であり、詳しくはＩＧＢＴ（Insulated Gate Bipolar Transistor）とダイオードとを内蔵するＲＣ－ＩＧＢＴ（Reverse Conducting IGBT）素子である。 As shown in FIG. 3, the first semiconductor element 20 has a top surface electrode 20a and a bottom surface electrode 20b. The upper surface electrode 20a is located on the upper surface of the first semiconductor element 20, and the lower surface electrode 20b is located on the lower surface of the first semiconductor element 20. The first semiconductor element 20 is a vertical semiconductor element having a pair of upper and lower electrodes 20a and 20b. Similarly, the second semiconductor element 40 has a top electrode 40a and a bottom electrode 40b. The upper surface electrode 40a is located on the upper surface of the second semiconductor element 40, and the lower surface electrode 40b is located on the lower surface of the second semiconductor element 40. That is, the second semiconductor element 40 is also a vertical semiconductor element having a pair of upper and lower electrodes 40a and 40b. The first semiconductor element 20 and the second semiconductor element 40 in this embodiment are semiconductor elements of the same type, and more specifically, they are RC-IGBT (Reverse Conducting IGBT) elements incorporating an IGBT (Insulated Gate Bipolar Transistor) and a diode. be.

但し、第１半導体素子２０と第２半導体素子４０の各々は、ＲＣ－ＩＧＢＴ素子に限定されず、例えばＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）素子といった他のパワー半導体素子であってもよい。あるいは、第１半導体素子２０と第２半導体素子４０の各々は、ダイオード素子とＩＧＢＴ素子（又はＭＯＳＦＥＴ素子）といった二以上の半導体素子に置き換えられてもよい。第１半導体素子２０と第２半導体素子４０の具体的な構成は特に限定されず、各種の半導体素子を採用することができる。この場合、第１半導体素子２０と第２半導体素子４０は、互いに異種の半導体素子であってもよい。また、第１半導体素子２０と第２半導体素子４０の各々は、例えばシリコン（Ｓｉ）、炭化ケイ素（ＳｉＣ）、又は窒化ガリウム（ＧａＮ）といった各種の半導体材料を用いて構成されることができる。第１半導体素子２０の上面電極２０ａ及び下面電極２０ｂを構成する材料には、特に限定されないが、例えばアルミニウム系又はその他の金属を採用することができる。同様に、第２半導体素子４０の上面電極４０ａ及び下面電極４０ｂを構成する材料には、特に限定されないが、例えばアルミニウム系又はその他の金属を採用することができる。 However, each of the first semiconductor element 20 and the second semiconductor element 40 is not limited to the RC-IGBT element, and may be another power semiconductor element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) element. good. Alternatively, each of the first semiconductor element 20 and the second semiconductor element 40 may be replaced with two or more semiconductor elements such as a diode element and an IGBT element (or MOSFET element). The specific configuration of the first semiconductor element 20 and the second semiconductor element 40 is not particularly limited, and various semiconductor elements can be adopted. In this case, the first semiconductor element 20 and the second semiconductor element 40 may be semiconductor elements different from each other. Further, each of the first semiconductor element 20 and the second semiconductor element 40 can be configured by using various semiconductor materials such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). The material constituting the upper surface electrode 20a and the lower surface electrode 20b of the first semiconductor element 20 is not particularly limited, and for example, an aluminum-based material or other metal can be adopted. Similarly, the material constituting the upper surface electrode 40a and the lower surface electrode 40b of the second semiconductor element 40 is not particularly limited, but for example, an aluminum-based material or another metal can be adopted.

半導体装置１０は、第１上側放熱板２２と、第１導体スペーサ２４と、第１下側放熱板２６と、をさらに備える。第１導体スペーサ２４は、例えば銅又はその他の金属といった導電性を有する材料を用いて構成されている。第１導体スペーサ２４は、概して板形状あるいはブロック形状の部材であり、上面２４ａと、上面２４ａとは反対側に位置する下面２４ｂと、を有する。第１導体スペーサ２４は封止体１２内に位置している。第１導体スペーサ２４の上面２４ａは、第１上側放熱板２２にはんだ層２３を介して接合されている。第１導体スペーサ２４の下面２４ｂは、第１半導体素子２０の上面電極２０ａにはんだ層２５を介して接合されている。即ち、第１導体スペーサ２４は、第１半導体素子２０に電気的に接続されている。第１導体スペーサ２４は、必ずしも必要とされないが、第１信号端子１８を第１半導体素子２０に接続する際のスペースを確保する。 The semiconductor device 10 further includes a first upper heat sink 22, a first conductor spacer 24, and a first lower heat sink 26. The first conductor spacer 24 is constructed using a conductive material such as copper or other metal. The first conductor spacer 24 is generally a plate-shaped or block-shaped member, and has an upper surface 24a and a lower surface 24b located on the opposite side of the upper surface 24a. The first conductor spacer 24 is located inside the sealing body 12. The upper surface 24a of the first conductor spacer 24 is joined to the first upper heat sink 22 via the solder layer 23. The lower surface 24b of the first conductor spacer 24 is bonded to the upper surface electrode 20a of the first semiconductor element 20 via the solder layer 25. That is, the first conductor spacer 24 is electrically connected to the first semiconductor element 20. The first conductor spacer 24 is not always required, but secures a space for connecting the first signal terminal 18 to the first semiconductor element 20.

第１上側放熱板２２及び第１下側放熱板２６は、例えば銅、アルミニウム又はその他の金属といった熱伝導性に優れた材料で構成されている。第１上側放熱板２２は、概して直方体形状又は板形状の部材であり、上面２２ａと、上面２２ａとは反対側に位置する下面２２ｂと、を有する。第１上側放熱板２２の上面２２ａは、封止体１２の上面１２ａにおいて外部に露出されている。また、第１上側放熱板２２の下面２２ｂは、前述した第１導体スペーサ２４の上面２４ａにはんだ層２３を介して接合されている。即ち、第１上側放熱板２２は第１導体スペーサ２４を介して第１半導体素子２０と電気的及び熱的に接続されている。これにより、第１上側放熱板２２は、半導体装置１０の電気回路の一部を構成するだけでなく、第１半導体素子２０の熱を外部に放出する放熱板としても機能する。 The first upper heat sink 22 and the first lower heat sink 26 are made of a material having excellent thermal conductivity, for example, copper, aluminum, or other metal. The first upper heat sink 22 is generally a rectangular parallelepiped or plate-shaped member, and has an upper surface 22a and a lower surface 22b located on the opposite side of the upper surface 22a. The upper surface 22a of the first upper heat sink 22 is exposed to the outside on the upper surface 12a of the sealing body 12. Further, the lower surface 22b of the first upper heat sink 22 is joined to the upper surface 24a of the first conductor spacer 24 described above via the solder layer 23. That is, the first upper heat sink 22 is electrically and thermally connected to the first semiconductor element 20 via the first conductor spacer 24. As a result, the first upper heat sink 22 not only constitutes a part of the electric circuit of the semiconductor device 10, but also functions as a heat sink that releases the heat of the first semiconductor element 20 to the outside.

第１下側放熱板２６は、概して直方体形状又は板形状の部材であり、上面２６ａと、上面２６ａとは反対側に位置する下面２６ｂと、を有する。第１下側放熱板２６の下面２６ｂは、封止体１２の下面１２ｂにおいて外部に露出されている。また、第１下側放熱板２６の上面２６ａは、第１半導体素子２０の下面電極２０ｂにはんだ層２７を介して接合されている。即ち、第１下側放熱板２６は、第１半導体素子２０と電気的及び熱的に接続されている。これにより、第１下側放熱板２６においても半導体装置１０の電気回路の一部を構成するだけでなく、第１半導体素子２０の熱を外部に放出する放熱板としても機能する。このように、本実施例の半導体装置１０は、封止体１２の両面１２ａ、１２ｂに第１上側放熱板２２及び第１下側放熱板２６が露出される両面冷却構造を有する。 The first lower heat sink 26 is generally a rectangular parallelepiped or plate-shaped member, and has an upper surface 26a and a lower surface 26b located on the opposite side of the upper surface 26a. The lower surface 26b of the first lower heat sink 26 is exposed to the outside on the lower surface 12b of the sealing body 12. Further, the upper surface 26a of the first lower heat sink 26 is bonded to the lower surface electrode 20b of the first semiconductor element 20 via the solder layer 27. That is, the first lower heat sink 26 is electrically and thermally connected to the first semiconductor element 20. As a result, the first lower heat sink 26 not only constitutes a part of the electric circuit of the semiconductor device 10, but also functions as a heat sink that releases the heat of the first semiconductor element 20 to the outside. As described above, the semiconductor device 10 of the present embodiment has a double-sided cooling structure in which the first upper heat sink 22 and the first lower heat sink 26 are exposed on both sides 12a and 12b of the sealing body 12.

また、半導体装置１０は、第２上側放熱板４２と、第２導体スペーサ４４と、第２下側放熱板４６と、をさらに備える。第２導体スペーサ４４は、例えば銅又はその他の金属といった導電性を有する材料を用いて構成されている。第２導体スペーサ４４は、概して板形状あるいはブロック形状の部材であり、上面４４ａと、上面４４ａとは反対側に位置する下面４４ｂと、を有する。第２導体スペーサ４４は封止体１２内に位置している。第２導体スペーサ４４の上面４４ａは、第２上側放熱板４２にはんだ層４３を介して接合されている。第２導体スペーサ４４の下面４４ｂは、第２半導体素子４０の上面電極４０ａにはんだ層４５を介して接合されている。即ち、第２導体スペーサ４４は、第２半導体素子４０に電気的に接続されている。第２導体スペーサ４４は、必ずしも必要とされないが、第２信号端子１９を第２半導体素子４０に接続する際のスペースを確保する。 Further, the semiconductor device 10 further includes a second upper heat sink 42, a second conductor spacer 44, and a second lower heat sink 46. The second conductor spacer 44 is constructed using a conductive material such as copper or other metal. The second conductor spacer 44 is generally a plate-shaped or block-shaped member, and has an upper surface 44a and a lower surface 44b located on the opposite side of the upper surface 44a. The second conductor spacer 44 is located inside the sealing body 12. The upper surface 44a of the second conductor spacer 44 is joined to the second upper heat sink 42 via the solder layer 43. The lower surface 44b of the second conductor spacer 44 is bonded to the upper surface electrode 40a of the second semiconductor element 40 via the solder layer 45. That is, the second conductor spacer 44 is electrically connected to the second semiconductor element 40. The second conductor spacer 44 is not always required, but secures a space for connecting the second signal terminal 19 to the second semiconductor element 40.

第２上側放熱板４２及び第２下側放熱板４６は、例えば銅、アルミニウム又はその他の金属といった熱伝導性に優れた材料で構成されている。第２上側放熱板４２は、概して直方体形状又は板形状の部材であり、上面４２ａと、上面４２ａとは反対側に位置する下面４２ｂと、を有する。第２上側放熱板４２の上面４２ａは、封止体１２の上面１２ａにおおいて外部に露出されている。また、第２上側放熱板４２の下面４２ｂは、前述した第２導体スペーサ４４の上面４４ａにはんだ層４３を介して接合されている。即ち、第２上側放熱板４２は第２導体スペーサ４４を介して第２半導体素子４０と電気的及び熱的に接続されている。これにより、第２上側放熱板４２は、半導体装置１０の電気回路の一部を構成するだけでなく、第２半導体素子４０の熱を外部に放出する放熱板としても機能する。 The second upper heat sink 42 and the second lower heat sink 46 are made of a material having excellent thermal conductivity, for example, copper, aluminum, or other metal. The second upper heat sink 42 is generally a rectangular parallelepiped or plate-shaped member, and has an upper surface 42a and a lower surface 42b located on the opposite side of the upper surface 42a. The upper surface 42a of the second upper heat sink 42 is exposed to the outside on the upper surface 12a of the sealing body 12. Further, the lower surface 42b of the second upper heat sink 42 is joined to the upper surface 44a of the second conductor spacer 44 described above via the solder layer 43. That is, the second upper heat sink 42 is electrically and thermally connected to the second semiconductor element 40 via the second conductor spacer 44. As a result, the second upper heat sink 42 not only constitutes a part of the electric circuit of the semiconductor device 10, but also functions as a heat sink that releases the heat of the second semiconductor element 40 to the outside.

第２下側放熱板４６は、概して直方体形状又は板形状の部材であり、上面４６ａと、上面４６ａとは反対側に位置する下面４６ｂと、を有する。第２下側放熱板４６の下面４６ｂは、封止体１２の下面１２ｂにおいて外部に露出されている。また、第２下側放熱板４６の上面４６ａは、第２半導体素子４０の下面電極４０ｂにはんだ層４７を介して接合されている。即ち、第２下側放熱板４６は、第２半導体素子４０と電気的及び熱的に接続されている。これにより、第２下側放熱板４６においても半導体装置１０の電気回路の一部を構成するだけでなく、第２半導体素子４０の熱を外部に放出する放熱板としても機能する。このように、本実施例の半導体装置１０は、封止体１２の両面１２ａ、１２ｂに第２上側放熱板４２及び第２下側放熱板４６が露出される両面冷却構造を有する。第２下側放熱板４６は、第１上側継手部２２ｃ及び第２下側継手部４６ｃを介して、第１上側放熱板２２に接続されている。 The second lower heat sink 46 is generally a rectangular parallelepiped or plate-shaped member, and has an upper surface 46a and a lower surface 46b located on the opposite side of the upper surface 46a. The lower surface 46b of the second lower heat sink 46 is exposed to the outside on the lower surface 12b of the sealing body 12. Further, the upper surface 46a of the second lower heat sink 46 is bonded to the lower surface electrode 40b of the second semiconductor element 40 via the solder layer 47. That is, the second lower heat sink 46 is electrically and thermally connected to the second semiconductor element 40. As a result, the second lower heat sink 46 not only constitutes a part of the electric circuit of the semiconductor device 10, but also functions as a heat sink that releases the heat of the second semiconductor element 40 to the outside. As described above, the semiconductor device 10 of the present embodiment has a double-sided cooling structure in which the second upper heat sink 42 and the second lower heat sink 46 are exposed on both sides 12a and 12b of the sealing body 12. The second lower heat sink 46 is connected to the first upper heat sink 22 via the first upper joint portion 22c and the second lower joint portion 46c.

上述したように、半導体装置１０は、外部接続端子として、Ｐ端子１４、Ｎ端子１５及びＯ端子１６を備える。本実施例におけるＰ端子１４、Ｎ端子１５及びＯ端子１６は、銅で構成されている。但し、Ｐ端子１４、Ｎ端子１５及びＯ端子１６は、銅に限定されず、他の導体で構成されてもよい。Ｐ端子１４は、封止体１２の内部において、第１下側放熱板２６の上面２６ａに接続されている。Ｎ端子１５は、封止体１２の内部において、第２上側放熱板４２の下面４２ｂに接続されている。そして、Ｏ端子１６は、第２下側放熱板４６の上面４６ａに接続されている。一例ではあるが、Ｐ端子１４及びＯ端子１６は、それぞれ第１下側放熱板２６及び第２下側放熱板４６に一体に形成されている。但し、Ｐ端子１４及びＯ端子１６の一方又は両方は、それぞれ第１下側放熱板２６及び第２下側放熱板４６に例えば溶接によって接合されてもよい。また、Ｎ端子１５は、後述するが、第２上側放熱板４２の第２上側継手部４２ｃにはんだ付けによって接合されている。半導体装置１０は外部接続端子として、複数の第１信号端子１８及び複数の第２信号端子１９もまた備える。本実施例における複数の信号端子１８、１９は、第１半導体素子２０及び第２半導体素子４０に、それぞれ、ボンディングワイヤ１８ａ、１９ａによって接続されている。 As described above, the semiconductor device 10 includes P terminal 14, N terminal 15, and O terminal 16 as external connection terminals. The P terminal 14, the N terminal 15, and the O terminal 16 in this embodiment are made of copper. However, the P terminal 14, the N terminal 15, and the O terminal 16 are not limited to copper, and may be composed of other conductors. The P terminal 14 is connected to the upper surface 26a of the first lower heat sink 26 inside the sealing body 12. The N terminal 15 is connected to the lower surface 42b of the second upper heat sink 42 inside the sealing body 12. The O terminal 16 is connected to the upper surface 46a of the second lower heat sink 46. As an example, the P terminal 14 and the O terminal 16 are integrally formed with the first lower heat sink 26 and the second lower heat sink 46, respectively. However, one or both of the P terminal 14 and the O terminal 16 may be joined to the first lower heat sink 26 and the second lower heat sink 46, respectively, by welding, for example. Further, as will be described later, the N terminal 15 is joined to the second upper joint portion 42c of the second upper heat sink 42 by soldering. The semiconductor device 10 also includes a plurality of first signal terminals 18 and a plurality of second signal terminals 19 as external connection terminals. The plurality of signal terminals 18 and 19 in this embodiment are connected to the first semiconductor element 20 and the second semiconductor element 40 by bonding wires 18a and 19a, respectively.

図２、図３に示すように、半導体装置１０の第１上側放熱板２２は、導体で構成された第１上側継手部２２ｃをさらに有する。同様に第２下側放熱板４６は、導体で構成された第２下側継手部４６ｃをさらに有する。第１上側継手部２２ｃ及び第２下側継手部４６ｃは、封止体１２の内部に位置している。第１上側放熱板２２の第１上側継手部２２ｃは、第２下側放熱板４６の第２下側継手部４６ｃにはんだ層５０を介して接合されている。即ち、第１上側継手部２２ｃ及び第２下側継手部４６ｃは、第１上側放熱板２２と第２下側放熱板４６との間を電気的に接続している。これにより、第１半導体素子２０と第２半導体素子４０は、第１上側継手部２２ｃ及び第２下側継手部４６ｃを介して直列に接続される。第１上側継手部２２ｃ及び第２下側継手部４６ｃは、例えば銅で構成されることができる。第１上側継手部２２ｃと第１上側放熱板２２とは、一体に形成されていてもよいし、互いに接合されていてもよい。この場合の接合手法は、特に限定されず、例えば溶接によって接合されていてもよい。同様に、第２下側継手部４６ｃの第２下側放熱板４６とは、一体に形成されていてもよいし、互いに接合されていてもよい。この場合の接合手法においても、特に限定されず、例えば溶接によって接合されていてもよい。 As shown in FIGS. 2 and 3, the first upper heat sink 22 of the semiconductor device 10 further includes a first upper joint portion 22c composed of a conductor. Similarly, the second lower heat sink 46 further includes a second lower joint 46c made of a conductor. The first upper joint portion 22c and the second lower joint portion 46c are located inside the sealing body 12. The first upper joint portion 22c of the first upper heat sink 22 is joined to the second lower joint portion 46c of the second lower heat sink 46 via the solder layer 50. That is, the first upper joint portion 22c and the second lower joint portion 46c are electrically connected between the first upper heat sink 22 and the second lower heat sink 46. As a result, the first semiconductor element 20 and the second semiconductor element 40 are connected in series via the first upper joint portion 22c and the second lower joint portion 46c. The first upper joint portion 22c and the second lower joint portion 46c can be made of, for example, copper. The first upper joint portion 22c and the first upper heat sink 22 may be integrally formed or may be joined to each other. The joining method in this case is not particularly limited, and may be joined by welding, for example. Similarly, the second lower heat radiating plate 46 of the second lower joint portion 46c may be integrally formed or may be joined to each other. The joining method in this case is also not particularly limited, and may be joined by welding, for example.

図２、図３に示すように、第１上側放熱板２２の下面２２ｂには、はんだ層２３を取り囲むようにはんだ吸収溝２２ｄが設けられている。このはんだ吸収溝２２ｄにより、第１導体スペーサ２４と第１上側放熱板２２とをはんだ付けする際に、余剰なはんだは収容され、意図しない範囲まではんだが濡れ広がることを防止することができる。同様に、第２上側放熱板４２の下面４２ｂには、はんだ層４３を取り囲むようにはんだ吸収溝４２ｄが設けられている。このはんだ吸収溝４２ｄにより、第２導体スペーサ４４と第２上側放熱板４２とをはんだ付けする際に、余剰なはんだは収容され、意図しない範囲まで濡れ広がることを防止することができる。一例ではあるが、本実施例の半導体装置１０では、第１上側放熱板２２と第２上側放熱板４２とに、同じ形状の部材が採用されている。 As shown in FIGS. 2 and 3, a solder absorption groove 22d is provided on the lower surface 22b of the first upper heat sink 22 so as to surround the solder layer 23. The solder absorption groove 22d accommodates excess solder when the first conductor spacer 24 and the first upper heat sink 22 are soldered, and can prevent the solder from spreading to an unintended range. Similarly, the lower surface 42b of the second upper heat sink 42 is provided with a solder absorption groove 42d so as to surround the solder layer 43. With the solder absorption groove 42d, when the second conductor spacer 44 and the second upper heat sink 42 are soldered, excess solder is accommodated and can be prevented from spreading to an unintended range. As an example, in the semiconductor device 10 of this embodiment, members having the same shape are adopted for the first upper heat sink 22 and the second upper heat sink 42.

第１上側放熱板２２では、第１上側継手部２２ｃにも、はんだ吸収溝２２ｅが設けられている。はんだ吸収溝２２ｅは、第２下側継手部４６ｃとの間に位置するはんだ層５０を取り囲むように設けられている。このはんだ吸収溝２２ｅにより、第１上側継手部２２ｃと第２下側継手部４６ｃとをはんだ付けする際に、余剰なはんだは収容され、意図しない範囲まではんだが濡れ広がることを防止することができる。 In the first upper heat sink 22, the solder absorption groove 22e is also provided in the first upper joint portion 22c. The solder absorption groove 22e is provided so as to surround the solder layer 50 located between the solder absorption groove 22e and the second lower joint portion 46c. When the first upper joint portion 22c and the second lower joint portion 46c are soldered, the solder absorption groove 22e accommodates excess solder and prevents the solder from spreading to an unintended range. can.

図２、図４、図５に示すように、半導体装置１０の第２上側放熱板４２は、導体で構成された第２上側継手部４２ｃをさらに有しており、Ｎ端子１５にはんだ層６０を介して接続されている。第２上側継手部４２ｃは、例えば銅で構成されることができる。第２上側継手部４２ｃと第２上側放熱板４２とは、一体に形成されている。但し、第２上側継手部４２ｃと第２上側放熱板４２とは、溶接などによって、互いに接合されていてもよい。 As shown in FIGS. 2, 4, and 5, the second upper heat sink 42 of the semiconductor device 10 further has a second upper joint portion 42c composed of a conductor, and the solder layer 60 is attached to the N terminal 15. It is connected via. The second upper joint portion 42c can be made of, for example, copper. The second upper joint portion 42c and the second upper heat sink 42 are integrally formed. However, the second upper joint portion 42c and the second upper heat sink 42 may be joined to each other by welding or the like.

第２上側放熱板４２の第２上側継手部４２ｃには、はんだ吸収溝４２ｅが設けられている。このはんだ吸収溝４２ｅは、Ｎ端子１５との間に位置するはんだ層６０を取り囲むように設けられている。このはんだ吸収溝４２ｅにより、第２上側放熱板４２の第２上側継手部４２ｃとＮ端子１５とをはんだ付けする際に、余剰なはんだは収容され、意図しない範囲まで濡れ広がることを防止することができる。 A solder absorption groove 42e is provided in the second upper joint portion 42c of the second upper heat sink 42. The solder absorption groove 42e is provided so as to surround the solder layer 60 located between the solder absorption groove 42e and the N terminal 15. When the second upper joint portion 42c of the second upper heat sink 42 and the N terminal 15 are soldered by the solder absorption groove 42e, excess solder is accommodated and prevented from spreading to an unintended range. Can be done.

Ｎ端子１５は、はんだ層６０と接触している領域である接合エリアＳ１と、それに隣接する領域である非接合エリアＳ２と、を備える。また、Ｎ端子１５は、Ｚ方向における厚み寸法の大きさが厚みｔ１である厚板区間と、Ｚ方向における厚み寸法の大きさが厚みｔ１よりも小さい厚みｔ２である薄板区間と、で構成される。接合エリアＳ１は、厚板区間と薄板区間との両者に跨って形成されており、非接合エリアＳ２は、薄板区間にのみ形成されている。Ｎ端子１５は、薄板区間であり、接合エリアＳ１と非接合エリアＳ２との境界Ｂにおいて、Ｎ端子１５がＺ方向に屈曲している屈曲部１５ａを有する。屈曲部１５ａは、はんだ吸収溝４２ｅの下側に位置している。 The N terminal 15 includes a joining area S1 which is a region in contact with the solder layer 60, and a non-joining area S2 which is a region adjacent to the joining area S1. Further, the N terminal 15 is composed of a thick plate section having a thickness dimension of t1 in the Z direction and a thin plate section having a thickness t2 having a thickness dimension smaller than the thickness t1 in the Z direction. To. The joining area S1 is formed so as to straddle both the thick plate section and the thin plate section, and the non-joining area S2 is formed only in the thin plate section. The N terminal 15 is a thin plate section, and has a bent portion 15a in which the N terminal 15 is bent in the Z direction at the boundary B between the joining area S1 and the non-joining area S2. The bent portion 15a is located below the solder absorption groove 42e.

上記の構成によると、Ｎ端子１５は、はんだ層６０に接触する接合エリアＳ１とそれに隣接する非接合エリアＳ２との境界Ｂに、屈曲部１５ａを有する。この屈曲部１５ａは、Ｎ端子１５のＺ方向に屈曲しているので、半導体装置１０の製造段階では、流動性を有するはんだ層６０が、屈曲部１５ａを超えて濡れ広がることが抑制される。即ち、Ｎ端子１５の屈曲部１５ａ及び第２上側放熱板４２の第２上側継手部４２ｃによって、製造段階におけるはんだ層６０の濡れ広がりは抑制される。これにより、接合エリアＳ１と非接合エリアＳ２との意図された境界Ｂを越えて、はんだ層５０が過剰に濡れ広がることが防止される。 According to the above configuration, the N terminal 15 has a bent portion 15a at the boundary B between the joining area S1 in contact with the solder layer 60 and the non-joining area S2 adjacent thereto. Since the bent portion 15a is bent in the Z direction of the N terminal 15, it is suppressed that the solder layer 60 having fluidity is wetted and spread beyond the bent portion 15a at the manufacturing stage of the semiconductor device 10. That is, the bending portion 15a of the N terminal 15 and the second upper joint portion 42c of the second upper heat sink 42 suppress the wet spread of the solder layer 60 in the manufacturing stage. This prevents the solder layer 50 from being excessively wetted and spread beyond the intended boundary B between the joining area S1 and the non-joining area S2.

また、屈曲部１５ａは、半導体装置１０の製造段階において曲げ加工などにより、容易に形成することができる。即ち、屈曲部１５ａが形成される位置を変更することで、Ｎ端子１５のうち接合エリアＳ１が占めるエリアを容易に変更することができる。このため、接合エリアＳ１を、第２上側放熱板４２の第２上側継手部４２ｃの形状に対応させ、第２上側放熱板４２とＮ端子１５との間の接合面積を最大化させることができる。例えば、本実施例でが、屈曲部１５ａが第２上側放熱板４２の第２上側継手部４２ｃのはんだ吸収溝４２ｅの下側に位置されるように、屈曲部１５ａの位置を容易に調整することができる。これにより、Ｎ端子１５の屈曲部１５ａ及び第２上側放熱板４２の第２上側継手部４２ｃによって、製造段階におけるはんだ層６０の濡れ広がりはさらに抑制される。 Further, the bent portion 15a can be easily formed by bending or the like at the manufacturing stage of the semiconductor device 10. That is, by changing the position where the bent portion 15a is formed, the area occupied by the joining area S1 in the N terminal 15 can be easily changed. Therefore, the joint area S1 can be made to correspond to the shape of the second upper joint portion 42c of the second upper heat sink 42, and the joint area between the second upper heat sink 42 and the N terminal 15 can be maximized. .. For example, in this embodiment, the position of the bent portion 15a is easily adjusted so that the bent portion 15a is located below the solder absorption groove 42e of the second upper joint portion 42c of the second upper heat sink 42. be able to. As a result, the bending portion 15a of the N terminal 15 and the second upper joint portion 42c of the second upper heat sink 42 further suppress the wet spread of the solder layer 60 in the manufacturing stage.

また、本実施例では、厚み寸法が厚みｔ２の薄板区間に屈曲部１５ａが設けられている。このため、屈曲部１５ａを厚み寸法が厚みｔ１の厚板区間に形成する場合と比較して、屈曲部１５ａをより容易に形成することができる。従って、例えば、はんだ吸収溝４２ｅの位置が変更されても、Ｎ端子１５における屈曲部１５ａの位置を変更後のはんだ吸収溝４２ｅの位置に容易に対応させることができる。従って、第２上側放熱板４２とＮ端子１５との間の接合面積を容易に最大化させることができる。 Further, in this embodiment, the bent portion 15a is provided in the thin plate section having a thickness dimension of t2. Therefore, the bent portion 15a can be formed more easily as compared with the case where the bent portion 15a is formed in a plate section having a thickness dimension of t1. Therefore, for example, even if the position of the solder absorption groove 42e is changed, the position of the bent portion 15a in the N terminal 15 can be easily made to correspond to the position of the solder absorption groove 42e after the change. Therefore, the joint area between the second upper heat sink 42 and the N terminal 15 can be easily maximized.

なお、第２上側放熱板４２とＮ端子１５との間の接合面積が大きいほど、第１半導体素子２０の発熱時に、Ｎ端子１５に生じる熱応力は大きくなる。この点に関して、Ｎ端子１５に屈曲部１５ａが設けられていると、この熱応力を屈曲部１５ａによって緩和することができる。従って、第２上側放熱板４２とＮ端子１５との間の接合面積を最大化させても、半導体装置１０の信頼性が低下することを防止することができる。 The larger the joint area between the second upper heat sink 42 and the N terminal 15, the larger the thermal stress generated in the N terminal 15 when the first semiconductor element 20 generates heat. In this regard, if the N terminal 15 is provided with a bent portion 15a, this thermal stress can be relaxed by the bent portion 15a. Therefore, even if the joint area between the second upper heat sink 42 and the N terminal 15 is maximized, it is possible to prevent the reliability of the semiconductor device 10 from being lowered.

上述したように、Ｎ端子１５における屈曲部１５ａの位置を変更することで、はんだ層６０による接合面積を調整することができる。ここで、はんだ層６０による接合面積を大きくするほど、屈曲部１５ａの位置は、Ｎ端子１５の長手方向に沿って封止体１２の外表面（即ち、封止体１２の外部）に近づいていく。この場合、封止体１２の外表面から、はんだ層６０による接合部分までの距離が短くなるので、外部からＮ端子１５に加えられた振動が、はんだ層６０による接合部分まで伝わりやすくなる。はんだ層６０による接合部分に、外部からの振動が伝わりやすくなると、例えば、はんだ層６０にクラックが生じるといった信頼性の低下が懸念される。しかしながら、Ｎ端子１５に屈曲部１５ａが設けられていると、この振動を屈曲部１５ａによって緩和することができる。従って、Ｎ端子１５に屈曲部１５ａを設けることで、はんだ層６０による接合面積を大きくしながら、半導体装置１０の信頼性が低下することを防止することができる。 As described above, the joining area of the solder layer 60 can be adjusted by changing the position of the bent portion 15a at the N terminal 15. Here, as the bonding area formed by the solder layer 60 is increased, the position of the bent portion 15a approaches the outer surface of the sealing body 12 (that is, the outside of the sealing body 12) along the longitudinal direction of the N terminal 15. go. In this case, since the distance from the outer surface of the sealing body 12 to the joint portion by the solder layer 60 is shortened, the vibration applied to the N terminal 15 from the outside is easily transmitted to the joint portion by the solder layer 60. If vibration from the outside is easily transmitted to the joint portion formed by the solder layer 60, there is a concern that the reliability may be lowered, for example, a crack may occur in the solder layer 60. However, if the N terminal 15 is provided with the bent portion 15a, this vibration can be alleviated by the bent portion 15a. Therefore, by providing the bent portion 15a on the N terminal 15, it is possible to prevent the reliability of the semiconductor device 10 from being lowered while increasing the joining area by the solder layer 60.

（対応関係）
第１下側放熱板２６、はんだ層６０、Ｎ端子１５が、それぞれ、「放熱板」、「接合材」、「電力端子」の一例である。Ｚ方向が、「厚み方向」の一例である。 (Correspondence)
The first lower heat sink 26, the solder layer 60, and the N terminal 15 are examples of a “heat sink”, a “joining material”, and a “power terminal”, respectively. The Z direction is an example of the "thickness direction".

以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。また、本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples exemplified above. Further, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in the present specification or the drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

１０ ：半導体装置
１２ ：封止体
１４ ：Ｐ端子
１５ ：Ｎ端子
１５ａ ：屈曲部
１６ ：Ｏ端子
１８、１９ ：信号端子
２０、４０ ：第１半導体素子
２２ ：第１上側放熱板
２２ｃ ：第１上側継手部
２２ｅ ：第１上側継手部のはんだ吸収溝
２３、２５、２７、４３、４５、４７、５０、６０ ：はんだ層
２４ ：導体スペーサ
２６ ：第１下側放熱板
４０ ：第２半導体素子
４２ ：第２上側放熱板
４２ｃ ：第２上側継手部
４２ｅ ：第２上側継手部のはんだ吸収溝
４６ ：第２下側放熱板
４６ｃ ：第２下側継手部
Ｂ ：境界
Ｓ１ ：接合エリア
Ｓ２ ：非接合エリア 10: Semiconductor device 12: Encapsulant 14: P terminal 15: N terminal 15a: Bent portion 16: O terminal 18, 19: Signal terminal 20, 40: First semiconductor element 22: First upper heat sink 22c: First Upper joint portion 22e: Solder absorption groove 23, 25, 27, 43, 45, 47, 50, 60 of the first upper joint portion: Solder layer 24: Conductor spacer 26: First lower heat sink 40: Second semiconductor element 42: Second upper heat sink 42c: Second upper joint 42e: Solder absorption groove 46 of the second upper joint 46: Second lower heat sink 46c: Second lower joint B: Boundary S1: Joint area S2: Non-junction area

Claims (1)

半導体装置であって、
半導体素子と、
前記半導体素子に接続された放熱板と、
前記放熱板に接合材を介して接合された電力端子と、を備え、
前記電力端子は、前記接合材に接触する接合エリアとそれに隣接する非接合エリアとの境界において、前記電力端子の厚み方向に屈曲する屈曲部が形成されており、
前記電力端子は、前記厚み方向の寸法の大きさが第１の厚みである厚板区間と、前記厚み方向の寸法の大きさが前記第１の厚みよりも小さい第２の厚みである薄板区間と、を有しており、
前記接合エリアは、前記厚板区間と前記薄板区間との両者に跨っており、
前記非接合エリアは、前記薄板区間に位置しており、
前記境界は、前記薄板区間に位置している、
半導体装置。 It ’s a semiconductor device,
With semiconductor devices
A heat sink connected to the semiconductor element and
A power terminal bonded to the heat sink via a bonding material is provided.
The power terminal has a bent portion that bends in the thickness direction of the power terminal at the boundary between the joining area in contact with the joining material and the non-joining area adjacent to the joining area.
The power terminal has a thick plate section in which the size of the dimension in the thickness direction is the first thickness and a thin plate section in which the size of the dimension in the thickness direction is a second thickness smaller than the first thickness. And have,
The joint area straddles both the thick plate section and the thin plate section.
The non-joining area is located in the thin plate section.
The boundary is located in the thin plate section,
Semiconductor device.
JP2018039958A 2018-03-06 2018-03-06 Semiconductor device Active JP7069848B2 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012169044A1 (en) 2011-06-09 2012-12-13 三菱電機株式会社 Semiconductor device
US20140103510A1 (en) 2012-10-17 2014-04-17 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US20150214139A1 (en) 2014-01-30 2015-07-30 Kabushiki Kaisha Toshiba Semiconductor device
JP2017208385A (en) 2016-05-16 2017-11-24 株式会社デンソー Electronic device

Patent Citations (7)

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Publication number Priority date Publication date Assignee Title
WO2012169044A1 (en) 2011-06-09 2012-12-13 三菱電機株式会社 Semiconductor device
US20140103510A1 (en) 2012-10-17 2014-04-17 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
JP2014082384A (en) 2012-10-17 2014-05-08 Renesas Electronics Corp Semiconductor device, and method of manufacturing the same
US20150214139A1 (en) 2014-01-30 2015-07-30 Kabushiki Kaisha Toshiba Semiconductor device
JP2015142072A (en) 2014-01-30 2015-08-03 株式会社東芝 semiconductor device
JP2017208385A (en) 2016-05-16 2017-11-24 株式会社デンソー Electronic device
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