JP7512953B2 - Semiconductor Device - Google Patents

Description

The disclosure in this specification relates to a semiconductor device.

Patent Document 1 discloses a semiconductor device that includes a semiconductor element (semiconductor chip) having main electrodes on both sides, a pair of wiring members (support member and terminal) arranged to sandwich the semiconductor element, and a sintered member that serves as a bonding material. The contents of the prior art documents are incorporated by reference as explanations of the technical elements in this specification.

JP 2021-2563 A

In Patent Document 1, the sintered member joins the main electrode of the semiconductor element to the terminal that constitutes the wiring member. In this configuration, there is a risk that the semiconductor element may be damaged, such as by cracking the main electrode due to concentration of thermal stress. In terms of the above and other aspects not mentioned, further improvements are required in semiconductor devices.

One disclosed objective is to provide a semiconductor device that can suppress element damage.

The semiconductor device disclosed herein comprises:
a semiconductor element (40) having a semiconductor substrate (41), a first main electrode (40D) on a high potential side provided on one surface of the semiconductor substrate, and a second main electrode (40S) on a low potential side provided on a back surface opposite to the one surface in a plate thickness direction;
a first wiring member (50) to which the first main electrode is electrically connected;
a second wiring member (60, 70) disposed so as to sandwich the semiconductor element between itself and the first wiring member in the plate thickness direction, the second wiring member being connected to a second main electrode;
a bonding material (101C, 101) interposed between the second main electrode and the second wiring member and bonding the second main electrode and the second wiring member,
the bonding material has a multilayer structure including a sintered layer (106) having a Young's modulus and/or a yield stress greater than those of the second main electrode, and a fragile layer (107, 108) adjacent to the sintered layer in the plate thickness direction and having a Young's modulus and/or a yield stress smaller than those of the second main electrode ;
The fragile layer (107) is a sintered body made of the same type of particles as the sintered layer, but the particles are spaced farther apart than in the sintered layer.
The bonding material has a three-layer structure having sintered layers on both ends in the plate thickness direction and a brittle layer between the sintered layers .

According to the disclosed semiconductor device, the bonding material that bonds the second main electrode and the second wiring member has a fragile layer as well as a sintered layer. Thermal stress is concentrated in the fragile layer. For example, cracks occur in the fragile layer before cracks occur in the second main electrode. As a result, a semiconductor device that can suppress element damage can be provided.

The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The claims and the reference characters in parentheses in this section are illustrative of the corresponding relationships with the embodiments described below, and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become clearer with reference to the detailed description that follows and the accompanying drawings.

1 is a diagram showing a circuit configuration of a power conversion device to which a semiconductor device according to a first embodiment is applied; FIG. 1 is a perspective view showing a semiconductor device. FIG. 1 is a perspective view showing a semiconductor device. FIG. 1 is a plan view showing a semiconductor device. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 4 . FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 4 . FIG. 9 is an enlarged view of region IX shown in FIG. 8 . FIG. 2 is an exploded perspective view for explaining a semiconductor device. 2 is a plan view showing a state in which a semiconductor element is mounted on a substrate on the drain electrode side. FIG. FIG. 2 is a plan view showing a circuit pattern on the substrate on the drain electrode side. FIG. 2 is a plan view showing a circuit pattern of the substrate on the source electrode side. FIG. 2 is a diagram showing the arrangement of a circuit pattern, a semiconductor element, and terminals on the drain electrode side. FIG. 2 is a diagram showing the arrangement of a circuit pattern, a semiconductor element, and a terminal on the source electrode side. FIG. 13 is a plan view showing a current loop of a reference example. FIG. 2 is a plan view showing a current loop. FIG. 2 is a side view showing a current loop. FIG. 13 is a diagram showing current density in a reference example. FIG. 4 is a diagram showing current density for this embodiment. FIG. FIG. FIG. 13 is a plan view showing a circuit pattern on a substrate on the drain electrode side in a modified example. FIG. 13 is a plan view showing a circuit pattern on a substrate on the source electrode side in a modified example. FIG. 11 is a cross-sectional view showing a semiconductor device according to a second embodiment. 11A and 11B are diagrams for explaining the effect of inductance Ls. 11A and 11B are diagrams for explaining the effect of inductance Ls. FIG. 2 is a plan view showing a circuit pattern of the substrate on the source electrode side. FIG. FIG. 4 is a cross-sectional view showing an arm connection portion. FIG. 13 is a plan view showing a modified example of the substrate on the source electrode side. 2 is a plan view showing a state in which a semiconductor element is mounted on a substrate on the drain electrode side. FIG. FIG. FIG. 11 is a plan view showing a modified example of the substrate on the drain electrode side; FIG. 13 is a cross-sectional view showing a modified example of the arm connection portion. FIG. 13 is a cross-sectional view showing a modified example of the arm connection portion. FIG. FIG. 13 is a plan view showing a circuit pattern on a substrate on the source electrode side in a modified example. FIG. 1 is a cross-sectional view showing warpage at high temperatures. FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment. FIG. 2 is a cross-sectional view showing a semiconductor device at room temperature. FIG. 1 is a cross-sectional view showing a semiconductor device at a high temperature. FIG. 11 is a diagram showing the relationship between the ratio of thicknesses T1 and T2 and the amount of warping. FIG. 11 is a cross-sectional view showing a modified example. FIG. 11 is a cross-sectional view showing a modified example. FIG. 13 is an enlarged plan view of the periphery of a signal terminal in a semiconductor device according to a fourth embodiment. A cross-sectional view taken along line XLVII-XLVII in Figure 46. FIG. 1 is a diagram illustrating wire bonding. FIG. 11 is a cross-sectional view showing a modified example. FIG. 11 is a cross-sectional view showing a modified example. FIG. 11 is a cross-sectional view showing a modified example. FIG. 11 is a cross-sectional view showing a modified example. FIG. FIG. FIG. 54 is a cross-sectional view taken along line LV-LV in FIG. 53. FIG. 11 is a cross-sectional view showing a modified example. FIG. 13 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. FIG. 58 is a plan view seen from the LVIII direction shown in FIG. 57. FIG. 58 is an enlarged view of the area LVIX shown in FIG. 57. This is a diagram in which the bonding material is omitted, as compared to FIG. 59 . FIG. This is a plan view seen from the LXII direction shown in Figure 61. FIG. FIG. 11 is a cross-sectional view showing a modified example. FIG. 65 is an enlarged view of area LXV shown in FIG. 64. FIG. 11 is a cross-sectional view showing a modified example. FIG. 67 is an enlarged view of area LXVII shown in FIG. 66. FIG. 11 is a cross-sectional view showing a modified example. FIG. 13 is a cross-sectional view showing a semiconductor device according to a sixth embodiment. FIG. 4 is a diagram showing the relationship between the glass transition point and the linear expansion coefficient for the sealing body and the insulating base material. FIG. 13 is a diagram showing warpage in a reference example. FIG. 13 is a diagram showing warpage at high temperatures. FIG. 13 is a cross-sectional view showing a semiconductor device according to a seventh embodiment. FIG. 74 is an enlarged view of area LXXIV of FIG. 73. 1A to 1C are diagrams illustrating a method for forming a roughened portion. FIG. 11 is a cross-sectional view showing a modified example. FIG. 11 is a cross-sectional view showing a modified example. FIG. 11 is a cross-sectional view showing a modified example. FIG. 13 is a cross-sectional view showing a semiconductor device according to an eighth embodiment. FIG. 80 is an enlarged view of area LXXX in FIG. 79. FIG. 13 is a diagram showing the relationship between the interval, thickness and inductance. FIG. 13 is a diagram showing a simulation result in the case where the interval is smaller than the thickness. FIG. 13 is a diagram showing a simulation result in the case where the interval is greater than the thickness. FIG. 13 is a cross-sectional view showing a semiconductor device according to a ninth embodiment. FIG. FIG. 85 is an enlarged view of area LXXXVI of FIG. 84. FIG. 1 shows dimensions and angles. FIG. FIG. 23 is a cross-sectional view showing a semiconductor device according to a tenth embodiment. FIG. 2 is a plan view showing a semiconductor element. FIG. 89 is an enlarged view of region XCI in FIG. 89. FIG. 4 is a cross-sectional view showing the arrangement of sintered members. 4A to 4C are cross-sectional views showing a joining method. 13 is a diagram showing the relationship between the distance between the inner circumferential surface of the protective film and the sintered member and the strain amplitude of the base electrode. FIG. FIG. 4 is a cross-sectional view showing the arrangement of solder as a bonding material. FIG. 23 is a cross-sectional view showing a semiconductor device according to an eleventh embodiment. This is an enlarged view of area XCVII in Figure 96. 2 is a plan view showing the arrangement of a semiconductor element, a sintered member, and a rough oxide film. FIG. FIG. 98 is an enlarged view of area XCIX in FIG. 97. FIG. 11 is a cross-sectional view showing a modified example. 2 is a plan view showing the arrangement of a semiconductor element, a sintered member, and a rough oxide film. FIG. FIG. 11 is a cross-sectional view showing a modified example. 2 is a plan view showing the arrangement of a semiconductor element, a sintered member, and a rough oxide film. FIG. FIG. 11 is a cross-sectional view showing a modified example. FIG. 23 is a cross-sectional view showing a semiconductor device according to a twelfth embodiment. FIG. 106 is an enlarged view of area CVI in FIG. 105. FIG. 4 is a diagram showing the relationship between the Young's modulus and the yield stress of the base electrode, the sintered layer, and the brittle layer. FIG. 11 is a cross-sectional view showing a modified example. FIG. 11 is a cross-sectional view showing a modified example. FIG. 11 is a cross-sectional view showing a modified example. 23 is a diagram showing a circuit configuration of a power conversion device to which a semiconductor device according to a thirteenth embodiment is applied. FIG. 1 is a perspective view showing a semiconductor device. FIG. 1 is a plan view showing a semiconductor device. 2 is a plan view showing a state in which a semiconductor element is mounted on a substrate on the drain electrode side. FIG. FIG. 2 is a plan view showing a circuit pattern on the substrate on the drain electrode side. FIG. 2 is a plan view showing a circuit pattern of the substrate on the source electrode side. A cross-sectional view taken along line CXVII-CXVII in Figure 113. A cross-sectional view taken along line CXVIII-CXVIII in Figure 113. FIG. 114 is a cross-sectional view taken along line CXIX-CXIX in FIG. 113. This is a cross-sectional view taken along line CXX-CXX in Figure 113. FIG. 121 is an enlarged view of area CXXI of FIG. 120.

Below, several embodiments will be described with reference to the drawings. Note that in each embodiment, corresponding components are given the same reference numerals, and duplicated descriptions may be omitted. When only a portion of the configuration is described in each embodiment, the configuration of the other embodiment described above can be applied to the other portions of the configuration. In addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations of several embodiments can be partially combined together even if not explicitly stated, as long as there is no particular problem with the combination.

The semiconductor device of this embodiment is applied, for example, to a power conversion device of a moving body that uses a rotating electric machine as a drive source. The moving body is, for example, an electric vehicle such as an electric vehicle (EV), a hybrid vehicle (HV), or a plug-in hybrid vehicle (PHV), an aircraft such as a drone, a ship, a construction machine, or an agricultural machine. An example of application to a vehicle is described below.

First Embodiment
First, a schematic configuration of a vehicle drive system 1 will be described with reference to FIG.

<Vehicle drive system>
As shown in FIG. 1 , a vehicle drive system 1 includes a DC power supply 2 , a motor generator 3 , and a power conversion device 4 .

The DC power source 2 is a DC voltage source composed of a chargeable and dischargeable secondary battery. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, i.e., an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion device 4 converts power between the DC power source 2 and the motor generator 3.

<Power conversion device>
Next, a circuit configuration of the power conversion device 4 will be described with reference to Fig. 1. The power conversion device 4 includes a power conversion circuit. The power conversion device 4 of this embodiment includes a smoothing capacitor 5 and an inverter 6 which is a power conversion circuit.

The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to the P line 7, which is the high-potential power supply line, and the N line 8, which is the low-potential power supply line. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative electrode of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

The inverter 6 is a DC-AC conversion circuit. In accordance with switching control by a control circuit (not shown), the inverter 6 converts DC voltage into three-phase AC voltage and outputs it to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to rotational force from the wheels into DC voltage in accordance with switching control by the control circuit and outputs it to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power source 2 and the motor generator 3.

The inverter 6 is configured with upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. Each of the upper and lower arm circuits 9 has an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. The inverter 6 has six arms. Each arm is configured with a switching element. At least a portion of each of the P line 7, the N line 8, and the output line 10 is configured with a conductive member such as a bus bar.

In this embodiment, an n-channel MOSFET 11 is used as the switching element that constitutes each arm. There is no particular limit to the number of switching elements that constitute each arm. There may be one or more. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

As an example, in this embodiment, each arm has two MOSFETs 11. The two MOSFETs 11 constituting one arm are connected in parallel. In the upper arm 9H, the drains of the two MOSFETs 11 connected in parallel are connected to the P line 7. In the lower arm 9L, the sources of the two MOSFETs 11 connected in parallel are connected to the N line 8. The sources of the two MOSFETs 11 connected in parallel in the upper arm 9H and the drains of the two MOSFETs 11 connected in parallel in the lower arm 9L are connected to each other. The two MOSFETs 11 connected in parallel are turned on and off at the same time by a common gate drive signal (drive voltage).

A freewheeling diode 12 is connected in inverse parallel to each MOSFET 11. The diode 12 may be a parasitic diode (body diode) of the MOSFET 11, or may be provided separately from the parasitic diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain. The upper and lower arm circuits 9 for one phase are provided by one semiconductor device 20. Details of the semiconductor device 20 will be described later.

The power conversion device 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage into a DC voltage of a different value. The converter is provided between the DC power source 2 and the smoothing capacitor 5. The converter is configured to include, for example, a reactor and the above-mentioned upper and lower arm circuits 9. With this configuration, voltage can be increased or decreased. The power conversion device 4 may also include a filter capacitor that removes power supply noise from the DC power source 2. The filter capacitor is provided between the DC power source 2 and the converter.

The power conversion device 4 may include a drive circuit for switching elements constituting the inverter 6, etc. The drive circuit supplies a drive voltage to the gate of the MOSFET 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11, i.e., turns it on and off, by applying the drive voltage. The drive circuit is sometimes called a driver.

The power conversion device 4 may include a control circuit for the switching element. The control circuit generates a drive command for operating the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured to include, for example, a processor and a memory. PWM is an abbreviation for Pulse Width Modulation.

<Semiconductor Device>
Next, the semiconductor device will be described with reference to Figs. 2 to 13. Fig. 2 is a perspective view of the semiconductor device 20. Fig. 3 is a perspective view of the semiconductor device 20 similar to Fig. 2. Fig. 3 is a see-through view showing the internal structure. Fig. 4 is a plan view of the semiconductor device 20. Fig. 4 is a see-through view showing the internal structure. Fig. 5 is a cross-sectional view taken along line VV in Fig. 4. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 4. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 4. Fig. 8 is a cross-sectional view taken along line VIII-VIII in Fig. 4. Fig. 9 is an enlarged view of region IX indicated by a dashed line in Fig. 8.

Figure 10 is an exploded perspective view for explaining the semiconductor device 20. For convenience, a lead frame 94 is shown in Figure 10. Figure 11 is a plan view showing a state in which a semiconductor element 40 is mounted on a substrate 50. Figure 12 is a plan view showing the circuit pattern of a surface metal body 52 on the substrate 50. Figure 13 is a plan view showing the circuit pattern of a surface metal body 62 on the substrate 60.

In the following, the thickness direction of the semiconductor element (semiconductor substrate) is referred to as the Z direction. The direction perpendicular to the Z direction, in which the semiconductor elements constituting the upper arm 9H and the semiconductor elements constituting the lower arm 9L are arranged, is referred to as the Y direction. The direction perpendicular to both the Z direction and the Y direction is referred to as the X direction. Unless otherwise specified, the shape viewed from the Z direction, in other words the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. The planar view from the Z direction is sometimes simply referred to as the planar view. Furthermore, the arrangement is not limited to the mounting surface, and may be referred to as an arrangement when there is an overlapping positional relationship in a planar view.

As shown in Figures 2 to 13, the semiconductor device 20 constitutes one of the upper and lower arm circuits 9 described above, i.e., one phase of the upper and lower arm circuit 9. The semiconductor device 20 includes a sealing body 30, a semiconductor element 40, substrates 50 and 60, a conductive spacer 70, an arm connection portion 80, and an external connection terminal 90.

The sealing body 30 seals a portion of the other elements constituting the semiconductor device 20. The remaining portions of the other elements are exposed to the outside of the sealing body 30. The sealing body 30 is made of, for example, a resin. One example of a resin is an epoxy resin. The sealing body 30 is made of a resin and is molded, for example, by a transfer molding method. Such a sealing body 30 may be called a sealing resin body, a molded resin, or a resin molded body. The sealing body 30 may be formed, for example, using a gel. The gel is filled (placed) in the opposing regions of the pair of substrates 50, 60.

As shown in Figures 2 to 4, the sealing body 30 has a generally rectangular shape in plan view. The sealing body 30 has one surface 30a as a surface forming an outer shell, and a back surface 30b that is the surface opposite to the one surface 30a in the Z direction. The one surface 30a and the back surface 30b are, for example, flat surfaces. The sealing body 30 also has side surfaces that connect the one surface 30a and the back surface 30b. The side surfaces include two side surfaces 30c, 30d from which the external connection terminals 90 protrude. The side surface 30d is the surface opposite to the side surface 30c in the X direction.

The semiconductor element 40 is formed by forming a switching element on a semiconductor substrate made of silicon (Si), a wide band gap semiconductor having a wider band gap than silicon, or the like. Examples of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), _gallium oxide ( _Ga2O3 ), and diamond. The semiconductor element 40 is sometimes called a power element or a semiconductor chip.

The semiconductor element 40 of this embodiment is formed by forming the above-mentioned n-channel MOSFET 11 on a semiconductor substrate made of SiC. The MOSFET 11 has a vertical structure so that the main current flows in the thickness direction of the semiconductor element 40 (semiconductor substrate), i.e., in the Z direction. The semiconductor element 40 has main electrodes of the switching element on both sides in its thickness direction, i.e., in the Z direction. Specifically, as main electrodes, it has a drain electrode 40D on one side and a source electrode 40S on the back side, which is the side opposite to the one side in the Z direction.

When the diode 12 is a parasitic diode, the source electrode 40S also serves as the anode electrode, and the drain electrode 40D also serves as the cathode electrode. The diode 12 may be configured on a chip separate from the MOSFET 11. The drain electrode 40D is the main electrode on the high potential side (first main electrode), and the source electrode 40S is the main electrode on the low potential side (second main electrode). In the following, the drain electrode 40D and the source electrode 40S may be referred to as the main electrodes 40D and 40S.

The semiconductor element 40 has a generally rectangular shape in plan view. As shown in FIG. 11, the semiconductor element 40 has a pad 40P formed on the back surface at a position different from the source electrode 40S. The source electrode 40S and the pad 40P are exposed from a protective film (not shown) formed on the back surface of the semiconductor substrate. The drain electrode 40D is formed on almost the entire surface. The source electrode 40S is formed on a portion of the back surface of the semiconductor element 40. In a plan view, the drain electrode 40D has a larger area than the source electrode 40S.

The pad 40P is an electrode for signals. The pad 40P is electrically isolated from the source electrode 40S. The pad 40P is formed at the end opposite the formation area of the source electrode 40S in the Y direction. The pad 40P includes a pad for a gate electrode.

The semiconductor device 20 includes a plurality of semiconductor elements 40 having the above-described configuration. The configuration of each semiconductor element 40 is common to each other. The plurality of semiconductor elements 40 includes a semiconductor element 40H constituting the upper arm 9H and a semiconductor element 40L constituting the lower arm 9L. The semiconductor element 40H is sometimes referred to as an upper arm element, and the semiconductor element 40L is sometimes referred to as a lower arm element. Each of the semiconductor elements 40H and 40L is an arm element constituting one arm. The semiconductor device 20 of this embodiment includes two semiconductor elements 40H and two semiconductor elements 40L. The two semiconductor elements 40H are aligned in the X direction. Similarly, the two semiconductor elements 40L are aligned in the X direction. The semiconductor elements 40H and 40L are aligned in the Y direction. The Y direction is a first direction perpendicular to the Z direction, which is the plate thickness direction of the semiconductor element 40. The X direction is a second direction perpendicular to the Z direction and the first direction (Y direction). The semiconductor device 20 has two rows of semiconductor elements 40H and 40L arranged along the Y direction.

The semiconductor elements 40 are arranged at approximately the same positions as each other in the Z direction. The drain electrode 40D of each semiconductor element 40 faces the substrate 50. The source electrode 40S of each semiconductor element 40 faces the substrate 60.

The substrates 50 and 60 are arranged in the Z direction to sandwich the multiple semiconductor elements 40. The substrates 50 and 60 are arranged so that at least a portion of each substrate faces each other in the Z direction. The substrates 50 and 60 contain all of the multiple semiconductor elements 40 (40H, 40L) in a plan view.

The substrate 50 is disposed on the drain electrode 40D side of the semiconductor element 40. The substrate 60 is disposed on the source electrode 40S side of the semiconductor element 40. The substrate 50 is electrically connected to the drain electrode 40D as described below, and provides a wiring function. Similarly, the substrate 60 is electrically connected to the source electrode 40S, and provides a wiring function. For this reason, the substrates 50 and 60 are sometimes referred to as wiring substrates. The substrate 50 is sometimes referred to as a drain substrate, and the substrate 60 is sometimes referred to as a source substrate. The substrates 50 and 60 provide a heat dissipation function for dissipating heat generated by the semiconductor element 40. For this reason, the substrates 50 and 60 are sometimes referred to as heat dissipation members. Of the pair of substrates 50 and 60 that sandwich the semiconductor element 40 in the Z direction, the substrate 50 is the first substrate, and the substrate 60 is the second substrate.

The substrate 50 has an opposing surface 50a facing the semiconductor element 40 and a back surface 50b opposite the opposing surface 50a. The substrate 50 includes an insulating substrate 51, a front metal body 52, and a back metal body 53. The substrate 50 is a substrate in which the insulating substrate 51 and the metal bodies 52 and 53 are laminated. The substrate 60 has an opposing surface 60a facing the semiconductor element 40 and a back surface 60b opposite the opposing surface 60a. The substrate 60 includes an insulating substrate 61, a front metal body 62, and a back metal body 63. The substrate 60 is a substrate in which the insulating substrate 61 and the metal bodies 62 and 63 are laminated. In the substrate 50, which is the first substrate, the insulating substrate 51 is the first insulating substrate, the front metal body 52 is the first front metal body, and the back metal body 53 is the first back metal body. In the substrate 60, which is the second substrate, the insulating substrate 61 is the second insulating substrate, the front surface metal body 62 is the second front surface metal body, and the rear surface metal body 63 is the second rear surface metal body. Hereinafter, the front surface metal bodies 52, 62 and the rear surface metal bodies 53, 63 may be simply referred to as metal bodies 52, 53, 62, 63.

The insulating substrate 51 electrically separates the front metal body 52 from the back metal body 53. Similarly, the insulating substrate 61 electrically separates the front metal body 62 from the back metal body 63. The insulating substrates 51 and 61 are sometimes referred to as insulating layers. The material of the insulating substrates 51 and 61 is resin or ceramic, which is an inorganic material. For example, epoxy resin or polyimide resin can be used as the resin. For example, Al ₂ O ₃ (alumina) or Si ₃ N ₄ (silicon nitride) can be used as the ceramic. When the insulating substrates 51 and 61 are resin, the substrates 50 and 60 are sometimes referred to as metal-resin substrates. When the insulating substrates 51 and 61 are ceramic, the substrates 50 and 60 are sometimes referred to as metal-ceramic substrates.

In the case of the insulating base material 51, 61 using a resin material, an inorganic filler (inorganic filling material) may be contained in the resin in order to improve heat dissipation and insulation properties. The linear expansion coefficient may be adjusted by adding a filler. As the filler, for example, Al ₂ O ₃ , SiO ₂ (silicon dioxide), AlN (aluminum nitride), BN (boron nitride), etc. may be used. The insulating base material 51, 61 may contain only one type of filler or may contain multiple types of fillers.

Considering heat dissipation and insulation, in the case of a resin-based insulating substrate, the thickness of each of the insulating substrates 51 and 61, that is, the length in the Z direction, is preferably about 50 μm to 300 μm. In the case of a ceramic-based insulating substrate, the thickness of the insulating substrates 51 and 61 is preferably about 200 μm to 500 μm. In the Z direction, the front surface of the insulating substrates 51 and 61 is the inner surface, that is, the surface on the semiconductor element 40 side, and the back surface, which is the surface opposite the front surface in the Z direction, is the outer surface. The insulating substrates 51 and 61 may have the same material composition or may be different from each other. In this embodiment, the resin-based insulating substrates 51 and 61 are used, and the material composition is the same. The linear expansion coefficient of the insulating substrates 51 and 61 is adjusted to approximately the same value as that of the sealing body 30 by adding a filler to the resin. By adding filler to the resin, the linear expansion coefficient of the insulating substrates 51, 61 and the sealing body 30 is close to that of the metal (Cu) that constitutes the metal bodies 52, 53, 62, and 63.

The metal bodies 52, 53, 62, and 63 are provided, for example, as metal plates or metal foils. The metal bodies 52, 53, 62, and 63 are formed from metals with good electrical conductivity and thermal conductivity, such as Cu and Al. The thickness of each of the metal bodies 52, 53, 62, and 63 is, for example, about 0.1 mm to 3 mm. The front metal body 52 is disposed on the front surface of the insulating substrate 51 in the Z direction. The back metal body 53 is disposed on the back surface of the insulating substrate 51. Similarly, the front metal body 62 is disposed on the front surface of the insulating substrate 61 in the Z direction. The back metal body 63 is disposed on the back surface of the insulating substrate 61. The insulating substrates 51 and 61 are opposed to the semiconductor element 40 in the Z direction. As shown in Figures 5 to 9, in this embodiment, the front metal body 52 is thicker than the back metal body 53. The front metal body 62 is thicker than the back metal body 63. The front surface metal body 52 on the drain electrode 40D side is thicker than the front surface metal body 62 on the source electrode 40S side. Alternatively, the back surface metal bodies 53, 63 may be made thicker than the corresponding front surface metal bodies 52, 62. The front surface metal body 52 and the back surface metal body 53 may be made approximately equal in thickness, or the front surface metal body 62 and the back surface metal body 63 may be made approximately equal in thickness.

The surface metal bodies 52, 62 are patterned. The surface metal bodies 52, 62 provide wiring, i.e., circuits. For this reason, the surface metal bodies 52, 62 may be referred to as a circuit pattern, wiring layer, or circuit conductor. The surface metal bodies 52, 62 may have a plating film of Ni-based or Au, etc., on the metal surface. Hereinafter, the pattern of the surface metal bodies 52, 62 may be referred to as a circuit pattern. The surface metal body 52 and the non-placement area of the surface metal body 52 on the surface of the insulating base material 51 form the opposing surface 50a of the substrate 50. Similarly, the surface metal body 62 and the non-placement area of the surface metal body 62 on the surface of the insulating base material 61 form the opposing surface 60a of the substrate 60.

For example, the front metal bodies 52, 62 may be prepared by patterning into a predetermined shape by pressing or etching, and then attached to a two-layer laminate of the insulating base material 51, 61 and the back metal body 53, 63 to form the substrates 50, 60. After forming a three-layer laminate of the front metal bodies 52, 62, the insulating base material 51, 61, and the back metal body 53, 63, the front metal bodies 52, 62 may be patterned by cutting or etching.

As shown in FIG. 11, the surface metal body 52 has a P wiring 54 and a relay wiring 55. The P wiring 54 and the relay wiring 55 are electrically separated by a predetermined distance (gap). This gap is filled with the sealing body 30.

The P wiring 54 is connected to the P terminal 91P and the drain electrode 40D of the semiconductor element 40H, which will be described later. The P wiring 54 electrically connects the P terminal 91P and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 is sometimes referred to as a positive wiring or a high potential power supply wiring. The relay wiring 55 is connected to the drain electrode 40D of the semiconductor element 40L, the arm connection part 80, and the output terminal 92. The relay wiring 55 electrically connects the arm connection part 80 and the drain electrode 40D of the semiconductor element 40L. The relay wiring 55 electrically connects the source electrode 40S of the semiconductor element 40H and the drain electrode of the semiconductor element 40L to the output terminal 92. In the surface metal body 52 (first surface metal body), the P wiring 54 is the first power supply wiring, and the relay wiring 55 is the first relay wiring.

The P wiring 54 and the relay wiring 55 are arranged side by side in the Y direction. In the Y direction, the P wiring 54 is arranged on the power supply terminal 91 side, and the relay wiring 55 is arranged on the output terminal 92 side. In other words, the P wiring 54 is arranged close to the side surface 30c of the sealing body 30, and the relay wiring 55 is arranged close to the side surface 30d.

The P wiring 54 has a notch 540. The notch 540 opens on one of the four sides of a substantially rectangular shape in plan, with the X direction as the longitudinal direction. The notch 540 is provided on the side facing the side surface 30c, approximately in the center in the X direction. The P wiring 54 has a base 541 and a pair of extensions 542. The base 541 and the pair of extensions 542 define the notch 540. The P wiring 54 has a substantially U-shape (concave shape) in plan.

The base 541 is a portion closer to the relay wiring 55 than the notch 540 and the extension 542, and has a generally rectangular shape in plan view. The base 541 overlaps the semiconductor element 40H in plan view. In other words, the semiconductor element 40H is disposed on the base 541. The drain electrode 40D of the semiconductor element 40H is connected to the base 541.

The two extensions 542 extend from the base 541 in the same direction, specifically in the Y direction, toward the side surface 30c of the sealing body 30. One of the extensions 542 is connected to the vicinity of one end of the base 541 in the X direction, and the other is connected to the vicinity of the other end of the base 541. Both ends of the U-shape of the P wiring 54, that is, the ends of the two extensions 542 opposite the base 541, are at approximately the same position in the Y direction. The pair of extensions 542 sandwich the notch 540 in the X direction. The length of the base 541 in the Y direction is longer than the depth of the notch 540 and the extensions 542.

The relay wiring 55 also has a notch 550. The notch 550 opens on one of the four sides of the approximately rectangular shape in plan view. The notch 550 is provided in approximately the center in the X direction on the side opposite the side surface 30d. In other words, the surface metal body 52 has a notch 540 provided on one of the ends in the Y direction, and a notch 550 provided on the other end.

The relay wiring 55 has a base 551 and a pair of extensions 552. The base 551 and the pair of extensions 552 define a notch 550. The relay wiring 55 has a generally U-shape (concave shape) in plan. The base 551 is a portion closer to the P wiring 54 than the notch 550 and the extensions 552, and has a generally rectangular shape in plan. The base 551 overlaps the semiconductor element 40L in a planar view. That is, the semiconductor element 40L is disposed on the base 551. The drain electrode 40D of the semiconductor element 40L is connected to the base 551.

The two extensions 552 extend from the base 551 in the same direction, specifically the Y direction, toward the side surface 30d of the sealing body 30. One of the extensions 552 is connected to the vicinity of one end of the base 551 in the X direction, and the other is connected to the vicinity of the other end of the base 551. Both ends of the U-shape of the relay wiring 55, that is, the ends of the two extensions 552 opposite the base 551, are at approximately the same position in the Y direction. The pair of extensions 552 sandwich the notch 550 in the X direction. The length of the base 551 in the Y direction is longer than the depth of the notch 550 and the extensions 552.

On the other hand, the surface metal body 62 has an N wiring 64 and a relay wiring 65, as shown in Figures 10 and 13. The N wiring 64 and the relay wiring 65 are electrically separated by a predetermined distance (gap). This gap is filled with the sealing body 30.

The N wiring 64 is connected to the N terminal 91N and the source electrode 40S of the semiconductor element 40L, which will be described later. The N wiring 64 electrically connects the N terminal 91N and the source electrode 40S of the semiconductor element 40L. The N wiring 64 is sometimes referred to as the N wiring. The relay wiring 65 is connected to the source electrode 40S of the semiconductor element 40H and the arm connection part 80. The relay wiring 65 electrically connects the source electrode 40S of the semiconductor element 40H and the arm connection part 80. In the surface metal body 62 (second surface metal body), the N wiring 64 is the second power supply wiring, and the relay wiring 65 is the second relay wiring.

The N wiring 64 has a base 640 and a pair of extensions 641. The N wiring 64 has a generally U-shape in plan view. The base 640 is arranged alongside the relay wiring 65 in the Y direction. The base 640 is arranged on the side surface 30d in the Y direction. The base 640 has a generally rectangular shape in plan view with the X direction as its longitudinal direction. As shown in FIG. 15, the base 640 overlaps the semiconductor element 40L in plan view. That is, the semiconductor element 40L is arranged on the base 640. The source electrode 40S of the semiconductor element 40L is connected to the base 640.

The two extensions 641 extend from the base 640 in the same direction, specifically the Y direction, toward the side surface 30c of the sealing body 30. One of the extensions 641 is connected to the vicinity of one end of the base 640 in the X direction, and the other is connected to the vicinity of the other end of the base 640. Both ends of the U-shape of the N wiring 64, that is, the ends of the two extensions 641 opposite the base 640, are at approximately the same position in the Y direction.

The pair of extensions 641 form both ends of the surface metal body 62 in the X direction. The pair of extensions 641 are disposed near the ends of the substrate 60. In a plan view, a portion of each of the pair of extensions 641 overlaps the P wiring 54. The length of the extensions 641 in the Y direction is longer than that of the base 640. The N wiring 64 also has a notch 642. The notch 642 opens on one of the four sides of a substantially rectangular shape in plan view with the Y direction as the longitudinal direction. The notch 642 is provided on the side facing the side surface 30c, approximately in the center in the X direction. The base 640 and the pair of extensions 641 define the notch 642.

As described above, the relay wiring 65 is arranged in line with the N wiring 64, specifically the base 640, in the Y direction. In the Y direction, the relay wiring 65 is arranged close to the side surface 30c of the sealing body 30, and the base 640 is arranged close to the side surface 30d. The relay wiring 65 is arranged between a pair of extension parts 641 in the X direction. The relay wiring 65 is sandwiched between the pair of extension parts 641. The relay wiring 65 is arranged in the cutout 642. The relay wiring 65 is arranged with a predetermined interval (gap) between it and the N wiring 64. In a plan view, a part of the relay wiring 65 overlaps with the P wiring 54, and another part overlaps with the relay wiring 55.

As shown in FIG. 15, the relay wiring 65 overlaps the semiconductor element 40H in a plan view. In other words, the semiconductor element 40H is disposed on the relay wiring 65. The source electrode 40S of the semiconductor element 40H is connected to the relay wiring 65. A more detailed example of the circuit pattern of the surface metal body 62 will be described later.

The back metal body 53, 63 is electrically isolated from the circuit including the semiconductor element 40 by the insulating substrate 51, 61. The back metal body 53, 63 is sometimes called a metal base substrate. The heat generated by the semiconductor element 40 is transferred to the back metal body 53, 63 through the front metal body 52, 62 and the insulating substrate 51, 61. The back metal body 53, 63 provides a heat dissipation function. The back metal body 53, 63 of this embodiment has a substantially rectangular shape in plan view, and its outer contour almost coincides with the outer contour of the front metal body 52, 62. The back metal body 53, 63 is a so-called solid conductor arranged over almost the entire back surface of the insulating substrate 51, 61. As described above, the linear expansion coefficient of the insulating substrate 51, 61 is adjusted by adding a filler, so that warping can be suppressed even if the patterns are changed on the front and back. Of course, the back metal bodies 53, 63 may be patterned so that they coincide with the front metal bodies 52, 62 in a plan view.

The back metal bodies 53, 63 in this embodiment are disposed over almost the entire back surface of the corresponding insulating substrate 51, 61. To further enhance the heat dissipation effect, at least one of the back metal bodies 53, 63 may be exposed from the sealing body 30. In this embodiment, the back metal body 53 is exposed from one surface 30a of the sealing body 30, and the back metal body 63 is exposed from the back surface 30b. The exposed surface of the back metal body 53 is approximately flush with the one surface 30a. The exposed surface of the back metal body 63 is approximately flush with the back surface 30b. The back metal bodies 53, 63 form the back surfaces 50b, 60b of the substrates 50, 60.

The conductive spacer 70 provides a spacer function that ensures a predetermined distance between the semiconductor element 40 and the substrate 60. For example, the conductive spacer 70 ensures a height for electrically connecting the corresponding signal terminal 93 to the pad 40P of the semiconductor element 40. The conductive spacer 70 is located midway along the electrical and thermal conduction paths between the source electrode 40S of the semiconductor element 40 and the substrate 60, and provides wiring and heat dissipation functions. The conductive spacer 70 contains a metal material with good electrical and thermal conductivity, such as Cu. The conductive spacer 70 may have a plating film on its surface. The conductive spacer 70 is a columnar body that is approximately rectangular in plan view and has approximately the same size as the source electrode 40S in a plan view.

The conductive spacers 70 may be referred to as terminals, terminal blocks, or metal blocks. The semiconductor device 20 includes the same number of conductive spacers 70 as the semiconductor elements 40. Specifically, the semiconductor device 20 includes four conductive spacers 70. The conductive spacers 70 are individually connected to the semiconductor elements 40.

The arm connection part 80 electrically connects the relay wiring 55, 65. That is, the arm connection part 80 electrically connects the upper arm 9H and the lower arm 9L. The arm connection part 80 is provided between the semiconductor element 40H and the semiconductor element 40L in the Y direction. The arm connection part 80 is provided in the overlapping area of the relay wiring 55 and the relay wiring 65 in a plan view. The arm connection part 80 in this embodiment is configured with a joint part 81 and a bonding material 103 described later.

The joint part 81 is a metal columnar body provided separately from the surface metal bodies 52, 62. Such a joint part 81 is sometimes called a joint terminal. In the Z direction, a bonding material 103 is interposed between one end of the joint part 81 and the relay wiring 55, and a bonding material 103 is interposed between the other end and the relay wiring 65.

Alternatively, the joint portion 81 may be integrally connected to at least one of the surface metal bodies 52, 62. In other words, the joint portion 81 may be provided integrally with the surface metal bodies 52, 62 as part of the substrates 50, 60. The arm connection portion 80 may not include the joint portion 81. In other words, the arm connection portion 80 may include only the bonding material 103.

The external connection terminal 90 is a terminal for electrically connecting the semiconductor device 20 to an external device. The external connection terminal 90 is formed using a metal material with good conductivity such as copper. The external connection terminal 90 is, for example, a plate material. The external connection terminal 90 is sometimes called a lead. The external connection terminal 90 includes a power terminal 91, an output terminal 92, and a signal terminal 93. The power terminal 91 includes a P terminal 91P and an N terminal 91N. The P terminal 91P, the N terminal 91N, and the output terminal 92 are main terminals electrically connected to the main electrodes of the semiconductor element 40. The signal terminal 93 includes a signal terminal 93H on the upper arm 9H side and a signal terminal 93L on the lower arm 9L side.

The power supply terminal 91 is an external connection terminal 90 that is electrically connected to the power supply lines 7 and 8 described above. The P terminal 91P is electrically connected to the positive terminal of the smoothing capacitor 5. The P terminal 91P is sometimes referred to as a positive terminal or a high potential power supply terminal. The P terminal 91P is connected to the P wiring 54 of the surface metal body 52. In other words, the P terminal 91P is connected to the drain electrode 40D of the semiconductor element 40H that constitutes the upper arm 9H.

The P terminal 91P is connected to the P wiring 54 near one end in the Y direction. The P terminal 91P extends in the Y direction from the connection (joint) with the P wiring 54, and protrudes from the center of the side surface 30c in the Z direction to the outside of the sealing body 30. The semiconductor device 20 of this embodiment has two P terminals 91P. As shown in FIG. 11, one of the P terminals 91P is connected to one of the pair of extension parts 542, and the other is connected to the other of the pair of extension parts 542. The P terminal 91P is disposed in a position close to the notch 540, that is, on the inner side, in each of the extension parts 542 so as to be adjacent to the N terminal 91N in a plan view. The two P terminals 91P are disposed side by side in the X direction. The two P terminals 91P are disposed at approximately the same position in the Z direction.

The N terminal 91N is electrically connected to the negative terminal of the smoothing capacitor 5. The N terminal 91N is sometimes referred to as the negative terminal or low potential power supply terminal. The N terminal 91N is connected to the N wiring 64 of the surface metal body 62. In other words, the N terminal 91N is connected to the source electrode 40S of the semiconductor element 40L that constitutes the lower arm 9L.

The N terminal 91N is connected to the N wiring 64 near one end in the Y direction. The N terminal 91N extends in the Y direction from the joint with the N wiring 64, and protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30c. The semiconductor device 20 has two N terminals 91N. As shown in FIG. 15 etc., one of the N terminals 91N is connected to one of the pair of extension portions 641, and the other is connected to the other one of the pair of extension portions 641. The two N terminals 91N are arranged side by side in the Y direction. The two N terminals 91N are arranged at approximately the same position in the Z direction.

The two N terminals 91N are arranged outside the two P terminals 91P in the X direction. In a plan view, one of the N terminals 91N is arranged near one of the P terminals 91P, and the other N terminal 91N is arranged near the other P terminal 91P. The N terminal 91N and P terminal 91P adjacent to each other in the X direction have their sides facing each other in a portion that includes a portion protruding from the sealing body 30.

The output terminal 92 is electrically connected to the winding 3a (stator coil) of the corresponding phase of the motor generator 3. The output terminal 92 may be referred to as an O terminal, an AC terminal, etc. As shown in Figures 3 and 7, the output terminal 92 is connected to the relay wiring 55 of the surface metal body 52 on the substrate 50. In other words, the output terminal 92 is connected to the connection point between the upper arm 9H and the lower arm 9L.

The output terminal 92 is connected to the relay wiring 55 near one end in the Y direction. The output terminal 92 extends in the Y direction from the joint with the relay wiring 55, and protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30d. The semiconductor device 20 has two output terminals 92. One of the output terminals 92 is connected to one of the pair of extension portions 552, and the other is connected to the other of the pair of extension portions 552. The two output terminals 92 are arranged side by side in the X direction. The two output terminals 92 are arranged at approximately the same position in the Z direction.

The signal terminal 93 is electrically connected to a drive circuit (driver) not shown. The signal terminal 93H is electrically connected to the pad 40P of the semiconductor element 40H via a connection member such as a bonding wire 110. The number of signal terminals 93H is not particularly limited. The signal terminal 93H may include at least a terminal for applying a drive voltage to the gate electrode of the semiconductor element 40H. The semiconductor device 20 of this embodiment has two signal terminals 93H. One of the signal terminals 93H is a terminal for a gate electrode. The gate electrode pads 40P of the two semiconductor elements 40H are electrically connected to the signal terminal 93H for the gate electrode. The signal terminal 93H is arranged at a position overlapping the notch 540 of the P wiring 54 in a plan view. In the signal terminal 93H, the joint with the bonding wire 110 faces the insulating substrate 51, not the surface metal body 52. The two signal terminals 93H are arranged side by side in the X direction.

The signal terminal 93H extends in the Y direction from the joint with the bonding wire 110, and protrudes from the side surface 30c near the center in the Z direction outside the sealing body 30. At least a part of the protruding portion of the signal terminal 93H extends in the same direction as the power terminal 91. The signal terminal 93H is disposed between the two P terminals 91P in the X direction. In other words, the external connection terminals 90 protruding from the side surface 30c are disposed in the following order in the X direction: N terminal 91N, P terminal 91P, two signal terminals 93H, P terminal 91P, and N terminal 91N.

The signal terminal 93L is electrically connected to the pad 40P of the semiconductor element 40L via a connecting member such as a bonding wire 110. The number of signal terminals 93L is not particularly limited. The signal terminal 93L may include at least a terminal for applying a drive voltage to the gate electrode of the semiconductor element 40L. The semiconductor device 20 of this embodiment has four signal terminals 93L. One of the signal terminals 93L is a terminal for a gate electrode. The gate electrode pads 40P of the two semiconductor elements 40L are electrically connected to the signal terminal 93L for the gate electrode. The signal terminal 93L is arranged at a position overlapping the notch 550 of the relay wiring 55 in a plan view. In the signal terminal 93L, the joint with the bonding wire 110 faces the insulating substrate 51, not the surface metal body 52. The four signal terminals 93L are arranged side by side in the X direction.

The signal terminal 93L extends in the Y direction from the joint with the bonding wire 110, and protrudes from the side surface 30d near the center in the Z direction outside the sealing body 30. At least a portion of the protruding portion of the signal terminal 93L extends in the same direction as the output terminal 92. The signal terminal 93L is disposed between the two output terminals 92 in the X direction. In other words, the external connection terminals 90 protruding from the side surface 30d are disposed in the following order in the X direction: the output terminal 92, the four signal terminals 93L, and the output terminal 92.

The drain electrode 40D of the semiconductor element 40 is joined to the surface metal body 52 via a bonding material 100. The source electrode 40S of the semiconductor element 40 is joined to the conductive spacer 70 via a bonding material 101. The conductive spacer 70 is joined to the surface metal body 62 via a bonding material 102. The joint portion 81 is joined to the metal bodies 52, 62 via a bonding material 103. Of the external connection terminals 90, the P terminal 91P, N terminal 91N, and output terminal 92, which are main terminals, are joined to the corresponding surface metal bodies 52, 62 via a bonding material 104.

The bonding materials 100 to 104 are conductive bonding materials. For example, solder can be used as the bonding materials 100 to 104. An example of solder is a multi-element lead-free solder containing Cu, Ni, and the like in addition to Sn. A sintered bonding material such as sintered silver may be used instead of solder. The P terminal 91P, the N terminal 91N, and the output terminal 92 may be directly bonded to the corresponding surface metal bodies 52, 62 without using the bonding material 104. The P terminal 91P, the N terminal 91N, and the output terminal 92 may be directly bonded to the surface metal bodies 52, 62 by, for example, ultrasonic bonding, friction stir bonding, laser welding, or the like. When the joint portion 81 is provided separately from the substrates 50, 60, the joint portion 81 may be directly bonded to the surface metal bodies 52, 62.

As described above, in the semiconductor device 20, the multiple semiconductor elements 40 that constitute the upper and lower arm circuits 9 for one phase are sealed by the sealing body 30. The sealing body 30 integrally seals the multiple semiconductor elements 40, a part of the substrate 50, a part of the substrate 60, the multiple conductive spacers 70, the arm connection portion 80, and a part of each of the external connection terminals 90. The sealing body 30 seals the insulating substrates 51, 61 and the surface metal bodies 52, 62 in the substrates 50, 60.

The semiconductor element 40 is disposed between the substrates 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched between the substrates 50 and 60, which are disposed opposite each other. This allows the heat of the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of the substrate 50 is approximately flush with one surface 30a of the sealing body 30. The back surface 60b of the substrate 60 is approximately flush with the back surface 30b of the sealing body 30. Because the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be improved.

<Production Method>
Next, an example of a method for manufacturing the semiconductor device 20 will be described with reference to Fig. 10. In Fig. 10, the substrate 50 and the substrate 60 are shown facing each other in order to make the subsequent assembly easier to understand.

First, the semiconductor element 40, the substrates 50 and 60, the conductive spacer 70, the joint portion 81, and the lead frame 94 are prepared. As shown in FIG. 10, the lead frame 94 has external connection terminals 90. The lead frame 94 is formed by subjecting a metal plate to processing such as pressing. The external connection terminals 90 are supported by the outer frame 94b via tie bars 94a.

Next, the semiconductor element 40, the joint portion 81, and the external connection terminal 90 are joined (connected) to the substrate 50. In addition, the conductive spacer 70 is joined to the semiconductor element 40.

At this time, the lead frame 94 and the semiconductor element 40 are placed on the substrate 50. In addition, a conductive spacer 70 is placed on the source electrode 40S of the semiconductor element 40. The lead frame 94 is placed so that each of the external connection terminals 90 partially overlaps the substrate 50 in a plan view. Specifically, the P terminal 91P and the N terminal 91N are placed so that they overlap the P wiring 54 of the surface metal body 52, and the output terminal 92 overlaps the relay wiring 55. In addition, the signal terminal 93H is placed so that it overlaps the insulating base material 51 exposed from the cutout 540, and the signal terminal 93L is placed so that it overlaps the insulating base material 51 exposed from the cutout 550.

Then, the drain electrode 40D of the semiconductor element 40 is bonded to the surface metal body 52 with a bonding material 100. The source electrode 40S is bonded to the conductive spacer 70 with a bonding material 101. The joint portion 81 is bonded to the surface metal body 52 with a bonding material 103. The P terminal 91P and the output terminal 92 are bonded to the surface metal body 52 with a bonding material 104. For example, in the case of solder, the bonding can be performed all at once by reflow. Figure 10 shows this bonded state.

Next, the pad 40P of the semiconductor element 40H and the signal terminal 93H are electrically connected by a bonding wire 110. Similarly, the pad 40P of the semiconductor element 40L and the signal terminal 93L are electrically connected by a bonding wire 110.

Then, the substrate 60 is bonded (connected). The source electrode 40S of the semiconductor element 40 is bonded to the surface metal body 62 via a bonding material 102. The joint portion 81 is bonded to the surface metal body 62 via a bonding material 103. The N terminal 91N is bonded to the surface metal body 62 via a bonding material 104. For example, in the case of solder, the bonding can be performed all at once by reflow.

Next, the sealing body 30 is molded by the transfer molding method. Although not shown in the figure, in this embodiment, the sealing body 30 is molded so that the substrates 50 and 60 are completely covered, and cutting is performed after molding. The sealing body 30 is cut together with a part of the rear metal body 53, 63 of the substrates 50 and 60. This exposes the rear surfaces 50b and 60b. The rear surface 50b is approximately flush with one surface 30a of the sealing body 30, and the rear surface 60b is approximately flush with the rear surface 30b. The sealing body 30 may be molded with the rear surfaces 50b and 60b pressed against the cavity wall surface of the molding die and in close contact with each other. In this case, the rear surfaces 50b and 60b are exposed from the sealing body 30 at the time when the sealing body 30 is molded. Therefore, cutting after molding is not necessary.

Next, unnecessary parts of the lead frame 94, such as the tie bars 94a and the outer peripheral frame 94b, are removed. In this manner, the semiconductor device 20 can be obtained.

<Location>
Next, the positional relationship between the semiconductor element 40, the circuit patterns of the front surface metal bodies 52 and 62, the arm connection portion 80, and the external connection terminal 90 connected to the circuit pattern will be described with reference to Figs. 14 and 15. Fig. 14 is a diagram showing the arrangement of the circuit pattern of the front surface metal body 52, the semiconductor element 40, and the terminals. Fig. 15 is a diagram showing the arrangement of the circuit pattern of the front surface metal body 62, the semiconductor element 40, and the terminals. For convenience, Figs. 14 and 15 show only the external connection terminal 90 connected to the circuit pattern. In Fig. 14, the arrangement area of the semiconductor element 40 is indicated as D so that the main electrode (drain electrode 40D) connected to the front surface metal body 52 can be easily seen. Similarly, in Fig. 15, the arrangement area of the semiconductor element 40 is indicated as S so that the main electrode (source electrode 40S) connected to the front surface metal body 62 can be easily seen.

The imaginary line CL1 shown in FIG. 14 is an imaginary line that passes through the midpoints of the two semiconductor elements 40 that make up one arm. The imaginary line CL1 passes through the midpoint (center) of the two semiconductor elements 40 in the arrangement direction, and extends in the Y direction. The imaginary line CL1 is, for example, a line that passes through the midpoint of the two semiconductor elements 40H. Instead of the semiconductor element 40H, it may be a line that passes through the midpoint of the semiconductor element 40L.

As shown in FIG. 14, the arrangement of the two semiconductor elements 40H is approximately line-symmetrical with respect to the imaginary line CL1. Similarly, the arrangement of the two semiconductor elements 40L is also approximately line-symmetrical with respect to the imaginary line CL1. Here, approximately line-symmetrical allows for an error of the order of manufacturing variation. The circuit pattern of the surface metal body 52 is also approximately line-symmetrical with respect to the imaginary line CL1. In other words, each of the P wiring 54 and the relay wiring 55 is approximately line-symmetrical with respect to the imaginary line CL1.

The arrangement of the arm connection portion 80 connected to the relay wiring 55 is also approximately line-symmetrical with respect to the imaginary line CL1. The arrangement of the external connection terminal 90 connected to the surface metal body 52 is also approximately line-symmetrical with respect to the imaginary line CL1. In other words, the arrangement of the two P terminals 91P is also approximately line-symmetrical with respect to the imaginary line CL1. The arrangement of the two output terminals 92 is also approximately line-symmetrical with respect to the imaginary line CL1.

As in FIG. 14, FIG. 15 also shows a virtual line CL1. The arrangement of the semiconductor elements 40H, 40L is the same as in FIG. 14. As shown in FIG. 15, the circuit pattern of the surface metal body 62 is also approximately line-symmetrical with respect to the virtual line CL1. That is, each of the N wiring 64 and the relay wiring 65 is approximately line-symmetrical with respect to the virtual line CL1. As in FIG. 14, the arrangement of the arm connection portion 80 connected to the relay wiring 65 is also approximately line-symmetrical with respect to the virtual line CL1. The arrangement of the two N terminals 91N, which are external connection terminals 90 connected to the surface metal body 62, is also approximately line-symmetrical with respect to the virtual line CL1.

<Circuit pattern>
Next, the circuit pattern of the surface metal body 62 will be described in more detail with reference to Fig. 15. The dashed dotted lines shown in Fig. 15 indicate the boundaries of the respective regions.

As described above, the surface metal body 62 of the substrate 60 has an N wiring 64 and a relay wiring 65. The N wiring 64 has a base 640 and a pair of extension parts 641. The pair of extension parts 641 extend from the base 640 in the Y direction toward the side surface 30c of the sealing body 30. The N wiring 64 defines the outer contour of the surface metal body 62. The relay wiring 65 is sandwiched between the pair of extension parts 641. The relay wiring 65 is disposed within the cutout 642 of the N wiring 64.

15, the relay wiring 65 has an end 650 as one end in the Y direction. The end 650 is an end on the base 640 side in the Y direction. On the other hand, the base 640 of the N wiring 64 has an opposing side 640a with respect to the end 650. The opposing side 640a is a portion of the base 640 between a pair of extension parts 641. The base 640 also has an arrangement region 640b for the semiconductor element 40L. The arrangement region 640b is defined by the outer contour of the semiconductor element 40L as shown by the two-dot chain line in FIG. 15. The arrangement region 640b includes an area overlapping the semiconductor element 40L in a plan view, and also includes an area between the elements when multiple semiconductor elements 40L are included. The area between the elements is an opposing area between the semiconductor elements 40L in the arrangement direction of the semiconductor elements 40L.

Here, the lengths L1, L2, and L3 in the X direction are defined as follows. Length L1 is the length of the end 650 of the relay wiring 65 as shown in FIG. 15. Length L2 is the length of the opposing side 640a of the base 640. Length L3 is the length of the placement area 640b in the base 640. In this embodiment, the relationship L1<L2<L3 is satisfied.

The relay wiring 65 of this embodiment has a reduced width portion 651a. The reduced width portion 651a includes the end portion 650. The reduced width portion 651a is a portion within a predetermined range in the Y direction from the end portion 650. The length in the X direction of the reduced width portion 651a, i.e., the width, is smallest at the end portion 650. In the reduced width portion 651a, the width W1 at an arbitrary first position is equal to or smaller than the width W2 at a second position that is farther from the end portion 650 than the first position.

The width of the reduced width portion 651a may be reduced stepwise, for example, by a predetermined length in the Y direction. In other words, the end of the reduced width portion 651a in the X direction may change in a step-like manner. In this embodiment, the length of the reduced width portion 651a in the X direction is shorter the closer it is to the base 640. In other words, the width of the reduced width portion 651a is continuously reduced toward the base 640. The arm connection portion 80 is disposed in the reduced width portion 651a.

The relay wiring 65 may have only the reduced width portion 651a including the end portion 650. In this case, the semiconductor element 40H is also disposed in the reduced width portion 651a. In this embodiment, the relay wiring 65 has a constant width portion 651b. The constant width portion 651b is connected to the reduced width portion 651a and has a constant width over a predetermined range in the Y direction. The semiconductor element 40H is disposed in the constant width portion 651b.

The relay wiring 65 of this embodiment further has a reduced width portion 651c. The reduced width portion 651c includes an end portion 652 opposite the end portion 650. The reduced width portion 651c is opposite the reduced width portion 651a and is connected to the constant width portion 651b. The width of the reduced width portion 651c is smallest at the end portion 652. In the reduced width portion 651c, the width at an arbitrary first position is equal to or smaller than the width at a second position that is farther from the end portion 652 than the first position. In this embodiment, the width of the reduced width portion 651c is continuously reduced toward the end portion 652. In the relay wiring 65, the reduced width portions 651a and 651c become narrower the further away they are from the constant width portion 651b.

In this embodiment, the distance between the N wiring 64 and the relay wiring 65 is approximately constant throughout the entire opposing region. The extension portion 641 of the N wiring 64 is patterned so that the distance between the N wiring 64 and the relay wiring 65 is approximately constant. Each of the extension portions 641 has a widened portion 641a, a constant width portion 641b, and a widened portion 641c.

The widened portion 641a is connected to the base 640 and is a portion that is a predetermined range in the Y direction from the boundary with the base 640. The length in the X direction of the widened portion 641a, i.e., the width, is maximum at the boundary with the base 640. In the widened portion 641a, the width at an arbitrary first position is equal to or greater than the width at a second position that is farther from the base 640 than the first position. In this embodiment, the width of the widened portion 641a increases continuously toward the base 640. The constant width portion 641b is connected to the widened portion 641a and is a portion whose width is constant over a predetermined range in the Y direction. The constant width portion 641b faces the constant width portion 651b of the relay wiring 65.

The widening portion 641c is opposite to the widening portion 641a and is connected to the constant width portion 641b. The widening portion 641a extends to a position closer to the side surface 30c than the narrowing portion 651c. The widening portion 641c includes the tip 641d of the extension portion 641. The width of the widening portion 641c is maximum at the tip 641d. In the widening portion 641c, the width at any first position is equal to or greater than the width at a second position farther from the tip 641d than the first position. In this embodiment, the width of the widening portion 641c is continuously enlarged toward the tip 641d in the portion facing the narrowing portion 651c. In the widening portion 641c, the portion closer to the tip 641d than the facing portion has a constant width. In the N wiring 64, a portion of the widened portion 641c and the widened portion 641a become wider the further away from the fixed width portion 641b.

<Current Path>
Next, the current path will be described with reference to Figs. 16 to 20. Fig. 16 is a diagram showing a PN current loop of a reference example. In the reference example, the reference symbol of each element is the reference symbol of the related element of the semiconductor device 20 with r added to the end. The configuration of the reference example is almost the same as that of the semiconductor device 20, except that the number of signal terminals 93Lr and the patterns of the N wiring 64r and relay wiring 65r are different. Fig. 17 is a diagram showing a PN current loop in the semiconductor device 20 of this embodiment. Fig. 18 is a diagram showing a PN current loop in a side view of the semiconductor device 20 seen from the X direction. The PN current loop refers to the loop shape of the current path from the P terminal 91P to the N terminal 91N.

When examining inductance, the PN current loop of P terminal 91P → P wiring 54 → semiconductor element 40H → relay wiring 65 → arm connection part 80 → relay wiring 55 → semiconductor element 40L → N wiring 64 → N terminal 91N is taken into consideration. For this reason, to make the PN current loop easier to understand, a continuous solid line is shown from P terminal 91P to N terminal 91N. In reality, semiconductor elements 40H and 40L are controlled so that they are not turned on at the same time. For convenience, only the current path for one semiconductor element 40H and one semiconductor element 40L is shown, but the same is true for the other semiconductor element 40H and the other semiconductor element 40L.

Figures 19 and 20 show the results of electromagnetic field simulations. Figure 19 shows the current density of the reference example shown in Figure 18. Figure 20 shows the current density for the configuration of this embodiment shown in Figure 16. The conditions for the electromagnetic field simulations were the same for both, except that the circuit patterns of the surface metal body 62 were different. In Figures 19 and 20, the lower the current density, the coarser it is (lighter color), and the higher the current density, the denser it is (darker color).

16, in the semiconductor device 20r of the reference example, the relay wiring 65r has a substantially rectangular shape in plan. The length of the end 650r of the relay wiring 65r is substantially equal to the length of the placement area 640br of the semiconductor element 40Lr in the base 640r. The length of the opposing side 640ar in the base 640r is longer than the placement area 640br. For this reason, as shown by the solid arrow in FIG. 16, a current enters the substantially rectangular semiconductor element 40Lr from one side 400r and exits from another side 401r. The side 400r is the side opposing the relay wiring 65r. The side 401r is the side opposite to the side where the two semiconductor elements 40Lr face each other. In this way, the current flows from the semiconductor element 40Lr outward in the X direction, so the PN current loop is large. The simulation results shown in FIG. 19 also clearly show that current flows from the semiconductor element 40Lr through the base 640r outward in the X direction.

On the other hand, in the semiconductor device 20 of this embodiment, as described above, the N wiring 64 and the relay wiring 65 are patterned and satisfy a predetermined positional relationship with the semiconductor element 40L. Due to this positional relationship, as shown in FIG. 17, the N wiring 64 (extension portion 641) is also present above one side 400 of the semiconductor element 40L in a planar view. The side 400 is the side opposite the relay wiring 65. Therefore, a current enters from the side 400 of the semiconductor element 40L and exits from the same side 400. The Y-direction component of the current flowing from the semiconductor element 40L to the N terminal 91N increases, especially in the vicinity of the semiconductor element 40L. It is also clear from the simulation results shown in FIG. 20 that the current flows from the semiconductor element 40L with a Y-direction component.

In this way, the current flowing through the N wiring 64 approaches the relay wiring 65, and the current path through the N wiring 64, i.e., the current path between the semiconductor element 40L and the N terminal 91N, becomes shorter. Therefore, the PN current loop is smaller than in the reference example. As shown in FIG. 18, the PN current loop is also small in the Z direction. The P wiring 54 and the N wiring 64 face each other in the Z direction. Also, the relay wiring 55 and the N wiring 64 face each other in the Z direction.

Summary of the First Embodiment
If the inductance of the main circuit wiring is large, the surge voltage will be large. If the semiconductor element is made thicker to ensure the withstand voltage, steady-state loss will increase. In order to reduce steady-state loss, the element area must be increased. Surge voltage can also be reduced by slowing down the switching speed. In this case, the output to the motor generator will be smaller. Thus, if the inductance is large, the size of the semiconductor element will be larger or the output will be smaller.

When components through which currents flow in opposite directions are arranged opposite each other, the inductance can be reduced due to the cancellation effect of the magnetic fluxes generated by the currents. If the PN current loops in the main circuit wiring are smaller, the components through which currents flow in opposite directions are closer to each other, which increases the cancellation effect of the magnetic fluxes, thereby reducing the inductance.

In this embodiment, the semiconductor elements 40H, 40L are arranged side by side in the Y direction, and the arm connection portion 80 is arranged between the semiconductor elements 40H, 40L. Of the main terminals, the power supply terminals 91 (91P, 91N) are drawn out in the same direction. In addition, in the Y direction, the P wiring 54 is arranged on the power supply terminal 91 side, and the relay wiring 55 is arranged on the opposite side. In the Y direction, the relay wiring 65 is arranged on the power supply terminal 91 side, and the base 640 of the N wiring 64 is arranged on the opposite side. The extension portion 641 of the N wiring 64 extends toward the power supply terminal 91 side so as to sandwich the relay wiring 65.

This configuration reduces the PN current loop. This allows the inductance of the main circuit wiring to be reduced. For example, the inductance can be reduced by arranging the P terminal 91P and the N terminal 91N side by side. The relay wiring 65 and the N wiring 64 are also arranged (side by side) with a predetermined distance between them. This allows the inductance to be reduced. In addition, the extension portion 641 of the N wiring 64 faces the P wiring 54. This allows the inductance to be reduced.

In this embodiment, the surface metal body 52 of the substrate 50 and the surface metal body 62 of the substrate 60 provide the wiring function for the semiconductor element 40. The surface metal bodies 52, 62 are sealed by the sealing body 30. Since there is no need to ensure a creepage distance as in the conventional case, the N wiring 64 and the relay wiring 65 can be arranged close to each other. This enhances the effect of canceling magnetic flux, and further reduces inductance.

As shown in FIG. 15, the length L1 of the end 650 of the relay wiring 65, the length L2 of the opposing side 640a of the base 640, and the length L3 of the placement area 640b of the semiconductor element 40L in the base 640 satisfy the relationship L1<L2<L3. By satisfying this dimensional relationship, as described above, a current enters from one side 400 of the semiconductor element 40L and exits from the same side 400. The Y-direction component of the current flowing from the semiconductor element 40L to the N-terminal 91N increases, especially in the vicinity of the semiconductor element 40L. This shortens the current path through the N-wiring 64, that is, the current path between the semiconductor element 40L and the N-terminal 91N, and the PN current loop becomes smaller. Therefore, the inductance of the main circuit wiring can be further reduced.

In addition, the higher the current frequency, the more the current concentrates on the opposing side of the extension 641 of the N wiring 64 and the relay wiring 65 due to the skin effect. This makes it possible to further reduce the PN current loop and, therefore, the inductance.

In this embodiment, as shown in FIG. 15, the relay wiring 65 has a reduced width portion 651a. This allows the width of the portion of the extension portion 641 that faces the reduced width portion 651a to be increased. This makes it possible to suppress heat generation due to current flow without changing the size of the surface metal body 62, and thus the substrate 60. In other words, heat generation can be suppressed while reducing inductance.

In particular, in this embodiment, the length of the narrowed portion 651a in the X direction becomes shorter as it approaches the base 640. In other words, the width of the narrowed portion 651a continuously decreases toward the base 640. The narrowed portion 651a of the relay wiring 65 has a tapered shape. This makes it easier to maintain a constant distance between the relay wiring 65 and the extension portion 641. In other words, the extension portion 641 can be brought closer to the relay wiring 65, making the PN current loop smaller. In addition, the width of the extension portion 641 can be increased to suppress heat generation.

In this embodiment, the relay wiring 65 has a constant width portion 651b. The semiconductor element 40H is disposed in the constant width portion 651b. The relay wiring 65 having the reduced width portion 651a and the constant width portion 651b has a shape that is the same as or similar to a baseball home base in a plan view. This allows the width of the extension portion 641 to be wider than in a configuration in which the semiconductor element 40H is disposed in the reduced width portion 651a. Therefore, heat generation due to current flow can be suppressed without changing the size of the surface metal body 62 and thus the substrate 60. In other words, heat generation can be suppressed while reducing inductance.

In this embodiment, the semiconductor device 20 includes two semiconductor elements 40H and two semiconductor elements 40L. The two semiconductor elements 40H are arranged side by side in the X direction. Similarly, the two semiconductor elements 40L are arranged side by side in the X direction. In this way, the semiconductor elements 40 constituting one arm are arranged side by side in a direction (X direction) perpendicular to the arrangement direction (Y direction) of the semiconductor elements 40H and 40L. In the X direction, a pair of extension portions 641 sandwich the relay wiring 65. This makes it possible to suppress current bias.

The semiconductor device 20 may be provided with one N terminal 91N whose tip is branched into two so as to be individually connected to the pair of extension parts 641. In this embodiment, the semiconductor device 20 is provided with two N terminals 91N, and the N terminals 91N are individually connected to the pair of extension parts 641. This makes it easy to arrange another external connection terminal 90 between the two N terminals 91N. Since there is no need to avoid the external connection terminal 90 arranged between them, the size can be made smaller.

The semiconductor device 20 may have only one P terminal 91P. In this embodiment, the semiconductor device 20 has two P terminals 91P. In the X direction, the N terminal 91N, P terminal 91P, signal terminal 93H, P terminal 91P, and N terminal 91N are arranged in this order. The P terminal 91P and the N terminal 91N are arranged side by side at both ends in the X direction. This makes it easier to make the PN current loop small. In addition, since the external connection terminals 90 are arranged with regularity in the X direction, it is easier to ensure linear symmetry for the circuit patterns of the semiconductor element 40, the surface metal bodies 52 and 62, and the external connection terminals 90, as described above. This makes it possible to suppress current bias.

In this embodiment, the P terminal 91P and the N terminal 91N protrude from the side surface 30c of the sealing body 30, and the output terminal 92 protrudes from the side surface 30d. In this way, the P terminal 91P and the N terminal 91N connected to the smoothing capacitor 5 are drawn out in the same direction, and the output terminal 92 is drawn out in the opposite direction. This improves the connectivity with the smoothing capacitor 5 and the connectivity with the motor generator 3. Furthermore, by arranging the P terminal 91P and the N terminal 91N in parallel, the inductance can be reduced. This terminal arrangement makes it easier to make the PN current loop smaller.

<Modification>
As an example of the semiconductor elements 40H and 40L, two of each are provided, but the present invention is not limited thereto. Three or more may be provided. For example, three semiconductor elements 40H may be arranged side by side in the X direction, and three semiconductor elements 40L may be arranged side by side in the X direction. The circuit pattern of the front metal body 62 and the arrangement of the semiconductor elements 40 are not limited to the above example. For example, they may be as shown in FIG. 21 and FIG. 22. In FIG. 21 and FIG. 22, for convenience, the sealing body 30 on the back surface 30b side of the insulating base material 51 is omitted. In addition, the insulating base material 61 and the back surface metal body 63 of the substrate 60 are omitted. As in FIG. 17, the PN current loop is indicated by a solid arrow. In FIG. 21 and FIG. 22, the semiconductor device 20 includes two signal terminals 93L.

21, the semiconductor device 20 has two arm connection parts 80. The relay wiring 65 has a substantially rectangular shape in plan view. The two arm connection parts 80 are arranged side by side in the X direction near the end 650. The distance between the two semiconductor elements 40L is larger than in the above example (see FIG. 17). The length of the placement area 640b of the semiconductor element 40L is longer than in the above example. This satisfies the relationship L1<L2<L3. Therefore, a current enters from the side 400 of the semiconductor element 40L, and a current exits from the same side 400. Even with this configuration, the current path through the N wiring 64 is shorter, and the PN current loop can be made smaller. However, the configuration shown in FIG. 17 allows the width of the N wiring 64, especially the width of the extension part 641, to be wider. Also, in the case of the configuration shown in FIG. 17, only one arm connection part 80 is required.

In FIG. 22, the semiconductor device 20 includes only one each of the semiconductor elements 40H and 40L. In this example, the placement area 640b coincides with the outer contour of the semiconductor element 40L. The length in the X direction of each of the semiconductor elements 40H and 40L is longer than in the example described above (see FIG. 17). This satisfies the relationship L1<L2<L3. Therefore, current enters from the side 400 of the semiconductor element 40L, and current exits from the same side 400. Even with this configuration, the current path through the N wiring 64 is shortened, and the PN current loop can be made smaller.

The arrangement of the external connection terminals 90 is not limited to the above example. For example, the P terminals 91P may be arranged on the outside in the X direction, and the N terminals 91N on the inside. In this case, the semiconductor elements 40 and the circuit patterns are also reversed, as shown in Figures 23 and 24. Figure 23 shows a substrate 50. Figure 24 shows a substrate 60.

As shown in FIG. 23, the circuit pattern of the surface metal body 52 of the substrate 50 is the same as the circuit pattern of the surface metal body 62 of the substrate 60 shown in FIG. 15. The P wiring 54 has the same pattern as the N wiring 64 shown in FIG. 15. The semiconductor element 40H is disposed on the N wiring 64. The relay wiring 55 has the same pattern as the relay wiring 65 shown in FIG. 15. The semiconductor element 40L and the arm connection portion 80 are disposed on the relay wiring 55.

As shown in FIG. 24, the circuit pattern of the surface metal body 62 of the substrate 60 is the same as the circuit pattern of the surface metal body 52 of the substrate 50 shown in FIG. 14. The N wiring 64 has the same pattern as the P wiring 54 shown in FIG. 14. The semiconductor element 40L is disposed on the N wiring 64. The relay wiring 65 has the same pattern as the relay wiring 55 shown in FIG. 14. The semiconductor element 40H and the arm connection portion 80 are disposed on the relay wiring 65.

In the case of the configurations shown in Figures 23 and 24, the first and second relationships described above are reversed. The semiconductor element 40L is the first element, and the semiconductor element 40H is the second element. The source electrode 40S is the first main electrode, and the drain electrode 40D is the second main electrode. The substrate 60 is the first substrate, and the substrate 50 is the second substrate. The insulating substrate 61 is the first insulating substrate, the front surface metal body 62 is the first front surface metal body, and the rear surface metal body 63 is the first rear surface metal body. The insulating substrate 51 is the second insulating substrate, the front surface metal body 52 is the second front surface metal body, and the rear surface metal body 53 is the second rear surface metal body.

Second Embodiment
This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to suppress the transient current imbalance during switching, as described in this embodiment, the surface metal body to which the multiple semiconductor elements are connected in parallel may have a predetermined structure.

<Semiconductor Device>
First, the semiconductor device 20 according to the present embodiment will be described with reference to Fig. 25. Fig. 25 is a cross-sectional view showing the semiconductor device 20 according to the present embodiment. Fig. 25 corresponds to Fig. 8.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 15). The semiconductor device 20 constitutes one phase of upper and lower arm circuits 9. As shown in Figure 25, the semiconductor device 20 includes a plurality of semiconductor elements 40 including two semiconductor elements 40H that are upper arm elements, substrates 50 and 60 arranged to sandwich the semiconductor elements 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the first main electrode on the high potential side of the semiconductor element 40. The surface metal body 62 of the substrate 60 is connected to the source electrode 40S, which is the second main electrode on the low potential side of the semiconductor element 40. Although not shown, the semiconductor device 20 includes two semiconductor elements 40L that are lower arm elements.

The surface metal body 62 is substantially symmetrical with respect to the imaginary line CL1, as in the previous embodiment. As shown in FIG. 25, in this embodiment, the relay wiring 65 of the surface metal body 62 has a slit 653. As described later, the N wiring 64 has a slit 643.

<Suppression effect of transient current imbalance>
Next, the effect of suppressing transient current imbalance during switching will be described with reference to Fig. 26 and Fig. 27. Fig. 26 is an equivalent circuit diagram of two semiconductor elements 40 (MOSFETs 11) that constitute one arm. Fig. 27 is an image diagram (potential diagram) that clearly shows potentials.

26 and 27, one of the MOSFETs 11 connected in parallel is shown as MOSFET1, and the other is shown as MOSFET2. The inductance of the wiring on the drain electrode side (hereinafter referred to as drain wiring) is shown as Ld, and the inductance of the wiring on the source electrode side (hereinafter referred to as source wiring) is shown as Ls. The gate potential is shown as Vg, the potential of the source electrode of MOSFET1 as Vks1, the potential of the source electrode of MOSFET2 as Vks1, and the common source potential as Vs. The midpoint potential between the potentials Vks1 and Vks2 is shown as Vm. The midpoint potential Vm is constant.
Vm=(Vks1+Vks2)/2.

Also, the gate voltage of MOSFET1 is denoted as Vgs1, and the gate voltage of MOSFET2 is denoted as Vgs2. The current flowing through MOSFET1 when it is turned on is denoted as I1, and the voltage generated across inductance Ls when current I1 flows is denoted as ΔVs1. Similarly, the current flowing through MOSFET2 when it is turned on is denoted as I2, and the voltage generated across inductance Ls when current I2 flows is denoted as ΔVs2.
ΔVs1=Ls×dI1/dt.
ΔVs2=Ls×dI2/dt.

Assume that a current I2 (I2>I1) larger than the current I1 flows due to the characteristic variation of the MOSFET 11, as shown in FIG. 26. At this time, the voltage ΔVs generated in the inductance Ls is ΔVs1<ΔVs2. That is, as shown in FIG. 27, the potential Vks2 of the source electrode rises relative to the midpoint potential Vm, and the potential Vks1 falls. Therefore, the gate voltage Vgs1>gate voltage Vgs2. To reduce the gate voltage Vgs2, the current I2 becomes smaller. In this way, the inductance Ls of the source wiring has the function of suppressing the transient current imbalance during switching caused by the characteristic variation of the semiconductor element 40 (MOSFET 11) connected in parallel.

However, if the inductance Ls of the source wiring is small, the function of suppressing the above-mentioned transient current imbalance is lost. This causes a bias in the switching loss, making it necessary to include a margin in the thermal design.

<Circuit pattern on board>
Next, the circuit pattern of the front surface metal body 62 in the semiconductor device 20 of this embodiment will be described with reference to Fig. 28. Fig. 28 corresponds to Fig. 15. In Fig. 28, like Fig. 15, the source electrode 40S is indicated as S in order to clarify the main electrode to which it is connected.

The N wiring 64 and the relay wiring 65 are source wirings to which the source electrode 40S of the semiconductor element 40 is connected. The N wiring 64 differs from the pattern of the preceding embodiment in that it has a slit 643. Similarly, the relay wiring 65 differs from the pattern of the preceding embodiment in that it has a slit 653. Except for the slits 643 and 653, the configuration is the same as that described in the preceding embodiment.

The slit 643 penetrates the N wiring 64 in its thickness direction (Z direction). The slit 643 is provided at a position in the base 640 where it overlaps with the opposing regions of the two semiconductor elements 40L. The opposing regions are regions where the semiconductor elements 40L face each other in the arrangement direction of the semiconductor elements 40L. That is, the slit 643 is provided between the semiconductor elements 40L, which are the lower arm elements, in a plan view in the Z direction. The slit 643 is provided at the base 640 between the electrical connection parts with the semiconductor element 40L. The slit 643 extends from between the semiconductor elements 40L in the Y direction, which is the arrangement direction of the semiconductor elements 40H and 40L. The slit 643 opens at the opposing side 640a of the base 640. The slit 643 is provided at approximately the center position of the N wiring 64 in the X direction.

In this way, the slit 643 extends in the Y direction from the source electrode 40S of the semiconductor element 40L to the side where the N terminal 91N, which is the main terminal, is arranged, that is, the side where the current flows. The slit 643 does not open to the end 640c of the base 640. The slit 643 is provided up to the vicinity of the lower end of the facing region of the semiconductor element 40L. The slit 643 divides the N wiring 64 into an area to which one of the semiconductor elements 40L is connected and an area to which the other one is connected. The slit 643 separates the current path of the source electrode 40S of the semiconductor element 40L, that is, the source current path.

The slit 653 penetrates the relay wiring 65 in its thickness direction (Z direction). The slit 653 is provided in the relay wiring 65 at a position that overlaps the opposing regions of the two semiconductor elements 40H. That is, the slit 653 is provided between the semiconductor elements 40H in a plan view. The slit 653 is provided in the relay wiring 65 between the electrical connection parts with the semiconductor element 40H. The slit 653 extends in the Y direction from between the semiconductor elements 40H. The slit 653 opens at the end 652. The slit 653 crosses from the end 652 between the semiconductor elements 40H (opposing region) and extends to the vicinity of the arm connection part 80. The slit 653 is provided at approximately the center position of the relay wiring 65 in the X direction.

In this way, the slit 653 extends from the source electrode 40S of the semiconductor element 40H toward the arm connection part 80 in the Y direction. The slit 653 extends from the source electrode 40S of the semiconductor element 40H toward the side where the current flows. The slit 653 does not open to the end part 650. The slit 643 is provided up to just before the arm connection part 80. The slit 653 divides the relay wiring 65 into an area to which one of the semiconductor elements 40H is connected and an area to which the other one is connected. The slit 653 separates the current path of the source electrode 40S of the semiconductor element 40H, i.e., the source current path.

<Summary of the Second Embodiment>
29 shows the source current path. The solid arrow indicates the source current path on the semiconductor element 40H side, and the dashed arrow indicates the source current path on the semiconductor element 40L side. As described above, in this embodiment, the slits 643, 653 are provided in the front surface metal body 62 to which the source electrode 40S, which is the main electrode on the low potential side, is connected.

The slits 643 are provided between adjacent semiconductor elements 40L in the N wiring 64 to which the semiconductor elements 40L are connected in parallel. The slits 643 divide the N wiring 64 and separate the source current paths of each semiconductor element 40L. This makes it possible to suppress the current (source current) coming out of the source electrode 40S of the semiconductor element 40L from merging in the vicinity of the source electrode 40S. In other words, the merging point of the source current is farther away from the source electrode 40S in a plan view. Therefore, in a parallel circuit of two semiconductor elements 40L (MOSFET 11), the inductance Ls of the source wiring can be made larger than a configuration without the slits 643. Since the inductance Ls is large, even if there is a variation (deviation) in the characteristics of the two semiconductor elements 40L, the transient current imbalance during switching can be suppressed. By providing the slits 643, the transient current imbalance can be suppressed while maintaining the high integration of the semiconductor elements 40L.

Similarly, the relay wiring 65 has a slit 653. The slit 653 is provided between the two semiconductor elements 40H. The slit 653 divides the relay wiring 65 and separates the source current paths of the semiconductor elements 40H. This makes it possible to suppress the current (source current) coming out of the source electrode 40S of the semiconductor element 40H from merging in the vicinity of the source electrode 40S. In other words, the merging point of the source current is farther away from the source electrode 40S in a plan view. Therefore, in a parallel circuit of two semiconductor elements 40H, the inductance Ls of the source wiring can be made larger than a configuration without the slit 653. Since the inductance Ls is large, even if there is a variation (deviation) in the characteristics of the two semiconductor elements 40H, the transient current imbalance during switching can be suppressed. By providing the slit 653, the transient current imbalance can be suppressed while maintaining the high integration of the semiconductor element 40H.

In this embodiment, the slit 643 extends from between adjacent semiconductor elements 40L in the Y direction toward the N terminal 91N. The slit 643 extends from the source electrode 40S of the semiconductor element 40L toward the side where the current flows. This allows the source current paths of each semiconductor element 40L to be separated by a longer distance. Therefore, in the parallel circuit of the semiconductor elements 40L, the inductance Ls of the source wiring can be made larger. In other words, the effect of suppressing transient current imbalance can be improved.

Similarly, the slit 653 extends from between adjacent semiconductor elements 40H in the Y direction toward the arm connection portion 80. The slit 653 extends from the source electrode 40S of the semiconductor element 40H toward the side where the current flows. This allows the source current paths of each semiconductor element 40L to be separated by a longer distance. Therefore, in the parallel circuit of the semiconductor elements 40H, the inductance Ls of the source wiring can be made larger. In other words, the effect of suppressing transient current imbalance can be improved.

Figure 30 is a cross-sectional view taken along line XXX-XXX in Figure 29. In this embodiment, the joint 81, the bonding material 103 connecting the joint 81 and the relay wiring 55, and the bonding material 103 connecting the joint 81 and the relay wiring 65 constitute the arm connection 80 that electrically connects the relay wirings 55, 65. The joint 81 is a separate member from the substrates 50, 60. The arm connection 80 electrically connects the relay wiring 65 connected to the source electrode 40S of the semiconductor element 40H and the relay wiring 55 connected to the drain electrode 40D of the semiconductor element 40L.

<Modification>
In the above example, the multiple semiconductor elements 40 include two each of the semiconductor elements 40H and 40L, but this is not limiting. The multiple semiconductor elements 40 may include two of the semiconductor elements 40H and 40L and one of the other. In this case, a slit may be provided in one of the two wirings (64, 65) of the front metal body 62, in which the multiple semiconductor elements 40 are connected in parallel to form one arm. For example, in the case of a configuration including two semiconductor elements 40H and one semiconductor element 40L, the slit 643 is not provided in the N wiring 64, and the slit 653 is provided in the relay wiring 65 to which the semiconductor element 40H is connected. In this way, the multiple semiconductor elements 40 may include two arm elements of at least one of the semiconductor elements 40H and 40L.

The number of semiconductor elements 40 connected in parallel is not limited to two. Three or more semiconductor elements 40 may be connected in parallel to form one arm. For example, in the case of a configuration including three semiconductor elements 40H, slits 653 may be provided between adjacent semiconductor elements 40H in a plan view for the three semiconductor elements 40H arranged side by side in the X direction. The multiple semiconductor elements 40 may include multiple arm elements of at least one of the semiconductor elements 40H, 40L. It may also include multiple arm elements of both, that is, multiple semiconductor elements 40H and multiple semiconductor elements 40L.

The arrangement of the N terminal 91N is not limited to the above example. For example, the P terminal 91P may protrude from the side surface 30c of the sealing body 30, and the N terminal 91N may protrude from the side surface 30d. In this case, the pattern of the N wiring 64 has a shape similar to that of the P wiring 54 or the relay wiring 55. That is, the extension portion 641 extends from the base 640 to the side surface 30d of the sealing body 30. Even in this configuration, the slit 643 only needs to be provided at least between the semiconductor elements 40L. In addition, by configuring the slit 643 to extend from the opposing region of the semiconductor element 40L to the outside of the opposing region toward the N terminal 91N side, the inductance Ls can be further increased.

Although only one slit 643, 653 is provided between the semiconductor elements 40, this is not limiting. At least one of the slits 643, 653 may be multiple.

The slits 643 and 653 are shown in an example in which they open at one of the ends of the surface metal body 62, but are not limited thereto. For example, in the example shown in FIG. 31 and FIG. 32, the slit 643 extends in the Y direction from the opposing side 640a of the base 640 to the end 640c. The slit 643 divides the base 640 and thus the N wiring 64 into two parts. The slit 643 crosses the opposing region of the semiconductor element 40L. One of the semiconductor elements 40L is disposed in one of the divided N wirings 64, and the other one of the semiconductor elements 40L is disposed in the other one of the N wirings 64. Similarly, the slit 653 extends in the Y direction from the end 652 of the relay wiring 65 to the end 650. The slit 653 divides the relay wiring 65 into two parts. One of the semiconductor elements 40H is disposed in one of the divided relay wirings 65, and the other one of the semiconductor elements 40H is disposed in the other one of the relay wirings 65.

The slits 643 and 653 are connected to each other to form a single slit extending in the Y direction. The surface metal body 62 is approximately linearly symmetrical with respect to the imaginary line CL1. FIG. 33 shows the source current path. The solid arrow indicates the source current path of the semiconductor element 40H, and the dashed arrow indicates the source current path of the semiconductor element 40L. As described above, the slit 643 divides the N wiring 64 into two. This prevents one source current of the semiconductor element 40L and the other source current from joining together on the substrate 60. Since the joining point of the source currents is farther away, the inductance Ls of the source wiring can be further increased.

Similarly, the slit 653 divides the relay wiring 65 into two. This prevents the source current of the semiconductor element 40H and another source current from merging on the substrate 60. Since the merging point of the source currents is farther away, the inductance Ls of the source wiring can be further increased. As a result, the effect of suppressing transient current imbalance can be improved. Figures 31, 32, and 33 are diagrams showing modified examples. Figure 31 corresponds to Figure 28. Figure 32 corresponds to Figure 11. Figure 33 corresponds to Figure 29.

In the example shown in Figures 31 to 33, the arm connection parts 80 are divided into the same number as the relay wirings 65 in accordance with the division of the relay wirings 65. The arm connection parts 80 are individually connected to the relay wirings 65. This prevents the source currents from merging at the arm connection parts 80, making it possible to further increase the inductance Ls.

In the configuration of the above-mentioned modified example, a slit may be further provided in the surface metal body 52 of the substrate 50. As shown in Figures 34 and 35, the relay wiring 55 of the surface metal body 52 has a slit 553. The slit 553 opens at an end 551a of the relay wiring 55. The end 551a faces the P wiring 54 in the Y direction. The slit 553 extends in the Y direction, crosses the arm connection portion 80 divided into two, and reaches the opposing area (between) of the semiconductor element 40L. The slit 553 is provided up to the vicinity of the lower end of the opposing area of the semiconductor element 40L.

When such a configuration is adopted, as shown in FIG. 35, a first current path by one pair of semiconductor elements 40H, 40L and a second current path by another pair of semiconductor elements 40H, 40L are almost completely separated within the semiconductor device 20. The current joining point is provided outside the N terminal 91N. This allows the inductance Ls of the source wiring to be further increased. FIGS. 34 and 35 are diagrams showing modified examples. FIG. 34 corresponds to FIG. 32. FIG. 35 corresponds to FIG. 33. Note that the semiconductor device 20 may include an N bus bar that connects multiple N terminals 91N. In this case, the currents join at the N bus bar. The N bus bar that connects the N terminals 91N may be provided, for example, on the smoothing capacitor 5 side.

An example in which the arm connection part 80 is composed of a joint part 81 and bonding material 103 arranged on both ends of the joint part 81 has been shown, but this is not limiting. In the example shown in FIG. 36, the joint part 81 is provided integrally with the substrate 60. The joint part 81 is provided as a protrusion extending in the Z direction from the relay wiring 65. The conductive spacer 70, like the joint part 81, is also provided integrally with the surface metal body 62 as a protrusion.

The surface metal body 62 having the protrusions may be formed, for example, by patterning a metal plate with a multi-gauge strip by press processing and attaching it to the insulating substrate 61. The surface metal body 62 having the protrusions may be formed by etching thick Cu. It may also be formed by directly bonding a metal body that is a separate member from the substrate 60 to the surface metal body 62. In the configuration shown in FIG. 36, the joint portion 81, which is the protrusion of the relay wiring 65, and the bonding material 103 interposed between the tip of the joint portion 81 and the relay wiring 55 constitute the arm connection portion 80. FIG. 36 is a view corresponding to FIG. 30.

In the example shown in FIG. 37, the joint portion 81 is eliminated. The bonding material 103 electrically connects the relay wirings 55 and 65. The bonding material 103 constitutes the arm connection portion 80. In FIG. 37, the conductive spacer 70 is also eliminated, and the source electrode 40S of the semiconductor element 40 is connected to the surface metal body 62 via the bonding material 101. Although not shown, the arm connection portion 80 may be configured to include only the joint portion 81 without the bonding material 103. In this case, the joint portion 81 is directly bonded to the relay wirings 55 and 65.

The circuit patterns of the substrates 50 and 60 are not limited to the above examples. The substrate 60 shown in FIG. 38 shows an example in which slits 643 and 653 are applied to the circuit pattern shown in FIG. 24. In the example shown in FIG. 38, the slit 643 is provided between adjacent semiconductor elements 40L. The slit 643 extends from between the semiconductor elements 40L in the Y direction toward the N terminal 91N, that is, the side where the source current flows. The slit 653 is provided between adjacent semiconductor elements 40H. The slit 653 extends from between the semiconductor elements 40H in the Y direction toward the arm connection portion 80.

In this embodiment, the arrangement of the external connection terminals 90 is not limited to the example shown in the figure. The P terminal 91P may be connected to the P wiring 54 at both ends in the X direction, for example. The N terminal 91N may be connected to the N wiring 64 at both ends in the X direction, for example. In this case, the N terminal 91N may be connected to the extension portion 641. The extension portion 641 may be removed from the N wiring 64 and connected to the base portion 640. The output terminal 92 may be connected to the relay wiring 55 at both ends in the X direction, for example.

The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment and its modified examples.

Third Embodiment
This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be used in this embodiment. In order to effectively dissipate heat from the semiconductor element, the thickness above the semiconductor element and the thickness below the semiconductor element may satisfy a predetermined relationship, as described in this embodiment.

<Warping at high temperatures>
Through careful investigation, it has become clear that even if insulating base materials 51, 61 made of resin are used and the linear expansion coefficient is made closer to that of metal bodies 52, 53, 62, 63 by adding filler, warping may occur in semiconductor device 20 as shown in Fig. 39. Fig. 39 shows the state of semiconductor device 20 when semiconductor element 40 is in operation, that is, at high temperatures. The dashed line in the figure is a reference line showing the direction of warping.

The configuration shown in FIG. 39 is the same as that described in the preceding embodiment (see FIG. 5). For convenience, the external connection terminal 90 is omitted in FIG. 39. In FIG. 39, the semiconductor device 20 and the heat exchanger 121 of the cooler 120 are arranged side by side in the Z direction, which is a predetermined direction. The heat exchanger 121 is arranged on both sides of the semiconductor device 20 in the Z direction so as to sandwich the semiconductor device. A heat conductive member 130 such as silicone gel is arranged between each of the heat exchanger 121 and the semiconductor device 20. The cooler 120 cools the semiconductor device 20 by circulating a refrigerant in the flow path of the heat exchanger 121. As the refrigerant flowing in the flow path, a refrigerant that changes phase, such as water or ammonia, or a refrigerant that does not change phase, such as an ethylene glycol-based refrigerant, can be used. The heat conductive member 130 is sometimes called a thermal interface material (TIM). The heat conductive member 130 follows the opposing surfaces of the heat exchanger 121 and the semiconductor device 20 and fills the gap between the opposing surfaces.

As described above, in the semiconductor element 40, the drain electrode 40D, which is the main electrode on the high potential side, has a larger electrode area than the source electrode 40S, which is the main electrode on the low potential side. In addition, a conductive spacer 70 is interposed between the source electrode 40S and the substrate 60, whereas a conductive spacer 70 is not interposed between the drain electrode 40D and the substrate 50. In other words, the thermal resistance of the heat transfer path from the semiconductor element 40 to the substrate 50 is smaller than that of the heat transfer path from the semiconductor element 40 to the substrate 60. In a semiconductor device 20 configured in this way, it is required to effectively dissipate heat to the substrate 50 side.

When warping occurs with the substrate 50 side concave and the substrate 60 side convex as shown in FIG. 39, the distance between the exposed back surface 50b of the substrate 50 and the heat exchanger 121 becomes longer, and the intervening heat conductive member 130 becomes thicker. This increases the thermal resistance between the substrate 50 and the heat exchanger 121, making it difficult to transfer heat (exchange heat) between the semiconductor device 20 and the cooler 120 (heat exchanger 121). The warping state shown in FIG. 39 is not preferable for effectively releasing the heat of the semiconductor element 40, that is, for efficiently cooling the semiconductor device 20. FIG. 39 shows an example of a double-sided cooling structure in which the cooler 120 (heat exchanger 121) is arranged on both sides of the semiconductor device 20. However, a single-sided cooling structure in which the cooler 120 is arranged only on the substrate 50 side in the Z direction also has the same problem.

<Structure of Semiconductor Device>
Through careful investigation, it has become clear that the warpage of the semiconductor device 20 can be controlled by controlling the thickness relationship between the portion of the semiconductor device 20 closer to the substrate 50 than the semiconductor element 40 and the portion of the semiconductor device 20 closer to the substrate 60. The semiconductor device 20 of this embodiment has a configuration based on this finding. Fig. 40 is a cross-sectional view showing the semiconductor device 20 of this embodiment. Fig. 40 shows an ideal state in which the semiconductor device 20 is free of warpage.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). Like Figure 39, Figure 40 shows the heat exchange section 121 of the cooler 120 and the heat conduction member 130 along with the semiconductor device 20. That is, Figure 40 shows a semiconductor module 140 including the semiconductor device 20, the cooler 120, and the heat conduction member 130. As an example, the semiconductor module 140 has a double-sided cooling structure in which the semiconductor device 20 is sandwiched between a pair of heat exchange sections 121. The semiconductor device 20 is arranged alongside the cooler 120 (heat exchange section 121) in the Z direction, which is a predetermined direction. The coolers 120 are arranged on both sides of the semiconductor device 20.

The rear surface metal bodies 53, 63 are exposed from the sealing body 30 as the rear surfaces 50b, 60b of the substrates 50, 60. One of the heat exchange sections 121 of the cooler 120 is disposed facing one surface 30a and the rear surface 50b of the sealing body 30, and the other of the heat exchange sections 121 is disposed facing the rear surfaces 30b and 60b of the sealing body 30. A heat conductive member 130 is disposed between the opposing surfaces of the semiconductor device 20 and the heat exchange section 121. The heat conductive member 130 is in close contact with the semiconductor device 20 and the heat exchange section 121.

The semiconductor device 20 is configured such that the thickness T1 on the substrate 50 side of the semiconductor element 40 and the thickness T2 on the substrate 60 side of the semiconductor element 40 satisfy the relationship T1 ≧ T2. The other configurations are the same as those described in the preceding embodiment (see FIG. 5). The thickness T1 is the total thickness of the bonding material 101, the conductive spacer 70, the bonding material 102, and the substrate 60. The thickness T2 is the total thickness of the bonding material 100 and the substrate 50. Since the relationship T1 ≧ T2 is satisfied, the substrate 50 is thicker than the substrate 60. The substrate 50 is thicker than the conductive spacer 70. In the substrate 50, the metal bodies 52 and 53 are thicker than the insulating substrate 51. In the substrate 60, the metal bodies 62 and 63 are thicker than the insulating substrate 61. The configurations of the parts other than the thickness relationship are the same as those described in the first embodiment.

<Simulation results>
41 to 43 show the results of thermal stress simulation. FIG. 41 shows the state of the semiconductor device 20 shown in FIG. 40 at room temperature (RT). FIG. 42 shows the state of the semiconductor device 20 shown in FIG. 40 at high temperature. At high temperature, the semiconductor element 40 generates heat due to current flow, that is, when the semiconductor element 40 is in operation. As shown in FIG. 41 and FIG. 42, warping occurs in the semiconductor device 20 at high temperature. In this embodiment, since the relationship T1≧T2 is satisfied as described above, the expansion amount on the substrate 50 side is larger than the expansion amount on the substrate 60 side, as shown by the dashed arrow in FIG. 42. This is because the linear expansion coefficient of Cu constituting the metal bodies 52, 53, 62, and 63 is the largest, and the substrate 50 is thick. As a result, a convex warp occurs on the substrate 50 side, which is the first substrate, and a concave warp occurs on the substrate 60 side, which is the second substrate. The dashed line in FIG. 42 is a reference line indicating the direction of warping.

Figure 43 shows the relationship between the ratio of thicknesses T1 and T2 and the amount of warping at high temperatures. In this simulation, the semiconductor element 40, conductive spacer 70, and bonding materials 100, 101, and 102 were all the same (common), and the thicknesses of the substrate 50 and substrate 60 were adjusted so that the thickness ratio T1:T2 was a predetermined value. The material configuration was all the same (common). The vertical axis in Figure 43 shows the amount of warping, and is in arbitrary units (a.u.). The amount of warping above 0 (zero) indicates that the warping is convex toward the substrate 50 side and concave toward the substrate 60 side, and below 0 (zero) indicates that the warping is concave toward the substrate 50 side and convex toward the substrate 60 side. T1:T2 was set to four levels: 1:2, 1:1.3, 1:1, and 1.5:1.

As shown in Figure 43, when T1:T2 = 1:2, concave warping occurred on the substrate 50 side and convex warping occurred on the substrate 60 side, with the amount of convex warping on the substrate 60 side being the largest among the four levels. When T1:T2 = 1:1.3, concave warping occurred on the substrate 50 side and convex warping on the substrate 60 side, with the amount of convex warping on the substrate 60 side being smaller than that of T1:T2 = 1:2. When T1:T2 = 1:1, the warping changed to convex warping on the substrate 50 side and concave warping on the substrate 60 side. When T1:T2 = 1.5:1, convex warping occurred on the substrate 50 side and concave warping on the substrate 60 side, with the amount of convex warping on the substrate 50 side being the largest among the four levels.

Thus, it was revealed that when T1<T2, concave warping occurs on the substrate 50 side and convex warping occurs on the substrate 60 side, and when T1≧T2, convex warping occurs on the substrate 50 side and concave warping occurs on the substrate 60 side. In other words, it was revealed that by satisfying the relationship T1≧T2, it is possible to control the warping that occurs at high temperatures to be convex on the substrate 50 side and concave on the substrate 60 side. It was also revealed that the greater T2 is relative to T1, the greater the amount of convex warping on the substrate 60 side, and the greater T1 is relative to T2, the greater the amount of convex warping on the substrate 50 side.

<Summary of the Third Embodiment>
In this embodiment, the semiconductor device 20 satisfies the above-mentioned relationship of thickness T1 ≧ thickness T2. The thickness T1 on the side where the conductive spacer 70 is not interposed between the semiconductor element 40 and the substrate 50 is equal to or greater than the thickness T2 on the side where the conductive spacer 70 is interposed between the semiconductor element 40 and the substrate 60. As a result, when the semiconductor element 40 is in operation (at high temperature), the semiconductor device 20 is warped in a convex manner toward the substrate 50 side and a concave manner toward the substrate 60 side. Therefore, the facing distance between the semiconductor device 20 and the cooler 120 (heat exchange section 121) on the substrate 50 side, which has a high contribution rate to heat dissipation, can be narrowed compared to a configuration that satisfies the relationship of thickness T1 < thickness T2. Since the facing distance is narrowed, the thermal resistance between the semiconductor device 20 and the cooler 120 is reduced. As a result, the heat generated by the semiconductor element 40 can be efficiently released to the outside of the semiconductor device 20. In other words, the cooling efficiency of the semiconductor device 20 can be improved.

Specifically, the thickness of the thermally conductive member 130 interposed between the semiconductor device 20 and the cooler 120 is thinner than in a configuration that satisfies the relationship of thickness T1 < thickness T2. This reduces the thermal resistance between the semiconductor device 20 and the cooler 120, making it easier to exchange heat between the semiconductor device 20 and the cooler 120. Therefore, the heat generated by the semiconductor element 40 can be efficiently released to the outside of the semiconductor device 20.

In this embodiment, the rear surface metal body 53 is exposed from the sealing body 30. Compared to a configuration in which the rear surface metal body 53 is covered by the sealing body 30, heat dissipation can be improved. Similarly, the rear surface metal body 63 is exposed from the sealing body 30. Compared to a configuration in which the rear surface metal body 63 is covered by the sealing body 30, heat dissipation can be improved.

<Modification>
Although an example of a double-sided heat dissipation structure is shown, the present invention is not limited to this. It is desired that the semiconductor device 20 efficiently dissipates heat mainly from the substrate 50 side. Therefore, the cooler 120 (heat exchange section 121) may be arranged only on the substrate 50 side in the Z direction with respect to the semiconductor device 20. Even in such a single-sided heat dissipation structure, by satisfying the relationship T1≧T2, a convex warp is formed on the substrate 50 side at high temperatures. This reduces the thermal resistance between the semiconductor device 20 and the cooler 120. Therefore, the heat generated by the semiconductor element 40 can be efficiently dissipated.

Although an example in which both rear surface metal bodies 53 and 63 are exposed from the sealing body 30 has been shown, this is not limiting. For example, a configuration in which only the rear surface metal body 53 is exposed may also be used.

The semiconductor device 20 has an example in which it includes a semiconductor element 40H that constitutes the upper arm 9H and a semiconductor element 40 that constitutes the lower arm 9L, but is not limited to this. It may include only a semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40. The semiconductor device 20 may include a semiconductor element 40, a pair of substrates 50, 60 arranged to sandwich the semiconductor element 40, and a conductive spacer 70 interposed between the semiconductor element 40 and the substrate 60.

No particular mention was made of the relationship between the thicknesses of the metal bodies 52, 53 in the substrate 50. For example, as shown in FIG. 44, the front surface metal body 52 may be made thicker than the back surface metal body 53. The drain electrode 40D, which is the first main electrode of the semiconductor element 40, is joined to the front surface metal body 52. The thermal resistance between the front surface metal body 52 and the semiconductor element 40 is small. By making the front surface metal body 52 closer to the semiconductor element 40 thicker, the heat generated by the semiconductor element 40 can be effectively diffused. In other words, the heat of the semiconductor element 40 can be efficiently dissipated. FIG. 44 is a cross-sectional view showing a modified example. FIG. 44 corresponds to FIG. 41.

As shown in FIG. 44, the front metal body 62 may be made thicker than the back metal body 63. By making the front metal body 62 closer to the semiconductor element 40 thicker, the heat generated by the semiconductor element 40 can be diffused more effectively.

As described above, the heat of the semiconductor element 40 having main electrodes on both sides is mainly transferred to the substrate 50 side, which has a smaller thermal resistance. For this reason, as shown in FIG. 45, the front metal body 62 may be made thinner than the back metal body 63. This makes it possible to reduce the thickness of the substrate 60 and thus the size of the semiconductor device 20. Since a thick metal body is not required, costs can also be reduced. FIG. 45 is a cross-sectional view showing a modified example. FIG. 45 corresponds to FIG. 44. In FIG. 45, the front metal body 52 is thicker than the back metal body 53, and the front metal body 62 is thinner than the back metal body 63. Therefore, it is possible to efficiently dissipate heat from the semiconductor element 40 while achieving a smaller size and lower costs.

The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment, second embodiment, and modified example.

Fourth Embodiment
This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve connection reliability, the substrate and the signal terminals may be arranged to satisfy a predetermined positional relationship as described in this embodiment.

<Semiconductor Device>
First, the semiconductor device 20 of this embodiment will be described with reference to Fig. 46 and Fig. 47. Fig. 46 shows the periphery of the signal terminal 93 in the semiconductor device 20 of this embodiment. In Fig. 46, some of the elements of the semiconductor device 20 are omitted in order to show the positional relationship between the substrate 50 and the signal terminal 93. Fig. 47 is a cross-sectional view taken along line XLVII-XLVII in Fig. 46. In Figs. 46 and 47, the signal terminal 93L on the lower arm 9L side will be described as an example.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 46, the semiconductor device 20 has two semiconductor elements 40L. The semiconductor element 40L has a drain electrode 40D, which is a first main electrode, on one side, and a source electrode 40S, which is a second main electrode, and a signal pad 40P on the back side. The semiconductor device 20 has four signal terminals 93L. Each signal terminal 93L extends in the Y direction and protrudes to the outside from the side surface 30d of the sealing body 30. The four signal terminals 93L are arranged in a line in the X direction between the output terminals 92 when viewed in a plan view in the Z direction.

<Shape and arrangement of signal terminals>
Next, the shape and arrangement of the signal terminals 93 will be described with reference to FIGS.

As shown in FIG. 46, each signal terminal 93L has an overlapping portion 930 that overlaps with the substrate 50 in a plan view, and a non-overlapping portion 931 that does not overlap with the substrate 50. The overlapping portion 930 faces the substrate 50 in the Z direction.

The overlapping portion 930 is a portion of the signal terminal 93L within a predetermined range from the end on the semiconductor element 40L side. The non-overlapping portion 931 is the portion excluding the overlapping portion 930. The overlapping portion 930 overlaps the insulating base material 51 of the substrate 50 to which the drain electrode 40D is electrically connected. The entire overlapping portion 930 overlaps the insulating base material 51. The overlapping portion 930 overlaps the exposed portion 510 exposed from the surface metal body 52 of the insulating base material 51. In this way, the signal terminal 93L is extended onto the substrate 50. In other words, the signal terminal 93L is inserted and positioned to a position where it overlaps the substrate 50 in a plan view.

Of the four signal terminals 93L, the overlapping portion 930 of two signal terminals 93L has a main portion 930a and a protruding portion 930b. The other two signal terminals 93L do not have a protruding portion 930b. The main portion 930a extends in the Y direction, which is the main extension direction of the signal terminal 93L. The protruding portion 930b is connected to the main portion 930a and protrudes from the main portion 930a. The protruding portion 930b extends in a direction different from that of the main portion 930a. The protruding portion 930b is sometimes called a branch portion. The planar shape of the main portion 930a can be various shapes such as a planar approximately L-shape, a planar approximately Y-shape, or a planar approximately T-shape. In the example shown in FIG. 46, one of the signal terminals 93L is planar approximately L-shaped, and the other signal terminal 93L is planar approximately T-shaped.

As described in the previous embodiment (see FIG. 11), the relay wiring 55 of the surface metal body 52 has a notch 550. The overlapping portion 930 of the signal terminal 93L overlaps with the portion of the insulating substrate 51 exposed from the notch 550. The four signal terminals 93L are arranged in a line in the X direction between the output terminals 92 in a plan view. Each signal terminal 93L has a tie bar mark 93a. As described in the previous embodiment (see FIG. 10), the tie bar mark 93a is a mark left on the side of the signal terminal 93L when the tie bar 94a of the lead frame 94 is cut off. The tie bar mark 93a is sometimes called a cut mark. Each signal terminal 93L has a tie bar mark 93a on both side surfaces in the X direction. The tie bar mark 93a is provided in the non-overlapping portion 931 at an external position of the sealing body 30.

As shown in FIG. 47, each signal terminal 93L has a joint 93b, a tip 93c, a bent portion 93d, and an extension 93e. The joint 93b is a portion to which a bonding wire 110, which is a connecting member, is joined. The joint 93b preferably includes a portion that is approximately parallel to the XY plane. The joint 93b is the portion of the signal terminal 93L that is closest to the surface of the insulating substrate 51 (exposed portion 510). In this embodiment, the joint 93b is floating with respect to the surface of the insulating substrate 51. The joint 93b is not in contact with the insulating substrate 51, and the sealing body 30 fills the gap between the lower surface of the joint 93b and the surface of the insulating substrate 51. The bonding wire 110 electrically connects the pad 40P formed on the same surface as the source electrode 40S to the signal terminal 93L.

The tip 93c is located on the tip side of the joint 93b, that is, on the semiconductor element 40 (40L) side. The tip 93c is located above the joint 93b, that is, at a position farther from the surface of the insulating substrate 51 in the Z direction. The tip 93c rises upward as it moves away from the joint 93b. The tip 93c has an R-shape in the ZY cross section. The bent portion 93d is provided between the joint 93b and the extension portion 93e, which is a portion on the rear end side of the joint 93b. The bent portion 93d is bent so that the extension portion 93e is located above the joint 93b, that is, away from the surface of the insulating substrate 51. The bent portion 93d has a smaller cross-sectional area than other portions of the signal terminal 93, specifically the joint 93b, the tip 93c, and the extension portion 93e, due to the bending process. In other words, it is thin. The extension portion 93e is a portion on the rear end side of the joint 93b. The extension portion 93e extends in the Y direction and is disposed on both the inside and outside of the sealing body 30.

At least a portion of the joint portion 93b, the tip portion 93c, and the bent portion 93d are included in the overlapping portion 930 described above. At least a portion of the extension portion 93e is included in the non-overlapping portion 931. In this embodiment, the entire extension portion 93e is included in the non-overlapping portion 931. Each signal terminal 93L is formed by press punching. In the signal terminal 93L, the surface facing the insulating substrate 51 is the press R surface 93f, and the back surface of the facing surface is the burr surface 93g where burrs are generated by punching. The configuration other than the above is the same as the configuration described in the first embodiment.

<Bonding wire connection method>
Next, a method of connecting the signal terminal 93 having the above-mentioned structure to the bonding wire 110 will be described with reference to Fig. 48. Fig. 48 is a diagram for explaining wire bonding. Reference numeral 111 shown in Fig. 48 denotes a jig for holding the signal terminal 93L. Reference numeral 112 denotes a tool for ultrasonic bonding. The tool 112 is sometimes called an ultrasonic bonding device. The dashed line shown in Fig. 48 indicates the position of the signal terminal 93L that is bent by being pressed by the jig 111.

As shown in FIG. 48, first, the overlapping portion 930 of the signal terminal 93L is positioned so as to overlap the insulating substrate 51, and the wire 110a is set in the portion to be joined. Then, pressure is applied in the Z direction by the jig 111 to elastically deform the signal terminal 93L, and the overlapping portion 930 is brought into contact with the surface of the insulating substrate 51. The jig 111 presses the overlapping portion 930 of the signal terminal 93L or the vicinity thereof.

Then, with the signal terminal 93L in contact with the insulating base material 51, ultrasonic bonding is performed using the tool 112. Because the signal terminal 93L is received by the insulating base material 51, a separate receiving jig is not required. When ultrasonic bonding is completed and the tool 112 and jig 111 are released from the signal terminal 93L, the signal terminal 93L is released from its elastically deformed state and returns to the position it was in before pressure was applied. The signal terminal 93L is part of the lead frame 94. Because the signal terminal 93L is supported by the tie bar 94a on the outer frame 94b, it returns to its original position when pressure is released.

The above description has been given using the signal terminal 93L as an example. However, the above configuration may also be applied to the signal terminal 93H on the upper arm 9H side. Both signal terminals 93H and 93L may have the above configuration. In the configuration described in the previous embodiment (see FIG. 11), each of the signal terminals 93H and 93L overlaps the exposed portion of the insulating substrate 51. The P wiring 54 of the surface metal body 52 has a notch 540, and the signal terminal 93H overlaps the surface of the insulating substrate 51 exposed from the notch 540.

<Summary of the Fourth Embodiment>
In this embodiment, the signal terminal 93 (93L) overlaps the exposed portion 510 of the insulating base material 51. However, the signal terminal 93 is not bonded to the exposed portion 510. That is, the signal terminal 93 is not fixed to the insulating base material 51, and thus to the substrate 50. This allows the signal terminal 93 to absorb dimensional variations within the tolerances of the elements constituting the semiconductor device 20, as well as assembly variations when assembling the elements. Therefore, during molding of the sealing body 30, it is possible to suppress stress concentration on the electrical connection portion (joint portion) of the signal terminal 93 with the semiconductor element 40. As a result, it is possible to provide a semiconductor device 20 with high connection reliability.

In this embodiment, the signal terminal 93 is inserted and positioned up to a position where it overlaps the substrate 50, that is, onto the substrate 50. By adopting such a positioning, the signal terminal 93 approaches the pad 40P of the semiconductor element 40 (40L) in the Y direction. Therefore, the length of the bonding wire 110, which is the connecting member, can be made shorter than in a configuration in which the signal terminal 93 is positioned only at a position where it does not overlap the substrate 50. Since the length of the bonding wire 110 can be made shorter, it is possible to suppress the occurrence of wire sweep, short circuits due to wire sweep, wire breakage, etc., when molding the sealing body 30 by a transfer molding method or the like.

In this embodiment, the overlapping portion 930 of the signal terminal 93 is floating above the surface of the exposed portion 510 of the insulating base material 51. The sealing body 30 is interposed between the lower surface of the overlapping portion 930 and the surface of the exposed portion 510. The sealing body 30 is also interposed between the joint portion 93b and the exposed portion 510. This makes it possible to absorb the manufacturing variation even if there is a large variation in the plate thickness direction. In addition, since the signal terminal 93 is located above the insulating base material 51, it is easy to ensure an insulating distance from the back metal body 53.

In this embodiment, the surface metal body 52 has a notch 550 (540). The notch 550 opens at an end in the Y direction, which is a direction perpendicular to the Z direction. The overlapping portion 930 of the signal terminal 93 overlaps the surface of the exposed portion 510 exposed from the notch 550. In this way, by providing the notch 550 in the surface metal body 52 of the substrate 50, it is possible to suppress an increase in the size of the substrate 50 while ensuring the insulation distance between the surface metal body 52 and the signal terminal 93.

In this embodiment, the non-overlapping portion 931 of the signal terminal 93 has a tie bar mark 93a. As described above, the signal terminal 93L is part of the lead frame 94, and is supported by the tie bar 94a on the outer frame 94b. Therefore, the signal terminal 93 is bent by applying pressure and brought into contact with the exposed portion 510 of the insulating substrate 51, and in this contact state, the bonding wire 110 can be joined by ultrasonic bonding. Then, by releasing the pressure after joining is completed, the signal terminal 93 returns to its original position.

In this embodiment, the signal terminal 93 has a bent portion 93d between the joint portion 93b and the extension portion 93e. The bent portion 93d positions the extension portion 93e at a position farther from the exposed portion 510 (insulating substrate 51) in the Z direction than the joint portion 93b. By having the bent portion 93d in this manner, it is possible to ensure the insulation distance between the signal terminal 93 and the back metal body 53 while suppressing an increase in size in the Z direction.

In this embodiment, the signal terminal 93 has a tip 93c. The tip 93c is farther from the exposed portion 510 (insulating substrate 51) in the Z direction than the joint 93b. This makes it possible to prevent the tip of the signal terminal 93 from scratching the insulating substrate 51 during the above-mentioned joining (ultrasonic joining) and the like. In other words, it is possible to prevent the insulation performance from deteriorating. In particular, in this embodiment, the tip 93c is raised upward as it moves away from the joint 93b, so that the tip 93c is less likely to come into contact with the insulating substrate 51. In addition, since the tip 93c has an R-shape in the ZY cross section, even if it does come into contact, it is possible to prevent the insulating substrate 51 from being scratched.

If the opposing surface is a burr surface 93g, the insulating base material 51 may be scratched, and the insulating performance may be reduced. In this embodiment, the signal terminal 93 is configured so that the surface facing the exposed portion 510 is a pressed R surface 93f, and the back side of the opposing surface is a burr surface 93g. This makes it possible to prevent the insulating performance of the insulating base material 51 from being reduced.

<Modification>
The non-bonding configuration between the signal terminal 93 and the exposed portion 510 is not limited to the above example. For example, in FIG. 49, the overlapping portion 930 of the signal terminal 93 is floating above the insulating base material 51 with a slight gap between the overlapping portion 930 and the surface of the exposed portion 510 so that the sealing body does not enter. The sealing body 30 has a gap 31 between the lower surface of the overlapping portion 930 and the surface of the exposed portion 510. The signal terminal 93 is not fixed to the insulating base material 51 (exposed portion 510). Therefore, the same effect as the configuration shown in FIG. 47 can be achieved. FIG. 49 is a cross-sectional view showing a modified example, and corresponds to FIG. 47.

In FIG. 50, the overlapping portion 930 of the signal terminal 93 is in contact with the surface of the exposed portion 510. Although the signal terminal 93 is in contact with the insulating substrate 51 (exposed portion 510), it is not fixed. Therefore, it is possible to achieve the same effect as the configuration shown in FIG. 47. FIG. 50 is a cross-sectional view showing a modified example, and corresponds to FIG. 47. Note that it is also possible to arrange the joint 93b so that a portion of the lower surface is in contact with the insulating substrate 51, and the other portion is not in contact.

In the example shown in FIG. 47, the substrate 60 is arranged so as not to overlap the signal terminal 93 in a plan view. In other words, the substrate 60 is not arranged above the signal terminal 93. By adopting such an arrangement, the size of the substrate 60 can be reduced. In addition, it is easier to ensure the insulation distance between the surface metal body 62 and the signal terminal 93. However, the positional relationship between the signal terminal 93 and the substrate 60 is not limited to the example shown in FIG. 47. For example, as shown in FIG. 51, the overlapping portion 930 of the signal terminal 93 also overlaps with the substrate 60. The surface metal body 62 of the substrate 60 overlaps with the overlapping portion 930 and the exposed portion 510 of the insulating base material 51 in a plan view. This can improve heat dissipation. FIG. 51 is a cross-sectional view showing a modified example, and corresponds to FIG. 47.

In FIG. 52, in contrast to FIG. 51, the front metal body 62 is patterned so as not to overlap the overlapping portion 930 of the signal terminal 93. The insulating substrate 61 and the back metal body 63 are located above the overlapping portion 930. By making the front metal body 62 smaller, it becomes easier to ensure the insulation distance between the front metal body 62 and the signal terminal 93. Since the back metal body 63 is large, heat dissipation can be improved. FIG. 52 is a cross-sectional view showing a modified example, and corresponds to FIG. 47.

The example shows how the length of the bonding wire 110 (connecting member) can be shortened by inserting the signal terminal 93 into the substrate 50. Alternatively, the length of the bonding wire 110 can be shortened by using the relay substrate 150 shown in Figs. 53 to 55. Fig. 53 is a plan view showing a modified example, and corresponds to Fig. 46. In Fig. 53, some of the elements of the semiconductor device 20 are omitted in order to show the positional relationship between the substrate 50, the signal terminal 93, and the relay substrate 150. Fig. 54 is a cross-sectional view showing the relay substrate. Fig. 55 is a cross-sectional view taken along the line LV-LV in Fig. 53. Here, the relay wiring 55 and the signal terminal 93L are shown as an example, but the same configuration can also be adopted for the P wiring 54 and the signal terminal 93H.

The semiconductor device 20 further includes a relay board 150. As shown in Figs. 53 and 55, the relay board 150 is disposed on the surface metal body 52 (relay wiring 55) of the board 50. As shown in Fig. 54, the relay board 150 has an insulating substrate 151 and a conductor portion 152 disposed on the insulating substrate 151. A portion of the conductor portion 152 provides a wiring function. The relay board 150 is sometimes referred to as a printed circuit board or a wiring board.

The conductor portion 152 has lands 152a and 152b. The lands 152a and 152b are exposed on one surface of the relay substrate 150. Specifically, they are exposed from a solder resist 153 provided on one surface 151a of the insulating substrate 151. The land 152a is electrically connected to the pad 40P via a bonding wire 110. The signal terminal 93 overlaps with the substrate 50 in a plan view. The signal terminal 93 is connected to the land 152b.

The conductor portion 152 has wiring 152c and via conductor 152d other than the lands 152a and 152b. At least a part of the wiring 152c is an inner layer wiring arranged inside the insulating substrate 151. The lands 152a and 152b are electrically connected via the wiring 152c and the via conductor 152d. The multiple lands 152a include two lands 152a individually connected to pads 40P for the gate electrodes of the two semiconductor elements 40. The two lands 152a for the gate electrodes are electrically connected to one land 152b for the gate electrode via the wiring 152c and the via conductor 152d.

In this way, by using the relay board 150, the connection target (land 152a) of the bonding wire 110 can be brought closer to the pad 40P. This allows the length of the bonding wire 110 that electrically connects the pad 40P and the signal terminal 93 to be shortened. In addition, the wiring 152c can be freely routed within the relay board 150. This makes it possible to prevent the bonding wires 110 from crossing in a configuration in which the semiconductor elements 40 are connected in parallel. Therefore, it is possible to prevent the wires from contacting each other when the sealing body 30 is molded. In addition, by using fine wiring technology for printed circuit boards, it is possible to achieve a size reduction to the same extent as the configuration shown in FIG. 47.

The conductor portion 152 further has a fixing land 152e. The fixing land 152e is a land for fixing the relay board 150 to the board 50. The fixing land 152e does not provide an electrical connection function, i.e., a wiring function. The fixing land 152e is disposed on the back surface 151b of the insulating base material 151. The fixing land 152e (relay board 150) is joined to the front metal body 52 via a joining material 154. For example, solder can be used as the joining material 154.

In this way, the relay substrate 150 is fixed to the front metal body 52, so wire bonding can be performed stably. Solder containing Ni balls may be used as the bonding material 154. In this case, the Ni balls can be used to control the thickness of the bonding material 154. In addition, the inclination of the relay substrate 150 can be suppressed.

The wiring function provided by the conductor portion 152 is electrically separated from the surface metal body 52 by the insulating base material 151. For example, the insulating base material 151 may have a non-placement area 151c in which the conductor portion 152 is not placed, and a placement area 151d in which the conductor portion 152 is placed, in the Z direction. In the Z direction, the non-placement area 151c is provided in the center of the insulating base material 151, and the placement area 151d is provided on the surface layer on both sides. The non-placement area 151c is sometimes referred to as a core layer. In this way, by the insulating base material 151 having the non-placement area 151c, the conductor portion 152 that provides the wiring function and is placed on the one surface 151a side can be electrically separated from the fixing land 152e and therefore the surface metal body 52.

The solder resist 153 has low adhesion to the sealing body 30. Also, peeling of the sealing body 30 due to thermal stress progresses from the outer peripheral edge of the relay substrate 150. For example, the insulating base material 151 may have an exposed portion 151e exposed from the solder resist 153. The exposed portion 151e is provided on the outer peripheral edge of one surface 151a of the insulating base material 151. The insulating base material 151 has higher adhesion to the sealing body 30 than the solder resist 153. In the exposed portion 151e, the sealing body 30 is in close contact with the relay substrate 150. This makes it possible to suppress peeling of the sealing body 30 from the relay substrate 150. Since the sealing body 30 is in close contact with the outer peripheral edge, the conductor portions 152 such as the lands 152a and 152b exposed from the solder resist 153 can be protected.

As shown in FIG. 55, the signal terminal 93 (93L) has a first extension portion 93h, a second extension portion 93i, and a bent portion 93j. The first extension portion 93h and the second extension portion 93i extend in the Y direction. The first extension portion 93h is disposed inside the sealing body 30. The second extension portion 93i is disposed both inside and outside the sealing body 30. The bent portion 93j is disposed between the first extension portion 93h and the second extension portion 93i. The first extension portion 93h is a portion closer to the tip end than the bent portion 93j, and the second extension portion 93i is a portion closer to the rear end than the bent portion 93j.

The signal terminal 93 may have a protrusion 93k. The protrusion 93k is provided near the tip of the signal terminal 93. The protrusion 93k protrudes from the first extension 93h toward the land 152b in the Z direction. The protrusion 93k is joined to the land 152b. In the signal terminal 93, the tip of the first extension 93h and the protrusion 93k overlap with the land 152b in a plan view in the Z direction. The portion where the tip of the first extension 93h and the protrusion 93k are connected is a thick portion, and the other portion of the signal terminal 93 is a thin portion. By providing the protrusion 93k in this manner, the signal terminal 93 (first extension 93h) is moved away from the surface metal body 52, making it easier to ensure an insulation distance between the surface metal body 52.

Figure 56 shows another example different from Figure 54. Figure 56 corresponds to Figure 54. In Figure 56, the relay board 150 is fixed to the exposed portion 510 of the insulating base material 51. In this case, the thickness of the bonding material 154 and the relay board 150 ensures the insulation distance between the signal terminal 93 and the rear metal body 53. If the solder containing Ni balls described above is used as the bonding material 154, a predetermined thickness can be ensured, making it easier to ensure the insulation distance. In addition, the inclination of the relay board 150 can be suppressed.

The surface metal body 52 (relay wiring 55) has a notch 550 as shown in FIG. 46, for example, to expose the insulating base material 51. For example, the surface metal body 52 may have a chamfered portion 554. The chamfered portion 554 is provided at least on the surface of the end face that defines the notch 550, where an imaginary straight line connecting the semiconductor element 40 and the relay substrate 150 intersects. The chamfered portion 554 is provided at the upper end of the end face. This ensures an insulating distance between the bonding wire 110 and the surface metal body 52.

An example has been shown in which the semiconductor device 20 includes a substrate 60 electrically connected to the source electrode 40S. In other words, an example of a semiconductor device 20 with a double-sided heat dissipation structure including a pair of substrates 50, 60 has been shown. However, this is not a limitation. It is also possible to apply to a semiconductor device 20 with a single-sided heat dissipation structure that includes only a substrate 50 to which a drain electrode 40D (first main electrode) is connected. Although an example has been shown in which both rear surface metal bodies 53, 63 are exposed from the sealing body 30, this is not a limitation.

The semiconductor device 20 has an example in which it includes a semiconductor element 40H that constitutes the upper arm 9H and a semiconductor element 40 that constitutes the lower arm 9L, but is not limited to this. It may include only a semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, and third embodiments, and the modified examples.

Fifth Embodiment
This embodiment is a modification of the preceding embodiment as a basic form, and the description of the preceding embodiment can be used. In order to ensure insulation reliability while reducing the size, the connection between the metal member and the surface metal body via the bonding material may be of a predetermined structure as described in this embodiment.

<Semiconductor Device>
First, the semiconductor device 20 of this embodiment will be described with reference to Fig. 57. Fig. 57 corresponds to Fig. 5.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 57, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The surface metal body 52 is connected to the P terminal 91P, which is the main terminal, and the output terminal 92 via a bonding material 104. The surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The surface metal body 62 is connected to the N terminal 91N (not shown), which is the main terminal, via a bonding material 104. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, parts of the main terminals, and the bonding material 104.

<Main terminal joint structure>
Next, the joining structure of the main terminal will be described with reference to Figs. 57 to 60. Fig. 58 is a plan view of the periphery of the output terminal 92 in Fig. 57 as viewed from the LVIII direction. In Fig. 58, some parts are hatched for clarity. Fig. 59 is an enlarged view of the area LVIX shown by the dashed line in Fig. 57. Fig. 60 is a view showing a state in which the joining material 104 has been removed from Fig. 59. For convenience, the sealing body 30 is omitted in Figs. 59 and 60.

As shown in FIG. 57, the joining structure of the P terminal 91P, which is a main terminal, and the output terminal 92, with the substrate 50 is different from the configuration described in the preceding embodiment (see FIG. 5). Although not shown, the joining structure of the N terminal 91N, which is a main terminal, is also different. The other configurations are the same as those described in the preceding embodiment. The output terminal 92 will be used as an example below. The joining material 104 wets and spreads over the metal surface when joined. As an example, the joining material 104 is solder.

As shown in FIG. 57, the substrate 50 has ends 50c and 50d in the Y direction. End 50c is the end on the side surface 30c side of the sealing body 30, and end 50d is the end on the side surface 30d side. The output terminal 92 extends in the Y direction, straddling end 50d of the substrate 50. In a plan view in the Z direction, a portion of the output terminal 92 overlaps with the surface metal body 52 (relay wiring 55), and another portion does not overlap. As shown in FIGS. 58 to 60, the output terminal 92 has an opposing surface 920 and a housing portion 921.

The facing surface 920 is a portion of the lower surface of the output terminal 92 that faces the surface metal body 52 (relay wiring 55) of the substrate 50 in the Z direction. The facing surface 920 is a flat surface from a macroscopic perspective, and ideally the entire surface contacts the upper surface 52a of the surface metal body 52. The facing surface 920 has minute irregularities on its surface from a microscopic perspective, and at least a portion of it contacts the upper surface 52a. The facing surface 920 is sometimes referred to as a metal touch surface. In a plan view, the facing surface 920 is a portion of a predetermined range in the Y direction from a position where it overlaps with the end 52b of the surface metal body 52. The end 52b is an end surface (side surface) on the side of the side surface 30d of the sealing body 30 in the Y direction, and is continuous with the upper surface 52a. The end 52b forms a part of the end 50d. The facing surface 920 is approximately rectangular in plan view.

The storage section 921 is provided adjacent to the opposing surface 920 and provides a storage space for the bonding material 104. For example, the storage section 921 is a recess recessed in a direction away from the upper surface 52a with respect to the opposing surface 920. The recessed storage section 921 is a surface including a Z-direction component, and has a side surface 921a connected to the opposing surface 920 and a bottom surface 921b connected to the side surface 921a. The side surface 921a is, for example, a surface that is approximately parallel to the Z direction. The storage section 921 opens to a tip surface 922, which is a side surface on the front side of the output terminal 92 in the Y direction. The storage section 921 opens to side surfaces 923 and 924 on both sides of the output terminal 92 in the X direction. The storage section 921 is provided within a predetermined range from the tip surface 922 of the output terminal 92 in the Y direction. The storage section 921 has an approximately rectangular shape in plan view. The storage section 921 is provided in the Y direction in line with the X direction.

The output terminal 92 accommodates the bonding material 104 in the accommodation portion 921 with the opposing surface 920 in contact with the front surface metal body 52. The bonding material 104 may be disposed only in the accommodation portion 921, or as shown in FIG. 59, a portion of the bonding material 104 may be disposed outside the accommodation portion 921. In FIG. 59, the bonding material 104 forms a fillet with respect to the tip surface 922. The output terminal 92 is connected (joined) to the front surface metal body 52 via the bonding material 104 disposed in the accommodation portion 921.

<Main terminal joining method>
The joint structure between the output terminal 92 and the surface metal body 52 is formed, for example, as follows. With the joint material 104 (solder) placed in the accommodation portion 921, the upper portion of the opposing surface 920 of the output terminal 92 is pressed toward the substrate 50 in the Z direction so that the opposing surface 920 is in strong contact with the upper surface 52a. Reflow is performed with the opposing surface 920 in strong contact with the upper surface 52a. For this reason, the joint material 104 does not wet and spread toward the opposing surface 920 during reflow, or even if it does wet and spread, it only penetrates into the concaves of the minute concaves and convexes on the surface of the opposing surface 920.

<Summary of Fifth Embodiment>
In this embodiment, the opposing surface 920 of the output terminal 92, which is a metal member, comes into contact (metal touch) with the upper surface 52a of the front metal body 52. This makes it possible to suppress overflow of the bonding material 104 from the accommodation portion 921 to the opposing surface 920 side. This makes it possible to suppress the bonding material 104 from spreading wetly in unintended directions and ensure insulation reliability. In addition, the output terminal 92, which is a single member, has both the accommodation portion 921 and the opposing surface 920. As a result, it is possible to provide a semiconductor device 20 that can achieve both insulation reliability and a compact size.

In a configuration including a substrate 50, when the bonding material 104 spreads over the end 52b (end surface) of the front metal body 52 and the insulating substrate 51, the portion having the same potential as the front metal body 52 spreads, and the distance to the back metal body 53 becomes closer. There is a risk that the bonding material 104 may come into contact with the back metal body 53. In this embodiment, the opposing surface 920 is provided at a position closer to the end 50d of the substrate 50, that is, the end 52b of the front metal body 52, than the housing portion 921. By arranging the opposing surface 920 on the end 52b side, it is possible to prevent the bonding material 104 from spreading over the surface of the output terminal 92 and/or the front metal body 52 and reaching the end 52b and the insulating substrate 51. This makes it possible to improve insulation reliability without increasing the physical size.

As described above, the metal member having an opposing surface and a housing portion can also be applied to the other main terminals, the P terminal 91P and the N terminal 91N. The P terminal 91P is connected to the surface metal body 52 (P wiring 54) of the substrate 50 via the bonding material 104. The opposing surface of the P terminal 91P comes into contact with the surface metal body 52, thereby preventing the bonding material 104 from overflowing from the housing portion of the P terminal 91P to the opposing surface side. As shown in FIG. 57, by providing the opposing surface on the end portion 50c side of the substrate 50, the bonding material 104 can be prevented from spreading wet onto the end portion of the surface metal body 52 and the insulating substrate 51.

The N terminal 91N is connected to the surface metal body 62 (N wiring 64) of the substrate 60 via the bonding material 104. The opposing surface of the N terminal 91N comes into contact with the surface metal body 62, thereby preventing the bonding material 104 from overflowing from the accommodation portion of the N terminal 91N to the opposing surface side. In addition, by providing the opposing surface on the end 60c side of the substrate 60 shown in FIG. 57, the bonding material 104 can be prevented from spreading wet onto the end of the surface metal body 62 and the insulating base material 61. The end 60c is the end face (side face) on the side of the side 30c of the sealing body 30 in the Y direction.

<Modification>
The arrangement of the opposing surface 920 and the storage portion 921 is not limited to the above example. For example, the configurations shown in Figs. 61 and 62 may be adopted. Fig. 61 is a plan view showing a modified example and corresponds to Fig. 58. Fig. 62 is a plan view seen from the LXII direction shown in Fig. 61. In this example, the storage portion 921 does not open on the side surfaces 923 and 924, but only on the tip surface 922. The storage portion 921 has an opening 921c on the tip surface 922, which is a side surface.

The facing surface 920 has a first facing portion 920a and a second facing portion 920b. The first facing portion 920a is provided on the opposite side of the opening 921c with respect to the housing portion 921. In the Y direction, which is the extension direction of the output terminal 92, the first facing portion 920a is adjacent to the housing portion 921. The second facing portion 920b is adjacent to the housing portion in the X direction. In the example shown in FIG. 61 and FIG. 62, the facing surface 920 has a pair of second facing portions 920b. The pair of second facing portions 920b sandwich the housing portion 921 in the X direction. The facing surface 920 has a planar approximately U-shaped shape. Since the facing surface 920 is arranged on three sides with respect to the housing portion 921, the overflow direction of the bonding material 104 from the housing portion 921 can be limited to one direction on the opening 921c side. This can further improve the insulation reliability.

The opposing surface 920 may be configured to have only one second opposing portion 920b. In this case, the opposing surface 920 has a generally L-shaped planar shape. Since the opposing surface 920 is disposed on two sides of the storage portion 921, the overflow direction of the bonding material 104 from the storage portion 921 can be restricted with respect to the arrangement in FIG. 58. This can improve the insulation reliability.

Although an example in which the storage section 921 opens on the side surface of the output terminal 92 has been shown, this is not limiting. In addition, the planar shape of the storage section 921 is not limited to a substantially rectangular shape. For example, as shown in FIG. 63, a storage section 921 without an opening on the side surface may be provided. FIG. 63 is a plan view showing a modified example, and corresponds to FIG. 58. In FIG. 63, the storage section 921 has a substantially circular planar shape. The storage section 921 is a hole that opens on the lower surface of the output terminal 92. The storage section 921 shown in FIG. 63 is a non-through hole. The storage section 921, which is a non-through hole, has a side surface 921a and a bottom surface 921b that are continuous with the opposing surface 920, similar to the storage section 921 described above. Instead of this, a through hole that opens on the upper surface of the output terminal 92 may be adopted. The storage section 921, which is a through hole, does not have a bottom surface 921b, but has a side surface 921a.

The metal member having an opposing surface and a housing portion is not limited to a main terminal. For example, as shown in Figures 64 and 65, in a semiconductor device 20 constituting an upper and lower arm circuit 9, a joint portion 81 may be provided with an opposing surface and a housing portion. Figure 64 is a cross-sectional view showing a modified example, and corresponds to Figure 57. Figure 65 is an enlarged view of the area LXV indicated by the dashed line in Figure 64. For convenience, the sealing body 30 is omitted in Figure 65.

As described in the preceding embodiment, the semiconductor device 20 includes a semiconductor element 40H, which is a first semiconductor element constituting the upper arm 9H, and a semiconductor element 40L, which is a second semiconductor element constituting the lower arm 9L. The joint portion 81 electrically connects the source electrode 40S of the semiconductor element 40H and the drain electrode 40D of the semiconductor element 40L. The joint portion 81 is a metal column extending in the Z direction. An end portion 81a of the joint portion 81 is connected to the relay wiring 55, which is the first wiring of the substrate 50, via a bonding material 103. An end portion 81b opposite to the end portion 81a is connected to the relay wiring 65, which is the third wiring of the substrate 60, via a bonding material 103. The surface metal body 52 has a P wiring 54, which is the second wiring, provided with a predetermined interval between it and the relay wiring 55. The surface metal body 62 has an N wiring 64, which is the fourth wiring, provided with a predetermined interval between it and the relay wiring 65.

In the example shown in Figures 64 and 65, an opposing surface 810 and a storage portion 811 are provided at each of the ends 81a and 81b of the joint portion 81. The configurations of the opposing surface 810 and the storage portion 811 are similar to those of the opposing surface 920 and the storage portion 921 described above. At the end 81a, the opposing surface 810 faces the upper surface 52a of the surface metal body 52 (relay wiring 55). The opposing surface 810 is in contact with the upper surface 52a. The storage portion 811 is a recess that is recessed relative to the opposing surface 810. The storage portion 811 has a side surface 811a that is continuous with the opposing surface 810, and a bottom surface 811b. The storage portion 811 stores the bonding material 103.

The opposing surface 810 and the accommodation portion 811 are arranged side by side in the Y direction. The opposing surface 810 is arranged on the side of the wiring gap 52G that separates the relay wiring 55 and the P wiring 54, that is, in a position close to the P wiring 54, which is a different wiring from the relay wiring 55 to which the joint portion 81 is connected. The accommodation portion 811 opens to a side surface 812 of the joint portion 81 in the Y direction, and does not open to a side surface 813 opposite the side surface 812. The accommodation portion 811 may open only to the side surface 812, or may open to three side surfaces including the two side surfaces adjacent to the side surface 812.

In this way, the opposing surface 810 of the joint portion 81 comes into contact (metal touch) with the surface metal body 52. This makes it possible to prevent the bonding material 103 from overflowing from the housing portion 811 to the opposing surface 810. This makes it possible to provide a semiconductor device 20 that can achieve both insulation reliability and compact size.

Furthermore, when the bonding material 103 wets and spreads into the wiring gap 52G of the surface metal body 52, the portion having the same potential as the relay wiring 55 spreads, and the distance to the P wiring 54 becomes closer. There is a risk that the bonding material 103 may come into contact with the P wiring 54. In contrast, in the above example, the opposing surface 810 is provided at a position closer to the P wiring 54, i.e., the wiring gap 52G, than the accommodation portion 811. This makes it possible to prevent the bonding material 103 from reaching the wiring gap 52G. Therefore, it is possible to improve insulation reliability without increasing the physical size.

The configuration of the end 81b is the same as that of the end 81a. In the end 81b, the facing surface 810 faces the upper surface 62a of the surface metal body 62 (relay wiring 65). The facing surface 810 is in contact with the upper surface 52a. The accommodation portion 811 is a recess. The accommodation portion 811 accommodates the bonding material 103. The facing surface 810 and the accommodation portion 811 are arranged side by side in the Y direction. The facing surface 810 is provided on the side of the wiring gap 62G that separates the relay wiring 65 and the N wiring 64, that is, in a position close to the N wiring 64, which is a wiring different from the relay wiring 65 to which the joint portion 81 is connected. The accommodation portion 811 opens to the side surface 813 of the joint portion 81 in the Y direction, and does not open to the side surface 812. The accommodation portion 811 may open only to the side surface 813, or may open to three side surfaces including two side surfaces adjacent to the side surface 813.

In this way, the opposing surface 810 of the joint portion 81 comes into contact (metal touch) with the surface metal body 62. This makes it possible to prevent the bonding material 103 from overflowing from the accommodation portion 811 to the opposing surface 810. This makes it possible to provide a semiconductor device 20 that can achieve both insulation reliability and compact size. In addition, the opposing surface 810 is located closer to the N wiring 64, i.e., the wiring gap 62G, than the accommodation portion 811. This makes it possible to prevent the bonding material 103 from reaching the wiring gap 62G. This makes it possible to improve insulation reliability without increasing the size.

In the above example, overflow of the bonding material was suppressed by contact of the surface metal body with the opposing surfaces of the metal members. The function of suppressing overflow may be enhanced by further adding an uneven oxide film formed by laser irradiation to this configuration. An example is shown in Figures 66 and 67. Figure 66 is a cross-sectional view corresponding to Figure 65, and for convenience, the sealing body 30 is omitted. Figure 67 is an enlarged view of the area LXVII indicated by the dashed line in Figure 66, and only the surface metal body 52 is shown.

In the example shown in FIG. 66, uneven oxide films 520, 620 are provided on the surface metal bodies 52, 62, respectively, corresponding to the joint portion 81. The uneven oxide film 520 will be described below as an example. As shown in FIG. 67, the surface metal body 52 has a base material 521, a metal film 522 provided on the surface of the base material 521, and an uneven oxide film 520. The base material 521 forms the main part of the surface metal body 52. The base material 521 is formed using, for example, a Cu-based material. The metal film 522 is formed containing a material that is more wettable to solder than the base material 521. The metal film 522 is formed over the entire upper surface 52a. The metal film 522 in this embodiment is formed over the entire surface of the base material 521. The uneven oxide film 520 is formed locally on the upper surface 52a.

The uneven oxide film 520 is formed locally on the metal film 522 on the upper surface 52a by irradiating the metal film 522 with a laser beam. The metal film 522 has an undercoat film mainly composed of Ni (nickel) and an overcoat film mainly composed of Au (gold). In this embodiment, an electroless Ni plating film containing P (phosphorus) is used as the undercoat film. When the bonding material 103 is solder, the overcoat film (Au) of the metal film 522 exposed from the uneven oxide film 520 in the portion in contact with the bonding material 103 diffuses into the solder during reflow. The overcoat film (Au) of the metal film 522 in the portion where the uneven oxide film 520 is formed is removed by irradiation with a laser beam when the uneven oxide film 520 is formed. The uneven oxide film 520 is an oxide film mainly composed of Ni. For example, the components constituting the uneven oxide film 520 are 80% NI ₂ O ₃ , 10% NiO, and 10% Ni.

The recesses 523 on the surface of the metal film 522 are formed by irradiating a pulsed laser beam. One recess 523 is formed for each pulse. The uneven oxide film 520 is formed by melting, vaporizing, and depositing the surface portion of the metal film 522 by irradiating the laser beam. The uneven oxide film 520 is an oxide film derived from the metal film 522. The uneven oxide film 520 is a film of oxide of the metal (Ni), which is the main component of the metal film 522. The uneven oxide film 520 is formed following the unevenness of the surface of the metal film 522 having the recesses 523. The unevenness is formed on the surface of the uneven oxide film 520 at a pitch finer than the width of the recesses 523. In other words, very fine unevenness (roughened portion) is formed.

Such an uneven oxide film 520 can be formed by the process shown below. First, a pulsed laser beam is irradiated onto the upper surface 52a of the surface metal body 52, in which the metal film 522 is formed on the base material 521, to melt and evaporate the surface of the metal film 522. The pulsed laser beam is adjusted so that the energy density is greater than 0 J/ ^cm2 and less than or equal to 100 J/ ^cm2 , and the pulse width is less than or equal to 1 μsec. To satisfy this condition, a YAG laser, a _YVO4 laser, a fiber laser, or the like can be used. For example, in the case of a YAG laser, it is sufficient that the energy density is 1 J/ ^cm2 or more. In the case of electroless Ni plating, the metal film 522 can be processed even with, for example, about 5 J/ ^cm2 .

At this time, the laser light source and the surface metal body 52 are moved relative to each other to scan the laser light and irradiate multiple positions in sequence. By irradiating the laser light and melting and vaporizing the surface of the metal film 522, recesses 523 are formed on the surface of the metal film 522. The average thickness of the parts of the metal film 522 irradiated with the laser light is thinner than the average thickness of the parts not irradiated with the laser light. In addition, the multiple recesses 523 formed corresponding to the spots of the laser light are connected together, for example, in the shape of scales. A spot is the range irradiated by one pulse. For example, the laser light is scanned so that adjacent spots of the laser light in the X direction partially overlap, and adjacent spots of the laser light in the Y direction partially overlap.

Then, the molten metal film 522 is solidified. Specifically, the molten and vaporized metal film 522 is deposited on the portion irradiated with the laser light and the surrounding area. In this manner, the molten and vaporized metal film 522 is deposited to form an uneven oxide film 520 on the surface of the metal film 522.

In FIG. 66, the uneven oxide film 520 is not provided in the first region 524 of the upper surface 52a of the surface metal body 52 that overlaps with the accommodation portion 811 of the joint portion 81 in a plan view. The uneven oxide film 520 is selectively provided in the second region 525 that overlaps with the opposing surface 810. The configuration of the surface metal body 62 and the uneven oxide film 620 is similar to that of the surface metal body 52 and the uneven oxide film 520. The uneven oxide film 620 is not provided in the first region 624 of the upper surface 62a of the surface metal body 62 that overlaps with the accommodation portion 811 of the joint portion 81 in a plan view. The uneven oxide film 620 is selectively provided in the second region 625 that overlaps with the opposing surface 810.

The oxide film (uneven oxide film 520, 620) has a lower wettability with respect to the bonding material 103 than the metal film. Since the uneven oxide film 520, 620 has fine unevenness on the surface, the contact area with the bonding material 103 is small, and part of the bonding material 103 becomes spherical due to surface tension. In other words, the contact angle is large. This results in a low wettability with respect to the bonding material 103. Therefore, due to the effect of the wettability reduction caused by the uneven oxide film 520, 620 and the effect of contact with the opposing surface 810, the bonding material 103 is less likely to pass between the opposing surface 810 and the second region 525, 625. This makes it possible to more effectively suppress overflow of the bonding material 103. The uneven oxide film 520, 620 is formed using laser light as described above, making patterning easy.

As shown in FIG. 68, the uneven oxide films 520, 620 may be provided in the peripheral regions 526, 626. The peripheral region 526 is the region around the second region 525 in a plan view, excluding the first region 524. The peripheral region 626 is the region around the second region 625 in a plan view, excluding the first region 624. Even if the joining material 103 passes directly under the opposing surface 810 of the joint portion 81, it can be blocked by the uneven oxide films 520, 620. In addition, since very fine unevenness is formed on the surface of the uneven oxide films 520, 620, the sealing body 30 is entangled, and an anchor effect is generated. In addition, the contact area with the sealing body 30 is increased. Therefore, the adhesion force of the surface metal bodies 52, 62 to the sealing body 30 can be increased.

The uneven oxide films 520, 620 may be provided in the second regions 525, 625 and the peripheral regions 526, 626. Only one of the uneven oxide films 520, 620 may be provided. The uneven oxide films 520, 620 may be used at the junctions with the main terminals, which are metal members, that is, the P terminal 91P, the N terminal 91N, and the output terminal 92.

An example has been shown in which the semiconductor device 20 includes a substrate 60 electrically connected to the source electrode 40S (second main electrode). That is, an example of a semiconductor device 20 with a double-sided heat dissipation structure including a pair of substrates 50, 60 has been shown. However, the present invention is not limited to this example. It is also applicable to a semiconductor device 20 with a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a semiconductor device 20 including a pair of substrates 50, 60, the above structure may be applied only to the joint between one of the substrates 50, 60 and the metal member. An example has been shown in which both rear surface metal bodies 53, 63 are exposed from the sealing body 30, but the present invention is not limited to this example.

Although an example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, and fourth embodiments, and the modified examples.

Sixth Embodiment
This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve the reliability of the semiconductor device, the physical properties of the sealing body and the physical properties of the insulating base material may satisfy a predetermined relationship as described in this embodiment.

<Semiconductor device and heat dissipation structure>
The semiconductor device 20 of this embodiment and its heat dissipation structure will be described with reference to Fig. 69. Fig. 69 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. Fig. 69 is an enlarged view of a portion of Fig. 5. In Fig. 69, the external connection terminals 90 are omitted for convenience.

The semiconductor device 20 of this embodiment has a structure similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 69, the semiconductor device 20 includes a semiconductor element 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The front metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The front metal body 62 of the substrate 60 is connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The back metal bodies 53 and 63 are exposed from the sealing body 30. The insulating substrates 51 and 61 contain resin. The sealing body 30 contains resin. Although not shown, the semiconductor device 20 includes a semiconductor element 40L.

Figure 69 shows the semiconductor device 20, as well as the heat exchanger 121 of the cooler 120 and a heat conductive member 130 such as a heat dissipation gel. In other words, Figure 69 shows a semiconductor module 140 that includes the semiconductor device 20, the cooler 120, and the heat conductive member 130. As an example, the semiconductor module 140 has a double-sided cooling structure in which the semiconductor device 20 is sandwiched between a pair of heat exchangers 121. The semiconductor device 20 is arranged alongside the cooler 120 (heat exchanger 121) in the Z direction, which is a predetermined direction. The coolers 120 are arranged on both sides of the semiconductor device 20.

The rear surface metal bodies 53, 63 are exposed from the sealing body 30 as the rear surfaces 50b, 60b of the substrates 50, 60. One of the heat exchange sections 121 of the cooler 120 is disposed facing one surface 30a and the rear surface 50b of the sealing body 30, and the other of the heat exchange sections 121 is disposed facing the rear surfaces 30b and 60b of the sealing body 30. A heat conductive member 130 is disposed between the opposing surfaces of the semiconductor device 20 and the heat exchange section 121. The heat conductive member 130 is in close contact with the semiconductor device 20 and the heat exchange section 121.

<Relationship to glass transition temperature>
Next, the relationship between the glass transition points of the sealing body 30 and the insulating base materials 51 and 61 will be described with reference to FIGS.

Figure 70 is a diagram showing an example of the relationship between the glass transition point Tgs and linear expansion coefficient αs of the sealing body 30 and the glass transition point Tgi and linear expansion coefficient αi of the insulating substrates 51 and 61. In Figure 70, the vertical axis indicates the linear expansion coefficient α, and the horizontal axis indicates temperature. In Figure 70, the solid line indicates the linear expansion coefficient αs of the sealing body 30, and the dashed line indicates the linear expansion coefficient αi of the insulating substrates 51 and 61. Of the linear expansion coefficients αs, α1s indicates the linear expansion coefficient at a temperature lower than the glass transition point Tgs, that is, the linear expansion coefficient of the α1 region. α2s indicates the linear expansion coefficient at a temperature higher than the glass transition point Tgs, that is, the linear expansion coefficient of the α2 region. The same is true for the linear expansion coefficient αi, where α1i indicates the linear expansion coefficient of the α1 region and α2s indicates the linear expansion coefficient of the α2 region.

As shown in FIG. 69, the sealing body 30 is in close contact with the semiconductor element 40. The insulating base materials 51, 61 are thermally connected to the semiconductor element 40 via the bonding materials 100, 101, 102 and the surface metal bodies 52, 62. Therefore, when the semiconductor element 40 is in operation (heat generation), the temperature of the peripheral position MP1 of the semiconductor element 40 in the sealing body 30 is higher than the temperatures of the positions MP2, MP3 of the insulating base materials 51, 61 that overlap with the semiconductor element 40. In this way, the sealing body 30 has a higher temperature than the insulating base materials 51, 61.

When the temperature of the sealing body 30 exceeds the glass transition point Tgs, the Young's modulus decreases, and the sealing function of the sealing body 30 decreases. The decrease in sealing function may cause thermal stress to concentrate on the drain electrode 40D, the source electrode 40S, and their junctions, which may cause cracks or the like. In other words, there is a risk of a decrease in connection reliability. In contrast, in this embodiment, as shown in FIG. 70, the relationship Tgs>Tgi is satisfied.

<Relationship between linear expansion coefficient>
Next, the relationship between the linear expansion coefficients of the sealing body 30 and the insulating base materials 51 and 61 will be described with reference to Figures 70 to 72. Figures 71 and 72 are conceptual diagrams showing warping of the semiconductor device 20. Figures 71 and 72 show only the resin elements that make up the semiconductor device 20, that is, only the sealing body 30 and the insulating base materials 51 and 61.

When the semiconductor element 40 is in operation (heat generation), if the linear expansion coefficient αs of the sealing body 30 is greater than the linear expansion coefficient αi of the insulating substrates 51 and 61, the amount of expansion of the sealing body 30 will be greater than the amount of expansion of the insulating substrates 51 and 61, as shown by the dashed arrows in Figure 71. In other words, the amount of expansion will be greater in the center in the Z direction and smaller at both ends. Therefore, both ends in the Z direction will be recessed, resulting in a concave shape.

In this embodiment, as shown in FIG. 70, the relationship αi>αs is satisfied. Specifically, the relationship α1i>α1s is satisfied in the α1 region, and the relationship α2i>α2s is satisfied in the α2 region. As described above, since the relationship Tgs>Tgi is satisfied, the relationship αi>αs is satisfied throughout the entire operating temperature range. Therefore, when the semiconductor element 40 is in operation (when heat is generated), the amount of expansion of the insulating substrates 51 and 61 is greater than the amount of expansion of the sealing body 30, as shown by the dashed arrows in FIG. 72. In other words, the amount of expansion is smaller in the center in the Z direction and larger at both ends. Therefore, as shown in FIG. 72, the shape of the semiconductor device 20 is convex at both ends in the Z direction.

<Summary of the Sixth Embodiment>
According to this embodiment, the glass transition point Tgs of the sealing body 30 is higher than the glass transition point Tgi of the insulating base materials 51 and 61. This makes it difficult for the temperature of the sealing body 30, which becomes hotter during operation of the semiconductor element 40, to exceed the glass transition point Tgs. The temperature of the sealing body 30 does not exceed the glass transition point Tgs, or exceeds it only slightly. Therefore, the Young's modulus of the sealing body 30 becomes smaller, and the sealing function can be suppressed from being deteriorated. Since the deterioration of the sealing function can be suppressed, it is possible to suppress the concentration of stress on the drain electrode 40D and the source electrode 40S, which are the main electrodes, and on the joints thereof. In other words, the connection reliability can be improved.

The glass transition point Tgs of the sealing body 30 may be approximately equal to the glass transition point Tgi of the insulating substrates 51 and 61. Compared to when Tgs is less than Tgi, the temperature of the sealing body 30, which becomes higher when heat is generated, is less likely to exceed the glass transition point Tgs.

In addition, the linear expansion coefficient αi of the insulating substrates 51 and 61 is greater than the linear expansion coefficient αs of the sealing body 30. As a result, when the semiconductor element 40 is in operation, the amount of expansion of the insulating substrates 51 and 61 is greater than the amount of expansion of the sealing body 30. In other words, the amount of expansion is small at the center in the Z direction, and large at both ends. As a result, the semiconductor device 20 is warped outward in the Z direction. Therefore, the opposing distance between the semiconductor device 20 and the cooler 120 (121) is narrowed, and the thermal resistance between the semiconductor device 20 and the cooler 120 is reduced. Specifically, the thickness of the thermal conductive member 130 is reduced, and the thermal resistance is reduced. Since the heat of the semiconductor element 40 can be efficiently dissipated, the semiconductor element 40 can be prevented from becoming overheated. In other words, the heat dissipation can be improved.

The linear expansion coefficient αi of the insulating substrates 51 and 61 may be approximately equal to the linear expansion coefficient αs of the sealing body 30. In this case, the amount of expansion is approximately equal at the center and both ends in the Z direction, and it is possible to prevent both ends in the Z direction from becoming concave. In other words, it is possible to prevent the thermal resistance between the semiconductor device 20 and the cooler 120 from increasing due to the concave shape.

In this way, by satisfying the relationships Tgs ≧ Tgi and αi ≧ αs, a highly reliable semiconductor device 20 can be provided.

<Modification>
Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50 and 60 has been shown, the present invention is not limited to this example. The present invention can also be applied to a semiconductor device 20 having a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected.

Although an example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, and fifth embodiments, and the modified examples.

Seventh Embodiment
This embodiment is a modification of the preceding embodiment as a basic form, and the description of the preceding embodiment can be used. In order to suppress peeling of the sealing body, the surface metal body may have a predetermined structure as described in this embodiment.

<Semiconductor Device>
73 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. FIG. 73 corresponds to FIG.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figs. 2 to 13). As shown in Fig. 73, the semiconductor device 20 includes two semiconductor elements 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The front metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40, via a bonding material 100. The front metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40, via a bonding material 102. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the bonding materials 100 and 102. The rear metal bodies 53 and 63 of the substrates 50 and 60 are exposed from the sealing body 30. Although not shown, the semiconductor device 20 includes two semiconductor elements 40L.

As shown in FIG. 73, the surface metal bodies 52, 62 have roughened portions 527, 627 and non-roughened portions 528, 628.

<Rough oxide film>
Next, the uneven oxide film 520 constituting the roughened portion 527 will be described in detail with reference to Fig. 74 and Fig. 75. Fig. 74 is an enlarged view of an area LXXIV in Fig. 73. Fig. 75 is a view showing a method for forming the roughened portion.

The surface metal bodies 52, 62 have uneven oxide films 520, 620, similar to the configuration described in the modified example of the fifth embodiment (see Figures 66 and 67). The uneven oxide films 520, 620 provide roughened portions 527, 627 on the surfaces of the surface metal bodies 52, 62. The portions of the surfaces of the surface metal bodies 52, 62 where the uneven oxide films 520, 620 are not formed provide non-roughened portions 528, 628. The following description will be given using the surface metal body 52 as an example.

As shown in FIG. 74, the surface metal body 52 has a base material 521, and a plating film 522p and an uneven oxide film 520 provided on the surface of the base material 521. The base material 521 forms the main part of the surface metal body 52. The base material 521 is formed using, for example, a Cu-based material. The plating film 522p is formed containing a material that has higher wettability with a joining material 100 such as solder than the base material 521. The plating film 522p is formed over the entire upper surface 52a and the entire side surface 52c of the surface metal body 52. The side surface 52c is a surface that connects the upper surface 52a and the lower surface 52d facing the insulating substrate 51 in the surface metal body 52.

The uneven oxide film 520 is formed by irradiating the plating film 522p with laser light as described in the modified example of the fifth embodiment. In this embodiment, the upper surface 52a and the side surface 52c of the surface metal body 52 are irradiated with laser light. The roughened portion 527 provided by the uneven oxide film 520 is a portion of the upper surface 52a excluding the non-roughened portion 528. As an example, the roughened portion 527 is formed over the entire side surface 52c. At the end of the surface metal body 52, the roughened portion 527 is continuously provided from the side surface 52c to the upper surface 52a. The roughened portion 527 is provided on a part of the upper surface 52a and on the side surface 52c. The roughened portion 527 may be provided only on the edge of the upper surface 52a. The non-roughened portion 528 is provided on a part of the upper surface 52a and includes at least the arrangement area (bonding area) of the bonding material 100. The non-roughened portion 528 may be provided only in the bonding region, or may include a region other than the bonding region. The roughened portion 527 is provided on at least a portion of the side surface 52c. The roughened portion 527 may be provided on only a portion of the side surface 52c. For example, the roughened portion 527 may be provided on only a portion of the side surface 52c so that the uneven oxide film 520 does not contact the insulating substrate 51.

The plating film 522p of this embodiment has an undercoat film mainly composed of Ni (nickel) and an upper layer mainly composed of Au (gold). Specifically, an electroless Ni plating film containing P (phosphorus) is used as the undercoat film. When the bonding material 100 is solder, the upper layer (Au) of the plating film 522p exposed from the uneven oxide film 520, which is in contact with the bonding material 100, diffuses into the solder during reflow. The upper layer (Au) of the plating film 522p, where the uneven oxide film 520 is formed, is removed by irradiation with laser light when the uneven oxide film 520 is formed. The uneven oxide film 520 is an oxide film mainly composed of Ni. The uneven oxide film 520 is continuously provided from the side surface 52c to the upper surface 52a at the end of the surface metal body 52.

As described in the modified example of the fifth embodiment, the uneven oxide film 520 is formed by melting, vaporizing, and depositing the surface portion of the plating film 522p by irradiation with laser light. The uneven oxide film 520 is an oxide film derived from the plating film 522p. The uneven oxide film 520 is a film of oxide of the metal (Ni) that is the main component of the plating film 522p. The surface of the uneven oxide film 520 always has fine unevenness (roughened portions). The uneven oxide film 520 has a continuously uneven surface.

In this embodiment, the surface metal body 52 has a larger area on the lower surface 52d than on the upper surface 52a. Therefore, as shown in FIG. 74, the lower surface 52d protrudes from the upper surface 52a. In other words, in a plan view in the Z direction, at least a portion of the side surface 52c is located outside the upper surface 52a. Therefore, as shown in FIG. 75, by irradiating laser light in the Z direction, a rough oxide film 520 can be formed on the upper surface 52a and the side surface 52c.

Summary of the Seventh Embodiment
In a configuration in which the plating film 522p is provided on the upper surface 52a and the side surface 52c of the surface metal body 52, the sealing body 30 is likely to peel off from the end of the surface metal body 52, i.e., the side surface 52c, due to thermal stress. In contrast, in this embodiment, the roughened portion 527 is provided on the portion of the upper surface 52a excluding the non-roughened portion 528 and on the side surface 52c. This makes the adhesion between the sealing body 30 and the side surface 52c of the surface metal body 52 higher than in a configuration in which the roughened portion 527 is not provided. Therefore, it is possible to suppress peeling of the sealing body 30 from occurring on the side surface 52c of the surface metal body 52. By suppressing peeling, it is possible to suppress concentration of thermal stress on the bonding portion of the bonding material 100 and the like in the surface metal body 52. As a result, it is possible to provide a highly reliable semiconductor device 20.

The surface metal body 62 has a similar configuration to the surface metal body 52. The surface metal body 62 has a roughened portion 627 on the upper surface 62a, excluding the non-roughened portion 628, and on the side surface 62c. This makes it possible to prevent peeling of the sealing body 30 from occurring on the side surface 62c of the surface metal body 62.

In this embodiment, the roughened portions 527, 627 are provided continuously across the side surfaces 52c, 62c and the upper surfaces 52a, 62a. This makes it possible to prevent peeling of the sealing body 30 near the ends of the surface metal bodies 52, 62.

The roughening treatment for forming the roughened portions 527, 627 can be roughening plating, sandblasting, chemical treatment, etc. In this embodiment, laser roughening is used. The uneven oxide films 520, 620 are formed by irradiating the plating film with laser light. The surface metal bodies 52, 62 have the uneven oxide films 520, 620 in the roughened portions 527, 627.

The surface of the uneven oxide film 520, 620 has continuous unevenness, and the sealing body 30 is entangled to produce an anchor effect. In addition, the contact area with the sealing body 30 is increased. Therefore, the adhesion force to the sealing body 30 can be increased in the roughened parts 527, 627. In addition, the uneven oxide film 520, 620 has a lower wettability with the bonding material 100, 102 than the plating film (plating film 522p). Since the uneven oxide film 520, 620 has fine unevenness on the surface, the contact area with the bonding material 100, 102 is reduced, and a part of the bonding material 100, 102 becomes spherical due to surface tension. In other words, the contact angle is increased. Therefore, the overflow of the bonding material 100, 102 can be suppressed. In this way, by adopting the uneven oxide film 520, 620, the adhesion force to the sealing body 30 can be increased and the overflow of the bonding material 100, 102 from the bonding part can be suppressed.

In this embodiment, the area of the surface metal bodies 52, 62 is larger on the lower surfaces 52d, 62d than on the upper surfaces 52a, 62a. The lower surfaces 52d, 62d protrude from the upper surfaces 52a, 62a. This makes it easier to physically roughen the side surfaces 52c, 62c from the Z direction. In the case of the laser roughening described above, by irradiating the laser light in the Z direction, it is possible to form the uneven oxide films 520, 620 not only on the upper surfaces 52a, 62a but also on the side surfaces 52c, 62c.

<Modification>
The side shape of the front surface metal bodies 52, 62 is not limited to the above-mentioned example. When the front surface metal bodies 52, 62 are patterned by pressing, etching, cutting, or the like, the side surface can be processed into a predetermined shape. Fig. 76 is a cross-sectional view showing a modified side surface shape. Fig. 76 shows the front surface metal body 52 as an example, and for convenience, the plating film 522p is omitted. Although not shown, a similar configuration can also be adopted for the front surface metal body 62.

In the example shown in FIG. 76, the surface metal body 52 has a side surface 52c that is approximately parallel to the Z direction. In other words, the area of the surface metal body 52 is approximately constant in the Z direction. To physically roughen such a surface metal body 52, for example, the top surface 52a and the side surface 52c may be roughened separately. In the case of laser roughening, the side surface 52c is irradiated with laser light from a direction different from the direction of irradiation of the top surface 52a with the laser light, for example, from a direction tilted with respect to the Z direction. This allows an uneven oxide film 520 to be provided on the side surface 52c.

Figure 77 is a cross-sectional view showing a modified example of the side shape, and corresponds to Figure 76. In the example shown in Figure 77, the area of the surface metal body 52 perpendicular to the Z direction becomes larger as it approaches the lower surface 52d. The side surface 52c has an R-shape. In this case, the entire area of the side surface 52c is located outside the upper surface 52a in a plan view. Therefore, it is easier to physically roughen the side surface 52c from the Z direction, for example, by laser roughening, than with the configuration shown in Figure 75.

Figure 78 is a cross-sectional view showing a modified example of the side shape, and corresponds to Figure 76. In the example shown in Figure 78, the area of the surface metal body 52 perpendicular to the Z direction increases as it approaches the lower surface 52d. The surface metal body 52 has a substantially trapezoidal shape in the ZY plane, for example. In this case, too, the entire area of the side surface 52c is located outside the upper surface 52a in a planar view, so that the side surface 52c can be easily roughened physically from the Z direction.

An example of a semiconductor device 20 having a double-sided heat dissipation structure with a pair of substrates 50 and 60 has been shown, but the present invention is not limited to this. It is also possible to apply the semiconductor device 20 having a single-sided heat dissipation structure with only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a configuration having a pair of substrates 50 and 60, the roughened portion structure including the side surface described above may be applied to only one of the substrates 50 and 60. The entire area of the side surfaces 52 and 62 may be roughened.

Although an example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, and sixth embodiments, and the modified examples.

Eighth embodiment
This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to reduce inductance, the thickness of the surface metal body and the spacing between the wirings may satisfy a predetermined relationship, as described in this embodiment.

<Semiconductor Device>
First, the semiconductor device 20 according to this embodiment, particularly the circuit patterns of the front surface metal bodies 52 and 62, will be described with reference to Fig. 79. Fig. 79 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. Fig. 79 illustrates a part of the configuration described in the preceding embodiment (see Fig. 8).

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 79, the semiconductor device 20 includes a semiconductor element 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The front metal body 52 of the substrate 50 is electrically connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The front metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the bonding materials 100 and 102. Of the substrates 50 and 60, the back metal bodies 53 and 63 are exposed from the sealing body 30. Although not shown, the semiconductor device 20 includes a semiconductor element 40L that constitutes a lower arm 9L.

<Relationship between wiring spacing and thickness>
Next, the relationship between the wiring interval and the thickness will be described with reference to Figures 79 and 80. Figure 80 is an enlarged view of an area LXXX in Figure 79. In Figure 80, only the substrate 60 is shown.

The surface metal bodies 52, 62 have inter-wiring gaps 52G, 62G, similar to the configuration described in the preceding embodiment (see FIG. 65). As shown in FIGS. 79 and 80, the inter-wiring gap 62G separates the adjacent N wiring 64 and relay wiring 65. The inter-wiring gap 62G is a predetermined gap provided in the surface metal body 62 between wirings having different potentials.

As shown in FIG. 80, in this embodiment, the distance L10 between the N wiring 64 and the relay wiring 65 is equal to or less than the thickness T10 of the surface metal body 62 (L10≦T10). The distance L10 is the length of the wiring gap 62G, that is, the pattern distance between the N wiring 64 and the relay wiring 65. In FIG. 79 and FIG. 80, the distance L10 and the thickness T10 in the surface metal body 62 satisfy the relationship L10<T10. Although not shown, the substrate 50 including the surface metal body 52 has the same configuration as the substrate 60. In the surface metal body 52, the distance L10 between the P wiring 54 and the relay wiring 55 is equal to or less than the thickness T10 of the surface metal body 52 (L10≦T10).

<Simulation results>
81 to 83 show the results of the electromagnetic field simulation. FIG. 81 is a diagram summarizing the simulation results in terms of the relationship between length (spacing, thickness) and inductance. The circles (○) at the measurement points show the results of three levels of thickness T10 (0.3 mm, 1.5 mm, 2.5 mm) when the spacing L10 is fixed at 1.5 mm. The solid line in the figure shows the change in inductance with the change in thickness T10 when the spacing L10 is fixed. The squares (□) at the measurement points show the results of three levels of spacing L10 (0.5 mm, 1.5 mm, 2.5 mm) when the thickness T10 is fixed at 1.5 mm. The dashed line in the figure shows the change in inductance with the change in spacing L10 when the thickness T10 is fixed. The length of the horizontal axis shown in FIG. 81 shows the length of thickness T10 when the spacing L10 is fixed, and shows the length of spacing L10 when the thickness T10 is fixed.

Figure 82 shows the simulation results when L10>T10. Figure 82 shows the simulation results when the first condition C1 shown in Figure 81 is met, specifically, when the distance L10=1.5 mm and the thickness T10=0.3 mm. Figure 83 shows the simulation results when L10<T10. Figure 83 shows the simulation results when the second condition C2 shown in Figure 81 is met, specifically, when the distance L10=1.5 mm and the thickness T10=2.5 mm. In the simulations, all conditions are the same except for the distance L10 and the thickness T10.

From the results shown in Figure 81, it is clear that inductance can be reduced in the range where the relationship L10≦T10 is satisfied. In particular, it is clear that inductance can be effectively reduced in the range where the relationship L10<T10 is satisfied.

As shown in FIG. 82, when L10>T10, the current is distributed in the width direction in the extension portion 641 of the N wiring 64, but flows biased toward the end side of the surface metal body 62 (substrate 60). Therefore, the PN current loop (see FIG. 17) described in the previous embodiment is large. Because the current path flowing through the extension portion 421 is far from the relay wiring 65, the effect of canceling the magnetic flux by the reverse current component is weakened. FIG. 82 shows that the inductance is larger than when the relationship L10≦T10 is satisfied.

As shown in FIG. 83, when L10<T10, the current flows biased toward the end of the extension portion 641 on the relay wiring 65 side in the width direction. Therefore, the PN current loop is small. Because the current path through the extension portion 421 is close to the relay wiring 65, the effect of canceling out the magnetic flux by the reverse current component is strengthened. FIG. 83 shows that the inductance is smaller than when the relationship L10>T10 is satisfied.

<Summary of the Eighth Embodiment>
In this embodiment, the front surface metal body 52 has a P wiring 54 which is a first wiring, and a relay wiring 55 which is a second wiring having a different potential from the first wiring. The distance L10 between the P wiring 54 and the relay wiring 55 and the thickness T1 of the front surface metal body 52 satisfy the relationship L10≦T10. Similarly, the front surface metal body 62 has an N wiring 64 which is a first wiring, and a relay wiring 65 which is a second wiring having a different potential from the first wiring. The distance L10 between the N wiring 64 and the relay wiring 65 and the thickness T1 of the front surface metal body 62 satisfy the relationship L10≦T10.

When the relationship L10≦T10 is satisfied, the spacing between adjacent wiring is narrow, so the cancellation effect between the magnetic flux caused by the current flowing through the first wiring and the magnetic flux caused by the current flowing through the second wiring is enhanced, and inductance can be reduced. In addition, since the surface metal body is thick, the cross-sectional area of the current path is large, and inductance can be reduced. As a result, the semiconductor device 20 of this embodiment can reduce inductance. In particular, when the relationship L1<T10 is satisfied, the above-mentioned effect is enhanced, and inductance can be reduced more effectively.

<Modification>
Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50 and 60 has been shown, the present invention is not limited to this. The present invention can also be applied to a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a configuration including a pair of substrates 50 and 60, only one of the surface metal bodies 52 and 62 may satisfy the above-mentioned relationship L10≦T10. That is, in at least one substrate electrically connected to the main electrode of the semiconductor element, the surface metal body has a first wiring and a second wiring, and the relationship L10≦T10 is satisfied. In addition, an example has been shown in which the relationship L10≦T10 is satisfied in all of the opposing regions between the N wiring 64, which is the first wiring, and the relay wiring 65, which is the second wiring having a different potential from the first wiring, but the present invention is not limited to this. The relationship L10≦T10 is satisfied in at least a part of the opposing regions. The same applies to the opposing region between the P wiring 54, which is the first wiring, and the relay wiring 55, which is the second wiring having a different potential from the first wiring.

Although an example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, sixth, seventh, and modified embodiments.

Ninth embodiment
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve heat dissipation and reliability, the side shape of the substrate may be a predetermined shape as described in this embodiment.

<Semiconductor Device>
First, the semiconductor device 20 according to this embodiment will be described with reference to Fig. 84. Fig. 84 is a cross-sectional view corresponding to Fig. 5. In Fig. 84, for the sake of convenience, the external connection terminals 90 are omitted from illustration.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 84, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50 is electrically connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the bonding materials 100 and 102.

<Substrate>
Next, the substrates 50 and 60 will be described with reference to Figs. 84 to 86. Fig. 85 is a plan view showing the center of the substrate. Fig. 85 corresponds to Fig. 12. Fig. 86 is an enlarged view of the area LXXXVI shown by the dashed line in Fig. 84. In the following, "inside" and "outside" indicate a relative positional relationship with the centers 50sc and 60sc of the substrates 50 and 60 in a plan view in the Z direction as the reference positions. The side closer to the center is the inside, and the side farther from the center is the outside. Fig. 85 shows the center 50sc of the substrate 50 as an example. Fig. 84 is a cross-sectional view, but for convenience of explanation, the centers 50sc and 60sc are shown.

In the substrates 50 and 60 of this embodiment, the insulating substrates 51 and 61 contain resin. The surface metal bodies 52 and 62 are disposed on the surfaces 51a and 61a of the insulating substrates 51 and 61. The surface metal bodies 52 and 62 are patterned as described in the preceding embodiment. As a result, the insulating substrates 51 and 61 have exposed portions 510 and 610 exposed from the surface metal bodies 52 and 62. The exposed portion 510 of the insulating substrate 51, which is the first exposed portion, and the exposed portion 610 of the insulating substrate 61, which is the second exposed portion, at least partially overlap each other in a plan view in the Z direction. The exposed portions 510 and 610 overlap each other. That is, at least a portion of the exposed portion 510 faces the exposed portion 610 in the Z direction.

The back metal body 53, 63 is disposed on the back surface 51b, 61b of the insulating substrate 51, 61. The back metal body 53, 63 is exposed from the sealing body 30. In the back metal body 53, 63, the surface opposite to the surface 53a, 63a facing the insulating substrate 51 is the exposed surface 53b, 63b. The exposed surface 53b is exposed approximately flush with one surface 30a of the sealing body 30. The exposed surface 63b is exposed approximately flush with the back surface 30b of the sealing body 30. The exposed surfaces 53b, 63b form the back surfaces 50b, 60b of the substrates 50, 60. The sealing body 30 has a side surface 30e as a second surface connected to the first surface 30a and the back surface 30b. The side surface 30e includes the side surfaces 30c, 30d in the Y direction, and also includes a side surface in the X direction. The side surface 30e includes all the side surfaces. The side surface 30e, which is the second surface, is a tapered surface that is inclined in the Z direction for removal from the mold during molding. The side surface 30e has a draft angle. In the previous embodiment, the draft angle is omitted for convenience. The side surface 30e has a bent portion approximately near the center in the Z direction, and the closer to the one surface 30a and the back surface 30b from the bent portion, the closer to the semiconductor element 40 in a plan view in the Z direction. In other words, in a plan view, the bent portion is on the outside, and the one surface 30a and the back surface 30b are on the inside. Hereinafter, the one surface 30a and the back surface 30b of the sealing body 30 may be referred to as the first surface 30a, 30b.

As shown in Figures 84 and 86, the substrates 50 and 60 have laminates 500 and 600. The laminate 500 is a two-layer laminate of an insulating substrate 51 and a back metal body 53. Similarly, the laminate 600 is a two-layer laminate of an insulating substrate 61 and a back metal body 63. In the laminates 500 and 600, the side surfaces connecting the surfaces 51a and 61a of the insulating substrates 51 and 61 and the exposed surfaces 53b and 63b of the back metal bodies 53 and 63 have a so-called V-cut shape. The side surfaces of the laminates 500 and 600 have a shape in which the center portion is convex outward relative to the surfaces 51a and 61a at the upper end and the exposed surfaces 53b and 63b at the lower end.

The side surfaces of the laminates 500 and 600 have first inclined portions 501 and 601, second inclined portions 502 and 602, and intermediate portions 503 and 603. First, the laminate 500 will be described.

The first inclined portion 501 is a portion within a predetermined range from the surface 51a. In a plan view, the first inclined portion 501 has an inclination such that the distance to the center 50sc is closest at the upper end on the surface 51a side and farther away at the lower end than the upper end side. In other words, the lower end of the first inclined portion 501 is located outside the upper end. As shown in FIG. 85, the first inclined portion 501 is provided on the edge portion of the substrate 50. The first inclined portion 501 is annular so as to surround the surface metal body 52.

In this embodiment, the first inclined portion 501 has an inclination that is more distant from the center 50sc in a plan view as it moves away from the surface 51a in the Z direction. In other words, in the upper portion of the laminate 500 including the first inclined portion 501, the area perpendicular to the Z direction at the surface 51a is the smallest, and the area becomes larger as it moves away from the surface 51a. The inclination of the first inclined portion 501 can tolerate manufacturing variations. The first inclined portion 501 has the inclination described above from a macroscopic perspective. The first inclined portion 501 is a tapered surface.

The second inclined portion 502 is a portion within a predetermined range from the exposed surface 53b. In a plan view, the second inclined portion 502 has a slope such that the distance to the center 50sc is closest at the lower end on the exposed surface 53b side and farther away at the upper end than the lower end side. In other words, the upper end of the second inclined portion 502 is located outside the lower end. The second inclined portion 502 is provided on the edge of the substrate 50, like the first inclined portion 501. The second inclined portion 502 is annular so as to surround the back metal body 53.

In this embodiment, the second inclined portion 502 has an inclination that is further away from the center 50sc in a plan view as it moves away from the exposed surface 53b in the Z direction. In other words, in the lower part of the laminate 500 including the second inclined portion 502, the area is smallest at the exposed surface 53b, and the area becomes larger as it moves away from the exposed surface 53b. The inclination of the second inclined portion 502 can tolerate manufacturing variations. The second inclined portion 502 has the above-mentioned inclination from a macroscopic perspective. The second inclined portion 502 is a tapered surface. If the first inclined portion 501 is a forward taper, the second inclined portion 502 is a reverse taper.

The intermediate portion 503 is connected to the first inclined portion 501 and the second inclined portion 502. The intermediate portion 503 is a portion that connects the first inclined portion 501 and the second inclined portion 502, and has a predetermined length in the Z direction. The intermediate portion 503 is the apex portion of the side of the laminate 500. The side of the laminate 500 is farthest from the center 50sc at the intermediate portion 503. The intermediate portion 503 is the outermost portion of the laminate 500 in a planar view. The area of the laminate 500 perpendicular to the Z direction is the largest at the intermediate portion 503. At the intermediate portion 503, the area of the laminate 500 is almost constant. The distance of the first inclined portion 501 from the center 50sc in a planar view is shorter the farther it is from the intermediate portion 503. The distance of the second inclined portion 502 from the center 50sc in a planar view is shorter the farther it is from the intermediate portion 503.

The laminate 600 has the same configuration as the laminate 500. The first inclined portion 601 is a portion within a predetermined range from the surface 61a. In a plan view, the first inclined portion 601 has an inclination such that the distance from the center 60sc to the upper end on the surface 61a side is closest, and the lower end is farther away from the upper end. In other words, the lower end of the first inclined portion 601 is located outside the upper end. The first inclined portion 601 is provided on the edge of the substrate 60. The first inclined portion 601 is annular so as to surround the surface metal body 62.

In this embodiment, the first inclined portion 601 has an inclination that is more distant from the center 60sc in a plan view as it moves away from the surface 61a in the Z direction. In other words, in the upper portion of the laminate 600 including the first inclined portion 601, the area perpendicular to the Z direction at the surface 61a is smallest, and the area becomes larger as it moves away from the surface 61a. The inclination of the first inclined portion 601 can tolerate manufacturing variations. The first inclined portion 601 has the above-mentioned inclination from a macroscopic perspective. The first inclined portion 601 is a tapered surface.

The second inclined portion 602 is a portion within a predetermined range from the exposed surface 63b. In a plan view, the second inclined portion 602 has an inclination such that the distance to the center 60sc is closest at the lower end on the exposed surface 63b side and farther away at the upper end than at the lower end. In other words, the upper end of the second inclined portion 602 is located outside the lower end. The second inclined portion 602 is provided on the edge of the substrate 60, like the first inclined portion 501. The second inclined portion 602 is annular so as to surround the back metal body 63.

In this embodiment, the second inclined portion 602 has an inclination that is further away from the center 60sc in a plan view as it moves away from the exposed surface 63b in the Z direction. In other words, in the lower part of the laminate 600 including the second inclined portion 602, the area is smallest at the exposed surface 63b, and the area becomes larger as it moves away from the exposed surface 63b. The inclination of the second inclined portion 602 can tolerate manufacturing variations. The second inclined portion 602 has the above-mentioned inclination from a macroscopic perspective. The second inclined portion 602 is a tapered surface. If the first inclined portion 601 is a forward taper, the second inclined portion 602 is a reverse taper.

The intermediate portion 603 is connected to the first inclined portion 601 and the second inclined portion 602. The intermediate portion 603 is a portion that connects the first inclined portion 601 and the second inclined portion 602, and has a predetermined length in the Z direction. The intermediate portion 603 is the apex portion of the side of the laminate 600. The side of the laminate 600 is furthest from the center 60sc at the intermediate portion 603. The intermediate portion 603 is the outermost portion of the laminate 600 in a planar view. The laminate 600 has the largest area at the intermediate portion 603. At the intermediate portion 603, the area of the laminate 600 is almost constant. The distance between the first inclined portion 601 and the center 60sc in a planar view is shorter the farther away from the intermediate portion 603. The distance between the second inclined portion 602 and the center 60sc in a planar view is shorter the farther away from the intermediate portion 603.

<Dimensions and angles>
Next, the dimensions and angles of the stacked bodies 500 and 600 will be described with reference to Fig. 87. Fig. 87 corresponds to Fig. 86 and shows the dimensions and angles. The following description will be given taking the stacked body 500 as an example.

The length L11 shown in FIG. 87 is the length of the first inclined portion 501 in a plan view, that is, the width of the first inclined portion 501 that forms an annular shape. The length L12 is the length of the second inclined portion 502 in a plan view, that is, the width of the second inclined portion 502 that forms an annular shape. The length L21 is the length of the first inclined portion 501 in the Z direction, that is, the height of the first inclined portion 501. The length L22 is the length of the second inclined portion 502 in the Z direction, that is, the height of the second inclined portion 502. The length L23 is the length of the intermediate portion 503 in the Z direction, that is, the height of the intermediate portion 503. The length L24 is the length of the insulating substrate 51 in the Z direction, that is, the thickness of the insulating substrate 51. The length L25 is the length of the back metal body 53 in the Z direction, that is, the thickness of the back metal body 53.

Angle R1 is the inclination angle of the back metal body 53 with respect to the Z direction, which is the plate thickness direction of the semiconductor element 40, at the first inclined portion 501. Angle R2 is the inclination angle of the back metal body 53 with respect to the Z direction at the second inclined portion 502. Angle R3 is the inclination angle of the insulating substrate 51 with respect to the Z direction at the first inclined portion 501. Angle R4 is the inclination angle of the second inclined portion 502 with respect to the exposed surface 53b of the back metal body 53. Angle R5 is the inclination angle of the side surface 30e with respect to one surface 30a of the sealing body 30.

As shown in FIG. 87, in this embodiment, the length of the second inclined portion 502 is shorter than the length of the first inclined portion 501. In other words, the relationship L11>L12 is satisfied. The angle R1 satisfies the relationship 0°<R1≦45°, and the angle R2 satisfies the relationship 0°<R2<45°. The closer the angle R1 is to 45°, the more effectively the heat generated by the semiconductor element 40 can be diffused. The closer the angle R2 is to 45°, the smaller the thermal resistance can be, as described below.

Furthermore, the first inclined portion 501 is provided from the insulating substrate 51 to the back metal body 53, and the second inclined portion 502 is provided on the back metal body 53. In other words, the relationships L21>L24 and L22<L25 are satisfied. In the configuration including the intermediate portion 503, the intermediate portion 503 is provided on the back metal body 53. In other words, the relationship L24<(L24+L25-L23)/2 is satisfied.

Furthermore, in a configuration in which the first inclined portion 501 is provided from the insulating substrate 51 to the rear metal body 53, the inclination angle of the rear metal body 53 and the inclination angle of the insulating substrate 51 are approximately equal. In other words, the relationship R1 = R3 is satisfied.

Furthermore, the inclination angle of the second inclined portion 502 with respect to the exposed surface 53b of the rear metal body 53 is smaller than the inclination angle of the side surface 30e (second surface) with respect to the surface 30a (first surface) of the sealing body 30. In other words, the relationship R4<R5 is satisfied. Although the explanation is omitted, the laminate 600 has a similar configuration to the laminate 500.

<Method of manufacturing laminate>
Next, an example of a method for manufacturing the laminate 500 described above will be described. First, a mother board having a two-layer structure of an insulating base material 51 containing a resin and a back metal body 53 is formed. Next, the insulating base material 51 is simultaneously cut (V-cut) from both the front surface 51a and the exposed surface 53b of the insulating base material 51 with a blade. In this cutting, the first inclined portion 501 and the second inclined portion 502 are formed without completely cutting off the mother board. In the mother board, the adjacent laminates 500 are connected at the middle portion 503. Then, the adjacent laminates 500 are separated (cut off) at the middle portion 503, thereby obtaining a laminate 500 having a side surface in a V-cut shape.

Figure 88 is a side view of the laminate 500 obtained by the above-mentioned manufacturing method. The first inclined portion 501 has a cutting mark 501a along the circumferential direction due to cutting (machining) using a blade. Similarly, the second inclined portion 502 has a cutting mark 502a along the circumferential direction. Adjacent laminates 500 are separated at the intermediate portion 503, so the intermediate portion 503 has an uneven portion 503a. Although not explained here, the laminate 600 is also formed by the same method as the laminate 500.

<Summary of the ninth embodiment>
In this embodiment, the side surface of the laminate 500, 600 has a first inclined portion 501, 601 and a second inclined portion 502, 602. That is, the side surface has a curved shape (approximately V-shaped). As a result, even if peeling that occurs in the sealing body 30 starting from the interface with the exposed surface 53b, 63b progresses along the second inclined portion 502, 602, the curved shape can suppress the progress to the first inclined portion 501, 601. Therefore, it is possible to suppress the progress of peeling to the surface metal body 52, 62, the semiconductor element 40, the joint between the surface metal body 52, 62 and the semiconductor element 40, etc. In other words, it is possible to suppress the concentration of thermal stress on the surface metal body 52, 62, the semiconductor element 40, etc., and the like, and the decrease in connection reliability, etc. can be suppressed. Therefore, reliability can be ensured.

The second inclined portions 502, 602 can also prevent the rear metal bodies 53, 63 from falling off (falling off) from the sealing body 30 when the above-mentioned peeling occurs.

Ideally, heat spreads at an angle of 45 degrees. In this embodiment, the stack 500, 600 has the first inclined portion 501, 601 on the semiconductor element 40 side in the Z direction. As a result, the heat generated by the semiconductor element 40 is diffused above the bent portion, that is, in the portion corresponding to the first inclined portion 501, 601. On the other hand, by having the second inclined portion 502, 602, the heat transfer path of the portion corresponding to the second inclined portion 502, 602 is narrower than the heat transfer path of the portion corresponding to the first inclined portion 501, 601. The narrow heat transfer path increases the thermal resistance. In this embodiment, the length L12 of the second inclined portion 502, 602 is made shorter than the length L11 of the first inclined portion 501, 601 (L11>L12). This allows the length L22 of the second inclined portions 502, 602 in the Z direction to be shorter than in a configuration where L11≦L12 is satisfied, and thus the thermal resistance below the bent portion can be reduced. In other words, the heat diffused in the upper portion of the stacked bodies 500, 600 can be efficiently dissipated from the exposed surfaces 53b, 63b. As a result, the semiconductor device 20 of this embodiment can ensure reliability while improving heat dissipation.

The first inclined portion 501, 601 may be provided on the insulating substrate 51, 61, and the second inclined portion 502, 602 may be provided on the back metal body 53, 63. The first inclined portion 501, 601 may be provided on the insulating substrate 51, 61, and the second inclined portion 502, 602 may be provided across the insulating substrate 51, 61 and the back metal body 53, 63. In this embodiment, the first inclined portion 501, 601 is provided across the insulating substrate 51, 61 and the back metal body 53, 63, and the second inclined portion 502, 602 is provided on the back metal body 53, 63. In other words, the bent portion exists in the back metal body 53, 63. Therefore, even if the peeling that occurs in the sealing body 30 starts from the interface with the exposed surface 53b, 63b and progresses along the second inclined portion 502, 602, the peeling can be suppressed from progressing to the interface with the insulating substrate 51, 61. This prevents thermal stress from concentrating on the insulating substrates 51 and 61, which reduces insulation reliability. In other words, reliability can be further improved.

The first inclined portion 501, 601 and the second inclined portion 502, 602 may be connected. In this embodiment, an intermediate portion 503, 603 is provided between the first inclined portion 501, 601 and the second inclined portion 502, 602. In this configuration, the intermediate portion 503, 603 forms a bent portion. By providing the intermediate portion 503, 603, as described above, even if cutting (cutting) is performed simultaneously from both the surface 51a, 61a of the insulating substrate 51, 61 and the exposed surface 53b, 63b of the back metal body 53, 63, contact between the blades can be avoided. In addition, since the intermediate portion 503, 603 is provided on the back metal body 53, 63, it is possible to suppress the peeling from progressing to the interface with the insulating substrate 51, 61, as described above.

In a configuration in which the first inclined portion 501, 601 is provided from the insulating substrate 51, 61 to the back metal body 53, 63, the inclination angle R1 of the back metal body 53, 63 and the inclination angle R3 of the insulating substrate 51, 61 may be made different. For example, if R1<R3, thermal stress is concentrated at the end of the insulating substrate 51, 61 containing resin, and there is a risk of insulation performance being reduced. If R1>R3, thermal stress is concentrated at the interface between the insulating substrate 51, 61 and the back metal body 53, 63, and there is a risk of interface peeling occurring. In this embodiment, the inclination angle R1 and the inclination angle R3 are set to be approximately equal angles (R1=R3). In other words, in the first inclined portion 501, 601, the inclined surface of the insulating substrate 51, 61 and the inclined surface of the back metal body 53, 63 are approximately flush and continuous. The inclined surfaces of the insulating substrates 51 and 61 and the inclined surfaces of the rear metal bodies 53 and 63 are continuous to form a single flat surface. This makes it possible to prevent thermal stress from concentrating at the triple points of the sealing body 30, the insulating substrates 51 and 61, and the rear metal bodies 53 and 63.

The inclination angle R4 of the second inclined portion 502, 602 with respect to the exposed surface 53b, 63b may be equal to or larger than the inclination angle R5 of the side surface 30e (second surface) with respect to the first surface 30a, 30b of the sealing body 30. In this embodiment, the inclination angle R4 is smaller than the inclination angle R5 (R4<R5). As described in the previous embodiment (see, for example, FIG. 72), when the semiconductor element 40 generates heat, the semiconductor device 20 warps. As described above, if a configuration that has a warped shape with high heat dissipation properties is adopted, peeling is likely to occur at the interface between the back metal body 53, 63 and the sealing body 30 due to the warp that is convex in the Z direction. By using a configuration that satisfies the relationship of R4<R5, it is possible to suppress the back metal body 53, 63 from falling off the sealing body 30 even if peeling occurs.

In this embodiment, the exposed portion 510 of the insulating substrate 51, which is the first exposed portion, and the exposed portion 610 of the insulating substrate 61, which is the second exposed portion, overlap each other in a plan view in the Z direction. This makes it possible to suppress imbalance in the arrangement of the front metal body 52 of the substrate 50, which is the first substrate, and the front metal body 62 of the substrate 60, which is the second substrate, and thus to suppress imbalance in the warping of the semiconductor device 20. It is possible to suppress the tendency for interface peeling to occur between the back metal bodies 53, 63 and the sealing body 30 on the side with larger deformation due to biased warping.

In this embodiment, the first inclined portion 501 and the second inclined portion 502 have cutting marks 501a, 502a along the circumferential direction. The cutting marks 501a, 502a create an anchor effect, increasing the adhesion with the sealing body 30. This makes it possible to prevent the sealing body 30 from peeling off from the laminate 500, 600. Note that only one of the first inclined portion 501 and the second inclined portion 502 may have cutting marks along the circumferential direction. In this embodiment, the intermediate portion 503 also has an uneven portion 503a, so peeling can be prevented by the anchor effect.

<Modification>
Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50 and 60 has been shown, the present invention is not limited to this. It is also possible to apply the present invention to a semiconductor device 20 having a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a configuration including a pair of substrates 50 and 60, the above-mentioned structure (V-cut shape) may be applied to only one of the substrates 50 and 60.

Although an example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, sixth, seventh, and eighth embodiments, and the modified examples.

Tenth embodiment
This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve the connection reliability, the sintered members, which are the joining materials, may be arranged in a predetermined manner as described in this embodiment.

<Semiconductor Device>
First, the semiconductor device 20 according to this embodiment will be described with reference to Fig. 89. Fig. 89 is a cross-sectional view corresponding to Fig. 5. In Fig. 89, for the sake of convenience, the external connection terminals 90 are omitted from illustration.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 89, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 that are wiring members arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50, which is the first wiring member, is connected to the drain electrode 40D, which is the first main electrode of the semiconductor element 40. The surface metal body 62 of the substrate 60, which is the second wiring member, is connected to the source electrode 40S, which is the second main electrode of the semiconductor element 40, via the conductive spacer 70, which is the second wiring member. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the conductive spacer 70. The source electrode 40S and the conductive spacer 70 are joined by the sintered member 101A, which is the joining material 101.

<Semiconductor element>
Next, the semiconductor element 40 will be described with reference to Fig. 90 and Fig. 91. Fig. 90 is a plan view showing the semiconductor element 40 (40H). Fig. 91 is an enlarged view of the region XCI in Fig. 89. Fig. 91 is a cross-sectional view corresponding to the line XCI-XCI in Fig. 90. Although Fig. 91 illustrates the semiconductor element 40H, the semiconductor element 40L also has a similar configuration, and therefore will be described below as the semiconductor element 40.

As described above, the semiconductor element 40 has a semiconductor substrate 41 on which a switching element is formed. The semiconductor substrate 41 has a generally rectangular shape in plan view. The drain electrode is provided on one side of the semiconductor substrate 41, and the source electrode 40S and the pad 40P are provided on the back side of the semiconductor substrate 41. The source electrode 40S has a multi-layer structure. The source electrode 40S has a base electrode 42 and a connection electrode 43. The pad 40P has a similar configuration to the source electrode 40S.

The semiconductor element 40 further has a protective film 44. The protective film 44 is an insulating film provided on the back surface of the semiconductor substrate 41 so as to cover the peripheral portion of the source electrode 40S. For example, polyimide, silicon nitride film, etc. can be used as the material of the insulating film. The protective film 44 has an opening 440 that defines the connection area of the source electrode 40S. The opening 440 exposes the source electrode 40S so that it can be bonded. The protective film 44 has an opening 441 that defines the connection area of the pad 40P. The openings 440 and 441 are both through holes that penetrate the protective film 44 in the Z direction. The portion of the source electrode 40S (connection electrode 43) exposed from the opening 440 of the protective film 44 forms a joint with the sintered member 101A.

The protective film 44 in this embodiment is made of polyimide. The protective film 44 covers the peripheral portion 420 of the base electrode 42, which will be described later. The protective film 44 is not provided in a scribe region that is a predetermined range from the outer peripheral edge of the semiconductor substrate 41, for example. The opening shape of the opening 440, i.e., the inner peripheral surface 442 of the protective film 44 that defines the opening 440, is substantially rectangular in plan view. The inner peripheral surface 442 may be referred to as the inner peripheral end or opening end.

The base electrode 42 is a metal layer formed adjacent to the semiconductor substrate 41 in the multi-layered source electrode 40S. The base electrode 42 may be referred to as a lower electrode, lower layer electrode, wiring electrode, base layer, first metal layer, etc. The base electrode 42 is connected to the rear surface of the semiconductor substrate 41. The base electrode 42 is formed using a material containing, for example, Al (aluminum) as a main component. In this embodiment, the material is an AlSi-based alloy such as AlSi or AlSiCu.

In plan view, the base electrode 42 includes an element region (active region) (not shown) of the semiconductor substrate 41 and extends onto the outer peripheral region surrounding the element region. The peripheral portion 420 of the base electrode 42 has a generally rectangular ring shape in plan view. The peripheral portion 420 is covered with a protective film 44.

The connection electrode 43 is layered on the base electrode 42. The connection electrode 43 is also called the top electrode, upper electrode, upper layer electrode, top layer, or second metal layer. The connection electrode 43 contains at least a precious metal such as Au (gold), Ag (silver), Pt (platinum), or Pd (palladium) for bonding with the sintered member 101A. The connection electrode 43 may contain a base metal in addition to the precious metal.

The connection electrode 43 in this embodiment contains Ni (nickel). Ni is harder than the Al alloy that constitutes the base electrode 42. The connection electrode 43 contains Ni and a precious metal, such as Au or Ag. The connection electrode 43 is formed in multiple layers, for example, by a plating method. At least a portion of the precious metal of the connection electrode 43 diffuses into the sintered member 101A during joining.

The connection electrode 43 is laminated on the base electrode 42 in the opening 440 of the protective film 44. The outer peripheral end of the connection electrode 43 is in contact with the inner peripheral surface 442 of the protective film 44 all around.

<Joint structure>
Next, the joining structure of the semiconductor element 40 will be described with reference to Figures 90 to 92. In Figure 90, the outer peripheral edge of the sintered member 101A is indicated by a dashed line, and the outer peripheral edge of the conductive spacer 70 is indicated by a two-dot chain line. Figure 92 is a cross-sectional view showing the arrangement of the sintered member 101A. Figure 92 corresponds to Figure 91. In the following, "inside" and "outside" indicate the relative positional relationship with the center of the semiconductor element 40 as the reference position. The side closer to the center is the inside, and the side furthest from the center is the outside.

In this embodiment, the substrate 60 and the conductive spacer 70 are wiring members (second wiring members) electrically connected to the source electrode 40S. As shown in Figures 90 and 91, the sintered member 101A is interposed between the source electrode 40S of the semiconductor element 40 and the conductive spacer 70. The sintered member 101A joins the source electrode 40S and the conductive spacer 70.

The sintered member 101A is made of Ag or Cu. The sintered member 101A is a sintered body made of Ag particles or Cu particles. The sintered member 101A can be bonded at a lower temperature than solder. As shown in FIG. 92, the sintered member 101A is arranged with a predetermined distance L30 between it and the inner peripheral surface 442 of the protective film 44. As shown in FIGS. 90 to 92, the sintered member 101A is arranged inside the inner peripheral surface 442. The sintered member 101A has, for example, a substantially rectangular shape in plan view. The outer peripheral end of the sintered member 101A is not in contact with the protective film 44 all around. In other words, the inner peripheral surface 442 of the protective film 44 contains the sintered member 101A in plan view.

The conductive spacer 70 has a metal film (not shown) on the joint surface with the sintered member 101A. The metal film contains at least a precious metal, like the connection electrode 43. In this embodiment, the metal film is a plating film containing Ni and a precious metal, such as Au or Ag.

As shown in Figures 90 to 92, the conductive spacer 70 is disposed inside the inner peripheral surface 442. The conductive spacer 70 has, for example, a generally rectangular shape in plan view. The outer peripheral end of the conductive spacer 70 is disposed so as to be outside the outer peripheral end of the sintered member 101A in plan view, or so as to be approximately aligned with the outer peripheral end of the sintered member 101A. In other words, the conductive spacer 70 is disposed so as to contain the sintered member 101A in plan view, or so as to be approximately aligned with the sintered member 101A. In this embodiment, the conductive spacer 70 contains the sintered member 101A.

<Joining method>
Next, a method for forming the above-mentioned joint structure, that is, a joining method, will be described with reference to Fig. 93. Fig. 93 is a cross-sectional view showing the joining method. Fig. 93 corresponds to Fig. 91.

In this embodiment, a sintered sheet 105 is used to form the sintered member 101A. The sintered sheet 105 is sometimes called a sintered film. The sintered sheet 105 contains Ag or Cu. As shown in FIG. 93, the sintered sheet 105 is placed on the source electrode 40S (connection electrode 43) of the semiconductor element 40. The sintered sheet 105 has a predetermined size that does not contact the protective film 44 in a plan view.

Next, the conductive spacer 70 is placed on the sintered sheet 105. Then, while heating, pressure is applied from the conductive spacer 70 side using a pressure device (not shown). As a result, the sintered sheet 105 is pressed and spread between the opposing surfaces of the connection electrode 43 and the conductive spacer 70, reducing its thickness, and is sintered to become the sintered member 101A. The size of the sintered sheet 105 is determined so that the sintered member 101A has the predetermined positional relationship described above with respect to the inner surface 442 of the protective film 44 and the conductive spacer 70.

<Simulation results>
Fig. 94 shows the results of a thermal stress simulation. In this simulation, the strain amplitude generated in the base electrode 42 was measured in a power cycle test in which room temperature and 150°C were alternately repeated. Fig. 94 shows the relationship between the distance L30 and the strain amplitude. In Fig. 94, distance L30 of 0 (zero) is a position that coincides with the inner circumferential surface 442 of the protective film 44 in a plan view. Negative values for distance L30 indicate the distance inward from the inner circumferential surface 442, and positive values indicate the distance outward.

As shown in FIG. 94, it has become clear that when the distance L30 is 5 μm or more, the distortion amplitude generated in the base electrode 42 becomes nearly 0 (zero). Based on this finding, in this embodiment, the predetermined distance L30 is set to 5 μm.

<Summary of the Tenth Embodiment>
FIG. 95 shows a connection structure using solder 101B as the bonding material 101. FIG. 95 corresponds to FIG. 93. In the case of solder 101B, the solder 101B is reflowed to perform bonding. During bonding, the molten solder 101B wets and spreads over the surface of the connection electrode 43. Therefore, as shown by the dashed line in FIG. 95, a triple point is formed between the sealing body 30, the source electrode 40S (connection electrode 43), and the solder 101B (bonding material 101). Thermal stress based on the difference in linear expansion coefficients is concentrated at the triple point. The thermal stress is concentrated in the base electrode 42, directly below the outer circumferential end of the connection electrode 43. Therefore, there is a risk that cracks will occur in the base electrode 42, and ultimately damage will occur in the semiconductor substrate 41.

In this embodiment, a sintered member 101A is used instead of solder 101B. The sintered member 101A is formed by heating at a temperature lower than the melting point. The sintered member 101A does not become molten when joined, unlike the solder 101B. The sintered member 101A has lower wettability to the connection electrode 43 and the conductive spacer 70 than the solder 101B. Therefore, the sintered member 101A does not wet and spread over the surface of the connection electrode 43 or the surface of the conductive spacer 70 when joined, unlike the solder 101B.

The sintered member 101A can be easily held in a predetermined position and can be positioned with a predetermined distance L30 between it and the inner circumferential surface 442 of the protective film 44. This prevents a triple point between the sealing body 30, the source electrode 40S (connection electrode 43), and the sintered member 101A (joint material 101) from being formed. This makes it possible to provide a semiconductor device 20 that suppresses the concentration of thermal stress and has high connection reliability. In addition, the sintered member 101A has a higher thermal conductivity than the solder 101B. This also makes it possible to improve heat dissipation.

The distance L30 is not particularly limited. The sintered member 101A only needs to be spaced apart from the inner peripheral surface 442. In this embodiment, the distance L30 between the sintered member 101A and the inner peripheral surface 442 of the protective film 44 is set to 5 μm or more. This effectively reduces the distortion amplitude of the base electrode 42 due to thermal stress. In other words, the connection reliability can be further improved.

In plan view, the positional relationship between the conductive spacer 70 and the sintered member 101A is not particularly limited. For example, in plan view, the sintered member 101A may protrude from the conductive spacer 70. As described above, the sintered member 101A is formed by sintering Ag particles or Cu particles by heating and pressurizing. The portion protruding from the conductive spacer 70 is not pressurized, so it remains unsintered and may fall off as a conductive foreign body. In other words, there is a risk of a short circuit or the like occurring.

In this embodiment, in plan view, the inner peripheral surface 442 of the protective film 44 contains the conductive spacer 70, and the conductive spacer 70 coincides with or contains the sintered member 101A. This allows pressure to be applied to the entire area of the sintered member 101A (sintered sheet 105) before sintering via the conductive spacer 70. Therefore, it is possible to prevent the occurrence of unsintered parts while avoiding contact between the sintered member 101A and the protective film 44.

<Modification>
Although the sintered sheet 105 is used to form the sintered portion 101A, the present invention is not limited to this. For example, a sintering paste having Ag particles or Cu particles dispersed in a solvent may be used. The sintered sheet 105 is easier to hold in place than the sintering paste.

In the above example, the second wiring member to which the source electrode 40S is connected includes the substrate 60, which is a wiring board, and the conductive spacer 70, but is not limited to this. Instead of the conductive spacer 70, a convex portion may be provided on the surface metal body 62. In other words, the second wiring member may be configured to include only the substrate 60 without including the conductive spacer 70. In this case, the sintered member 101A is interposed between the tip surface of the convex portion of the surface metal body 62 and the source electrode 40S (connection electrode 43).

Although an example of a substrate 50 is shown as the first wiring member, this is not limiting. A metal plate (lead frame) may be used instead of the substrate 50. Although an example of a substrate 60 is shown as the second wiring member, this is not limiting. A metal plate (lead frame) may be used instead of the substrate 60. The second wiring member may have a metal plate and a conductive spacer 70, or a convex portion may be provided on the metal plate instead of the conductive spacer 70.

Although an example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth embodiments, and the modified examples.

Eleventh Embodiment
This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve heat dissipation, a sintered member may be used at the joint between the main electrode and the wiring member, as described in this embodiment.

<Semiconductor Device>
First, the semiconductor device 20 according to this embodiment will be described with reference to Fig. 96. Fig. 96 is a cross-sectional view corresponding to Fig. 5. In Fig. 96, for the sake of convenience, the external connection terminals 90 are omitted from illustration.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 96, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60, which are wiring members arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the first main electrode of the semiconductor element 40. The surface metal body 62 of the substrate 60 is connected to the source electrode 40S, which is the second main electrode of the semiconductor element 40, via a conductive spacer 70. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the conductive spacer 70. The drain electrode 40D and the surface metal body 52 of the substrate 50 are joined by a sintered member 100A, which is a joining material 100.

<Arrangement of sintered member and uneven oxide film>
Next, the arrangement of the sintered member 100A and the uneven oxide film 520 relative to the semiconductor element 40 will be described with reference to Fig. 97 to Fig. 99. Fig. 97 is an enlarged view of region XCVII in Fig. 96. Fig. 98 is a plan view showing the positional relationship between the semiconductor element 40, the sintered member 100A, and the uneven oxide film 520. Fig. 99 is an enlarged view of region XCVIX in Fig. 97.

As shown in Figures 97 and 98, the upper surface 52a of the surface metal body 52 has a mounting portion 529a, an outer periphery 529b, and an intermediate portion 529c. The uneven oxide film 520 is not provided on the mounting portion 529a, but is provided on the outer periphery 529b and intermediate portion 529c.

The mounting portion 529a includes a portion that overlaps with the semiconductor element 40 (drain electrode 40D) in a plan view in the Z direction, and is a portion to which the drain electrode 40D is joined via the sintered member 100A. The outer peripheral portion 529b includes a portion that is outside the outer peripheral end 402 of the semiconductor element 40 in a plan view, and is a portion that surrounds the semiconductor element 40. The intermediate portion 529c is a portion between the mounting portion 529a and the outer peripheral portion 529b, and surrounds the mounting portion 529a. In this embodiment, the mounting portion 529a approximately coincides with the semiconductor element 40 (drain electrode 40D) in a plan view. The intermediate portion 529c has a substantially rectangular ring shape in a plan view, and the inner peripheral end of the intermediate portion 529c approximately coincides with the outer peripheral end 402 of the semiconductor element 40. The entire intermediate portion 529c is located outside the semiconductor element 40 in a plan view.

As shown in Figures 97 to 99, the surface metal body 52 of the substrate 50 has an uneven oxide film 520, similar to the configuration described in the preceding embodiment (see Figures 67 and 74). As shown in Figure 99, the surface metal body 52 has a base material 521, and a metal film 522 and an uneven oxide film 520 provided on the surface of the base material 521.

The metal film 522 of this embodiment has a base film mainly composed of Ni and an upper film mainly composed of a precious metal capable of bonding to the sintered member 100A, such as Au or Ag. Specifically, a Ni-plated film containing P and an Au-plated film are used as the base film. A plurality of recesses 523 are formed in the outer peripheral portion 529b of the upper surface 52a of the metal film 522. The recesses 523 are not formed in the mounting portion 529a and the intermediate portion 529c. In the portion where the recesses 523 are not formed, the film thickness of the metal film 522 is, for example, about 10 μm. In other words, the film thickness before the irradiation of the laser light is about 10 μm. The recesses 523 are formed by irradiation of a pulsed laser light. One recess 523 is formed for each pulse. In the outer peripheral portion 529b, the surface of the metal film 522 is scale-like due to the plurality of recesses 523. The outer periphery 529b is the area irradiated with laser light, while the mounting portion 529a and the middle portion 529c are non-irradiated areas.

The uneven oxide film 520 is formed on the metal film 522. The uneven oxide film 520 is not formed on the mounting portion 529a, but is formed on the outer peripheral portion 529b and the intermediate portion 529c, which are the portions surrounding the mounting portion 529a. As described in the preceding embodiment, the uneven oxide film 520 is formed by irradiating the metal film 522 with laser light. The uneven oxide film 520 is a laser irradiated film formed by irradiating the metal film 522 with laser light. The main component of the uneven oxide film 520 is an oxide of the main component metal of the metal film 522.

In the outer peripheral portion 529b, i.e., the area irradiated with the laser light, the average thickness of the uneven oxide film 520 is 10 nm to several hundred nm. The uneven oxide film 520 is formed following the unevenness of the surface of the metal film 522 having the recesses 523. In addition, the surface of the uneven oxide film 520 has unevenness formed at a pitch finer than the width of the recesses 523. In other words, very fine unevenness (roughened portion) is formed. In other words, multiple protrusions 520a (columnar bodies) are formed at a fine pitch. For example, the average width of the protrusions 520a is 1 nm to 300 nm, and the average distance between the protrusions 520a is 1 nm to 300 nm. In addition, the average height of the protrusions 520a is 10 nm to several hundred nm.

The uneven oxide film 520 is formed by irradiating the metal film 522 with laser light and melting and vapor deposition of the surface layer of the metal film 522, so that it is formed not only in the outer peripheral portion 529b, which is the area irradiated with the laser light, but also in the periphery (vicinity) of the outer peripheral portion 529b. In this embodiment, of the areas not irradiated with the laser light, the uneven oxide film 520 is formed over the entire intermediate portion 529c, and the uneven oxide film 520 is not formed in the mounting portion 529a. The width of the intermediate portion 529c, which has the uneven oxide film 520 over its entire area, is, for example, 0.2 mm to 0.3 mm.

The average thickness of the uneven oxide film 520 in the intermediate portion 529c is thinner than the average thickness of the uneven oxide film 520 in the outer peripheral portion 529b, and thicker than the natural oxide film, because the laser light is not directly irradiated thereto. Specifically, it is 0.1 nm to 10 nm. The height of the convex portions 520a on the surface of the uneven oxide film 520 is also lower than that of the outer peripheral portion 529b. Specifically, it is 0.1 nm to 10 nm. The average width and average spacing of the convex portions 520a are approximately the same as those of the outer peripheral portion 529b.

Thus, the uneven oxide film 520 has a thick film portion 520X and a thin film portion 520Y. The thick film portion 520X is a portion of the uneven oxide film 520 that is provided in the laser light irradiated area, i.e., the outer peripheral portion 529b. The thin film portion 520Y is a portion of the uneven oxide film 520 that is provided in the laser light non-irradiated area, i.e., the intermediate portion 529c. The thin film portion 520Y is thinner than the thick film portion 520X, and the height of the convex portion 520a is lower. The thick film portion 520X is provided in the outer peripheral portion 529b. The thin film portion 520Y is provided in the intermediate portion 529c.

Since the protrusions 520a of the thick film portion 520X are taller than those of the thin film portion 520Y, the plug 30 becomes entangled therewith, creating an anchor effect. In addition, the contact area with the plug 30 increases. This allows the plug 30 to adhere closely to the outer periphery 529b. The thick film portion 520X is sometimes referred to as a roughened portion or an adhered portion.

The sintered member 100A is made of Ag or Cu, similar to the sintered member 101A described in the preceding embodiment. The sintered member 100A is a sintered body made of Ag particles or Cu particles. The sintered member 100A can be bonded at a lower temperature than solder. The sintered member 100A is formed by heating and pressing a sintered sheet or sintered paste. The sintered member 100A protrudes outward from the outer peripheral end 402 of the semiconductor element 40 in a plan view. The sintered member 100A is arranged so as to overlap the mounting portion 529a and the intermediate portion 529c in a plan view. In this embodiment, the outer peripheral end of the sintered member 100A is almost the same as the outer peripheral end of the intermediate portion 529c. The sintered member 100A overlaps the entire mounting portion 529a and the entire intermediate portion 529c in a plan view.

<Summary of the eleventh embodiment>
As described above, the intermediate portion 529c has the thin film portion 520Y of the uneven oxide film 520. Due to the presence of the thin film portion 520Y, the intermediate portion 529c has a lower wettability with solder than the mounting portion 529a. As a result, the solder is less likely to wet and spread from the mounting portion 529a to the intermediate portion 529c.

In this embodiment, a sintered member 100A is used instead of solder. The sintered member 100A is formed by heating at a temperature lower than the melting point. The sintered member 100A does not become molten when joined, unlike solder. The sintered member 100A does not wet and spread over the surface of the surface metal body 52 when joined, unlike solder.

During pressure sintering, the sintered member 100A is pressed and spread between the opposing surfaces of the drain electrode 40D and the surface metal body 52. By being pressed and spread, the sintered member 100A is placed not only on the mounting portion 529a but also on the intermediate portion 529c. The sintered member 100A does not wet and spread, but is pressed and spread by pressure to contact the thin film portion 520Y. As a result, not only the joint between the sintered member 100A and the mounting portion 529a, but also the contact portion between the sintered member 100A and the intermediate portion 529c functions as a heat dissipation path. As a result, a semiconductor device 20 with high heat dissipation properties can be provided. In addition, the sintered member 100A has a higher thermal conductivity than solder. This can also improve heat dissipation.

The height of the convex portion 520a of the thin film portion 520Y is lower than that of the thick film portion 520X. In other words, the adhesion of the intermediate portion 529c to the sealing body 30 is lower than that of the outer peripheral portion 529b. As a result, the sealing body 30 is less likely to adhere to the intermediate portion 529c. In this embodiment, the sintered member 100A is in contact with the intermediate portion 529c. The sintered member 100A covers the portion of the upper surface 52a with low adhesion. Therefore, it is possible to prevent the sealing body 30 from peeling off from the upper surface 52a around (near) the semiconductor element 40. This prevents thermal stress from concentrating on the joint portion of the sintered member 100A and the drain electrode 40D, thereby improving the connection reliability.

In this embodiment, the entire intermediate portion 529c is located outside the semiconductor element 40. This allows the joint between the sintered member 100A and the mounting portion 529a to be larger. In addition, the contact portion between the sintered member 100A located outside the semiconductor element 40 and the intermediate portion 529c also functions as a heat dissipation path. This further improves heat dissipation.

<Modification>
Although an example in which the sintered member 100A overlaps the entire intermediate portion 529c has been shown, this is not limiting. The sintered member 100A only needs to overlap at least a portion of the intermediate portion 529c. In other words, the sintered member 100A only needs to contact at least a portion of the thin film portion 520Y of the uneven oxide film 520. This can expand the heat dissipation path and improve the heat dissipation performance.

The arrangement of the intermediate portion 529c is not limited to the above example. Only a portion of the intermediate portion 529c in the width direction may be located outside the semiconductor element 40. By locating at least a portion of the intermediate portion 529c in the width direction outside the semiconductor element 40, the joint can be enlarged and the heat dissipation path can be enlarged. This improves heat dissipation.

Also, at least a portion of the intermediate portion 529c in the width direction may be located inside the outer peripheral end 402 of the semiconductor element 40. In this way, the sintered member 100A can be brought into contact with the thin film portion 520Y (intermediate portion 529c) to improve heat dissipation, while the position of the outer peripheral portion 529b can be brought closer to the semiconductor element 40. In other words, peeling of the sealing body 30 around the semiconductor element 40 can be suppressed.

In the example shown in Fig. 100 and Fig. 101, the intermediate portion 529c straddles the outer peripheral end 402 of the semiconductor element 40 in a plan view. That is, a part of the width direction of the intermediate portion 529c is located outside the outer peripheral end 402, and another part is located inside the outer peripheral end 402. The sintered member 100A overlaps the entire mounting portion 529a and the entire intermediate portion 529c in a plan view. As a result, as described above, it is possible to improve heat dissipation while suppressing peeling of the sealing body 30 around the semiconductor element 40. Fig. 100 and Fig. 101 are diagrams showing modified examples. Fig. 100 corresponds to Fig. 97, and Fig. 101 corresponds to Fig. 98.

102 and 103, the outer peripheral end of the intermediate portion 529c is approximately aligned with the outer peripheral end 402 of the semiconductor element 40 in plan view. The outer peripheral end of the sintered member 100A is also approximately aligned with the outer peripheral end 402 of the semiconductor element 40 in plan view. This allows the outer peripheral portion 529b (thick film portion 520X) to be located adjacent to the semiconductor element 40 in plan view. Therefore, the contact of the sintered member 100A with the intermediate portion 529c can enhance heat dissipation while more effectively suppressing peeling of the sealing body 30 around the semiconductor element 40. FIGS. 102 and 103 are diagrams showing modified examples. FIG. 102 corresponds to FIG. 97, and FIG. 103 corresponds to FIG. 98.

In the example shown in FIG. 104, a part of the outer peripheral portion 529b overlaps with the semiconductor element 40 in a plan view. The middle portion 529c is located inside the outer peripheral end 402 of the semiconductor element 40. FIG. 104 is a diagram showing a modified example. FIG. 104 corresponds to FIG. 98. In this case, the sintered member 100A may contact only the thin film portion 520Y. The sintered member 100A may contact both the thin film portion 520Y and the portion of the thick film portion 520X directly below the semiconductor element 40.

Although an example has been shown in which the uneven oxide film 520 is provided only on the surface metal body 52 to which the drain electrode 40D is connected, this is not limiting. In addition to the surface metal body 52, the uneven oxide film 520 may be provided on the side of the conductive spacer 70 to which the source electrode 40S is connected, and/or on the surface metal body 62 of the substrate 60. As described above, the thick film portion 520X of the uneven oxide film 520 provides the function of increasing the adhesion to the sealing body 30 and the function of suppressing the spreading of the solder, which is the bonding material. The uneven oxide film 520 may be provided in places where it is desired to suppress the overflow of solder or to increase the adhesion to the sealing body 30.

Although the example of the substrate 50 is shown as the wiring member, the present invention is not limited to this. A metal plate (lead frame) may be used instead of the substrate 50. Also, a metal plate (lead frame) may be used instead of the substrate 60. Instead of the conductive spacer 70, a protrusion may be provided on the metal plate on the source electrode 40S side.

Although an example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth embodiments, and the modified examples.

Twelfth Embodiment
This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to suppress cracks occurring in the main electrode, the sintered member, which is the bonding material, may have a multi-layer structure as described in this embodiment.

<Semiconductor Device>
First, the semiconductor device 20 according to this embodiment will be described with reference to Fig. 105. Fig. 105 is a cross-sectional view corresponding to (a part of) Fig. 7. For convenience, the external connection terminals 90 and the bonding wires 110 are omitted from Fig. 105.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 105, the semiconductor device 20 includes a semiconductor element 40 (40H), substrates 50 and 60 that are wiring members arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The semiconductor element 40 has a drain electrode 40D, which is a first main electrode, on one surface of the semiconductor substrate 41, and a source electrode 40S, which is a second main electrode, on the back surface. The drain electrode 40D is a main electrode on the high potential side, and the source electrode 40S is a main electrode on the low potential side. The source electrode 40S is provided on the same surface as the pad 40P.

The surface metal body 52 of the substrate 50, which is the first wiring member, is connected to the drain electrode 40D. The substrate 60 and conductive spacer 70, which are the second wiring members, are connected to the source electrode 40S. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the conductive spacer 70. Although not shown, the semiconductor device 20 includes a semiconductor element 40L.

The drain electrode 40D and the surface metal body 52 of the substrate 50 are joined by a sintered member 100A, which is a bonding material 100, in the same manner as in the configuration described in the preceding embodiment (see FIG. 97). The source electrode 40S and the conductive spacer 70 are joined by a multilayer bonding material 101C, which is a bonding material 101.

<Multi-layered bonding material and its surrounding structure>
Next, the multilayer bonding material 101C and its surrounding structure will be described with reference to Figures 106 and 107. Figure 106 is an enlarged view of region CVI in Figure 105. For convenience, pads are omitted from Figure 106. Figure 107 is a diagram showing the relationship between the Young's modulus and yield stress of the base electrode 42, sintered layer 106, and fragile layer 107. In the strain-stress diagram shown in Figure 107, the solid line indicates the fragile layer 107, the dashed line indicates the sintered layer 106, and the dashed line indicates the base electrode 42.

As with the configuration described in the preceding embodiment (see FIG. 91), the source electrode 40S has a base electrode 42 formed on a semiconductor substrate 41 and a connection electrode 43 formed on the base electrode 42. The base electrode 42 is made of an AlSi-based alloy such as AlSi or AlSiCu. The connection electrode 43 contains at least a precious metal for bonding with the multilayer bonding material 101C. The connection electrode 43 is, for example, a plating film containing Au or Ag and Ni.

The conductive spacer 70 includes a base material 71 that includes a metal such as Cu and forms the main part of the conductive spacer 70, and a metal film 72 formed on the surface of the base material 71. The metal film 72 includes at least a precious metal for bonding to the multilayer bonding material 101C. The metal film 72 is, for example, a plating film that includes Au or Ag and Ni. The metal film 72 is provided on a bonding surface that includes, for example, a surface facing the semiconductor element 40.

The multilayer bonding material 101C has a sintered layer 106 and a fragile layer 107. The sintered layer 106 has a structure similar to that of the sintered member 101A described in the preceding embodiment. The sintered layer 106 is a pressure-sintered body of Ag particles or Cu particles. The fragile layer 107 is intentionally made to have a low strength so that cracks will occur before the source electrode 40S, particularly the base electrode 42, when thermal stress is applied.

As shown in FIG. 107, the Young's modulus YM2 of the sintered layer 106 is slightly smaller than the Young's modulus YM1 of the base electrode 42. However, the yield stress YS2 of the sintered layer 106 is sufficiently larger than the yield stress YS1 of the base electrode 42. The yield strain of the sintered layer 106 is larger than the yield strain of the base electrode 42. On the other hand, the Young's modulus YM3 of the fragile layer 107 is smaller than the Young's modulus YM1 of the base electrode 42. Furthermore, the yield stress YS3 of the fragile layer 107 is smaller than the yield stress YS1 of the base electrode 42. The Young's modulus YM3 of the fragile layer 107 is smaller than the Young's modulus YM2 of the sintered layer 106. The yield stress YS3 of the fragile layer 107 is smaller than the yield stress YS2 of the sintered layer 106.

The fragile layer 107 in this embodiment is a sintered body made of the same type of particles (e.g., Ag particles) as the sintered layer 106. The fragile layer 107 is a low-pressure sintered body sintered at a lower pressure than the sintered layer 106. The fragile layer 107 is, for example, a pressureless sintered body sintered without pressure. Due to sintering at a low pressure, the fragile layer 107 has larger gaps between the particles than the sintered layer 106. The fragile layer 107 is sparser than the sintered layer 106.

The fragile layer 107 is a sintered body of Ag particles or Cu particles. The thermal conductivity of the fragile layer 107 is 200 W/m·K or more. The thermal conductivity of the sintered layer 106, which is denser than the fragile layer 107, is greater than that of the fragile layer 107.

As shown in FIG. 106, the multilayer bonding material 101C has a three-layer structure in the Z direction, which is the plate thickness direction of the semiconductor element 40, with sintered layers 106 at both ends and a fragile layer 107 between the sintered layers 106. The fragile layer 107 is laminated on the sintered layer 106, and the sintered layer 106 is laminated on the fragile layer 107. One of the sintered layers 106 is bonded to the connection electrode 43 of the source electrode 40S, and the other sintered layer 106 is bonded to the metal film 72 of the conductive spacer 70. The fragile layer 107 is sandwiched between the sintered layers 106 in the Z direction. Since the fragile layer 107 is a low-pressure sintered body as described above, the thickness of the fragile layer 107 is, for example, thicker than the thickness of each of the sintered layers 106.

<Summary of the twelfth embodiment>
As described in the preceding embodiment, thermal stress is likely to concentrate on the source electrode 40S, particularly on the base electrode 42. In addition, in a joint structure using the joint material 101, if only a sintered member is used as the joint material 101, the sintered member is less likely to reach the yield stress than the source electrode 40S, and therefore thermal stress is likely to concentrate on the source electrode 40S (base electrode 42).

In this embodiment, the bonding material 101 that bonds the source electrode 40S and the conductive spacer 70 is a multi-layer bonding material 101C. The multi-layer bonding material 101C has a sintered layer 106 and a fragile layer 107. The fragile layer 107 has a Young's modulus and/or a yield stress that is smaller than that of the source electrode 40S (base electrode 42). This causes thermal stress to concentrate in the fragile layer 107. For example, a crack occurs in the fragile layer 107 before a crack occurs in the source electrode 40S. Therefore, damage to the element can be suppressed.

In this embodiment, as shown in FIG. 107, the Young's modulus and yield stress of the fragile layer 107 are both smaller than those of the source electrode 40S (base electrode 42). This makes it possible to effectively suppress damage to the element.

The multi-layer bonding material 101C (bonding material 101) also contains a sintered body. The thermal conductivity of a sintered body is sufficiently higher than that of solder. Therefore, heat dissipation can be improved.

In this embodiment, the fragile layer 107 is a sintered body made of the same type of particles as the sintered layer 106. The fragile layer 107 has larger gaps between the particles than the sintered layer 106. The fragile layer 107 is a sintered body formed with a lower pressure than the sintered layer 106. By changing the pressure, the sintered layer 106 and the fragile layer 107 can be formed. This simplifies the configuration.

In this embodiment, the multi-layer bonding material 101C has a three-layer structure. The multi-layer bonding material 101C has sintered layers 106 on both ends, and a fragile layer 107 between the sintered layers 106. One of the sintered layers 106 forms a joint with the source electrode 40S, and the other sintered layer 106 forms a joint with the conductive spacer 70, which is the second wiring member. Therefore, it is possible to suppress damage to the element while ensuring the bond with the source electrode 40S and the conductive spacer 70.

<Modification>
Although an example of the fragile layer 107 sintered at a lower pressure than the sintered layer 106 is shown as the fragile layer, the present invention is not limited thereto. Instead of the fragile layer 107 which is a sintered body, a fragile layer 108 which is a non-sintered body may be adopted as shown in FIG. 108. The fragile layer 108 contains, for example, Al. The fragile layer 108 containing Al has a Young's modulus and/or a yield stress smaller than that of the source electrode 40S (base electrode 42). Therefore, like the fragile layer 107, element damage can be suppressed. The thermal conductivity of the fragile layer 108 containing Al is also 200 W/m·K or more. FIG. 108 is a cross-sectional view showing a modified example, and corresponds to FIG. 106.

Although an example of a three-layer structure of the multi-layer bonding material 101C has been shown, this is not limiting. For example, a structure of four or more layers may be used. Also, as shown in FIG. 109, a two-layer structure may be used. The multi-layer bonding material 101C has a sintered layer 106 on the conductive spacer 70 side, and a fragile layer 107 on the source electrode 40S side. In this way, the fragile layer 107 is disposed in a position close to the semiconductor element 40. This enhances the effect of suppressing element damage. FIG. 109 is a cross-sectional view showing a modified example, and corresponds to FIG. 106.

In the example shown in FIG. 110, the multilayer bonding material 101C has a sintered layer 106 on the source electrode 40S side and a fragile layer 107 on the conductive spacer 70 side. The sintered layer 106, which is a pressure-sintered body and has better heat dissipation properties than the fragile layer 107, is positioned closer to the semiconductor element 40. This improves heat dissipation. FIG. 110 is a cross-sectional view showing a modified example and corresponds to FIG. 106.

In the above example, the second wiring member to which the source electrode 40S is connected includes the substrate 60, which is a wiring board, and the conductive spacer 70, but is not limited to this. Instead of the conductive spacer 70, a convex portion may be provided on the surface metal body 62. In other words, the second wiring member may not include the conductive spacer 70, and may include only the substrate 60. In this case, the multilayer bonding material 101C is interposed between the tip surface of the convex portion of the surface metal body 62 and the source electrode 40S (connection electrode 43).

Although an example of a substrate 50 is shown as the first wiring member, this is not limiting. A metal plate (lead frame) may be used instead of the substrate 50. Although an example of a substrate 60 is shown as the second wiring member, this is not limiting. A metal plate (lead frame) may be used instead of the substrate 60. The second wiring member may have a metal plate and a conductive spacer 70, or a convex portion may be provided on the metal plate instead of the conductive spacer 70.

Although an example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, and eleventh embodiments, and the modified examples.

Thirteenth Embodiment
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used as the basis for this embodiment. As described in this embodiment, each arm may be formed of a single semiconductor element 40.

<Power conversion device>
First, the circuit configuration of the power conversion device 4 to which the semiconductor device 20 is applied will be described with reference to Fig. 111. Fig. 111 is a diagram showing an equivalent circuit of the power conversion device 4.

The power conversion device 4 shown in FIG. 111 is also used in a vehicle drive system 1. The configuration of the power conversion device 4 is almost the same as the configuration described in the preceding embodiment (see FIG. 1). The difference is that each arm has only one MOSFET 11. The upper and lower arm circuits 9 for one phase are composed of two MOSFETs 11. The upper and lower arm circuits 9 for one phase are provided by one semiconductor device 20.

<Semiconductor Device>
Next, the semiconductor device will be described with reference to Figs. 112 to 121. Fig. 112 is a perspective view of the semiconductor device 20. Fig. 113 is a plan view showing the semiconductor device 20. Fig. 113 is a see-through view showing the internal structure. Fig. 114 is a plan view showing a state in which the semiconductor element 40 is mounted on the substrate 50. In Fig. 114, the lead frame 94 is shown for convenience in Fig. 10. Fig. 115 is a plan view showing the circuit pattern of the substrate 50. Fig. 115 shows a state in which the semiconductor element 40 and the joint portion 81 are mounted on the substrate 50. In Fig. 115, the P terminal 91P, the output terminal 92, and the guide frame 94c joined to the front metal body 52 are also shown by dashed lines.

Figure 116 is a plan view showing the circuit pattern of the substrate 60. In Figure 116, the semiconductor element 40, joint portion 81, and N terminal 91N joined to the surface metal body 62 are also shown by dashed lines. Figure 117 is a cross-sectional view taken along line CXVII-CXVII in Figure 113. Figure 118 is a cross-sectional view taken along line CXVIII-CXVIII in Figure 113. Figure 119 is a cross-sectional view taken along line CXIX-CXIX in Figure 113. Figure 120 is a cross-sectional view taken along line CXX-CXX in Figure 113. Figure 121 is an enlarged view of area CXXI shown by the dashed line in Figure 120.

In this embodiment, as in the previous embodiment, the thickness direction of the semiconductor element 40 (semiconductor substrate) is the Z direction, and the arrangement direction of the semiconductor elements 40H, 40L is the Y direction. The direction perpendicular to both the Z direction and the Y direction is the X direction. Unless otherwise specified, the shape viewed from the Z direction, in other words the shape along the XY plane defined by the X direction and the Y direction, is the planar shape. In the following, "inside" and "outside" refer to the relative positional relationship with the center of the semiconductor element 40 as the reference position. The side closer to the center is the inside, and the side furthest from the center is the outside.

The semiconductor device 20 of this embodiment, like the preceding embodiment, constitutes one of the upper and lower arm circuits 9, that is, one phase of the upper and lower arm circuit 9. The semiconductor device 20 has the same elements as the configuration described in the preceding embodiment (see Figures 2 to 13). As shown in Figures 112 to 121, the semiconductor device 20 has a sealing body 30, a semiconductor element 40, substrates 50 and 60, a conductive spacer 70, an arm connection portion 80, and an external connection terminal 90. The following mainly describes the parts that are different from the configuration described in the preceding embodiment.

As in the previous embodiment, the sealing body 30 seals some of the other elements that make up the semiconductor device 20. As shown in Figures 112 and 113, the sealing body 30 has a generally rectangular shape in plan view. In the Z direction, the sealing body 30 has one surface 30a and a back surface 30b. The side surface connecting the one surface 30a and the back surface 30b includes two side surfaces 30f and 30g from which the external connection terminals 90 protrude. Side surface 30g is the surface opposite side surface 30f in the X direction.

The semiconductor element 40 is formed by forming a switching element on a semiconductor substrate. As in the previous embodiment, the semiconductor element 40 of this embodiment is formed by forming an n-channel MOSFET 11 on a semiconductor substrate made of SiC. The semiconductor element 40 has a drain electrode 40D on one surface as main electrodes, and a source electrode 40S on the back surface. The semiconductor element 40 has a pad 40P on the back surface.

The semiconductor elements 40 include one semiconductor element 40H constituting the upper arm 9H and one semiconductor element 40L constituting the lower arm 9L. The semiconductor elements 40H, 40L have a common configuration. As shown in Figures 113 and 114, the semiconductor elements 40H, 40L are aligned in the Y direction. The semiconductor elements 40 are disposed at approximately the same positions as each other in the Z direction. The drain electrode 40D of each semiconductor element 40 faces the substrate 50. The source electrode 40S of each semiconductor element 40 faces the substrate 60.

The substrates 50 and 60 are arranged in the Z direction to sandwich the multiple semiconductor elements 40. The substrates 50 and 60 are arranged so that at least a portion of each substrate faces each other in the Z direction. The substrates 50 and 60 contain all of the multiple semiconductor elements 40 (40H, 40L) in a plan view.

The substrate 50 is disposed on the drain electrode 40D side. The substrate 60 is disposed on the source electrode 40S side. The substrate 50 is electrically connected to the drain electrode 40D and provides a wiring function. The substrate 60 is electrically connected to the source electrode 40S and provides a wiring function. The substrates 50 and 60 provide a heat dissipation function to dissipate heat generated by the semiconductor element 40.

The substrate 50 comprises an insulating substrate 51, a front metal body 52, and a rear metal body 53. The substrate 60 comprises an insulating substrate 61, a front metal body 62, and a rear metal body 63. The substrate 60 is a substrate in which the insulating substrate 61 and metal bodies 62, 63 are laminated. Hereinafter, the front metal bodies 52, 62 and the rear metal bodies 53, 63 may be simply referred to as metal bodies 52, 53, 62, 63.

The insulating substrate 51 electrically separates the front metal body 52 and the back metal body 53. Similarly, the insulating substrate 61 electrically separates the front metal body 62 and the back metal body 63. In this embodiment, resin-based insulating substrates 51 and 61 are used, and the material configuration is the same.

The metal bodies 52, 53, 62, 63 are provided, for example, as metal plates or metal foils. The surface metal bodies 52, 62 are patterned. The surface metal bodies 52, 62 may have a plating film of Ni-based or Au, etc., on the metal surface. Hereinafter, the pattern of the surface metal bodies 52, 62 may be referred to as a circuit pattern. The surface metal body 52 has a P wiring 54 and a relay wiring 55, as in the previous embodiment. The P wiring 54 and the relay wiring 55 are electrically separated by a predetermined interval (gap). This gap is filled with the sealing body 30.

The P wiring 54 is connected to the P terminal 91P and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 electrically connects the P terminal 91P and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 has a generally rectangular shape in plan with the X direction as the longitudinal direction. The relay wiring 55 is connected to the drain electrode 40D of the semiconductor element 40L, the arm connection portion 80, and the output terminal 92. The relay wiring 55 has a generally rectangular shape in plan.

The P wiring 54 and the relay wiring 55 are arranged side by side in the Y direction. The semiconductor element 40L is mounted on the relay wiring 55, biased toward one end side in the Y direction, specifically, the side farther from the P wiring 54. The joint portion 81 constituting the arm connection portion 80 is mounted on the relay wiring 55, biased toward the other end side in the Y direction, specifically, the side closer to the P wiring 54. The P terminal 91P is connected to the P wiring 54 near one end in the X direction. The output terminal 92 is connected to the relay wiring 55 near one end in the X direction. The P terminal 91P and the output terminal 92 are arranged on the same side in the X direction with respect to the semiconductor element 40.

The surface metal body 62 has an N wiring 64 and a relay wiring 65, as in the previous embodiment. The N wiring 64 and the relay wiring 65 are electrically separated by a predetermined distance (gap). This gap is filled with the sealing body 30. The N wiring 64 is connected to the N terminal 91N and the source electrode 40S of the semiconductor element 40L. The relay wiring 65 is connected to the source electrode 40S of the semiconductor element 40H and the arm connection part 80.

The N wiring 64 has a base 644 and an extension portion 645. The N wiring 64 is generally L-shaped in plan. The base 644 is generally rectangular in plan. The base 644 contains the semiconductor element 40L in plan view. The extension portion 645 is connected to one side of the base 644, which is generally rectangular in plan. The extension portion 645 extends from the side of the base 644 facing the relay wiring 65 toward the base 654 in the Y direction.

The relay wiring 65 has a base 654 and an extension portion 655. The relay wiring 65 has a generally L-shape in plan view. The base 654 has a generally rectangular shape in plan view. The base 654 contains the semiconductor element 40H in plan view. The extension portion 655 is connected to one side of the base 654, which has a generally rectangular shape in plan view. The extension portion 655 extends from the side of the base 654 facing the N wiring 64 toward the base 644 in the Y direction. At least a portion of the extension portion 655 overlaps with the relay wiring 55 in plan view.

The N wiring 64 and the relay wiring 65 are arranged side by side in the Y direction. The bases 644, 654 are arranged side by side in the Y direction. The source electrode 40S of the semiconductor element 40L is electrically connected to the base 644. The source electrode 40S of the semiconductor element 40H is electrically connected to the base 654. The extensions 645, 655 are arranged side by side in the X direction. The N terminal 91N is connected to the extension 645. The joint portion 81 is connected to the extension 655.

The back metal bodies 53, 63 are electrically isolated from the front metal bodies 52, 62 by the insulating substrates 51, 61. In this embodiment, the back metal bodies 53, 63 are so-called solid conductors arranged over almost the entire back surface of the insulating substrates 51, 61. The back metal body 53 is exposed from one surface 30a of the sealing body 30, and the back metal body 63 is exposed from the back surface 30b. The exposed surface of the back metal body 53 is approximately flush with the one surface 30a. The exposed surface of the back metal body 63 is approximately flush with the back surface 30b.

The conductive spacer 70 is interposed between the source electrode 40S of the semiconductor element 40 and the substrate 60. The conductive spacer 70 is individually connected to the source electrode 40S of the semiconductor element 40. The semiconductor device 20 includes two conductive spacers 70. One of the conductive spacers 70 electrically connects the source electrode 40S of the semiconductor element 40H to the relay wiring 65. The other conductive spacer 70 electrically connects the source electrode 40S of the semiconductor element 40L to the N wiring 64.

The arm connection part 80 electrically connects the relay wirings 55 and 65. The arm connection part 80 is provided between the semiconductor element 40H and the semiconductor element 40L in the Y direction. The arm connection part 80 is provided in the overlapping area of the relay wiring 55 and the relay wiring 65 (extension part 655) in a plan view. The arm connection part 80 of this embodiment is configured with a joint part 81 and a bonding material 103, as in the previous embodiment. The joint part 81 is a metal column. In the Z direction, the bonding material 103 is interposed between one of the ends of the joint part 81 and the relay wiring 55, and the bonding material 103 is interposed between the other end and the relay wiring 65.

Alternatively, the joint portion 81 may be integrally connected to at least one of the surface metal bodies 52, 62. In other words, the joint portion 81 may be provided integrally with the surface metal bodies 52, 62 as part of the substrates 50, 60. The arm connection portion 80 may not include the joint portion 81. In other words, the arm connection portion 80 may include only the bonding material 103.

The external connection terminal 90 includes a power terminal 91, an output terminal 92, and a signal terminal 93. The power terminal 91 includes a P terminal 91P and an N terminal 91N. Hereinafter, the P terminal 91P, the N terminal 91N, and the output terminal 92 may be referred to as main terminals 91P, 91N, and 92. The signal terminal 93 includes a signal terminal 93H on the upper arm 9H side, and a signal terminal 93L on the lower arm 9L side.

The P terminal 91P is connected to the P wiring 54 near one end in the X direction. The P terminal 91P extends outward in the X direction from the connection portion 91a with the P wiring 54. A portion of the P terminal 91P including the connection portion 91a is covered by the sealing body 30, and the remaining portion protrudes from the sealing body 30. The P terminal 91P protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30f.

The N terminal 91N is connected to the N wiring 64 near one end in the X direction. The N terminal 91N extends outward in the X direction from the connection portion 91b with the N wiring 64. A portion of the N terminal 91N including the connection portion 91b is covered by the sealing body 30, and the remaining portion protrudes from the sealing body 30. The N terminal 91N protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30f.

The output terminal 92 is connected to the relay wiring 55 near one end in the X direction. The output terminal 92 extends outward in the X direction from a connection portion 92a with the relay wiring 55. A portion of the output terminal 92 including the connection portion 92a is covered by the sealing body 30, and the remaining portion protrudes from the sealing body 30. The output terminal 92 protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30f.

The three main terminals 91P, 91N, and 92 are arranged side by side in the Y direction. The main terminals 91P, 91N, and 92 are arranged in the Y direction in the order of P terminal 91P, N terminal 91N, and output terminal 92. The P terminal 91P and N terminal 91N, which are power supply terminals 91, have their sides facing each other in a portion that includes the portion protruding from the sealing body 30.

The signal terminal 93 is electrically connected to the pad 40P of the corresponding semiconductor element 40 via a connecting member such as a bonding wire 110. The signal terminal 93H is connected to the pad 40P of the semiconductor element 40H via a bonding wire 110. The signal terminal 93L is connected to the pad 40P of the semiconductor element 40L via a bonding wire 110. The signal terminal 93 extends outward in the X direction and protrudes outside the sealing body 30 from near the center of the side surface 30g in the Z direction. The signal terminal 93 extends in the X direction on the opposite side to the main terminals 91P, 91N, and 92.

The lead frame 94 includes an external connection terminal 90, a tie bar 94a, and an outer peripheral frame 94b, similar to the configuration described in the previous embodiment. The lead frame 94 in this embodiment further includes a guide frame 94c. As described in the previous embodiment, the tie bar 94a and the outer peripheral frame 94b are removed as unnecessary parts during the manufacturing process of the semiconductor device 20. Meanwhile, the guide frame 94c remains together with the external connection terminal 90 as an element of the semiconductor device 20.

As shown in FIG. 114, the lead frame 94 has two guide frames 94c. One of the guide frames 94c is connected to the P terminal 91P. Before unnecessary portions are removed, the guide frame 94c connects the P terminal 91P and the outer frame 94b. The other guide frame 94c is connected to the output terminal 92. Before unnecessary portions are removed, the guide frame 94c connects the output terminal 92 and the outer frame 94b.

As shown in Figures 114, 119 to 121, the guide frame 94c has a connection portion 940, a first coupling portion 941, and a second coupling portion 942. The connection portion 940 is the connection portion of the guide frame 94c with the surface metal body 52. The guide frame 94c connected to the P terminal 91P is connected to the P wiring 54. Specifically, the connection portion 940 is the end of the P wiring 54 opposite the connection portion of the P terminal 91P, and is connected near the end opposite the relay wiring 55 in the Y direction. The connection portion 940 is connected to one of the four corners of the P wiring 54, which has a substantially rectangular shape in plan view.

The first connecting portion 941 connects the P terminal 91P and the connection portion 940. The first connecting portion 941 extends from the connection portion 91a of the P terminal 91P in the X direction toward the side surface 30g. The first connecting portion 941 does not overlap with the P wiring 54 (surface metal body 52) in a plan view. The first connecting portion 941 extends along the outer peripheral edge of the surface metal body 52 outside the surface metal body 52. The second connecting portion 942 connects the connection portion 940 and the outer peripheral frame 94b. The second connecting portion 942 extends outward from the connection portion 940 in the X direction.

The guide frame 94c connected to the output terminal 92 is connected to the relay wiring 55. Specifically, the connection portion 940 is connected to the end of the relay wiring 55 opposite the connection portion of the output terminal 92, near the end opposite the P wiring 54 in the Y direction. The connection portion 940 is connected to one of the four corners of the relay wiring 55, which has a substantially rectangular shape in plan view.

The first connecting portion 941 connects the output terminal 92 and the connection portion 940. The first connecting portion 941 extends from the connection portion 92a of the output terminal 92 in the X direction toward the side surface 30g. The first connecting portion 941 does not overlap with the relay wiring 55 (surface metal body 52) in a plan view. The first connecting portion 941 extends along the outer peripheral edge of the surface metal body 52 outside the surface metal body 52. The second connecting portion 942 connects the connection portion 940 and the outer peripheral frame 94b. The second connecting portion 942 extends outward from the connection portion 940 in the X direction.

The guide frame 94c can have a connection structure (joint structure) similar to that of the main terminals 91P, 91N, and 92. The guide frame 94c is connected to the surface metal body 52, for example, via a joint material 104. As described in the previous embodiment, the joint material 104 can be solder or a sintered material. The guide frame 94c may be directly joined to the surface metal body 52 without the joint material 104. For example, the guide frame 94c may be directly joined to the surface metal body 52 by ultrasonic welding, friction stir welding, laser welding, or the like.

As described above, in the semiconductor device 20 of this embodiment, the multiple semiconductor elements 40 that constitute the upper and lower arm circuits 9 for one phase are sealed by the sealing body 30. The sealing body 30 integrally seals the multiple semiconductor elements 40, part of the substrate 50, part of the substrate 60, the multiple conductive spacers 70, the arm connection portion 80, and part of each of the external connection terminals 90. The sealing body 30 seals the insulating substrates 51, 61 and the surface metal bodies 52, 62 in the substrates 50, 60.

The semiconductor element 40 is disposed between the substrates 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched between the substrates 50 and 60, which are disposed opposite each other. This allows the heat of the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of the substrate 50 is approximately flush with one surface 30a of the sealing body 30. The back surface 60b of the substrate 60 is approximately flush with the back surface 30b of the sealing body 30. Because the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be improved.

<Summary of the thirteenth embodiment>
The configuration described in this embodiment can be combined with the various configurations described in the preceding embodiments, excluding some of them. The above-mentioned some are a configuration in which a power supply terminal is connected to each of a pair of extension parts of the front surface metal body (see FIG. 15 and FIG. 23) and a configuration in which a slit is provided in the front surface metal body so as to separate a plurality of semiconductor elements connected in parallel (see FIG. 28, etc.). In other words, the configuration described in this embodiment can be combined with any of the configurations described in the other first embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, the eighth embodiment, the ninth embodiment, the tenth embodiment, the eleventh embodiment, the twelfth embodiment, and the modified examples.

Although an example in which the semiconductor device 20 includes a conductive spacer 70 has been shown, this is not limiting. Instead of the conductive spacer 70, a protrusion may be provided on the surface metal body 62.

The example of the wiring member connected to the drain electrode 40D is a substrate 50, but is not limited to this. In configurations that are not limited to the substrate 50, a metal plate (lead frame) may be used instead of the substrate 50. The example of the wiring member connected to the source electrode 40S is a substrate 60, but is not limited to this. In configurations that are not limited to the substrate 60, a metal plate (lead frame) may be used instead of the substrate 60.

Other Embodiments
The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure includes the exemplified embodiments and modifications by those skilled in the art based thereon. For example, the disclosure is not limited to the combination of parts and/or elements shown in the embodiments. The disclosure can be implemented by various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure includes the omission of parts and/or elements of the embodiments. The disclosure includes the substitution or combination of parts and/or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are indicated by the description of the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the description of the claims.

The disclosure in the specification and drawings, etc. is not limited by the claims. The disclosure in the specification and drawings, etc. encompasses the technical ideas described in the claims, and extends to more diverse and extensive technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification and drawings, etc., without being bound by the claims.

When an element or layer is referred to as being "on," "coupled," "connected," or "bonded," it may be directly coupled, connected, or bonded to another element or layer, and intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly coupled," "directly connected," or "directly bonded" to another element or layer, no intervening elements or layers are present. Other words used to describe relationships between elements should be construed in a similar manner (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.). As used in this specification, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Spatially relative terms such as "inside," "outside," "back," "bottom," "low," "top," "top," and the like are utilized herein for ease of description to describe the relationship of one element or feature to other elements or features as depicted in the figures. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the drawings. For example, if the device in the figures is turned over, elements described as "below" or "directly below" other elements or features would be oriented "above" the other elements or features. Thus, the term "bottom" can encompass both an orientation of top and bottom. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used in this specification would be interpreted accordingly.

The vehicle drive system 1 is not limited to the above-mentioned configuration. For example, an example has been shown in which one motor generator 3 is provided, but this is not limiting. Multiple motor generators may be provided. An example has been shown in which the power conversion device 4 is provided with an inverter 6 as a power conversion circuit, but this is not limiting. For example, a configuration may be provided with multiple inverters. A configuration may be provided with at least one inverter and a converter. A configuration may be provided with only a converter.

Although an example has been shown in which the semiconductor element 40 has a MOSFET 11 as a switching element, this is not limiting. For example, an IGBT can also be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor.

1...Drive system, 2...DC power supply, 3...Motor generator, 4...Power conversion device, 5...Smoothing capacitor, 6...Inverter, 7...P line, 8...N line, 9...Upper and lower arm circuits, 9H...Upper arm, 9L...Lower arm, 10...Output line, 11...MOSFET, 12...Diode, 20...Semiconductor device, 30...Sealing body, 30a...One side, 30b...Reverse side, 30c, 30d, 30e, 30f, 30g...Side, 31...Vacancy, 40, 40H, 40L...Semiconductor element, 40D...Drain electrode, 40S...Source electrode, 40P...Pad, 400, 401...Side, 402... Outer periphery, 41...semiconductor substrate, 41a...one surface, 41b...rear surface, 42...base electrode, 420...periphery, 43...connection electrode, 44...protective film, 440, 441...opening, 442...inner periphery, 50...substrate, 50a...opposing surface, 50b...rear surface, 50c, 50d...edge, 50sc...center, 500...laminated body, 501...first inclined portion, 501a...cutting mark, 502...second inclined portion, 502a...cutting mark, 503...middle portion, 503a...uneven portion, 51...insulating base material, 51a...surface, 51b...rear surface, 510...exposed portion, 52...surface metal body, 52a...upper surface, 52b...edge, 52c...side surface, 52 d...underside, 52G...gap between wirings, 520...uneven oxide film, 520a...protruding portion, 520X...thick film portion, 520Y...thin film portion, 521...base material, 522...metal film, 522p...plating film, 523...recess, 524...first region, 525...second region, 526...peripheral region, 527...roughened portion, 528...non-roughened portion, 529a...mounting portion, 529b...peripheral portion, 529c...middle portion, 53...back metal body, 53a...opposing surface, 53b...exposed surface, 54...P wiring, 540...notch, 541...base, 542...extension portion, 55...relay wiring, 550...notch, 551...base, 551a...opposing Side, 552...extension portion, 553...slit, 554...chamfered portion, 56...laminated body, 60...substrate, 60a...opposing surface, 60b...rear surface, 60c...end portion, 60sc...center, 600...laminated body, 601...first inclined portion, 602...second inclined portion, 603...middle portion, 61...insulating base material, 61a...front surface, 61b...rear surface, 610...exposed portion, 62...front metal body, 62a...upper surface, 62c...side surface, 62d...lower surface, 62G...interconnect gap, 620...uneven oxide film, 624...first region, 625...second region, 626...peripheral region, 627...roughened portion, 628...non-roughened portion, 63...rear metal body, 6 3a...opposing surface, 63b...exposed surface, 64...N wiring, 640, 644...base, 640a...opposing side, 640b...placement area, 640c...end, 641, 645...extension, 641a...widened portion, 641b...fixed width portion, 641c...widened portion, 641d...tip, 642...notch, 643...slit, 65...relay wiring, 650, 652...end, 651a...reduced width portion, 651b...fixed width portion, 651c...reduced width portion, 653...slit, 654...base, 655...extension, 70...conductive spacer, 700...uneven oxide film, 71...base material, 72...metal film, 80...arm connection portion, 81...joint Hand portion, 81a, 81b...end portion, 81c, 81d...side surface, 810...opposing surface, 811...accommodating portion, 811a...side surface, 811b...bottom surface, 90...external connection terminal, 91...power supply terminal, 91a, 91b...connecting portion, 91N...N terminal, 91P...P terminal, 92...output terminal, 92a...connecting portion, 920...opposing surface, 920a...first opposing portion, 920b...second opposing portion, 921...accommodating portion, 921a...side surface, 921b...bottom surface, 921c...opening, 922...tip surface, 923, 924...side surface, 93, 93H, 93L...signal terminal, 93a...tie bar mark, 93b...joint portion, 93c...tip portion, 9 3d...bent portion, 93e...extended portion, 93f...pressed R surface, 93g...burr surface, 93h...first extended portion, 93i...second extended portion, 93j...bent portion, 93k...projection portion, 930...overlapping portion, 930a...main portion, 930b...projection portion, 931...non-overlapping portion, 94...lead frame, 94a...tie bar, 94b...peripheral frame, 94c...guide frame, 940...connection portion, 941...first connecting portion, 941a...first extended portion, 941b...second extended portion, 942...second connecting portion, 100, 101, 102, 103, 104...joint material, 101A...sintered member, 101B...solder, 10 1C...multilayer bonding material, 105...sintered sheet, 106...sintered layer, 107, 108...weak layer, 110...bonding wire, 111...jig, 112...tool, 120...cooler, 121...heat exchanger, 130...thermal conductive member, 140...semiconductor module, 150...relay board, 151...insulating substrate, 151a...one side, 151b...back side, 151c...non-placement area, 151d...placement area, 151e...exposed portion, 152...conductor portion, 152a, 152b...land, 152c...wiring, 152d...via conductor, 152e...fixing land, 153...solder resist, 154...bonding material

Claims (3)

a semiconductor element (40) having a semiconductor substrate (41), a first main electrode (40D) on a high potential side provided on one surface of the semiconductor substrate, and a second main electrode (40S) on a low potential side provided on a back surface opposite to the one surface in a plate thickness direction;
a first wiring member (50) to which the first main electrode is electrically connected;
a second wiring member (60, 70) disposed between the semiconductor element and the first wiring member in the plate thickness direction and connected to the second main electrode;
a bonding material (101C, 101) interposed between the second main electrode and the second wiring member and bonding the second main electrode and the second wiring member,
the bonding material has a multilayer structure including a sintered layer (106) having a Young's modulus and/or a yield stress greater than those of the second main electrode, and a brittle layer (107) adjacent to the sintered layer in the plate thickness direction and having a Young's modulus and/or a yield stress smaller than those of the second main electrode,
The fragile layer (107) is a sintered body made of the same type of particles as the sintered layer, and the spacing between the particles is wider than that of the sintered layer.
The semiconductor device , wherein the bonding material has a three-layer structure having the sintered layers at both ends in the plate thickness direction and the brittle layer between the sintered layers . The second main electrode has a base electrode (42) formed on the back surface of the semiconductor substrate and a connection electrode (43) formed on the base electrode,
The semiconductor device according to claim 1 , wherein the base electrode contains aluminum and silicon. The second wiring member includes a wiring board (60) and a conductive spacer (70) interposed between the semiconductor element and the wiring board,
The semiconductor device according to claim 1 , wherein the bonding material bonds the second main electrode and the conductive spacer together.

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