JP3630070B2 - Semiconductor chip and semiconductor device - Google Patents

Semiconductor chip and semiconductor device Download PDF

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JP3630070B2
JP3630070B2 JP2000097911A JP2000097911A JP3630070B2 JP 3630070 B2 JP3630070 B2 JP 3630070B2 JP 2000097911 A JP2000097911 A JP 2000097911A JP 2000097911 A JP2000097911 A JP 2000097911A JP 3630070 B2 JP3630070 B2 JP 3630070B2
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surface
side
heat radiating
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joined
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JP2001284525A (en
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健 宮嶋
一雄 梶本
豊 福田
和仁 野村
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株式会社デンソー
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Priority to JP2000097911A priority Critical patent/JP3630070B2/en
Priority claimed from US09/717,227 external-priority patent/US6703707B1/en
Publication of JP2001284525A publication Critical patent/JP2001284525A/en
Priority claimed from US10/321,365 external-priority patent/US6693350B2/en
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    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor chip and its mounting structure, and is particularly suitable when a semiconductor chip on which a power element is formed is used.
[0002]
[Prior art]
Conventionally, a semiconductor chip (hereinafter simply referred to as a chip) on which a power device is formed is bonded to a heat radiating member made of Cu or the like through a bonding member such as solder to radiate heat. In recent years, in order to improve the heat dissipation efficiency, a heat dissipation member is provided also in an element formation region in which devices such as transistors and capacitors are formed in the chip in order to perform heat dissipation from both the front and back surfaces of the chip.
[0003]
FIG. 4 is a schematic cross-sectional view of an IGBT (Insulated Gate Bipolar Transistor) as an example of a chip. As shown in FIG. 4, a device J3 is formed on a chip J1 on a substrate J2 made of Si (silicon). Further, an emitter electrode (wiring) J4 made of a metal containing about 1% Si in Al (aluminum) is formed on the surface of the device J3.
[0004]
By the way, when Al containing no impurities (hereinafter referred to as pure Al) is used as the electrode J4, an alloy spike is generated when Si is dissolved in Al at the contact portion J5 where the substrate and the electrode are in direct contact. Occurs. The alloy spike greatly affects the characteristics of the device, for example, by destroying the PN junction. Therefore, the generation of this alloy spike is suppressed by containing Si in Al.
[0005]
[Problems to be solved by the invention]
However, if excessive Si is contained in Al, Si fine particles are deposited in the insulating film of the gate electrode portion J6 on the device surface (hereinafter referred to as Si nodule deposition). When the wire is ultrasonically bonded to the chip, wire bonding is performed on the electrode. At this time, when wire bonding is performed in the vicinity of the precipitated particles due to the Si nodule precipitation, the precipitated particles receive vibration energy at the time of bonding. Cracks occur in the device J3 and the gate electrode portion J6 starting from the grains.
[0006]
Incidentally, in recent years, there has been a demand for downsizing the power element, and accordingly, the cell pitch (indicated by L in FIG. 4) has become finer. In addition, the cell pitch L is further reduced by, for example, making the gate a trench structure in order to reduce the on-resistance. For example, a cell pitch of 4 μm or less has appeared.
[0007]
As the cell pitch L becomes finer, the problem that cracks occur in the device J3 becomes more serious as mechanical stress concentrates on the precipitated grains as described above.
[0008]
On the other hand, attention is focused on a configuration in which the chip J1 is sandwiched between a pair of heat radiating members by bonding a heat radiating member to the outside of the emitter electrode J4 and the collector electrode J7 in FIG. In this case, since the difference between the thermal expansion coefficient of the chip J1 made of Si and the thermal expansion coefficient of the heat radiating member made of Cu or the like is large, a large thermal stress is generated in the cooling cycle. Here, since Al containing Si has a larger elastic modulus than pure Al, relaxation of thermal stress in the electrodes J4 and J7 becomes insufficient. As a result, particularly on the element formation surface side, for example, thermal stress is concentrated on the emitter cell J8 and the gate electrode portion J6 of the chip, and there is a concern that the electrical characteristics such as the gate voltage threshold (hereinafter referred to as Vt) may fluctuate. The
[0009]
In addition, when a heat radiating member is provided also in an element forming region (for example, the region where the emitter cell J8 is formed in FIG. 4), and is in pressure contact with an external heat radiating fin as a cooling member, it contacts the end of the heat radiating member in the chip. It is conceivable that the stress due to the pressure welding is concentrated in the portion where the pressure is applied. Therefore, there is a possibility that the device J3 and the gate electrode portion J6 formed on the chip J1 or the chip J1 are broken, or the electrical characteristics of the device J3 are changed.
[0010]
In particular, in a power device through which a large current flows, there is a concern that due to the concentration of mechanical stress and thermal stress as described above, current concentrates on a specific cell and the device is thermally destroyed.
[0011]
In view of the above problems, an object of the present invention is to provide a semiconductor chip that can relieve stress applied from outside, and a semiconductor device that can relieve stress applied to an incorporated semiconductor chip. The other purpose is to provide.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, there is provided a semiconductor in which a heat dissipation member (21) is bonded to one side (1a) which is an element formation surface of a semiconductor chip (11) made of a Si substrate (110). In the device, the electrodes (112, 113) formed on one surface (1a) are pure Al containing no impurities, and a barrier metal (between the electrodes (112, 113) and the substrate (110) of the semiconductor chip (11) is formed. 111).
[0013]
When the semiconductor chip (11) is joined to the heat dissipation member (20) , Al containing no impurities has a low elastic modulus, and thus is generated due to a difference in thermal expansion coefficient between the semiconductor chip (11) and the heat dissipation member (20). The thermal stress to be relieved can be relieved.
[0014]
Further, since the barrier metal (111) is formed between the electrodes (112, 113) and the substrate (110), it is possible to prevent Si from dissolving in Al and to prevent the occurrence of alloy spikes. it can. As a result, since pure Al containing no Si can be used as the electrodes (112, 113), Si nodule precipitation in the vicinity of one surface (1a), which is an element formation surface , can be prevented, and the electrodes (112 113), mechanical stress can be prevented from concentrating on the Si precipitates when wire bonding is performed. Therefore, it is possible to provide a semiconductor device that can relieve stress applied to the incorporated semiconductor chip (11) .
[0015]
In this case, as in the invention described in claim 2, the electrode (115) formed on the surface (1b) opposite to the one surface (1a) which is the element forming surface of the semiconductor chip (11) contains impurities. There can be no pure Al. Thereby, also when joining a heat radiating member to the surface (1b) on the opposite side to one surface (1a) which is an element formation surface of a semiconductor chip (11), the thermal expansion coefficient of the semiconductor chip (11) and the heat radiating member is reduced. Thermal stress generated by the difference can be relaxed.
[0019]
Moreover, in invention of Claim 3 , in the invention of Claim 1 or 2 , the heat radiation direction from a heat radiating member (20) is opposite to one surface (1a) from one surface (1a) in a semiconductor chip (11). It is characterized by the direction toward the other surface (1b) on the side.
[0020]
According to the present invention, for example, when the cooling member is provided on the other surface (1b) side of the semiconductor chip (11), when the cooling member is pressed against the heat radiating member in order to dissipate heat, the semiconductor chip (11) It is possible to prevent stress due to pressure welding from concentrating on the one surface (1a) side. Therefore, in particular, it is possible to provide a semiconductor device that can relieve stress applied to the element formation surface (1a) of the incorporated semiconductor chip (11).
[0021]
Moreover, in invention of Claim 4 , in the invention of Claim 1 or 2 , a heat radiating member (24) is joined to the other surface (1b) on the opposite side to the one surface (1a) in the semiconductor chip (11), The heat radiating member (24) joined to the other surface (1b) side has a heat radiating surface (9) which is a portion joined to an external cooling member, and the heat radiating member (20) joined to the one surface (1a) side. And the heat radiating member (24) joined to the other surface (1b) side is joined, and the heat radiation from the one surface (1a) side is performed on the heat radiating surface (9).
[0022]
Thereby, the heat radiation direction from each heat radiating member (20, 24) is made to be a direction from one surface (1a) to the other surface (1b) in the semiconductor chip (11), similarly to the invention of claim 3. The same effect as that of the invention of claim 3 can be exhibited.
[0023]
Further, in this case, as in the invention described in claim 5 , the heat dissipating member (20) bonded to the one surface (1a) side and the heat dissipating member (24) bonded to the other surface (1b) side are highly thermally conductive. When bonded via the insulating substrate (4), the heat radiating member (20) bonded to the one surface (1a) side and the heat radiating member (24) bonded to the other surface (1b) side are electrically insulated, and further the heat Conduction can also be secured.
[0024]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
(This embodiment)
In the present embodiment, an example in which an IGBT is used as a semiconductor chip will be described. FIG. 1 is a schematic cross-sectional view of the semiconductor device of this embodiment. As shown in FIG. 1, for example, an IGBT 11 and an FWD (free wheel diode) 12 are used as semiconductor chips made of a Si substrate. First and second heat radiating members 21 and 22 for radiating heat from the chips 11 and 12 are joined to each IGBT 1 and FWD 12 on the side of the one surface 1 a that is an element forming surface via solder 31. ing.
[0026]
Further, the third heat radiating member 23 is bonded to the surface of the first and second heat radiating members 21 and 22 opposite to the surface bonded to the respective chips 11 and 12 via the solder 32. Has been. And these 1st-3rd heat radiating members 21-23 form the heat radiating member 20 of the one surface side.
[0027]
The third heat radiating member 23 has a plate-like shape having a protruding portion 23b, and its cross-sectional shape in the thickness direction is substantially L-shaped with the protruding portion 23b as a short side, and an L-shaped long side portion. The first and second heat radiating members 21 and 22 are joined together. Further, when viewed from the cross-sectional direction of each chip 11, 12, the tip 23 a of the projecting portion 23 b is substantially the same height as the other surface 1 b of each chip 11, 12. Here, the 1st-3rd heat radiating members 21-23 can use what consists of Cu, for example.
[0028]
Further, a DBC (direct bonding kappa) substrate 4 as a high thermal conductive insulating substrate is disposed on the other surface 1b side of each of the chips 11 and 12. The DBC substrate 4 is obtained by patterning copper foils 51 to 54 on both surfaces 5 a and 5 b of an AlN (aluminum nitride) substrate 5.
[0029]
And the other surface 1b side of each chip | tip 11 and 12 is joined via the solder 33 with respect to the 1st copper foil 51 of the one surface 5a side in the DBC board | substrate 4. FIG. In addition, the tip 23 a of the protrusion 23 b of the third heat radiating member 23 is joined to the second copper foil 52 on the one surface 5 a side of the DBC substrate 4 via the solder 34.
[0030]
Next, the configuration of the electrode (wiring) portion of the IGBT 11 will be described. FIG. 2 is an enlarged view of a portion A surrounded by a broken line in FIG. 1, and schematically shows the configuration thereof. As shown in FIG. 2, a barrier metal 111 is formed on the one surface 1 a side of the substrate 110 of the IGBT 11.
[0031]
Further, an emitter electrode 112 as an electrode on one side and a wire bond land 113 are formed of pure Al thereon. Here, the barrier metal 111 is formed by laminating Ti (titanium) and TiN (titanium nitride) in this order from the substrate 110 side, and the thickness thereof is, for example, about 0.1 μm. The thickness of the electrodes 112 and 113 on the one surface side is preferably about 5 μm, for example.
[0032]
In addition, a metal film 114 is formed on the emitter electrode 112 for good connection with solder. The metal film 114 is formed by stacking Ti, Ni (nickel), and Au (gold) in this order from the emitter electrode 112 side, and has a thickness of, for example, about 0.6 μm. The first heat radiating member 21 is bonded to the metal film 114 via the solder 31 as described above. Here, the thicknesses of the solder 31 and the first heat radiating member 21 can be set to, for example, about 0.1 mm and 1.5 mm, respectively.
[0033]
On the other hand, on the other surface 1b side of the substrate 110, a collector electrode 115 as an electrode on the other surface side made of pure Al is formed without forming a barrier metal. The collector electrode 115 can have a thickness of about 0.2 μm, for example. Further, a metal film 116 is formed on the collector electrode 115 in the same manner as the emitter electrode 112, and the metal film 116 is connected to the first copper on the one surface 5 a side of the DBC substrate 4 via the solder 33. The foil 51 is joined.
[0034]
The FWD 12 has the same electrode configuration as the IGBT 11.
[0035]
Next, as shown in FIG. 1 and FIG. 2, in order to energize the emitter electrode 112 and the lead (emitter terminal) 61 which is an external terminal, the third heat radiating member 23 and the lead 61 are connected to the connection terminal 6a. Electrically connected. Further, a land 53 is formed on the DBC substrate 4, and the land 53 and the wire bonding land 113 on the one surface 1 a of the IGBT 11 are wire-bonded by the wire 7, and the land 53 and the gate terminal 8 of the DBC substrate 4 are connected. Is wire-bonded by a wire 7.
[0036]
Here, as the wire 7, a material generally used for wire bonding, such as Au or Al, can be used. The land 53 of the DBC substrate 4 is provided for relaying between the wire bond land 113 and the gate terminal 8.
[0037]
A fourth heat radiation member (heat radiation member on the other surface side) 24 is joined to the copper foil 54 formed on the back surface 5 b side of the DBC substrate 4 via a solder 35. That is, the heat radiating member 20 on the one surface side and the heat radiating member 24 on the other surface side are joined via the DBC substrate 4 to ensure electrical insulation and heat conduction of the heat radiating members 20 and 24.
[0038]
Each member described above is sealed with resin 100. At this time, the surface of the heat radiating member 24 on the other surface side opposite to the surface bonded to the DBC substrate 4 is exposed to form the heat radiating surface 9. Here, as the resin 100, for example, an epoxy mold resin can be used.
[0039]
Next, a more detailed configuration of the electrical connection of each part in the semiconductor device of this embodiment will be described with reference to FIG. FIG. 3 is a top view schematically showing the semiconductor device when viewed from the direction of the white arrow in FIG. 1 corresponds to a cross section taken along line BB in FIG. As shown in FIG. 3, the semiconductor device of this embodiment includes two sets of IGBTs 11 and FWDs 12.
[0040]
The heat radiation member 20 (21 to 23) on the one surface side is indicated by an alternate long and short dash line in the drawing, and is electrically connected to the emitter terminal 61 via the connection terminal 6a as described above. Also, the first copper foil 51 of the DBC substrate 4 is bonded to all of the electrodes on the other surface 1b side of the two sets of IGBTs 11 and FWDs 12 so as not to contact the second copper foil 52 of the DBC substrate 4. It protrudes. Further, the protruding portion 51a and the collector terminal 62 which is a lead are electrically connected through the connection terminal 6b.
[0041]
In the semiconductor device having such a configuration, the heat radiating surface 9 is fixed to a heat radiating fin (not shown) as an external cooling member (external heat radiator) by screwing or the like. As a result, heat is radiated from the heat radiating surface 9 from the one surface 1 a side of each chip 11, 12 through the heat radiating member 20 on the one surface side, the DBC substrate 4, and the heat radiating member 24 on the other surface side. That is, the heat radiation direction from the one surface 1a side of each chip 11, 12 is the direction from the one surface 1a to the other surface 1b in each chip 11, 12 (the direction from the top to the bottom in FIG. 1).
[0042]
On the other hand, heat is radiated from the heat radiating surface 9 from the other surface 1 b side of each chip 11, 12 via the DBC substrate 4 and the heat radiating member 24 on the other surface side. Accordingly, in the semiconductor device in which the chips are incorporated, the positional relationship between the one surface 1a and the other surface 1b of each chip 11, 12 and the heat radiation surface 9 is in this order, and the heat radiation surface 9 is joined to an external cooling member. Thus, the heat radiation from both surfaces 1a and 1b of the respective chips 11 and 12 is performed mainly on the heat radiation surface 9.
[0043]
Next, a method for manufacturing the semiconductor device of this embodiment will be described. First, the IGBT 11 and the FWD 12 having the barrier metal 111, the emitter electrode 112, the collector electrode 115, and the metal films 114 and 116 as described above are prepared. These electrodes 112 and 115, barrier metal 111, metal films 114 and 116, and the like can be formed by sputtering, for example. Then, the first and second heat radiating members 21 and 22 are soldered to the one surface 1a of the chips 11 and 12, respectively.
[0044]
Next, the DBC substrate 4 in which the copper foils 51 to 54 are patterned on the one surface 5a and the other surface 5b is prepared, and the IGBT 11 and the FWD 12 are soldered to predetermined positions. Thereafter, the third heat radiating member 23 is soldered to the first and second heat radiating members 21 and 22 and the DBC substrate 4. In soldering the third heat radiating member 23, the solder is made slightly thicker at the joint portion with the DBC substrate 4 than at the joint portion with the first and second heat radiating members 21, 22. Try to absorb variations in height.
[0045]
Each soldering should be performed by reflow or the like, and if the melting point of the solder to be used is gradually lowered in the order of soldering, soldering is suitably performed without affecting the solder that was initially joined. Can do.
[0046]
Then, connection between the emitter terminal 61 and the collector terminal 62 and the third heat radiating member 23 and wire bonding between the IGBT 11 and the gate terminal 8 are performed. Subsequently, the fourth heat radiating member 24 is soldered to the DBC substrate 4, and finally, resin sealing is completed.
[0047]
By the way, according to this embodiment, since pure Al has a small elastic modulus, the thermal stress generated by the difference in thermal expansion coefficient between each of the chips 11 and 12 and each of the heat radiating members 21 to 24 can be relieved. Specifically, the elastic modulus of pure Al is 72 GPa, and the elastic modulus of Al containing 1% Si is about 75 GPa. When Si is segregated on the surface of the contact part J5 and the gate electrode part J6 shown in FIG. 4 used in the above prior art in the manufacturing process using Al containing Si, the elastic modulus of Si is 130 GPa. Locally, the ability to relieve thermal stress is very small.
[0048]
In particular, when the emitter electrode 112 of the IGBT 11 is made of pure Al, it is possible to suppress, for example, stress concentration on the emitter cell and fluctuation of electrical characteristics such as Vt. Therefore, a chip and a semiconductor device with high electrical reliability can be provided. Moreover, the curvature of each chip | tip 11 and 12 resulting from a thermal stress can be reduced by making the electrode by the side of the other surface 1b of each chip | tip 11 and 12 into pure Al.
[0049]
Further, since Si is not contained in the electrodes 112, 113, and 115, Si nodule precipitation can be prevented. This is particularly effective in the wire bond land 113. As described in the above problem, Si precipitate grains are formed on an insulating film (not shown) or the like in the Si substrate 110 near the wire bond land 113, and mechanical vibration ( When the stress is concentrated, the problem that cracks occur in the insulating film and the device in the Si substrate 110 can be solved.
[0050]
Thus, by making the electrodes 112, 113, and 115 pure Al, the stress applied from the outside is relieved, that is, the pure Al is added to the semiconductor chip acting as a cushion and the incorporated semiconductor chip. A semiconductor device capable of relieving stress can be provided.
[0051]
However, when pure Al is brought into direct contact with Si as the substrate 110, alloy spikes are generated. Therefore, a barrier metal 111 is formed between the electrodes 112, 113 and the substrate 110 to prevent the alloy spikes from being generated. . Although no barrier metal is formed on the other surface 1b side of the IGBT 11, even if an alloy spike occurs on the other surface 1b side, it is considered that the device formed on the one surface 1a side does not reach the barrier metal. May not be formed.
[0052]
Further, for example, in a semiconductor device in which a chip is sandwiched between a pair of heat radiating members and each of the heat radiating members has a heat radiating surface, the heat radiating surface and the cooling member are pressed against each other by sandwiching the semiconductor device with an external cooling member. And contact. However, with such a configuration, the pressure stress when sandwiched is concentrated on the chip.
[0053]
On the other hand, in the present embodiment, a heat radiating surface 9 that mainly radiates heat to the outside of the semiconductor device is formed on the other surface 1b side of each of the chips 11 and 12. In such a configuration, it is not necessary to sandwich the semiconductor device with a cooling member in order to perform heat dissipation. Therefore, even if the heat radiating surface 9 is firmly connected to an external cooling member, Large stress is not applied.
[0054]
Furthermore, since the heat dissipation members 21, 22, and 24 are bonded to each of the chips 11 and 12 both on the one surface 1a side and on the other surface 1b side, the both surfaces 1a and 1b of each chip 11 and 12 are connected. Heat dissipation.
[0055]
Therefore, the chip 11, 12 and the device formed on the chip can be prevented from cracking in a state in which the heat radiation effect from the both surfaces 1a, 1b of each chip 11, 12 is ensured. . In particular, since the heat radiating surface 9 is formed on the other surface 1b side of each chip 11, 12, it is possible to prevent stress from concentrating on the one surface 1a side of each chip, and for the device formed on the one surface 1a side. Variations in electrical characteristics can be suppressed.
[0056]
The heat radiation surface 9 is electrically insulated from the chips 11 and 12 by the DBC substrate 4 which is an insulating substrate used inside the semiconductor device. For this reason, it is not necessary to consider electrical insulation in joining with an external cooling member. Moreover, the insulation with both the one surface 1a side of each chip | tip and the other surface 1b side is securable by the sheet | seat 1 of the insulated substrate 4. FIG.
[0057]
In the present embodiment, the heat radiating surface 9 that mainly radiates heat is formed on the other surface 1b side of each of the chips 11 and 12. For example, the third heat radiating member 23 is exposed outside the resin 100. For example, the heat radiation may be supplemented by other portions. However, in this case, the exposed portion of the third heat radiating member 23 is brought into firm contact with an external cooling member so that no pressure stress is applied to the element forming surface 1a of the chips 11 and 12. Further, if no pressure stress is applied to the element forming surface 1a of the chips 11, 12, the semiconductor device may be sandwiched and fixed.
[0058]
When attention is paid to the protection of the devices of the respective chips 11 and 12, the electrode 115 on the other surface 1b side of each chip may not be pure Al. Moreover, although the 1st-3rd heat radiating members 21-23 were shown about the example formed separately and soldered, you may form integrally.
[0059]
Further, the electrode of the FWD 12 may not be made of pure Al as long as there is no problem such as thermal stress. If insulation between the heat radiation member 20 on the one surface side and the heat radiation member 24 on the other surface side is not necessary, the DBC substrate 4 made of AlN may not be used. The land 53 of the DBC substrate 4 may not be provided as long as the wire bond land 113 of the IGBT 11 and the gate terminal 8 can be directly wire bonded.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment.
FIG. 2 is a cross-sectional view showing a configuration of an IGBT in the present embodiment.
FIG. 3 is a top view of the semiconductor device according to the present embodiment.
FIG. 4 is a schematic cross-sectional view partially showing a conventional IGBT.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1a ... Element formation surface, 4 ... High heat conductive insulation board, 9 ... Heat dissipation surface,
11, 12 ... Semiconductor chip, 20-24 ... Heat dissipation member, 110 ... Substrate,
111 ... Barrier metal, 112, 113 ... One side electrode,
115: Electrode on the other side.

Claims (5)

  1. In a semiconductor device in which a heat radiating member (20) for radiating heat of the semiconductor chip (11) is joined to one surface (1a) side which is an element formation surface of a semiconductor chip (11) made of a Si substrate (110). ,
    The electrodes (112, 113) formed on the one surface (1a) are pure Al containing no impurities,
    A barrier metal (111) for preventing Si from dissolving in Al is formed between the electrodes (112, 113) and the substrate (110) of the semiconductor chip (11). Semiconductor device.
  2. Wherein the one surface of the semiconductor chip (11) (1a) electrode formed on the other surface opposite (1b) and (115), according to claim 1, characterized in that a pure Al containing no impurities Semiconductor device.
  3. The heat radiation direction from the heat radiating member (20) is a direction from the one surface (1a) of the semiconductor chip (11) toward the other surface (1b) on the opposite side to the one surface (1a). the semiconductor device according to claim 1 or 2, characterized.
  4. A heat dissipation member (24) is joined to the other surface (1b) side opposite to the one surface (1a) in the semiconductor chip (11),
    The heat dissipating member (24) joined to the other surface (1b) side has a heat dissipating surface (9) that is a part joined to an external cooling member,
    The heat radiating member (20) joined to the one surface (1a) side and the heat radiating member (24) joined to the other surface (1b) side are joined, and the heat radiation from the one surface (1a) side is the semiconductor device according to claim 1 or 2, characterized in that takes place in the heat radiating surface (9).
  5. The heat radiating member (20) joined to the one surface (1a) side and the heat radiating member (24) joined to the other surface (1b) side are joined via a high thermal conductive insulating substrate (4). The semiconductor device according to claim 4 .
JP2000097911A 2000-03-30 2000-03-30 Semiconductor chip and semiconductor device Expired - Fee Related JP3630070B2 (en)

Priority Applications (1)

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JP2000097911A JP3630070B2 (en) 2000-03-30 2000-03-30 Semiconductor chip and semiconductor device

Applications Claiming Priority (18)

Application Number Priority Date Filing Date Title
JP2000097911A JP3630070B2 (en) 2000-03-30 2000-03-30 Semiconductor chip and semiconductor device
US09/717,227 US6703707B1 (en) 1999-11-24 2000-11-22 Semiconductor device having radiation structure
FR0015130A FR2801423B1 (en) 1999-11-24 2000-11-23 Semiconductor device with radiant structure, method for manufacturing semiconductor device, and method for manufacturing electronic instrument
DE10066442A DE10066442B4 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating structure
DE10066446A DE10066446B4 (en) 1999-11-24 2000-11-24 Method for producing an electronic component with two emission components
DE10066443A DE10066443B8 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating components
DE10066445A DE10066445B4 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating structure
DE10066441A DE10066441B4 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating components
DE10058446A DE10058446B8 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating components
US10/321,365 US6693350B2 (en) 1999-11-24 2002-12-18 Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure
US10/699,828 US6992383B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,837 US6960825B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,784 US20040089941A1 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,838 US6798062B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,746 US6998707B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,954 US6967404B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,744 US20040089940A1 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,785 US6891265B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure

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JP3630070B2 true JP3630070B2 (en) 2005-03-16

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