JP3630070B2 - A semiconductor chip and semiconductor device - Google Patents

A semiconductor chip and semiconductor device Download PDF

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Publication number
JP3630070B2
JP3630070B2 JP2000097911A JP2000097911A JP3630070B2 JP 3630070 B2 JP3630070 B2 JP 3630070B2 JP 2000097911 A JP2000097911 A JP 2000097911A JP 2000097911 A JP2000097911 A JP 2000097911A JP 3630070 B2 JP3630070 B2 JP 3630070B2
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surface
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1a
heat
joined
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JP2001284525A (en )
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健 宮嶋
一雄 梶本
豊 福田
和仁 野村
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株式会社デンソー
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Description

【0001】 [0001]
【発明の属する技術分野】 BACKGROUND OF THE INVENTION
本発明は、半導体チップおよびその実装構造に関し、特にパワー素子が形成された半導体チップを用いる場合に好適である。 The present invention relates to a semiconductor chip and its mounting structure, is suitable in particular when the power device using a semiconductor chip formed is.
【0002】 [0002]
【従来の技術】 BACKGROUND OF THE INVENTION
従来、パワーデバイスが形成された半導体チップ(以下、単にチップという)は、半田等の接合部材を介して、Cu等からなる放熱部材に接合して放熱を行っている。 Conventionally, a semiconductor chip in which the power devices are formed (hereinafter, simply referred to as chips) via the junction member such as solder, and to radiate the heat joined to the heat radiating member made of Cu or the like. 近年、その放熱効率を向上させるために、チップの表裏両面から放熱を行うべく、チップにおけるトランジスタやコンデンサ等のデバイスが形成されている素子形成領域にも放熱部材を設けるようになっている。 Recently, in order to improve the heat dissipation efficiency, in order to perform the heat dissipation from both sides of the chip, in the element formation region devices such as transistors and capacitors are formed in the chip is adapted to provide a heat radiating member.
【0003】 [0003]
図4は、チップの一例としてのIGBT(Insulated Gate Bipolar Transistor)の概略断面図である。 Figure 4 is a schematic cross-sectional view of a IGBT (Insulated Gate Bipolar Transistor) as an example of a chip. 図4に示すように、チップJ1にはSi(珪素)からなる基板J2においてデバイスJ3が形成されている。 As shown in FIG. 4, the device J3 are formed in the substrate J2 made of Si (silicon) in the chip J1. また、デバイスJ3の表面には、Al(アルミニウム)に1%程度のSiを含んだ金属からなるエミッタ電極(配線)J4が形成されている。 The surface of the device J3, Al emitter electrode made of a metal containing Si of about 1% (aluminum) (wiring) J4 is formed.
【0004】 [0004]
ところで、この電極J4として不純物を含まないAl(以下、純Alという)を用いると、基板と電極とが直接接触する部分であるコンタクト部J5において、SiがAl中に溶解することで生じるアロイスパイクが生じる。 Meanwhile, Al (hereinafter, referred to as pure Al) free of impurities as the electrode J4 With, in the contact portion J5 is a portion where the substrate and the electrode are in direct contact, alloy spikes caused by Si dissolves in the Al It occurs. そして、このアロイスパイクが、例えばPN接合を破壊するなどしてデバイスの特性に大きな影響を与える。 Then, this alloy spike, a significant impact on the performance of the device for example, by destroying the PN junction. 従って、AlにSiを含有させることにより、このアロイスパイクの発生を抑制している。 Therefore, by incorporating Si into Al, thereby suppressing the occurrence of alloy spike.
【0005】 [0005]
【発明が解決しようとする課題】 [Problems that the Invention is to Solve
しかし、Alに過剰のSiが含有されていると、デバイス表面のゲート電極部J6の絶縁膜などにおいてSi微粒子が析出(以下、Siノジュール析出という)する。 However, an excess of Si to Al is contained, Si particles deposited (hereinafter, referred to as Si nodules precipitated) in an insulating film of the gate electrode portion J6 of the device surface is. そして、チップにワイヤを超音波接合する場合は、上記電極上にワイヤボンドするが、この際、上記Siノジュール析出による析出粒付近にワイヤボンドすると、析出粒がボンディング時の振動エネルギーを受け、析出粒を起点としてデバイスJ3及びゲート電極部J6にクラックが生じる。 When the ultrasonic bonding wire to the chip, the wire bonding onto the electrode, but this time, when the wire bonding in the vicinity of precipitated particles by the Si nodules precipitated is grains subjected to vibration energy at the time of bonding, deposition cracking the device J3 and the gate electrode portion J6 grain as a starting point.
【0006】 [0006]
ところで、近年、パワー素子を小型化する要望があり、これに伴い、セルピッチ(図4においてLで示している)が細かくなっている。 In recent years, there is a desire to reduce the size of the power element, with this, the cell pitch (indicated by L in FIG. 4) becomes finer. また、オン抵抗を下げるためゲートをトレンチ構造とすること等にもよりセルピッチLがさらに細かくなり、例えば4μm以下のものも現れてきている。 Further, also it becomes more cell pitch L is finer gate to lower the on-resistance in such a trench structure, also emerging for example 4μm as follows.
【0007】 [0007]
そして、セルピッチLが細かくなるほど、上述のように、析出粒に機械的な応力が集中することにより、デバイスJ3にクラックが発生するという問題が深刻になる。 Then, as the cell pitch L becomes finer, as described above, by mechanical stress concentrates on precipitation grains, a problem that cracks are generated becomes serious device J3.
【0008】 [0008]
一方、図4のエミッタ電極J4およびコレクタ電極J7の外側に放熱部材を接合させる等して、チップJ1を一対の放熱部材で挟んだ構成に着目する。 On the other hand, and the like joining the heat radiating member to the outside of the emitter electrode J4 and a collector electrode J7 of Figure 4, attention is paid to the structure sandwiching the chip J1 by a pair of heat radiation members. この場合、SiからなるチップJ1の熱膨張係数と、Cu等からなる放熱部材の熱膨張係数の差が大きいため、冷熱サイクルにおいて大きな熱応力が発生する。 In this case, the thermal expansion coefficient of the chip J1 consisting Si, since the difference in thermal expansion coefficient of the heat radiating member made of Cu or the like is large, a large thermal stress is generated in the thermal cycle. ここで、Siを含むAlは、純Alよりも弾性率が大きいため、電極J4、J7における熱応力の緩和が不十分となる。 Here, Al containing Si, because a large modulus of elasticity than that of pure Al, an insufficient relaxation of thermal stress in the electrode J4, J7. その結果、特に素子形成面側では、例えばチップのエミッタセルJ8及びゲート電極部J6に熱応力が集中し、ゲート電圧の閾値(以下、Vtとする)等の電気特性が変動することが懸念される。 As a result, in particular the element formation surface side, for example, thermal stress is concentrated on the emitter cell J8 and the gate electrode portion J6 of the chip, the gate voltage threshold (hereinafter referred to as Vt) electric properties such as are concerned may vary that.
【0009】 [0009]
また、放熱部材を素子形成領域(例えば、図4ではエミッタセルJ8の形成領域)にも設け、さらに、冷却部材としての外部放熱フィン等に圧接する場合は、チップにおける放熱部材の端部と接触する部分において、上記圧接による応力が集中することが考えられる。 Further, the heat radiating member an element formation region (e.g., formation areas of FIG. 4, the emitter cell J8) also provided, further, when pressed against the external radiation fins such as a cooling member, in contact with the end portion of the heat radiating member in the chip in portions, stress caused by the pressure is considered to concentrate. そのため、チップJ1やチップJ1に形成されたデバイスJ3及びゲート電極部J6が割れたり、デバイスJ3の電気特性が変動したりする可能性がある。 Therefore, it cracked chips J1 and devices J3 and the gate electrode portion J6 formed on the chip J1 is, electric characteristics of the device J3 is likely to be changing.
【0010】 [0010]
特に、大電流を流すパワーデバイスにおいては、上述のような、機械的応力および熱応力の集中により、特定セルに電流集中してデバイスが熱破壊することが懸念される。 In particular, in a power device for flowing a large current, as described above, the concentration of mechanical stresses and thermal stresses, the device and current concentration is feared that thermal destruction to a particular cell.
【0011】 [0011]
本発明は、上記問題点に鑑み、外部から加えられる応力を緩和することができる半導体チップを提供することを1つの目的とし、組み込まれた半導体チップに加わる応力を緩和することができる半導体装置を提供することを他の目的とする。 In view of the above problems, and one object is to provide a semiconductor chip capable of relaxing the stress applied from the outside, a semiconductor device capable of relieving the stress applied to the integrated semiconductor chip to provide and other purposes.
【0012】 [0012]
【課題を解決するための手段】 In order to solve the problems]
上記目的を達成するため、請求項1に記載の発明では、 Si基板(110)からなる半導体チップ(11)の素子形成面である一面(1a)側に、放熱部材(21)を接合した半導体装置において、一面 (1a)に形成した電極(112、113)が不純物を含まない純Alであり、電極(112、113)と半導体チップ(11)の基板(110)との間にバリアメタル(111)を形成していることを特徴としている。 To achieve the above object, according to the invention of claim 1, it was bonded to one surface (1a) side, which is the element forming surface of a semiconductor chip made of Si substrate (110) (11), the heat radiating member (21) Semiconductor in the device, a pure Al which electrodes formed on one surface (1a) (112, 113) is free of impurities, a barrier metal between the substrate electrode (112, 113) and the semiconductor chip (11) (110) ( It is characterized by forming a 111).
【0013】 [0013]
半導体チップ(11)を放熱部材(20)と接合させた場合に、不純物を含まないAlは弾性率が小さいため、半導体チップ(11)と放熱部材(20)との熱膨張係数の違いにより発生する熱応力を緩和することができる。 When the semiconductor chip (11) was bonded heat dissipating member (20), since the Al containing no impurities is small elastic modulus, caused by the difference in thermal expansion coefficient between the semiconductor chip (11) and the heat radiating member (20) heat stress can be alleviated.
【0014】 [0014]
また、電極(112、113)と基板(110)との間にバリアメタル(111)を形成しているため、SiがAl中に溶解することを防止し、アロイスパイクの発生を防止することができる。 Moreover, since forming the barrier metal (111) between the electrode (112, 113) and the substrate (110), to prevent the Si dissolves in Al, it is possible to prevent the occurrence of alloy spikes it can. その結果、電極(112、113)としてSiが含まれていない純Alを用いることができるため、素子形成面である一面 (1a)付近におけるSiのノジュール析出を防止することができ、電極(112、113)にワイヤボンドした際にSiの析出粒に機械的な応力が集中することを防止することができる。 As a result, it is possible to use a pure Al that does not contain Si as an electrode (112, 113), it is possible to prevent the nodule deposition of Si on the surface of the one (1a) around an element forming surface, the electrodes (112 , it is possible to prevent the mechanical stress is concentrated on the precipitation grains of Si upon wire bonding 113). 従って、 組み込まれた半導体チップ(11)に加わる応力を緩和することができる半導体装置を提供することができる。 Therefore, it is possible to provide a semiconductor device capable of relieving the stress applied to the integrated semiconductor chip (11).
【0015】 [0015]
この場合、請求項2に記載の発明のように、 半導体チップ(11)の素子形成面である一面 (1a)とは反対側の面(1b)に形成した電極(115)を、不純物を含まない純Alにすることができる。 In this case, as in the embodiment described in claim 2, one surface is an element forming surface of the semiconductor chip (11) and (1a) electrodes (115) formed on the opposite side (1b) and, free of impurities it can be in no net Al. これにより、半導体チップ(11)の素子形成面である一面 (1a)とは反対側の面(1b)に放熱部材を接合する場合も、半導体チップ(11)と放熱部材との熱膨張係数の違いにより発生する熱応力を緩和することができる。 Thus, even if one side is an element forming surface of the semiconductor chip (11) and (1a) joining the heat radiating member on the opposite side (1b), the thermal expansion coefficient between the heat radiating member semiconductor chip (11) thermal stress generated by the difference can be relaxed.
【0019】 [0019]
また、請求項に記載の発明では、請求項またはの発明において、放熱部材(20)からの放熱方向が、半導体チップ(11)における一面(1a)から、一面(1a)とは反対側の他面(1b)へ向かう方向となっていることを特徴としている。 Further, in the invention according to claim 3, contrary to the invention of claim 1 or 2, the heat radiation direction from the heat radiation member (20) from one surface of the semiconductor chip (11) (1a), and one surface (1a) is characterized in that has a direction toward the other surface side (1b).
【0020】 [0020]
本発明によれば、例えば、半導体チップ(11)の他面(1b)側において冷却部材を設けた場合、放熱を行うために冷却部材を放熱部材に圧接する際に、半導体チップ(11)の一面(1a)側に圧接による応力が集中することを防止できる。 According to the present invention, for example, the case of providing a cooling member at the other surface (1b) side of the semiconductor chip (11), when pressed against the cooling member to the heat radiating member to perform a heat dissipation, the semiconductor chip (11) possible to prevent the stress concentration due to pressure on one side (1a) side. 従って、特に、組み込まれた半導体チップ(11)の、素子形成面(1a)に加わる応力を緩和することができる半導体装置を提供することができる。 Thus, in particular, the integrated semiconductor chip (11), it is possible to provide a semiconductor device capable of relieving the stress applied to the element formation surface (1a).
【0021】 [0021]
また、請求項に記載の発明では、請求項またはの発明において、半導体チップ(11)における一面(1a)とは反対側の他面(1b)に放熱部材(24)を接合し、他面(1b)側に接合した放熱部材(24)が、外部の冷却部材と接合する部分である放熱面(9)を有しており、一面(1a)側に接合した放熱部材(20)と、他面(1b)側に接合した放熱部材(24)とを接合して、一面(1a)側からの放熱を放熱面(9)で行うことを特徴としている。 Further, in the invention according to claim 4, in the invention of claim 1 or 2, bonded to the heat radiating member (24) on the other surface opposite to (1b) and a surface of the semiconductor chip (11) (1a), the other surface (1b) bonded to side radiating member (24) has heat radiating surface is a portion to be bonded to the outside of the cooling member (9), one surface (1a) joining the heat radiating member side (20) If, by joining a second surface (1b) bonded to side radiating member (24), and characterized by performing heat radiating surface heat radiation from one surface (1a) side (9).
【0022】 [0022]
これにより、各々の放熱部材(20、24)からの放熱方向を、請求項の発明と同様に、半導体チップ(11)における一面(1a)から他面(1b)へ向かう方向とすることができ、請求項の発明と同様の効果を発揮することができる。 Thus, the heat radiation direction from each of the heat radiating member (20, 24), in the same manner as the invention of claim 3, be the direction toward one surface of the semiconductor chip (11) from (1a) to the other surface (1b) can, it is possible to exhibit the same effects as the invention of claim 3.
【0023】 [0023]
また、この場合、請求項に記載の発明のように、一面(1a)側に接合した放熱部材(20)と、他面(1b)側に接合した放熱部材(24)とを、高熱伝導絶縁基板(4)を介して接合すると、一面(1a)側に接合した放熱部材(20)と他面(1b)側に接合した放熱部材(24)との電気的な絶縁を行い、さらに熱伝導も確保することができる。 In this case, as in the invention of claim 5, the heat radiating member joined to the one surface (1a) side (20), and the other surface (1b) bonded to side radiating member (24), high thermal conductivity When bonded via the insulating substrate (4), the electrical insulation between the one surface (1a) joining the heat radiating member (20) bonded to the other surface (1b) side toward the heat radiating member (24), further heat conductivity can be ensured.
【0024】 [0024]
なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示すものである。 The reference numerals in parentheses of each means described above, shows the correspondence with specific means described in embodiments described later.
【0025】 [0025]
【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION
(本実施形態) (The present embodiment)
本実施形態は、半導体チップとしてIGBTを用いた例について示す。 This embodiment shows an example in which an IGBT is used as the semiconductor chip. 図1は、本実施形態の半導体装置の概略断面図である。 Figure 1 is a schematic cross-sectional view of a semiconductor device of the present embodiment. 図1に示すように、例えば、Si基板からなる半導体チップとしてのIGBT11およびFWD(フリーホイールダイオード)12を用いる。 As shown in FIG. 1, for example, IGBT 11 and FWD (free wheel diodes) as a semiconductor chip made of Si substrate used 12. このIGBT11およびFWD12の各々の素子形成面である一面1a側には、各々のチップ11、12の放熱を行うための第1および第2の放熱部材21、22が、半田31を介して接合されている。 On one surface 1a side is an element forming surface of each of the IGBT11 and FWD12, first and second heat radiating members 21 and 22 for performing the heat radiation of each of the chips 11 and 12 are bonded via the solder 31 ing.
【0026】 [0026]
また、この第1および第2の放熱部材21、22における、各々のチップ11、12と接合された面とは反対側の面に対して、半田32を介して第3の放熱部材23が接合されている。 Further, in the first and second heat radiating members 21 and 22, relative to the surface opposite to the respective chips 11 and 12 and bonded surface, the third heat radiating member 23 through the solder 32 is bonded It is. そして、これらの第1〜第3の放熱部材21〜23により一面側の放熱部材20を形成している。 Then, these first to third heat radiating member 21 to 23 to form a heat radiating member 20 of one side.
【0027】 [0027]
この第3の放熱部材23は、突出部23bを有する板状のもので、その厚み方向の断面形状が突出部23bを短辺とする略L字型になっており、L字の長辺部において第1および第2の放熱部材21、22が接合している。 The third heat radiating member 23 is of a plate shape having a protruding portion 23b, the thickness direction of the cross section are made substantially L-shaped and short side projections 23b, the long side portion of the L-shaped first and second heat radiating members 21, 22 are joined at. また、各々のチップ11、12の断面方向から見ると、突出部23bの先端部23aが、各々のチップ11、12の他面1bとほぼ同じ高さになっている。 Further, when viewed from a cross-sectional direction of each of the chips 11 and 12, the distal end portion 23a of the protruding portion 23b has almost the same height as the other surface 1b of the respective chips 11 and 12. ここで、第1〜第3の放熱部材21〜23は例えばCuからなるものを用いることができる。 Here, first to third heat radiating member 21 to 23 can be used made of, for example, Cu.
【0028】 [0028]
また、各々のチップ11、12の他面1b側には、高熱伝導絶縁基板としてのDBC(ダイレクトボンディングカッパ)基板4が配置されている。 In addition, the other surface 1b side of each chip 11, 12, DBC as high heat conductive insulating substrate (direct bonding kappa) substrate 4 is disposed. このDBC基板4は、AlN(窒化アルミニウム)基板5の両面5a、5bに銅箔51〜54がパターニングされてなる。 The DBC substrate 4, AlN (aluminum nitride) substrate 5 of the double-sided 5a, the copper foil 51 to 54 5b formed by patterning.
【0029】 [0029]
そして、各々のチップ11、12の他面1b側が、DBC基板4における一面5a側の第1の銅箔51に対して半田33を介して接合されている。 Then, they are joined through the solder 33 to the other surface 1b side is, the first copper foil 51 on one surface 5a side of the DBC substrate 4 of each of the chips 11 and 12. また、第3の放熱部材23における突出部23bの先端部23aが、DBC基板4における一面5a側の第2の銅箔52に対して、半田34を介して接合されている。 The tip portion 23a of the projecting portion 23b of the third heat radiating member 23, the second copper foil 52 on one surface 5a side of the DBC substrate 4 are bonded via the solder 34.
【0030】 [0030]
次に、IGBT11の電極(配線)部分の構成について述べる。 Next, there will be described a configuration of the electrodes (wiring) portion of the IGBT 11. 図2は、図1における破線で囲んだA部の拡大図であり、その構成を概略的に示す図である。 Figure 2 is an enlarged view of a portion A surrounded by a broken line in FIG. 1 is a diagram showing a configuration schematically. 図2に示すように、IGBT11の基板110における一面1a側にはバリアメタル111が形成されている。 As shown in FIG. 2, on one surface 1a side of the substrate 110 of the IGBT11 and a barrier metal 111 is formed.
【0031】 [0031]
また、その上に一面側の電極としてのエミッタ電極112およびワイヤボンド用ランド113が、純Alで形成されている。 The emitter electrode 112 and the wire bond lands 113 as an electrode on one surface side on which is formed of pure Al. ここで、バリアメタル111は基板110側から、Ti(チタン)、TiN(チタンナイドライド)の順に積層されて形成されてなり、その厚さは、例えば0.1μm程度である。 Here, the barrier metal 111 from the substrate 110 side, Ti (titanium), TiN becomes formed are laminated in this order (titanium Nai dry de) and has a thickness of, for example, about 0.1 [mu] m. また、この一面側の電極112、113の厚さは、例えば5μm程度にすると良い。 The thickness of the electrodes 112 and 113 of the one surface side, for example when about 5 [mu] m.
【0032】 [0032]
また、エミッタ電極112には半田と良好に接続するための金属膜114が形成されている。 Further, a metal film 114 for favorably connected with the solder is formed on the emitter electrode 112. この金属膜114は、エミッタ電極112側から、Ti、Ni(ニッケル)およびAu(金)の順に積層されて形成されており、合わせて例えば、0.6μm程度の厚さとなっている。 The metal film 114, the emitter electrode 112 side, Ti, Ni is formed by laminating in this order (nickel) and Au (gold), and has a total of example, of approximately 0.6μm thickness. そして、この金属膜114に対して、上述のように半田31を介して第1の放熱部材21が接合されている。 Then, the metal film 114, the first heat radiation member 21 are joined via the solder 31 as described above. ここで、半田31および第1の放熱部材21の厚さは、例えば、各々0.1mm、1.5mm程度にすることができる。 The thickness of the solder 31 and the first heat radiation member 21 is, for example, each 0.1 mm, can be set to about 1.5 mm.
【0033】 [0033]
一方、基板110の他面1b側には、バリアメタルを形成せずに、純Alからなる他面側の電極としてのコレクタ電極115が形成されている。 On the other hand, the other surface 1b of the substrate 110, without forming a barrier metal, the collector electrode 115 as the other side of the electrode made of pure Al is formed. このコレクタ電極115は、例えば0.2μm程度の厚さにすることができる。 The collector electrode 115 may be, for example, of about 0.2μm thick. また、コレクタ電極115に対しては、上記エミッタ電極112と同様にして、金属膜116が形成されており、この金属膜116が半田33を介してDBC基板4の一面5a側の第1の銅箔51と接合されている。 Further, with respect to the collector electrode 115, similarly to the emitter electrode 112, a metal film 116 is formed, a first copper on one surface 5a side of the DBC substrate 4 The metal film 116 via the solder 33 It is joined to the foil 51.
【0034】 [0034]
なお、FWD12も電極部分の構成はIGBT11と同様にしてある。 The configuration of the well electrode portion FWD12 is are in the same manner as in IGBT 11.
【0035】 [0035]
次に、図1および図2に示すように、エミッタ電極112と外部端子であるリード(エミッタ端子)61との通電を行うために、第3の放熱部材23とリード61とが接続端子6aで電気的に接続されている。 Next, as shown in FIGS. 1 and 2, in order to perform the energization of the lead (emitter terminal) 61 is an emitter electrode 112 and the external terminal, in the lead 61 the third heat radiating member 23 is connected to terminal 6a It is electrically connected. また、DBC基板4にはランド53が形成されており、このランド53とIGBT11の一面1aにおけるワイヤボンド用ランド113とが、ワイヤ7によりワイヤボンドされ、DBC基板4のランド53とゲート端子8とがワイヤ7によりワイヤボンドされている。 Also, the DBC substrate 4 and the land 53 is formed, and the wire bonding lands 113 in one surface 1a of the land 53 and IGBT11 is, the wire 7 is wire-bonded, the lands 53 and the gate terminal 8 of the DBC substrate 4 There are wire-bonded by wires 7.
【0036】 [0036]
ここで、ワイヤ7としては、AuやAl等、一般的にワイヤボンドに使われるものを用いることができる。 Here, the wire 7, it is possible to use those used Au or Al or the like, in general wire bonding. このDBC基板4のランド53は、ワイヤボンド用ランド113とゲート端子8との中継のために設けられたものである。 The lands 53 of the DBC substrate 4 is provided in order to relay the wire bonding lands 113 and the gate terminal 8.
【0037】 [0037]
また、DBC基板4の裏面5b側に形成された銅箔54には、半田35を介して第4の放熱部材(他面側の放熱部材)24が接合されている。 Further, the copper foil 54 formed on the rear surface 5b side of the DBC substrate 4, a fourth radiating member via a solder 35 (the other surface side of the heat radiating member) 24 is bonded. つまり、一面側の放熱部材20と他面側の放熱部材24とが、DBC基板4を介して接合され、各々の放熱部材20、24の電気的な絶縁、および熱伝導が確保されている。 That is, the heat radiating member 20 and the heat radiating member 24 of the other surface side of the one side is joined via a DBC substrate 4, electrical insulation of each of the heat radiating member 20, 24, and thermal conductivity are ensured.
【0038】 [0038]
そして、上述の各々の部材が樹脂100により封止されている。 Each of the members described above are sealed with a resin 100. この際、他面側の放熱部材24における、DBC基板4と接合した面とは反対側の面が露出して放熱面9となっている。 In this case, the heat radiating member 24 of the other side, has a radiating surface 9 to expose the surface opposite to the surface joined with the DBC substrate 4. ここで、樹脂100としては、例えばエポキシ系のモールド樹脂を用いることができる。 Here, as the resin 100 may be, for example, epoxy-based mold resin.
【0039】 [0039]
次に、本実施形態の半導体装置における各部の電気的な接続のより詳細な構成について、図3を参照して述べる。 Next, a more detailed structure of each part of the electrical connection of the semiconductor device of the present embodiment will be described with reference to FIG. 図3は、図1の白抜き矢印方向から見た場合の半導体装置を模式的に示す上面図である。 Figure 3 is a top view of a semiconductor device when viewed from the white arrow direction in FIG. 1 schematically. なお、図1は図3におけるB−B断面に相当する。 Incidentally, FIG. 1 corresponds to section B-B in FIG. 3. 図3に示すように、本実施形態の半導体装置はIGBT11とFWD12が2組、組み込まれている。 3, the semiconductor device of this embodiment IGBT11 and FWD12 two sets, are incorporated.
【0040】 [0040]
一面側の放熱部材20(21〜23)は、図中、一点鎖線で示され、上述のように、接続端子6aを介してエミッタ端子61と電気的に接続されている。 One side of the heat radiating member 20 (21-23) is in the figure shown by a chain line, as described above, are electrically connected to the emitter terminal 61 through the connection terminal 6a. また、DBC基板4の第1の銅箔51は、2組のIGBT11とFWD12における他面1b側の電極の全てと接合され、DBC基板4の第2の銅箔52と接触しないようにして、突出している。 The first copper foil 51 of the DBC substrate 4 is bonded to any other surface 1b side of the electrode in the two sets of IGBT11 and FWD12, to avoid contact with the second copper foil 52 of the DBC substrate 4, It protrudes. また、この突出した部分51aとリードであるコレクタ端子62とが、接続端子6bを介して電気的に接続されている。 Also, a collector terminal 62 is the protruding portion 51a and the lead are electrically connected via the connection terminal 6b.
【0041】 [0041]
そして、この様な構成の半導体装置は、放熱面9を外部の冷却部材(外部放熱器)としての放熱フィン(図示せず)にネジ止め等により圧接して固定する。 The semiconductor device having such a configuration will be fixed by pressure with screws or the like to the heat radiating fins (not shown) of the heat radiation surface 9 as an external cooling member (external radiator). これにより、各々のチップ11、12の一面1a側からは、一面側の放熱部材20、DBC基板4、および他面側の放熱部材24を介して、放熱面9から放熱される。 Thus, from the one surface 1a side of each of the chips 11 and 12, the heat radiation member 20 of one side, DBC substrate 4, and through the heat radiation member 24 of the other side is radiated from the heat radiating surface 9. つまり、各々のチップ11、12の一面1a側からの放熱方向が、各々のチップ11、12における一面1aから他面1bへ向かう方向(図1における上から下へ向かう方向)となっている。 In other words, the heat radiation direction from the one surface 1a side of each of the chips 11 and 12, has a direction from the one surface 1a of each of the chips 11 and 12 to the other surface 1b (direction from top to bottom in FIG. 1).
【0042】 [0042]
一方、各々のチップ11、12の他面1b側からは、DBC基板4、および他面側の放熱部材24を介して、放熱面9から放熱される。 On the other hand, from the other surface 1b side of each chip 11, 12, DBC substrate 4, and through the heat radiation member 24 of the other side is radiated from the heat radiating surface 9. 従って、チップが組み込まれた半導体装置において、各々のチップ11、12における一面1aおよび他面1b、そして放熱面9の位置関係がこの順になっており、放熱面9を外部の冷却部材と接合するなどして、各々のチップ11、12の両面1a、1bからの放熱を、主として放熱面9において行っている。 Accordingly, in the semiconductor device chip is incorporated, the one surface 1a and the other surface 1b in each of the chips 11 and 12, and the positional relationship of the heat radiation surface 9 has become in this order, bonding a heat radiating surface 9 with an external cooling member and the like, both sides 1a of each chip 11, 12, heat radiation from the 1b, is carried out mainly in the heat radiating surface 9.
【0043】 [0043]
次に、本実施形態の半導体装置の製造方法について述べる。 Next, the process for producing the semiconductor device of the present embodiment. まず、上述のようなバリアメタル111、エミッタ電極112、コレクタ電極115、および金属膜114、116等を有するIGBT11、およびFWD12を用意する。 First, a barrier metal 111 such as described above, the emitter electrode 112, providing a IGBT 11, and FWD12 having collector electrodes 115, and the metal film 114 or the like. これらの電極112、115やバリアメタル111、金属膜114、116等は、例えばスパッタ等により形成することができる。 These electrodes 112 and 115 and the barrier metal 111, a metal film 114 or the like can be formed by, for example, sputtering or the like. そして、各々のチップ11、12の一面1aに対して、第1および第2の放熱部材21、22を半田付けする。 Then, with respect to the one surface 1a of each of the chips 11 and 12, soldering the first and second heat radiating members 21 and 22.
【0044】 [0044]
次に、一面5aおよび他面5bに銅箔51〜54がパターニングされたDBC基板4を用意し、所定の位置にIGBT11およびFWD12を半田付けする。 Next, prepared DBC substrate 4 copper foil 51 to 54 is patterned on one surface 5a and the other surface 5b, soldering the IGBT11 and FWD12 in place. その後、第3の放熱部材23を、第1および第2の放熱部材21、22、およびDBC基板4に対して半田付けする。 Thereafter, the third heat radiating member 23 is soldered to the first and second heat radiating members 21, 22 and DBC substrate 4,. この第3の放熱部材23の半田付けにおいては、第1および第2の放熱部材21、22との接合部分よりも、DBC基板4との接合部分において半田を少し厚くしておき、半田付けの際の高さのバラツキを吸収するようにしておく。 In the third soldering of the heat radiation member 23, and also the joint portion between the first and second heat radiating members 21 and 22, leave a little thicker solder at the junction portion between the DBC substrate 4, soldering keep to absorb the variation in the height of the time.
【0045】 [0045]
この各々半田付けは、リフロー等により行うと良く、また半田付けの順に、用いる半田の融点を徐々に下げるようにすると、初めに接合された半田に影響を及ぼすこと無く、好適に半田付けすることができる。 The respective soldering may performed by reflow or the like, also in the order of soldering, is used when to lower gradually the melting point of the solder, without affecting the solder bonded to the first, it is suitably soldered can.
【0046】 [0046]
そして、エミッタ端子61およびコレクタ端子62と第3の放熱部材23との接続、およびIGBT11とゲート端子8とのワイヤボンドを行う。 Then, the emitter terminal 61 and the collector terminal 62 connected to the third heat radiating member 23, and IGBT11 and a wire bond between the gate terminal 8. 続いて、DBC基板4に第4の放熱部材24を半田付けし、最後に、樹脂封止して完成する。 Subsequently, a fourth radiating member 24 is soldered to the DBC substrate 4, finally, to complete the resin sealing.
【0047】 [0047]
ところで、本実施形態によれば、純Alは弾性率が小さいため、各々のチップ11、12と各放熱部材21〜24との熱膨張係数の違いにより発生する熱応力を緩和することができる。 Incidentally, according to this embodiment, pure Al is because the elastic modulus small, it is possible to alleviate the thermal stress generated by the difference in thermal expansion coefficient between the heat radiation members 21 to 24 with each of the chips 11 and 12. 具体的には、純Alの弾性率は72GPaであり、1%のSiを含有するAlの弾性率は約75GPaである。 Specifically, the elastic modulus of pure Al is 72 GPa, elastic modulus of the Al containing 1% of Si is about 75 GPa. そして、Siを含有するAlを用い、製造過程において、上記従来技術で用いた図4に示すコンタクト部J5やゲート電極部J6の表面にSiが偏析した場合、Siの弾性率は130GPaであるため、局所的には熱応力を緩和する能力が非常に小さくなる。 Then, an Al containing Si, in the manufacturing process, if the Si on the surface of the contact portion J5 and the gate electrode portion J6 shown in FIG. 4 used in the prior art have been segregated, the elastic modulus of Si is 130GPa ability becomes very small to alleviate the thermal stress locally.
【0048】 [0048]
特に、IGBT11のエミッタ電極112を純Alとすることにより、例えばエミッタセルに応力が集中し、Vt等の電気特性が変動することを抑制することができる。 In particular, it is possible to prevent by the pure Al and emitter electrode 112 of the IGBT 11, for example, stress is concentrated on the emitter cell, the electrical characteristics of Vt like varies. 従って、電気的な信頼性の高いチップおよび半導体装置を提供することができる。 Therefore, it is possible to provide a high electrical reliability chip and semiconductor device. また、各々のチップ11、12の他面1b側の電極を純Alとすることにより、熱応力に起因する各々のチップ11、12の反りを低減することができる。 Further, by making the other surface 1b of the side electrode of each of the chips 11 and 12 with pure Al, it is possible to reduce the warp of each of the chips 11 and 12 due to thermal stress.
【0049】 [0049]
また、電極112、113、115にSiが含まれていないため、Siノジュール析出を防止することができる。 Also, because it contains no Si in the electrode 112, 113, it is possible to prevent Si nodules deposited. これは、ワイヤボンド用ランド113において特に効果を発揮する。 This is particularly effective in the wire bonding lands 113. 上記課題で述べたように、ワイヤボンド用ランド113付近のSi基板110における絶縁膜(図示せず)等にSiの析出粒が形成され、この析出粒にワイヤボンドの際の機械的な振動(応力)が集中することにより、絶縁膜およびSi基板110におけるデバイスにクラックが生じるという問題を解消することができる。 As noted above object, the insulating film in the Si substrate 110 in the vicinity of the wire bond land 113 (not shown) Si precipitation grains or the like is formed, mechanical vibration during wire bonding to the precipitation grains ( by stress) is concentrated, it is possible to solve the problem of cracks in the devices in the insulating film and the Si substrate 110.
【0050】 [0050]
この様に、電極112、113、115を純Alとすることにより、外部から加えられる応力を緩和する、つまり純Alがクッションの様な働きをする半導体チップ、および、組み込まれた半導体チップに加わる応力を緩和することができる半導体装置を提供することができる。 Thus, by the electrodes 112, 113, 115 and pure Al, to relax the stress applied from the outside, that is a semiconductor chip that pure Al is acts like a cushion, and, applied to the integrated semiconductor chip stress can be provided a semiconductor device can be relaxed.
【0051】 [0051]
ただし、純Alを基板110であるSiに直接接触させると、アロイスパイクが生じるため、電極112、113と基板110との間にバリアメタル111を形成し、このアロイスパイクの発生を防止している。 However, pure Al is in direct contact with the Si which is a substrate 110, since the alloy spike occurs, a barrier metal 111 is formed between the electrodes 112, 113 and the substrate 110, thereby preventing the occurrence of this alloy spike . なお、IGBT11の他面1b側にはバリアメタルを形成していないが、他面1b側においてアロイスパイクが発生しても、一面1a側に形成されたデバイスまで到達しないと思われるため、バリアメタルを形成しなくても良い。 Although the other surface 1b of the IGBT11 not a barrier metal, for alloy spikes at the other surface 1b side also occurs, would not reach devices formed on one surface 1a side, a barrier metal it may not be formed.
【0052】 [0052]
また、例えば、チップを一対の放熱部材で挟んでなり、その各々の放熱部材に放熱面を有するような半導体装置では、外部の冷却部材により半導体装置を挟んで圧接して、放熱面と冷却部材とを接触させる。 Further, for example, be across the chip by a pair of heat radiation members, in the semiconductor device having a heat radiating surface to the heat dissipation member of each of which are pressed against each other across the semiconductor device by an external cooling member, the heat radiating surface and a cooling member contacting the door. しかし、この様な構成では、挟んだ際の圧接応力がチップに集中してしまう。 However, in such a configuration, the pressure stress of when the sandwich is concentrated in the chip.
【0053】 [0053]
それに対し、本実施形態では、主として半導体装置の外部に対して放熱を行う放熱面9が、各々のチップ11、12における他面1b側に形成されている。 In contrast, in the present embodiment, heat radiating surface 9 mainly radiates heat to the outside of the semiconductor device is formed on the other surface 1b side of each of the chips 11 and 12. この様な構成では、放熱を行うために、冷却部材で半導体装置を挟む構成にする必要が無いため、放熱面9を外部の冷却部材に強固に接続しても、各々のチップ11、12に大きな応力は加わらない。 In such a configuration, in order to perform heat dissipation, it is not necessary to adopt a configuration sandwiching the semiconductor device in the cooling member, be rigidly connected to the heat radiation surface 9 to the outside of the cooling member, each of the chips 11 and 12 a large stress is not applied.
【0054】 [0054]
さらに、各々のチップ11、12に対しては、一面1a側にも他面1b側にも放熱部材21、22、24が接合されているため、各々のチップ11、12の両面1a、1bからの放熱が行われる。 Furthermore, for each of the chips 11 and 12, since the heat radiating member 21, 22, and 24 are also bonded to the other surface to the one surface 1a side 1b side, both surfaces 1a of the respective chips 11 and 12, from 1b heat dissipation is made of.
【0055】 [0055]
従って、各々のチップ11、12の両面1a、1bからの放熱効果を確保した状態で、各々のチップ11、12やチップに形成されたデバイスが割れることを防止することができる構成となっている。 Therefore, has both surfaces 1a of the respective chips 11 and 12, while ensuring the heat dissipation effect from 1b, a configuration can prevent formed in each of the chips 11 and 12 and chip devices cracking . 特に、各々のチップ11、12の他面1b側に放熱面9が形成されているため、各々のチップの一面1a側に応力が集中することを防止でき、一面1a側に形成されたデバイスの電気特性の変動を抑えることができる。 In particular, since the heat radiation surface 9 is formed on the other surface 1b of the respective chips 11 and 12, it is possible to prevent the stress from being concentrated on one surface 1a side of each chip, a device formed on one surface 1a side it is possible to suppress the variation of the electrical characteristics.
【0056】 [0056]
また、半導体装置の内部で用いた絶縁基板であるDBC基板4により、この放熱面9は各々のチップ11、12との電気的な絶縁が確保されている。 Also, the DBC substrate 4 is an insulating substrate used in the semiconductor device, the heat radiating surface 9 electrical insulation between each of the chips 11 and 12 is ensured. このため、外部の冷却部材との接合において、電気的な絶縁を考慮する必要が無い。 Therefore, at the junction with the outside of the cooling member, it is not necessary to consider electrical insulation. また、1枚の絶縁基板4によって、各々のチップの一面1a側および他面1b側の両方との絶縁を確保することができる。 Further, the single insulating substrate 4, it is possible to ensure insulation between both the one surface 1a side of each chip and the other surface 1b side.
【0057】 [0057]
なお、本実施形態では、主として放熱を行う放熱面9が、各々のチップ11、12における他面1b側に形成されているが、例えば、第3の放熱部材23を樹脂100の外に露出させる等して、他の部分で放熱を補うようにしても良い。 In the present embodiment, heat radiating surface 9 for mainly heat radiation, are formed on the other surface 1b side of each of the chips 11 and 12, for example, to expose the third heat radiating member 23 to the outside of the resin 100 and etc. may be compensated heat radiation in other portions. ただし、この場合、第3の放熱部材23における露出した部分を、外部の冷却部材に強固に接触させる等して、チップ11、12の素子形成面1aに圧接応力が加わらないようにする。 However, in this case, the portions exposed in the third heat radiating member 23, and the like to firmly contact with the outside of the cooling member, to prevent pressure stresses applied to the element formation surface 1a of the chip 11. また、チップ11、12の素子形成面1aに圧接応力が加わらなければ半導体装置を挟んで固定してもいい。 Also, good fixed across the semiconductor device if pressure stress applied to the element formation surface 1a of the chip 11.
【0058】 [0058]
また、各々のチップ11、12のデバイスの保護に着目する場合は、各々のチップの他面1b側の電極115は、純Alでなくても良い。 Also, if attention is paid to the protection of devices in each of the chips 11 and 12, the other surface 1b of the side electrodes 115 of each chip may not be pure Al. また、第1〜第3の放熱部材21〜23は別体で形成して半田付けする例について示したが、一体で形成しても良い。 Further, the first to third heat radiating member 21 to 23 is shown an example of soldering formed separately, it may be formed integrally.
【0059】 [0059]
また、FWD12の電極は、熱応力等の問題が無ければ、特に純Alにしなくても良い。 The electrode of FWD12, if there is no thermal stress or the like problem, may not be particularly pure Al. また、一面側の放熱部材20と他面側の放熱部材24との絶縁が必要無ければ、AlNからなるDBC基板4を用いなくても良い。 Further, unless necessary insulation between the heat dissipation member 20 and the heat radiating member 24 of the other surface side of the one surface, may not be used DBC substrate 4 made of AlN. また、DBC基板4のランド53は、IGBT11のワイヤボンド用ランド113とゲート端子8とを直接ワイヤボンドできれば設けなくても良い。 Also, the lands 53 of the DBC substrate 4 may not be provided if direct wire bonding and wire bonding lands 113 and the gate terminal 8 of the IGBT 11.
【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS
【図1】本実施形態における半導体装置の概略断面図である。 1 is a schematic cross-sectional view of a semiconductor device in the present embodiment.
【図2】本実施形態におけるIGBTの構成を示す断面図である。 Is a sectional view showing a structure of an IGBT in Fig. 2 embodiment.
【図3】本実施形態における半導体装置の上面図である。 3 is a top view of the semiconductor device in this embodiment.
【図4】従来のIGBTを部分的に示す概略断面図である。 4 is a schematic cross-sectional view of the conventional IGBT shown partially.
【符号の説明】 DESCRIPTION OF SYMBOLS
1a…素子形成面、4…高熱伝導絶縁基板、9…放熱面、 1a ... element formation surface, 4 ... high heat conductive insulating substrate, 9 ... heat radiating surface,
11、12…半導体チップ、20〜24…放熱部材、110…基板、 11, 12 semiconductor chips, 20-24 ... heat radiating member, 110 ... substrate,
111…バリアメタル、112、113…一面側の電極、 111 ... barrier metal, 112, 113 ... one side of the electrode,
115…他面側の電極。 115 ... other surface side of the electrode.

Claims (5)

  1. Si基板(110)からなる半導体チップ(11)の素子形成面である一面(1a)側に、前記半導体チップ(11)の放熱を行うための放熱部材(20)が接合されてなる半導体装置において、 On one surface (1a) side, which is the element forming surface of the Si substrate (110) comprising a semiconductor chip (11), in a semiconductor device heat dissipating member (20) is formed by joining for performing the heat radiation of the semiconductor chip (11) ,
    前記一面(1a)に形成された電極(112、113)が不純物を含まない純Alであり、 The electrode formed on one surface (1a) (112,113) is a pure Al containing no impurities,
    前記電極(112、113)と前記半導体チップ(11)の基板(110)との間に、SiがAl中に溶解することを防止するバリアメタル(111)が形成されていることを特徴とする半導体装置。 Between the substrate (110) of the electrode (112, 113) and said semiconductor chip (11), Si is characterized in that the barrier metal to prevent the dissolving (111) is formed in the Al semiconductor device.
  2. 前記半導体チップ(11)における前記一面(1a)とは反対側の他面(1b)に形成された電極(115)が、不純物を含まない純Alであることを特徴とする請求項に記載の半導体装置。 Wherein the one surface of the semiconductor chip (11) (1a) electrode formed on the other surface opposite (1b) and (115), according to claim 1, characterized in that a pure Al containing no impurities semiconductor device.
  3. 前記放熱部材(20)からの放熱方向が、前記半導体チップ(11)における前記一面(1a)から、前記一面(1a)とは反対側の他面(1b)へ向かう方向となっていることを特徴とする請求項またはに記載の半導体装置。 That heat radiation direction from the heat radiating member (20) comprises the one surface of the semiconductor chip (11) from (1a), and has a direction toward the other surface opposite to (1b) and said one face (1a) the semiconductor device according to claim 1 or 2, characterized.
  4. 前記半導体チップ(11)における前記一面(1a)とは反対側の他面(1b)側に放熱部材(24)が接合され、 It said semiconductor chip the one surface in (11) the other surface opposite to the (1a) (1b) side to the heat radiating member (24) is joined,
    前記他面(1b)側に接合された放熱部材(24)が、外部の冷却部材と接合される部分である放熱面(9)を有しており、 Said other surface (1b) is joined to the side radiating member (24) has heat radiating surface is a portion to be joined with an external cooling member (9),
    前記一面(1a)側に接合された放熱部材(20)と、前記他面(1b)側に接合された放熱部材(24)とが接合されて、前記一面(1a)側からの放熱が前記放熱面(9)で行われることを特徴とする請求項またはに記載の半導体装置。 Wherein one surface (1a) is joined to the side radiating member (20), said heat radiating member (24) that is joined to the other surface (1b) side and are joined, the heat radiation is said from the one surface (1a) side the semiconductor device according to claim 1 or 2, characterized in that takes place in the heat radiating surface (9).
  5. 前記一面(1a)側に接合された放熱部材(20)と、前記他面(1b)側に接合された放熱部材(24)とが、高熱伝導絶縁基板(4)を介して接合されていることを特徴とする請求項に記載の半導体装置。 Wherein one surface (1a) is joined to the side radiating member (20), said other surface and (1b) is joined to the side radiating member (24), but are bonded via the high heat conductive insulating substrate (4) the semiconductor device according to claim 4, characterized in that.
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US09717227 US6703707B1 (en) 1999-11-24 2000-11-22 Semiconductor device having radiation structure
FR0015130A FR2801423B1 (en) 1999-11-24 2000-11-23 A semiconductor device a radiating structure, manufacturing process of a semiconductor device and method of fabricating an electronic instrument
DE2000158446 DE10058446B8 (en) 1999-11-24 2000-11-24 A semiconductor device having radiation components
DE2000166446 DE10066446B4 (en) 1999-11-24 2000-11-24 A process for producing an electronic component having two radiation components
DE2000166445 DE10066445B4 (en) 1999-11-24 2000-11-24 A semiconductor device having radiating structure
DE2000166441 DE10066441B4 (en) 1999-11-24 2000-11-24 A semiconductor device having radiation components
DE2000166443 DE10066443B8 (en) 1999-11-24 2000-11-24 A semiconductor device having radiation components
DE2000166442 DE10066442B4 (en) 1999-11-24 2000-11-24 A semiconductor device having radiating structure
US10321365 US6693350B2 (en) 1999-11-24 2002-12-18 Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure
US10699784 US20040089941A1 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10699838 US6798062B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10699828 US6992383B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10699837 US6960825B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10699785 US6891265B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10699744 US20040089940A1 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10699954 US6967404B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
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