JP3630070B2 - Semiconductor chip and semiconductor device - Google Patents

Semiconductor chip and semiconductor device Download PDF

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Publication number
JP3630070B2
JP3630070B2 JP2000097911A JP2000097911A JP3630070B2 JP 3630070 B2 JP3630070 B2 JP 3630070B2 JP 2000097911 A JP2000097911 A JP 2000097911A JP 2000097911 A JP2000097911 A JP 2000097911A JP 3630070 B2 JP3630070 B2 JP 3630070B2
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JP
Japan
Prior art keywords
heat radiating
heat
joined
chip
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000097911A
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Japanese (ja)
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JP2001284525A (en
Inventor
豊 福田
一雄 梶本
和仁 野村
健 宮嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2000097911A priority Critical patent/JP3630070B2/en
Priority to US09/717,227 priority patent/US6703707B1/en
Priority to FR0015130A priority patent/FR2801423B1/en
Priority to DE10066442A priority patent/DE10066442B4/en
Priority to DE10066441A priority patent/DE10066441B4/en
Priority to DE10066443A priority patent/DE10066443B8/en
Priority to DE10066446A priority patent/DE10066446B4/en
Priority to DE10058446A priority patent/DE10058446B8/en
Priority to DE10066445A priority patent/DE10066445B4/en
Publication of JP2001284525A publication Critical patent/JP2001284525A/en
Priority to US10/321,365 priority patent/US6693350B2/en
Priority to US10/699,744 priority patent/US20040089940A1/en
Priority to US10/699,785 priority patent/US6891265B2/en
Priority to US10/699,838 priority patent/US6798062B2/en
Priority to US10/699,837 priority patent/US6960825B2/en
Priority to US10/699,828 priority patent/US6992383B2/en
Priority to US10/699,746 priority patent/US6998707B2/en
Priority to US10/699,954 priority patent/US6967404B2/en
Priority to US10/699,784 priority patent/US20040089941A1/en
Application granted granted Critical
Publication of JP3630070B2 publication Critical patent/JP3630070B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップおよびその実装構造に関し、特にパワー素子が形成された半導体チップを用いる場合に好適である。
【０００２】
【従来の技術】
従来、パワーデバイスが形成された半導体チップ（以下、単にチップという）は、半田等の接合部材を介して、Ｃｕ等からなる放熱部材に接合して放熱を行っている。近年、その放熱効率を向上させるために、チップの表裏両面から放熱を行うべく、チップにおけるトランジスタやコンデンサ等のデバイスが形成されている素子形成領域にも放熱部材を設けるようになっている。
【０００３】
図４は、チップの一例としてのＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）の概略断面図である。図４に示すように、チップＪ１にはＳｉ（珪素）からなる基板Ｊ２においてデバイスＪ３が形成されている。また、デバイスＪ３の表面には、Ａｌ（アルミニウム）に１％程度のＳｉを含んだ金属からなるエミッタ電極（配線）Ｊ４が形成されている。
【０００４】
ところで、この電極Ｊ４として不純物を含まないＡｌ（以下、純Ａｌという）を用いると、基板と電極とが直接接触する部分であるコンタクト部Ｊ５において、ＳｉがＡｌ中に溶解することで生じるアロイスパイクが生じる。そして、このアロイスパイクが、例えばＰＮ接合を破壊するなどしてデバイスの特性に大きな影響を与える。従って、ＡｌにＳｉを含有させることにより、このアロイスパイクの発生を抑制している。
【０００５】
【発明が解決しようとする課題】
しかし、Ａｌに過剰のＳｉが含有されていると、デバイス表面のゲート電極部Ｊ６の絶縁膜などにおいてＳｉ微粒子が析出（以下、Ｓｉノジュール析出という）する。そして、チップにワイヤを超音波接合する場合は、上記電極上にワイヤボンドするが、この際、上記Ｓｉノジュール析出による析出粒付近にワイヤボンドすると、析出粒がボンディング時の振動エネルギーを受け、析出粒を起点としてデバイスＪ３及びゲート電極部Ｊ６にクラックが生じる。
【０００６】
ところで、近年、パワー素子を小型化する要望があり、これに伴い、セルピッチ（図４においてＬで示している）が細かくなっている。また、オン抵抗を下げるためゲートをトレンチ構造とすること等にもよりセルピッチＬがさらに細かくなり、例えば４μｍ以下のものも現れてきている。
【０００７】
そして、セルピッチＬが細かくなるほど、上述のように、析出粒に機械的な応力が集中することにより、デバイスＪ３にクラックが発生するという問題が深刻になる。
【０００８】
一方、図４のエミッタ電極Ｊ４およびコレクタ電極Ｊ７の外側に放熱部材を接合させる等して、チップＪ１を一対の放熱部材で挟んだ構成に着目する。この場合、ＳｉからなるチップＪ１の熱膨張係数と、Ｃｕ等からなる放熱部材の熱膨張係数の差が大きいため、冷熱サイクルにおいて大きな熱応力が発生する。ここで、Ｓｉを含むＡｌは、純Ａｌよりも弾性率が大きいため、電極Ｊ４、Ｊ７における熱応力の緩和が不十分となる。その結果、特に素子形成面側では、例えばチップのエミッタセルＪ８及びゲート電極部Ｊ６に熱応力が集中し、ゲート電圧の閾値（以下、Ｖｔとする）等の電気特性が変動することが懸念される。
【０００９】
また、放熱部材を素子形成領域（例えば、図４ではエミッタセルＪ８の形成領域）にも設け、さらに、冷却部材としての外部放熱フィン等に圧接する場合は、チップにおける放熱部材の端部と接触する部分において、上記圧接による応力が集中することが考えられる。そのため、チップＪ１やチップＪ１に形成されたデバイスＪ３及びゲート電極部Ｊ６が割れたり、デバイスＪ３の電気特性が変動したりする可能性がある。
【００１０】
特に、大電流を流すパワーデバイスにおいては、上述のような、機械的応力および熱応力の集中により、特定セルに電流集中してデバイスが熱破壊することが懸念される。
【００１１】
本発明は、上記問題点に鑑み、外部から加えられる応力を緩和することができる半導体チップを提供することを１つの目的とし、組み込まれた半導体チップに加わる応力を緩和することができる半導体装置を提供することを他の目的とする。
【００１２】
【課題を解決するための手段】
上記目的を達成するため、請求項１に記載の発明では、Ｓｉ基板（１１０）からなる半導体チップ（１１）の素子形成面である一面（１ａ）側に、放熱部材（２１）を接合した半導体装置において、一面（１ａ）に形成した電極（１１２、１１３）が不純物を含まない純Ａｌであり、電極（１１２、１１３）と半導体チップ（１１）の基板（１１０）との間にバリアメタル（１１１）を形成していることを特徴としている。
【００１３】
半導体チップ（１１）を放熱部材（２０）と接合させた場合に、不純物を含まないＡｌは弾性率が小さいため、半導体チップ（１１）と放熱部材（２０）との熱膨張係数の違いにより発生する熱応力を緩和することができる。
【００１４】
また、電極（１１２、１１３）と基板（１１０）との間にバリアメタル（１１１）を形成しているため、ＳｉがＡｌ中に溶解することを防止し、アロイスパイクの発生を防止することができる。その結果、電極（１１２、１１３）としてＳｉが含まれていない純Ａｌを用いることができるため、素子形成面である一面（１ａ）付近におけるＳｉのノジュール析出を防止することができ、電極（１１２、１１３）にワイヤボンドした際にＳｉの析出粒に機械的な応力が集中することを防止することができる。従って、組み込まれた半導体チップ（１１）に加わる応力を緩和することができる半導体装置を提供することができる。
【００１５】
この場合、請求項２に記載の発明のように、半導体チップ（１１）の素子形成面である一面（１ａ）とは反対側の面（１ｂ）に形成した電極（１１５）を、不純物を含まない純Ａｌにすることができる。これにより、半導体チップ（１１）の素子形成面である一面（１ａ）とは反対側の面（１ｂ）に放熱部材を接合する場合も、半導体チップ（１１）と放熱部材との熱膨張係数の違いにより発生する熱応力を緩和することができる。
【００１９】
また、請求項３に記載の発明では、請求項１または２の発明において、放熱部材（２０）からの放熱方向が、半導体チップ（１１）における一面（１ａ）から、一面（１ａ）とは反対側の他面（１ｂ）へ向かう方向となっていることを特徴としている。
【００２０】
本発明によれば、例えば、半導体チップ（１１）の他面（１ｂ）側において冷却部材を設けた場合、放熱を行うために冷却部材を放熱部材に圧接する際に、半導体チップ（１１）の一面（１ａ）側に圧接による応力が集中することを防止できる。従って、特に、組み込まれた半導体チップ（１１）の、素子形成面（１ａ）に加わる応力を緩和することができる半導体装置を提供することができる。
【００２１】
また、請求項４に記載の発明では、請求項１または２の発明において、半導体チップ（１１）における一面（１ａ）とは反対側の他面（１ｂ）に放熱部材（２４）を接合し、他面（１ｂ）側に接合した放熱部材（２４）が、外部の冷却部材と接合する部分である放熱面（９）を有しており、一面（１ａ）側に接合した放熱部材（２０）と、他面（１ｂ）側に接合した放熱部材（２４）とを接合して、一面（１ａ）側からの放熱を放熱面（９）で行うことを特徴としている。
【００２２】
これにより、各々の放熱部材（２０、２４）からの放熱方向を、請求項３の発明と同様に、半導体チップ（１１）における一面（１ａ）から他面（１ｂ）へ向かう方向とすることができ、請求項３の発明と同様の効果を発揮することができる。
【００２３】
また、この場合、請求項５に記載の発明のように、一面（１ａ）側に接合した放熱部材（２０）と、他面（１ｂ）側に接合した放熱部材（２４）とを、高熱伝導絶縁基板（４）を介して接合すると、一面（１ａ）側に接合した放熱部材（２０）と他面（１ｂ）側に接合した放熱部材（２４）との電気的な絶縁を行い、さらに熱伝導も確保することができる。
【００２４】
なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示すものである。
【００２５】
【発明の実施の形態】
（本実施形態）
本実施形態は、半導体チップとしてＩＧＢＴを用いた例について示す。図１は、本実施形態の半導体装置の概略断面図である。図１に示すように、例えば、Ｓｉ基板からなる半導体チップとしてのＩＧＢＴ１１およびＦＷＤ（フリーホイールダイオード）１２を用いる。このＩＧＢＴ１１およびＦＷＤ１２の各々の素子形成面である一面１ａ側には、各々のチップ１１、１２の放熱を行うための第１および第２の放熱部材２１、２２が、半田３１を介して接合されている。
【００２６】
また、この第１および第２の放熱部材２１、２２における、各々のチップ１１、１２と接合された面とは反対側の面に対して、半田３２を介して第３の放熱部材２３が接合されている。そして、これらの第１〜第３の放熱部材２１〜２３により一面側の放熱部材２０を形成している。
【００２７】
この第３の放熱部材２３は、突出部２３ｂを有する板状のもので、その厚み方向の断面形状が突出部２３ｂを短辺とする略Ｌ字型になっており、Ｌ字の長辺部において第１および第２の放熱部材２１、２２が接合している。また、各々のチップ１１、１２の断面方向から見ると、突出部２３ｂの先端部２３ａが、各々のチップ１１、１２の他面１ｂとほぼ同じ高さになっている。ここで、第１〜第３の放熱部材２１〜２３は例えばＣｕからなるものを用いることができる。
【００２８】
また、各々のチップ１１、１２の他面１ｂ側には、高熱伝導絶縁基板としてのＤＢＣ（ダイレクトボンディングカッパ）基板４が配置されている。このＤＢＣ基板４は、ＡｌＮ（窒化アルミニウム）基板５の両面５ａ、５ｂに銅箔５１〜５４がパターニングされてなる。
【００２９】
そして、各々のチップ１１、１２の他面１ｂ側が、ＤＢＣ基板４における一面５ａ側の第１の銅箔５１に対して半田３３を介して接合されている。また、第３の放熱部材２３における突出部２３ｂの先端部２３ａが、ＤＢＣ基板４における一面５ａ側の第２の銅箔５２に対して、半田３４を介して接合されている。
【００３０】
次に、ＩＧＢＴ１１の電極（配線）部分の構成について述べる。図２は、図１における破線で囲んだＡ部の拡大図であり、その構成を概略的に示す図である。図２に示すように、ＩＧＢＴ１１の基板１１０における一面１ａ側にはバリアメタル１１１が形成されている。
【００３１】
また、その上に一面側の電極としてのエミッタ電極１１２およびワイヤボンド用ランド１１３が、純Ａｌで形成されている。ここで、バリアメタル１１１は基板１１０側から、Ｔｉ（チタン）、ＴｉＮ（チタンナイドライド）の順に積層されて形成されてなり、その厚さは、例えば０．１μｍ程度である。また、この一面側の電極１１２、１１３の厚さは、例えば５μｍ程度にすると良い。
【００３２】
また、エミッタ電極１１２には半田と良好に接続するための金属膜１１４が形成されている。この金属膜１１４は、エミッタ電極１１２側から、Ｔｉ、Ｎｉ（ニッケル）およびＡｕ（金）の順に積層されて形成されており、合わせて例えば、０．６μｍ程度の厚さとなっている。そして、この金属膜１１４に対して、上述のように半田３１を介して第１の放熱部材２１が接合されている。ここで、半田３１および第１の放熱部材２１の厚さは、例えば、各々０．１ｍｍ、１．５ｍｍ程度にすることができる。
【００３３】
一方、基板１１０の他面１ｂ側には、バリアメタルを形成せずに、純Ａｌからなる他面側の電極としてのコレクタ電極１１５が形成されている。このコレクタ電極１１５は、例えば０．２μｍ程度の厚さにすることができる。また、コレクタ電極１１５に対しては、上記エミッタ電極１１２と同様にして、金属膜１１６が形成されており、この金属膜１１６が半田３３を介してＤＢＣ基板４の一面５ａ側の第１の銅箔５１と接合されている。
【００３４】
なお、ＦＷＤ１２も電極部分の構成はＩＧＢＴ１１と同様にしてある。
【００３５】
次に、図１および図２に示すように、エミッタ電極１１２と外部端子であるリード（エミッタ端子）６１との通電を行うために、第３の放熱部材２３とリード６１とが接続端子６ａで電気的に接続されている。また、ＤＢＣ基板４にはランド５３が形成されており、このランド５３とＩＧＢＴ１１の一面１ａにおけるワイヤボンド用ランド１１３とが、ワイヤ７によりワイヤボンドされ、ＤＢＣ基板４のランド５３とゲート端子８とがワイヤ７によりワイヤボンドされている。
【００３６】
ここで、ワイヤ７としては、ＡｕやＡｌ等、一般的にワイヤボンドに使われるものを用いることができる。このＤＢＣ基板４のランド５３は、ワイヤボンド用ランド１１３とゲート端子８との中継のために設けられたものである。
【００３７】
また、ＤＢＣ基板４の裏面５ｂ側に形成された銅箔５４には、半田３５を介して第４の放熱部材（他面側の放熱部材）２４が接合されている。つまり、一面側の放熱部材２０と他面側の放熱部材２４とが、ＤＢＣ基板４を介して接合され、各々の放熱部材２０、２４の電気的な絶縁、および熱伝導が確保されている。
【００３８】
そして、上述の各々の部材が樹脂１００により封止されている。この際、他面側の放熱部材２４における、ＤＢＣ基板４と接合した面とは反対側の面が露出して放熱面９となっている。ここで、樹脂１００としては、例えばエポキシ系のモールド樹脂を用いることができる。
【００３９】
次に、本実施形態の半導体装置における各部の電気的な接続のより詳細な構成について、図３を参照して述べる。図３は、図１の白抜き矢印方向から見た場合の半導体装置を模式的に示す上面図である。なお、図１は図３におけるＢ−Ｂ断面に相当する。図３に示すように、本実施形態の半導体装置はＩＧＢＴ１１とＦＷＤ１２が２組、組み込まれている。
【００４０】
一面側の放熱部材２０（２１〜２３）は、図中、一点鎖線で示され、上述のように、接続端子６ａを介してエミッタ端子６１と電気的に接続されている。また、ＤＢＣ基板４の第１の銅箔５１は、２組のＩＧＢＴ１１とＦＷＤ１２における他面１ｂ側の電極の全てと接合され、ＤＢＣ基板４の第２の銅箔５２と接触しないようにして、突出している。また、この突出した部分５１ａとリードであるコレクタ端子６２とが、接続端子６ｂを介して電気的に接続されている。
【００４１】
そして、この様な構成の半導体装置は、放熱面９を外部の冷却部材（外部放熱器）としての放熱フィン（図示せず）にネジ止め等により圧接して固定する。これにより、各々のチップ１１、１２の一面１ａ側からは、一面側の放熱部材２０、ＤＢＣ基板４、および他面側の放熱部材２４を介して、放熱面９から放熱される。つまり、各々のチップ１１、１２の一面１ａ側からの放熱方向が、各々のチップ１１、１２における一面１ａから他面１ｂへ向かう方向（図１における上から下へ向かう方向）となっている。
【００４２】
一方、各々のチップ１１、１２の他面１ｂ側からは、ＤＢＣ基板４、および他面側の放熱部材２４を介して、放熱面９から放熱される。従って、チップが組み込まれた半導体装置において、各々のチップ１１、１２における一面１ａおよび他面１ｂ、そして放熱面９の位置関係がこの順になっており、放熱面９を外部の冷却部材と接合するなどして、各々のチップ１１、１２の両面１ａ、１ｂからの放熱を、主として放熱面９において行っている。
【００４３】
次に、本実施形態の半導体装置の製造方法について述べる。まず、上述のようなバリアメタル１１１、エミッタ電極１１２、コレクタ電極１１５、および金属膜１１４、１１６等を有するＩＧＢＴ１１、およびＦＷＤ１２を用意する。これらの電極１１２、１１５やバリアメタル１１１、金属膜１１４、１１６等は、例えばスパッタ等により形成することができる。そして、各々のチップ１１、１２の一面１ａに対して、第１および第２の放熱部材２１、２２を半田付けする。
【００４４】
次に、一面５ａおよび他面５ｂに銅箔５１〜５４がパターニングされたＤＢＣ基板４を用意し、所定の位置にＩＧＢＴ１１およびＦＷＤ１２を半田付けする。その後、第３の放熱部材２３を、第１および第２の放熱部材２１、２２、およびＤＢＣ基板４に対して半田付けする。この第３の放熱部材２３の半田付けにおいては、第１および第２の放熱部材２１、２２との接合部分よりも、ＤＢＣ基板４との接合部分において半田を少し厚くしておき、半田付けの際の高さのバラツキを吸収するようにしておく。
【００４５】
この各々半田付けは、リフロー等により行うと良く、また半田付けの順に、用いる半田の融点を徐々に下げるようにすると、初めに接合された半田に影響を及ぼすこと無く、好適に半田付けすることができる。
【００４６】
そして、エミッタ端子６１およびコレクタ端子６２と第３の放熱部材２３との接続、およびＩＧＢＴ１１とゲート端子８とのワイヤボンドを行う。続いて、ＤＢＣ基板４に第４の放熱部材２４を半田付けし、最後に、樹脂封止して完成する。
【００４７】
ところで、本実施形態によれば、純Ａｌは弾性率が小さいため、各々のチップ１１、１２と各放熱部材２１〜２４との熱膨張係数の違いにより発生する熱応力を緩和することができる。具体的には、純Ａｌの弾性率は７２ＧＰａであり、１％のＳｉを含有するＡｌの弾性率は約７５ＧＰａである。そして、Ｓｉを含有するＡｌを用い、製造過程において、上記従来技術で用いた図４に示すコンタクト部Ｊ５やゲート電極部Ｊ６の表面にＳｉが偏析した場合、Ｓｉの弾性率は１３０ＧＰａであるため、局所的には熱応力を緩和する能力が非常に小さくなる。
【００４８】
特に、ＩＧＢＴ１１のエミッタ電極１１２を純Ａｌとすることにより、例えばエミッタセルに応力が集中し、Ｖｔ等の電気特性が変動することを抑制することができる。従って、電気的な信頼性の高いチップおよび半導体装置を提供することができる。また、各々のチップ１１、１２の他面１ｂ側の電極を純Ａｌとすることにより、熱応力に起因する各々のチップ１１、１２の反りを低減することができる。
【００４９】
また、電極１１２、１１３、１１５にＳｉが含まれていないため、Ｓｉノジュール析出を防止することができる。これは、ワイヤボンド用ランド１１３において特に効果を発揮する。上記課題で述べたように、ワイヤボンド用ランド１１３付近のＳｉ基板１１０における絶縁膜（図示せず）等にＳｉの析出粒が形成され、この析出粒にワイヤボンドの際の機械的な振動（応力）が集中することにより、絶縁膜およびＳｉ基板１１０におけるデバイスにクラックが生じるという問題を解消することができる。
【００５０】
この様に、電極１１２、１１３、１１５を純Ａｌとすることにより、外部から加えられる応力を緩和する、つまり純Ａｌがクッションの様な働きをする半導体チップ、および、組み込まれた半導体チップに加わる応力を緩和することができる半導体装置を提供することができる。
【００５１】
ただし、純Ａｌを基板１１０であるＳｉに直接接触させると、アロイスパイクが生じるため、電極１１２、１１３と基板１１０との間にバリアメタル１１１を形成し、このアロイスパイクの発生を防止している。なお、ＩＧＢＴ１１の他面１ｂ側にはバリアメタルを形成していないが、他面１ｂ側においてアロイスパイクが発生しても、一面１ａ側に形成されたデバイスまで到達しないと思われるため、バリアメタルを形成しなくても良い。
【００５２】
また、例えば、チップを一対の放熱部材で挟んでなり、その各々の放熱部材に放熱面を有するような半導体装置では、外部の冷却部材により半導体装置を挟んで圧接して、放熱面と冷却部材とを接触させる。しかし、この様な構成では、挟んだ際の圧接応力がチップに集中してしまう。
【００５３】
それに対し、本実施形態では、主として半導体装置の外部に対して放熱を行う放熱面９が、各々のチップ１１、１２における他面１ｂ側に形成されている。この様な構成では、放熱を行うために、冷却部材で半導体装置を挟む構成にする必要が無いため、放熱面９を外部の冷却部材に強固に接続しても、各々のチップ１１、１２に大きな応力は加わらない。
【００５４】
さらに、各々のチップ１１、１２に対しては、一面１ａ側にも他面１ｂ側にも放熱部材２１、２２、２４が接合されているため、各々のチップ１１、１２の両面１ａ、１ｂからの放熱が行われる。
【００５５】
従って、各々のチップ１１、１２の両面１ａ、１ｂからの放熱効果を確保した状態で、各々のチップ１１、１２やチップに形成されたデバイスが割れることを防止することができる構成となっている。特に、各々のチップ１１、１２の他面１ｂ側に放熱面９が形成されているため、各々のチップの一面１ａ側に応力が集中することを防止でき、一面１ａ側に形成されたデバイスの電気特性の変動を抑えることができる。
【００５６】
また、半導体装置の内部で用いた絶縁基板であるＤＢＣ基板４により、この放熱面９は各々のチップ１１、１２との電気的な絶縁が確保されている。このため、外部の冷却部材との接合において、電気的な絶縁を考慮する必要が無い。また、１枚の絶縁基板４によって、各々のチップの一面１ａ側および他面１ｂ側の両方との絶縁を確保することができる。
【００５７】
なお、本実施形態では、主として放熱を行う放熱面９が、各々のチップ１１、１２における他面１ｂ側に形成されているが、例えば、第３の放熱部材２３を樹脂１００の外に露出させる等して、他の部分で放熱を補うようにしても良い。ただし、この場合、第３の放熱部材２３における露出した部分を、外部の冷却部材に強固に接触させる等して、チップ１１、１２の素子形成面１ａに圧接応力が加わらないようにする。また、チップ１１、１２の素子形成面１ａに圧接応力が加わらなければ半導体装置を挟んで固定してもいい。
【００５８】
また、各々のチップ１１、１２のデバイスの保護に着目する場合は、各々のチップの他面１ｂ側の電極１１５は、純Ａｌでなくても良い。また、第１〜第３の放熱部材２１〜２３は別体で形成して半田付けする例について示したが、一体で形成しても良い。
【００５９】
また、ＦＷＤ１２の電極は、熱応力等の問題が無ければ、特に純Ａｌにしなくても良い。また、一面側の放熱部材２０と他面側の放熱部材２４との絶縁が必要無ければ、ＡｌＮからなるＤＢＣ基板４を用いなくても良い。また、ＤＢＣ基板４のランド５３は、ＩＧＢＴ１１のワイヤボンド用ランド１１３とゲート端子８とを直接ワイヤボンドできれば設けなくても良い。
【図面の簡単な説明】
【図１】本実施形態における半導体装置の概略断面図である。
【図２】本実施形態におけるＩＧＢＴの構成を示す断面図である。
【図３】本実施形態における半導体装置の上面図である。
【図４】従来のＩＧＢＴを部分的に示す概略断面図である。
【符号の説明】
１ａ…素子形成面、４…高熱伝導絶縁基板、９…放熱面、
１１、１２…半導体チップ、２０〜２４…放熱部材、１１０…基板、
１１１…バリアメタル、１１２、１１３…一面側の電極、
１１５…他面側の電極。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor chip and its mounting structure, and is particularly suitable when a semiconductor chip on which a power element is formed is used.
[0002]
[Prior art]
Conventionally, a semiconductor chip (hereinafter simply referred to as a chip) on which a power device is formed is bonded to a heat radiating member made of Cu or the like through a bonding member such as solder to radiate heat. In recent years, in order to improve the heat dissipation efficiency, a heat dissipation member is provided also in an element formation region in which devices such as transistors and capacitors are formed in the chip in order to perform heat dissipation from both the front and back surfaces of the chip.
[0003]
FIG. 4 is a schematic cross-sectional view of an IGBT (Insulated Gate Bipolar Transistor) as an example of a chip. As shown in FIG. 4, a device J3 is formed on a chip J1 on a substrate J2 made of Si (silicon). Further, an emitter electrode (wiring) J4 made of a metal containing about 1% Si in Al (aluminum) is formed on the surface of the device J3.
[0004]
By the way, when Al containing no impurities (hereinafter referred to as pure Al) is used as the electrode J4, an alloy spike is generated when Si is dissolved in Al at the contact portion J5 where the substrate and the electrode are in direct contact. Occurs. The alloy spike greatly affects the characteristics of the device, for example, by destroying the PN junction. Therefore, the generation of this alloy spike is suppressed by containing Si in Al.
[0005]
[Problems to be solved by the invention]
However, if excessive Si is contained in Al, Si fine particles are deposited in the insulating film of the gate electrode portion J6 on the device surface (hereinafter referred to as Si nodule deposition). When the wire is ultrasonically bonded to the chip, wire bonding is performed on the electrode. At this time, when wire bonding is performed in the vicinity of the precipitated particles due to the Si nodule precipitation, the precipitated particles receive vibration energy at the time of bonding. Cracks occur in the device J3 and the gate electrode portion J6 starting from the grains.
[0006]
Incidentally, in recent years, there has been a demand for downsizing the power element, and accordingly, the cell pitch (indicated by L in FIG. 4) has become finer. In addition, the cell pitch L is further reduced by, for example, making the gate a trench structure in order to reduce the on-resistance. For example, a cell pitch of 4 μm or less has appeared.
[0007]
As the cell pitch L becomes finer, the problem that cracks occur in the device J3 becomes more serious as mechanical stress concentrates on the precipitated grains as described above.
[0008]
On the other hand, attention is focused on a configuration in which the chip J1 is sandwiched between a pair of heat radiating members by bonding a heat radiating member to the outside of the emitter electrode J4 and the collector electrode J7 in FIG. In this case, since the difference between the thermal expansion coefficient of the chip J1 made of Si and the thermal expansion coefficient of the heat radiating member made of Cu or the like is large, a large thermal stress is generated in the cooling cycle. Here, since Al containing Si has a larger elastic modulus than pure Al, relaxation of thermal stress in the electrodes J4 and J7 becomes insufficient. As a result, particularly on the element formation surface side, for example, thermal stress is concentrated on the emitter cell J8 and the gate electrode portion J6 of the chip, and there is a concern that the electrical characteristics such as the gate voltage threshold (hereinafter referred to as Vt) may fluctuate. The
[0009]
In addition, when a heat radiating member is provided also in an element forming region (for example, the region where the emitter cell J8 is formed in FIG. 4), and is in pressure contact with an external heat radiating fin as a cooling member, it contacts the end of the heat radiating member in the chip. It is conceivable that the stress due to the pressure welding is concentrated in the portion where the pressure is applied. Therefore, there is a possibility that the device J3 and the gate electrode portion J6 formed on the chip J1 or the chip J1 are broken, or the electrical characteristics of the device J3 are changed.
[0010]
In particular, in a power device through which a large current flows, there is a concern that due to the concentration of mechanical stress and thermal stress as described above, current concentrates on a specific cell and the device is thermally destroyed.
[0011]
In view of the above problems, an object of the present invention is to provide a semiconductor chip that can relieve stress applied from outside, and a semiconductor device that can relieve stress applied to an incorporated semiconductor chip. The other purpose is to provide.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, there is provided a semiconductor in which a heat dissipation member (21) is bonded to one side (1a) which is an element formation surface of a semiconductor chip (11) made of a Si substrate (110). In the device, the electrodes (112, 113) formed on one surface (1a) are pure Al containing no impurities, and a barrier metal (between the electrodes (112, 113) and the substrate (110) of the semiconductor chip (11) is formed. 111).
[0013]
When the semiconductor chip (11) is joined to the heat dissipation member (20) , Al containing no impurities has a low elastic modulus, and thus is generated due to a difference in thermal expansion coefficient between the semiconductor chip (11) and the heat dissipation member (20). The thermal stress to be relieved can be relieved.
[0014]
Further, since the barrier metal (111) is formed between the electrodes (112, 113) and the substrate (110), it is possible to prevent Si from dissolving in Al and to prevent the occurrence of alloy spikes. it can. As a result, since pure Al containing no Si can be used as the electrodes (112, 113), Si nodule precipitation in the vicinity of one surface (1a), which is an element formation surface , can be prevented, and the electrodes (112 113), mechanical stress can be prevented from concentrating on the Si precipitates when wire bonding is performed. Therefore, it is possible to provide a semiconductor device that can relieve stress applied to the incorporated semiconductor chip (11) .
[0015]
In this case, as in the invention described in claim 2, the electrode (115) formed on the surface (1b) opposite to the one surface (1a) which is the element forming surface of the semiconductor chip (11) contains impurities. There can be no pure Al. Thereby, also when joining a heat radiating member to the surface (1b) on the opposite side to one surface (1a) which is an element formation surface of a semiconductor chip (11), the thermal expansion coefficient of the semiconductor chip (11) and the heat radiating member is reduced. Thermal stress generated by the difference can be relaxed.
[0019]
Moreover, in invention of Claim 3 , in the invention of Claim 1 or 2 , the heat radiation direction from a heat radiating member (20) is opposite to one surface (1a) from one surface (1a) in a semiconductor chip (11). It is characterized by the direction toward the other surface (1b) on the side.
[0020]
According to the present invention, for example, when the cooling member is provided on the other surface (1b) side of the semiconductor chip (11), when the cooling member is pressed against the heat radiating member in order to dissipate heat, the semiconductor chip (11) It is possible to prevent stress due to pressure welding from concentrating on the one surface (1a) side. Therefore, in particular, it is possible to provide a semiconductor device that can relieve stress applied to the element formation surface (1a) of the incorporated semiconductor chip (11).
[0021]
Moreover, in invention of Claim 4 , in the invention of Claim 1 or 2 , a heat radiating member (24) is joined to the other surface (1b) on the opposite side to the one surface (1a) in the semiconductor chip (11), The heat radiating member (24) joined to the other surface (1b) side has a heat radiating surface (9) which is a portion joined to an external cooling member, and the heat radiating member (20) joined to the one surface (1a) side. And the heat radiating member (24) joined to the other surface (1b) side is joined, and the heat radiation from the one surface (1a) side is performed on the heat radiating surface (9).
[0022]
Thereby, the heat radiation direction from each heat radiating member (20, 24) is made to be a direction from one surface (1a) to the other surface (1b) in the semiconductor chip (11), similarly to the invention of claim 3. The same effect as that of the invention of claim 3 can be exhibited.
[0023]
Further, in this case, as in the invention described in claim 5 , the heat dissipating member (20) bonded to the one surface (1a) side and the heat dissipating member (24) bonded to the other surface (1b) side are highly thermally conductive. When bonded via the insulating substrate (4), the heat radiating member (20) bonded to the one surface (1a) side and the heat radiating member (24) bonded to the other surface (1b) side are electrically insulated, and further the heat Conduction can also be secured.
[0024]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
(This embodiment)
In the present embodiment, an example in which an IGBT is used as a semiconductor chip will be described. FIG. 1 is a schematic cross-sectional view of the semiconductor device of this embodiment. As shown in FIG. 1, for example, an IGBT 11 and an FWD (free wheel diode) 12 are used as semiconductor chips made of a Si substrate. First and second heat radiating members 21 and 22 for radiating heat from the chips 11 and 12 are joined to each IGBT 1 and FWD 12 on the side of the one surface 1 a that is an element forming surface via solder 31. ing.
[0026]
Further, the third heat radiating member 23 is bonded to the surface of the first and second heat radiating members 21 and 22 opposite to the surface bonded to the respective chips 11 and 12 via the solder 32. Has been. And these 1st-3rd heat radiating members 21-23 form the heat radiating member 20 of the one surface side.
[0027]
The third heat radiating member 23 has a plate-like shape having a protruding portion 23b, and its cross-sectional shape in the thickness direction is substantially L-shaped with the protruding portion 23b as a short side, and an L-shaped long side portion. The first and second heat radiating members 21 and 22 are joined together. Further, when viewed from the cross-sectional direction of each chip 11, 12, the tip 23 a of the projecting portion 23 b is substantially the same height as the other surface 1 b of each chip 11, 12. Here, the 1st-3rd heat radiating members 21-23 can use what consists of Cu, for example.
[0028]
Further, a DBC (direct bonding kappa) substrate 4 as a high thermal conductive insulating substrate is disposed on the other surface 1b side of each of the chips 11 and 12. The DBC substrate 4 is obtained by patterning copper foils 51 to 54 on both surfaces 5 a and 5 b of an AlN (aluminum nitride) substrate 5.
[0029]
And the other surface 1b side of each chip | tip 11 and 12 is joined via the solder 33 with respect to the 1st copper foil 51 of the one surface 5a side in the DBC board | substrate 4. FIG. In addition, the tip 23 a of the protrusion 23 b of the third heat radiating member 23 is joined to the second copper foil 52 on the one surface 5 a side of the DBC substrate 4 via the solder 34.
[0030]
Next, the configuration of the electrode (wiring) portion of the IGBT 11 will be described. FIG. 2 is an enlarged view of a portion A surrounded by a broken line in FIG. 1, and schematically shows the configuration thereof. As shown in FIG. 2, a barrier metal 111 is formed on the one surface 1 a side of the substrate 110 of the IGBT 11.
[0031]
Further, an emitter electrode 112 as an electrode on one side and a wire bond land 113 are formed of pure Al thereon. Here, the barrier metal 111 is formed by laminating Ti (titanium) and TiN (titanium nitride) in this order from the substrate 110 side, and the thickness thereof is, for example, about 0.1 μm. The thickness of the electrodes 112 and 113 on the one surface side is preferably about 5 μm, for example.
[0032]
In addition, a metal film 114 is formed on the emitter electrode 112 for good connection with solder. The metal film 114 is formed by stacking Ti, Ni (nickel), and Au (gold) in this order from the emitter electrode 112 side, and has a thickness of, for example, about 0.6 μm. The first heat radiating member 21 is bonded to the metal film 114 via the solder 31 as described above. Here, the thicknesses of the solder 31 and the first heat radiating member 21 can be set to, for example, about 0.1 mm and 1.5 mm, respectively.
[0033]
On the other hand, on the other surface 1b side of the substrate 110, a collector electrode 115 as an electrode on the other surface side made of pure Al is formed without forming a barrier metal. The collector electrode 115 can have a thickness of about 0.2 μm, for example. Further, a metal film 116 is formed on the collector electrode 115 in the same manner as the emitter electrode 112, and the metal film 116 is connected to the first copper on the one surface 5 a side of the DBC substrate 4 via the solder 33. The foil 51 is joined.
[0034]
The FWD 12 has the same electrode configuration as the IGBT 11.
[0035]
Next, as shown in FIG. 1 and FIG. 2, in order to energize the emitter electrode 112 and the lead (emitter terminal) 61 which is an external terminal, the third heat radiating member 23 and the lead 61 are connected to the connection terminal 6a. Electrically connected. Further, a land 53 is formed on the DBC substrate 4, and the land 53 and the wire bonding land 113 on the one surface 1 a of the IGBT 11 are wire-bonded by the wire 7, and the land 53 and the gate terminal 8 of the DBC substrate 4 are connected. Is wire-bonded by a wire 7.
[0036]
Here, as the wire 7, a material generally used for wire bonding, such as Au or Al, can be used. The land 53 of the DBC substrate 4 is provided for relaying between the wire bond land 113 and the gate terminal 8.
[0037]
A fourth heat radiation member (heat radiation member on the other surface side) 24 is joined to the copper foil 54 formed on the back surface 5 b side of the DBC substrate 4 via a solder 35. That is, the heat radiating member 20 on the one surface side and the heat radiating member 24 on the other surface side are joined via the DBC substrate 4 to ensure electrical insulation and heat conduction of the heat radiating members 20 and 24.
[0038]
Each member described above is sealed with resin 100. At this time, the surface of the heat radiating member 24 on the other surface side opposite to the surface bonded to the DBC substrate 4 is exposed to form the heat radiating surface 9. Here, as the resin 100, for example, an epoxy mold resin can be used.
[0039]
Next, a more detailed configuration of the electrical connection of each part in the semiconductor device of this embodiment will be described with reference to FIG. FIG. 3 is a top view schematically showing the semiconductor device when viewed from the direction of the white arrow in FIG. 1 corresponds to a cross section taken along line BB in FIG. As shown in FIG. 3, the semiconductor device of this embodiment includes two sets of IGBTs 11 and FWDs 12.
[0040]
The heat radiation member 20 (21 to 23) on the one surface side is indicated by an alternate long and short dash line in the drawing, and is electrically connected to the emitter terminal 61 via the connection terminal 6a as described above. Also, the first copper foil 51 of the DBC substrate 4 is bonded to all of the electrodes on the other surface 1b side of the two sets of IGBTs 11 and FWDs 12 so as not to contact the second copper foil 52 of the DBC substrate 4. It protrudes. Further, the protruding portion 51a and the collector terminal 62 which is a lead are electrically connected through the connection terminal 6b.
[0041]
In the semiconductor device having such a configuration, the heat radiating surface 9 is fixed to a heat radiating fin (not shown) as an external cooling member (external heat radiator) by screwing or the like. As a result, heat is radiated from the heat radiating surface 9 from the one surface 1 a side of each chip 11, 12 through the heat radiating member 20 on the one surface side, the DBC substrate 4, and the heat radiating member 24 on the other surface side. That is, the heat radiation direction from the one surface 1a side of each chip 11, 12 is the direction from the one surface 1a to the other surface 1b in each chip 11, 12 (the direction from the top to the bottom in FIG. 1).
[0042]
On the other hand, heat is radiated from the heat radiating surface 9 from the other surface 1 b side of each chip 11, 12 via the DBC substrate 4 and the heat radiating member 24 on the other surface side. Accordingly, in the semiconductor device in which the chips are incorporated, the positional relationship between the one surface 1a and the other surface 1b of each chip 11, 12 and the heat radiation surface 9 is in this order, and the heat radiation surface 9 is joined to an external cooling member. Thus, the heat radiation from both surfaces 1a and 1b of the respective chips 11 and 12 is performed mainly on the heat radiation surface 9.
[0043]
Next, a method for manufacturing the semiconductor device of this embodiment will be described. First, the IGBT 11 and the FWD 12 having the barrier metal 111, the emitter electrode 112, the collector electrode 115, and the metal films 114 and 116 as described above are prepared. These electrodes 112 and 115, barrier metal 111, metal films 114 and 116, and the like can be formed by sputtering, for example. Then, the first and second heat radiating members 21 and 22 are soldered to the one surface 1a of the chips 11 and 12, respectively.
[0044]
Next, the DBC substrate 4 in which the copper foils 51 to 54 are patterned on the one surface 5a and the other surface 5b is prepared, and the IGBT 11 and the FWD 12 are soldered to predetermined positions. Thereafter, the third heat radiating member 23 is soldered to the first and second heat radiating members 21 and 22 and the DBC substrate 4. In soldering the third heat radiating member 23, the solder is made slightly thicker at the joint portion with the DBC substrate 4 than at the joint portion with the first and second heat radiating members 21, 22. Try to absorb variations in height.
[0045]
Each soldering should be performed by reflow or the like, and if the melting point of the solder to be used is gradually lowered in the order of soldering, soldering is suitably performed without affecting the solder that was initially joined. Can do.
[0046]
Then, connection between the emitter terminal 61 and the collector terminal 62 and the third heat radiating member 23 and wire bonding between the IGBT 11 and the gate terminal 8 are performed. Subsequently, the fourth heat radiating member 24 is soldered to the DBC substrate 4, and finally, resin sealing is completed.
[0047]
By the way, according to this embodiment, since pure Al has a small elastic modulus, the thermal stress generated by the difference in thermal expansion coefficient between each of the chips 11 and 12 and each of the heat radiating members 21 to 24 can be relieved. Specifically, the elastic modulus of pure Al is 72 GPa, and the elastic modulus of Al containing 1% Si is about 75 GPa. When Si is segregated on the surface of the contact part J5 and the gate electrode part J6 shown in FIG. 4 used in the above prior art in the manufacturing process using Al containing Si, the elastic modulus of Si is 130 GPa. Locally, the ability to relieve thermal stress is very small.
[0048]
In particular, when the emitter electrode 112 of the IGBT 11 is made of pure Al, it is possible to suppress, for example, stress concentration on the emitter cell and fluctuation of electrical characteristics such as Vt. Therefore, a chip and a semiconductor device with high electrical reliability can be provided. Moreover, the curvature of each chip | tip 11 and 12 resulting from a thermal stress can be reduced by making the electrode by the side of the other surface 1b of each chip | tip 11 and 12 into pure Al.
[0049]
Further, since Si is not contained in the electrodes 112, 113, and 115, Si nodule precipitation can be prevented. This is particularly effective in the wire bond land 113. As described in the above problem, Si precipitate grains are formed on an insulating film (not shown) or the like in the Si substrate 110 near the wire bond land 113, and mechanical vibration ( When the stress is concentrated, the problem that cracks occur in the insulating film and the device in the Si substrate 110 can be solved.
[0050]
Thus, by making the electrodes 112, 113, and 115 pure Al, the stress applied from the outside is relieved, that is, the pure Al is added to the semiconductor chip acting as a cushion and the incorporated semiconductor chip. A semiconductor device capable of relieving stress can be provided.
[0051]
However, when pure Al is brought into direct contact with Si as the substrate 110, alloy spikes are generated. Therefore, a barrier metal 111 is formed between the electrodes 112, 113 and the substrate 110 to prevent the alloy spikes from being generated. . Although no barrier metal is formed on the other surface 1b side of the IGBT 11, even if an alloy spike occurs on the other surface 1b side, it is considered that the device formed on the one surface 1a side does not reach the barrier metal. May not be formed.
[0052]
Further, for example, in a semiconductor device in which a chip is sandwiched between a pair of heat radiating members and each of the heat radiating members has a heat radiating surface, the heat radiating surface and the cooling member are pressed against each other by sandwiching the semiconductor device with an external cooling member. And contact. However, with such a configuration, the pressure stress when sandwiched is concentrated on the chip.
[0053]
On the other hand, in the present embodiment, a heat radiating surface 9 that mainly radiates heat to the outside of the semiconductor device is formed on the other surface 1b side of each of the chips 11 and 12. In such a configuration, it is not necessary to sandwich the semiconductor device with a cooling member in order to perform heat dissipation. Therefore, even if the heat radiating surface 9 is firmly connected to an external cooling member, Large stress is not applied.
[0054]
Furthermore, since the heat dissipation members 21, 22, and 24 are bonded to each of the chips 11 and 12 both on the one surface 1a side and on the other surface 1b side, the both surfaces 1a and 1b of each chip 11 and 12 are connected. Heat dissipation.
[0055]
Therefore, the chip 11, 12 and the device formed on the chip can be prevented from cracking in a state in which the heat radiation effect from the both surfaces 1a, 1b of each chip 11, 12 is ensured. . In particular, since the heat radiating surface 9 is formed on the other surface 1b side of each chip 11, 12, it is possible to prevent stress from concentrating on the one surface 1a side of each chip, and for the device formed on the one surface 1a side. Variations in electrical characteristics can be suppressed.
[0056]
The heat radiation surface 9 is electrically insulated from the chips 11 and 12 by the DBC substrate 4 which is an insulating substrate used inside the semiconductor device. For this reason, it is not necessary to consider electrical insulation in joining with an external cooling member. Moreover, the insulation with both the one surface 1a side of each chip | tip and the other surface 1b side is securable by the sheet | seat 1 of the insulated substrate 4. FIG.
[0057]
In the present embodiment, the heat radiating surface 9 that mainly radiates heat is formed on the other surface 1b side of each of the chips 11 and 12. For example, the third heat radiating member 23 is exposed outside the resin 100. For example, the heat radiation may be supplemented by other portions. However, in this case, the exposed portion of the third heat radiating member 23 is brought into firm contact with an external cooling member so that no pressure stress is applied to the element forming surface 1a of the chips 11 and 12. Further, if no pressure stress is applied to the element forming surface 1a of the chips 11, 12, the semiconductor device may be sandwiched and fixed.
[0058]
When attention is paid to the protection of the devices of the respective chips 11 and 12, the electrode 115 on the other surface 1b side of each chip may not be pure Al. Moreover, although the 1st-3rd heat radiating members 21-23 were shown about the example formed separately and soldered, you may form integrally.
[0059]
Further, the electrode of the FWD 12 may not be made of pure Al as long as there is no problem such as thermal stress. If insulation between the heat radiation member 20 on the one surface side and the heat radiation member 24 on the other surface side is not necessary, the DBC substrate 4 made of AlN may not be used. The land 53 of the DBC substrate 4 may not be provided as long as the wire bond land 113 of the IGBT 11 and the gate terminal 8 can be directly wire bonded.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment.
FIG. 2 is a cross-sectional view showing a configuration of an IGBT in the present embodiment.
FIG. 3 is a top view of the semiconductor device according to the present embodiment.
FIG. 4 is a schematic cross-sectional view partially showing a conventional IGBT.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1a ... Element formation surface, 4 ... High heat conductive insulation board, 9 ... Heat dissipation surface,
11, 12 ... Semiconductor chip, 20-24 ... Heat dissipation member, 110 ... Substrate,
111 ... Barrier metal, 112, 113 ... One side electrode,
115: Electrode on the other side.

Claims (5)

Ｓｉ基板（１１０）からなる半導体チップ（１１）の素子形成面である一面（１ａ）側に、前記半導体チップ（１１）の放熱を行うための放熱部材（２０）が接合されてなる半導体装置において、
前記一面（１ａ）に形成された電極（１１２、１１３）が不純物を含まない純Ａｌであり、
前記電極（１１２、１１３）と前記半導体チップ（１１）の基板（１１０）との間に、ＳｉがＡｌ中に溶解することを防止するバリアメタル（１１１）が形成されていることを特徴とする半導体装置。In a semiconductor device in which a heat radiating member (20) for radiating heat of the semiconductor chip (11) is joined to one surface (1a) side which is an element formation surface of a semiconductor chip (11) made of a Si substrate (110). ,
The electrodes (112, 113) formed on the one surface (1a) are pure Al containing no impurities,
A barrier metal (111) for preventing Si from dissolving in Al is formed between the electrodes (112, 113) and the substrate (110) of the semiconductor chip (11). Semiconductor device. 前記半導体チップ（１１）における前記一面（１ａ）とは反対側の他面（１ｂ）に形成された電極（１１５）が、不純物を含まない純Ａｌであることを特徴とする請求項１に記載の半導体装置。Wherein the one surface of the semiconductor chip (11) (1a) electrode formed on the other surface opposite (1b) and (115), according to claim 1, characterized in that a pure Al containing no impurities Semiconductor device. 前記放熱部材（２０）からの放熱方向が、前記半導体チップ（１１）における前記一面（１ａ）から、前記一面（１ａ）とは反対側の他面（１ｂ）へ向かう方向となっていることを特徴とする請求項１または２に記載の半導体装置。The heat radiation direction from the heat radiating member (20) is a direction from the one surface (1a) of the semiconductor chip (11) toward the other surface (1b) on the opposite side to the one surface (1a). the semiconductor device according to claim 1 or 2, characterized. 前記半導体チップ（１１）における前記一面（１ａ）とは反対側の他面（１ｂ）側に放熱部材（２４）が接合され、
前記他面（１ｂ）側に接合された放熱部材（２４）が、外部の冷却部材と接合される部分である放熱面（９）を有しており、
前記一面（１ａ）側に接合された放熱部材（２０）と、前記他面（１ｂ）側に接合された放熱部材（２４）とが接合されて、前記一面（１ａ）側からの放熱が前記放熱面（９）で行われることを特徴とする請求項１または２に記載の半導体装置。A heat dissipation member (24) is joined to the other surface (1b) side opposite to the one surface (1a) in the semiconductor chip (11),
The heat dissipating member (24) joined to the other surface (1b) side has a heat dissipating surface (9) that is a part joined to an external cooling member,
The heat radiating member (20) joined to the one surface (1a) side and the heat radiating member (24) joined to the other surface (1b) side are joined, and the heat radiation from the one surface (1a) side is the semiconductor device according to claim 1 or 2, characterized in that takes place in the heat radiating surface (9). 前記一面（１ａ）側に接合された放熱部材（２０）と、前記他面（１ｂ）側に接合された放熱部材（２４）とが、高熱伝導絶縁基板（４）を介して接合されていることを特徴とする請求項４に記載の半導体装置。The heat radiating member (20) joined to the one surface (1a) side and the heat radiating member (24) joined to the other surface (1b) side are joined via a high thermal conductive insulating substrate (4). The semiconductor device according to claim 4 .
JP2000097911A 1999-11-24 2000-03-30 Semiconductor chip and semiconductor device Expired - Fee Related JP3630070B2 (en)

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JP2000097911A JP3630070B2 (en) 2000-03-30 2000-03-30 Semiconductor chip and semiconductor device
US09/717,227 US6703707B1 (en) 1999-11-24 2000-11-22 Semiconductor device having radiation structure
FR0015130A FR2801423B1 (en) 1999-11-24 2000-11-23 SEMICONDUCTOR DEVICE WITH RADIANT STRUCTURE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING ELECTRONIC INSTRUMENT
DE10066442A DE10066442B4 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating structure
DE10066441A DE10066441B4 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating components
DE10066443A DE10066443B8 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating components
DE10066446A DE10066446B4 (en) 1999-11-24 2000-11-24 Method for producing an electronic component with two emission components
DE10058446A DE10058446B8 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating components
DE10066445A DE10066445B4 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating structure
US10/321,365 US6693350B2 (en) 1999-11-24 2002-12-18 Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure
US10/699,744 US20040089940A1 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,785 US6891265B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,838 US6798062B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,837 US6960825B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,828 US6992383B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,746 US6998707B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,954 US6967404B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,784 US20040089941A1 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure

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