JP2008252114A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device in which both soldering strength between an upper semiconductor element and a lower semiconductor element and wire connection strength can be highly obtained. <P>SOLUTION: The semiconductor device is provided with a lower semiconductor element 1; electrode layers 5, 6 formed on an upper surface 1a of the lower semiconductor element 1; an upper semiconductor element 2 fixed on an upper surface 6a of the electrode layers 5, 6; and a conductive adhesive layer 7 for fixing the upper semiconductor element 2 onto the upper surface 6a of electrode layers 5, 6. The electrode layers 5, 6 have a fixing region 16 for fixing the upper semiconductor element 2, a non-conductive protective film 9 for covering at least a part of the electrode layers 5, 6 is annularly formed along the periphery of the fixing region 16, and the adhesive layer 7 is disposed in the annular protective film 9. The protective film 9 surrounding the fixing region 16 can prevent the effluence of an adhesive such as solder. In this way, when the adhesive layer 7 is formed comparatively thick on the upper surface 6a of the electrode layers 5, 6, heat to be generated on the lower semiconductor element 1 and the upper semiconductor element 2 can be excellently dissipated to the outside through the adhesive layer 7 when the semiconductor device 10 is operated. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that can be downsized by stacking a plurality of semiconductor elements.

  A metal support plate; a first transistor and a second transistor sequentially stacked on the support plate; a third transistor and a fourth transistor sequentially stacked on the support plate; A control circuit (control IC) fixed on a support plate between the second transistor, the third transistor, and the fourth transistor, the first transistor, the second transistor, and the third transistor; A semiconductor device that forms an H-type bridge circuit with the fourth transistor and the fourth transistor is known from Patent Document 1 below. According to Patent Document 1, the first transistor and the second transistor are stacked, and the third transistor and the fourth transistor are stacked to reduce the occupation area of the support plate. The degree can be improved.

  In the semiconductor device disclosed in Patent Document 1, the upper electrode formed on the upper surfaces of the first transistor and the third transistor and the lower electrode formed on the lower surfaces of the second transistor and the fourth transistor are fixed by soldering. At the same time, the upper surface electrodes formed on the upper surfaces of the first transistor and the third transistor are connected to the upper surface electrodes of the control circuit and a plurality of external leads arranged around the support plate by wires. Since the first transistor, the second transistor, and the third transistor and the fourth transistor are electrically connected to each other by solder, the current connection path is shortened, and noise generation due to the extension of the current connection path Power loss can be suppressed. Moreover, wire connection can be simplified.

International Publication No. 2005/018001

However, the upper electrodes of the first transistor and the third transistor disposed below are suitable for connection to a metal or wire suitable for solder connection to the lower electrodes of the second transistor and the fourth transistor. It was formed of any of the metals. An electrode made of a metal such as nickel or copper having excellent solderability has poor connectivity with a wire made of a metal such as aluminum or gold. In addition, an electrode made of a metal such as aluminum having high connection strength with a wire has poor connectivity (solder wettability) with a solder made of a metal such as lead or tin. For this reason, in the semiconductor device of the above-mentioned Patent Document 1, it has been difficult to realize a semiconductor device in which both the soldering strength and the wire connection strength can be obtained.
Therefore, an object of the present invention is to provide a semiconductor device having an electrode having high connectivity with a wire and solder.

  The semiconductor device of the present invention includes a lower semiconductor element (1), an electrode layer (5, 6) formed on the upper surface (1a) of the lower semiconductor element (1), and an upper surface (6a) of the electrode layer (5, 6). ) And a conductive adhesive layer (7) for fixing the upper semiconductor element (2) to the upper surface (6a) of the electrode layers (5, 6). The electrode layer (5, 6) has a fixing region (16) for fixing the upper semiconductor element (2), and a non-conductive protective film (9) covering at least a part of the electrode layer (5, 6) Is formed in an annular shape along the outer periphery of the fixing region (16). An adhesive layer (7) is disposed in the annular protective film (9). The protective film (9) formed in an annular shape along the outer periphery of the fixing region (16) of the electrode layer (5, 6) of the lower semiconductor element (1) is an upper semiconductor element ( 2) can be positioned, and the upper semiconductor element (2) can be accurately fixed to the predetermined position of the lower semiconductor element (1) by the adhesive layer (7). Since the protective film (9) surrounding the fixing region (16) can prevent outflow of adhesive such as solder, the adhesive layer (7) is relatively thick on the upper surface (6a) of the electrode layer (5, 6). When the semiconductor device (10) is formed and operated, heat generated in the lower semiconductor element (1) and the upper semiconductor element (2) can be radiated to the outside through the adhesive layer (7). .

  In the embodiment of the present invention, a semiconductor device includes a lower semiconductor element (1), a lower electrode layer (5) formed on an upper surface (1a) of the lower semiconductor element (1), and a lower electrode layer (5). Upper electrode layer (6) formed on upper surface (5a), upper semiconductor element (2) fixed to upper surface (6a) of upper electrode layer (6), and upper surface (6a) of upper electrode layer (6) And a conductive adhesive layer (7) for fixing the upper semiconductor element (2), and the upper surface (5a) of the lower electrode layer (5) and the upper surface (6a) of the upper electrode layer (6) are made of different materials. To form. The upper electrode layer (6) has a fixing region (16) for fixing the upper semiconductor element (2), and is non-conductive covering at least part of the upper electrode layer (6) and the lower electrode layer (5). The protective film (9) is formed in an annular shape along the outer periphery of the fixing region (16), and the adhesive layer (7) is disposed in the annular protective film (9).

  Since the upper surface (5a) of the lower electrode layer (5) and the upper surface (6a) of the upper electrode layer (6) provided between the lower semiconductor element (1) and the upper semiconductor element (2) are formed of different materials, The upper surface (6a) of the upper electrode layer (6) can be formed of a material having excellent solderability, and the upper surface (5a) of the lower electrode layer (5) can be formed of a material having high connection strength with the lead wire (8). . Therefore, the lower semiconductor element (1) and the upper semiconductor element (2) are firmly fixed by the adhesive layer (7) made of solder or the like, and the lower semiconductor element (1) and the lead thin wire (8) are firmly fixed. Thus, a highly reliable semiconductor device can be formed.

  According to the present invention, it is possible to realize a semiconductor device in which both the soldering strength between the upper semiconductor element and the lower semiconductor element and the wire connection strength can be obtained.

Embodiments of a semiconductor device according to the present invention will be described below with reference to FIGS.
As shown in FIG. 1, the semiconductor device of this embodiment includes a lower IGBT (insulated gate bipolar transistor) (1) as a lower semiconductor element and a lower portion formed on the upper surface (1a) of the lower IGBT (1). An electrode layer (5), a spaced electrode layer (gate pad) (18) formed on the upper surface (1a) of the lower IGBT (1) and spaced from the lower electrode layer (5), and a lower electrode layer (5) An upper electrode layer (6) formed on the upper surface (5a), and an upper IGBT (2) as an upper semiconductor element fixed to the upper surface (6a) of the upper electrode layer (6) by solder (7) as an adhesive layer ), The uppermost electrode layer (27) formed on the upper surface (2a) of the upper IGBT (2), and part of the upper electrode layer (6), the spaced electrode layer (18), the lower electrode layer (5), etc. And a non-conductive protective film (29) that covers a part of the uppermost electrode layer (27) and the like. The lower electrode layer (5) has a connection region (15) exposed to the outside by a notch (36) provided in the upper electrode layer (6) and an opening (19) provided in the protective film (9). . The connection region (15) is formed flat, and one end of the wire (8) as a lead fine wire is connected (wire bonding).

  As shown in FIG. 2, the lower IGBT (1) includes a lower semiconductor substrate (51) made of a silicon single crystal substrate or the like, and a gate made of, for example, silicon dioxide formed on the upper surface (51a) of the lower semiconductor substrate (51). An insulating film (24), a gate electrode (control electrode) (25) made of polysilicon, for example, formed on the upper surface (51a) of the lower semiconductor substrate (51) via the gate insulating film (24), and a gate electrode ( 25) and a lower electrode layer (5), an interlayer insulating film (26), and a collector formed by laminating, for example, aluminum and nickel formed on the lower surface (51b) of the lower semiconductor substrate (51). An electrode (bottom electrode) (13).

  The lower semiconductor substrate (51) includes a collector region (31) composed of a P + type semiconductor region formed adjacent to the lower surface (51b) of the lower semiconductor substrate (51), and an upper portion adjacent to the collector region (31). N-type buffer region (32) formed, N-type base region (30) formed above and adjacent to N-type buffer region (32), and upper surface (51a) of lower semiconductor substrate (51) Formed in the N-type base region (30) adjacent to the upper surface (51a) of the lower semiconductor substrate (51) and in the P-type base region (33). And an N-type emitter region (34). A gate electrode (25) is formed on the P-type base region (33) sandwiched between the N-type emitter region (34) and the N-type base region (30) via a gate insulating film (24). The well-known channel region is formed. As shown in FIG. 2, an opening (26a) is formed in the interlayer insulating film (26) that electrically insulates the gate electrode (25) from the lower electrode layer (5), and the lower electrode layer (5) Are electrically connected to the N-type emitter region (34) and the P-type base region (33) through the opening (26a) to constitute an emitter electrode.

  3 and 4 show the upper surface (51a) of the lower semiconductor substrate (51). As shown in FIG. 3, the P-type base region (33) has a lattice shape or stripe shape in the N-type base region (30) with respect to the planar direction of the lower semiconductor substrate (51) (as viewed in plan). Are arranged in parallel. The N-type emitter region (34) is disposed so as to oppose each other along the edge of the P-type base region (33). The gate electrode (25) is formed in a stripe shape between the P-type base regions (33) so as to straddle adjacent P-type base regions (33). Thereby, a cell (20a) which is the minimum unit of the active region of the semiconductor element is formed. In the semiconductor device of the present embodiment, the N-type emitter region (34) is formed only on the center side of the lower semiconductor substrate (51), and the N-type emitter region (34) is formed on the outer peripheral side of the lower semiconductor substrate (51). ) Is not formed. For this reason, as shown in FIG. 4, a cell formation region (20) in which a plurality of cells (20a) are formed and a cell (20a) are not formed on the upper surface (1a) of the lower IGBT (1). A non-formation region (44) is formed. The cell formation region (20) is formed on the center side of the lower IGBT (1), and the non-formation region (44) is annularly formed on the outer peripheral side of the lower IGBT (1) so as to surround the cell formation region (20). Has been. The P-type base region (33) may be formed in an island shape in the N-type base region (30).

  A gate bus line (43) for electrically connecting the gate electrode (25) and the separated electrode layer (18) is formed on the upper surface (51a) of the lower semiconductor substrate (51). Formed along the surface. The separation electrode layer (18) and the gate bus line (43) are formed of a conductive metal such as aluminum and cover the extended portion of the gate electrode (25) formed in a stripe shape, and the gate electrode (25) Electrically connected. That is, the separation electrode layer (18) and the gate bus line (43) have a laminated structure of polysilicon and aluminum on the upper surface (51a) of the lower semiconductor substrate (51).

  The upper IGBT (2) has an upper surface (2a) and a lower surface (2b) that are smaller in area than the upper surface (1a) and the lower surface (1b) of the lower IGBT (1) in plan view. Although not shown, the upper IGBT (2) includes an upper semiconductor substrate (52) having a cell formation region (20) in which a plurality of cells are formed on the upper surface (52a), and an upper surface (52a) of the upper semiconductor substrate (52). A gate insulating film formed on the upper semiconductor substrate 52, a gate electrode formed on the upper surface 52a of the upper semiconductor substrate 52 through the gate insulating film, and an uppermost electrode layer (emitter electrode) electrically connected to the cell. (27), an interlayer insulating film that electrically insulates the gate electrode from the uppermost electrode layer (27), and a collector electrode (14) formed on the lower surface (52b) of the upper semiconductor substrate (52). . Similarly to the lower IGBT (1), the upper IGBT (2) may form the cell formation region (20) only on the center side of the semiconductor substrate (52), or the cell formation region (20) may be formed on the semiconductor substrate (52). ) May be formed entirely.

  The lower electrode layer (5) of the lower IGBT (1) is electrically connected to the N-type emitter region (34) and the P-type base region (33). Further, the lower electrode layer (5) extends to the outer peripheral side of the cell formation region (20) in a plan view and covers a part of the upper surface of the non-formation region (44). The upper electrode layer (6) is formed on the upper surface (5a) of the lower electrode layer (5), extends to the outer peripheral side of the cell formation region (20), and is viewed in plan view in the non-formation region (44). A part of the upper surface of) is also covered. In other words, the cell formation region (20) is disposed on the center side of the lower semiconductor substrate (51) with respect to the outer peripheral edges of the cell formation region (20) and the non-formation region (44) in plan view.

  Further, at least the upper surface (5a) of the lower electrode layer (5) and the upper surface (6a) of the upper electrode layer (6) are formed of different materials, and the lower electrode layer (5) is a metal that forms the wire (8). It has a connection layer (23) formed adjacent to the upper electrode layer (6) with a metal having high adhesiveness, and the upper electrode layer (6) is adhesive to the metal forming the solder (7). It has a fixing layer (21) formed adjacent to the solder (7) with a high metal. In the present embodiment, as shown in FIG. 2, the lower electrode layer (5) is composed only of the connection layer (23), and the connection layer (23) is adhesive to the aluminum forming the wire (8). Formed of the same high aluminum (Al) or silicon-containing aluminum. On the other hand, the upper electrode layer (6) has excellent adhesion to the solder (7), for example, an adhesion layer (21) made of nickel (Ni), an adhesion layer (21), and the lower electrode layer (5). And an intervening layer (22) made of, for example, titanium (Ti), and the fixed layer (21) forms the upper surface (6a) of the upper electrode layer (6). Similarly to the upper electrode layer (6), the lower electrode layer (5) may have a laminated structure made of a plurality of different materials.

  In the present embodiment, the fixing layer (21) of the upper electrode layer (6) is formed of nickel having excellent wettability (compatibility) with the solder (7), but excellent in wettability with the solder (7). You may form with another metal material (for example, gold). Similarly, other metals other than aluminum may be used for the lower electrode layer (5). The material of the intervening layer (22) of the upper electrode layer (6) is appropriately determined depending on the compatibility with the materials of both the fixing layer (21) and the connection layer (23) of the lower electrode layer (5).

  The protective film (9, 29) is formed of a heat-resistant material such as PIF (polyimide film) or PBO (polybenzoxazole), and the protective film (9) provided on the lower IGBT (1) is formed of the lower electrode layer (5 The protective film (29) provided on the upper IGBT (2) has an opening (19) that exposes the connection region (15) to the outside, and the connection region (35) of the uppermost electrode layer (27). It has an opening (39) exposed to the outside. The protective films (9, 29) protect the semiconductor surfaces of the lower IGBT (1) and the upper IGBT (2) from impurities such as ions. The uppermost electrode layer (27) formed on the upper surface (2a) of the upper IGBT (2) is formed of a metal having high adhesiveness to the metal forming the wire (8), like the lower electrode layer (5). Is done.

  As shown in FIG. 1, the connection region (15) of the lower electrode layer (5) constitutes the wire connection region (wire bonding pad) of the emitter electrode of the lower IGBT (1), and the external element or the like is formed by the wire (8). Connected. Further, the upper surface (6a) of the upper electrode layer (6) exposed in the opening (19) of the protective film (9) constitutes a soldering region (die bonding pad) of the upper IGBT (2), and the upper IGBT ( It is electrically connected to the collector electrode (14) of 2). That is, the fixed region (16) of the upper electrode layer (6) to which the upper IGBT (2) is fixed becomes a nickel electrode surface excellent in solderability, and the connection region (15) to which the wire (8) is connected is The aluminum electrode surface has excellent wire (8) connectivity. In the present invention, the upper surface (5a) of the lower electrode layer (5) provided between the lower IGBT (1) and the upper IGBT (2) and the upper surface (6a) of the upper electrode layer (6) are formed of different materials. Therefore, the upper surface (6a) of the upper electrode layer (6) is formed of a material having excellent solderability, and the upper surface (5a) of the lower electrode layer (5) is formed of a material having high connection strength with the wire (8). Can be formed. For this reason, the lower IGBT (1) and the upper IGBT (2) are firmly fixed by the solder (7), and the lower IGBT (1) and the wire (8) are firmly connected to each other, thereby providing a highly reliable semiconductor. A device (10) can be formed. The adhesive referred to in the present invention includes an adhesive such as a solder material, a brazing material, and a silver paste, and it is particularly desirable to have conductivity. As the solder material, lead-free solder made of a material such as tin, silver, copper or aluminum that does not contain lead is used, but general solder made of tin and lead or other well-known solder may be used. . As the wire (8), for example, a well-known wire made of gold, aluminum or silicon-containing aluminum can be used.

  When the semiconductor device 10 of FIG. 1 is manufactured, a lower IGBT (1) in which a cell forming region (20) in which a plurality of cells (20a) are formed is provided on the center side of the upper surface (1a), and a lower IGBT ( Similar to 1), an upper IGBT (2) having a cell formation region on the upper surface (2a) is formed. As shown in FIG. 3, the cell formation region (20) of the lower IGBT (1) is formed on the center side of the upper surface (51a) of the lower semiconductor substrate (51) and surrounds the cell formation region (20). The formation region (44) is formed in an annular shape. Manufacturing methods of semiconductor elements such as the lower IGBT (1) and the upper IGBT (2) are well known and will not be described.

  As shown in FIG. 5, a lower electrode layer (5) made of aluminum is formed on the upper surface (51a) of the lower semiconductor substrate (51) by a known method such as a vapor deposition method such as CVD or PVD, a sputtering method or a plating method. Is done. Next, an etching mask (not shown) is formed on the upper surface (5a) of the lower electrode layer (5), and through the opening formed in the etching mask, the separation electrode is formed by an aluminum etching solution such as a phosphoric acid-based etching solution that dissolves aluminum. Unnecessary portions of the lower electrode layer (5) including the separation portion (37) between the layer (18) and the lower electrode layer (5) are removed. The lower electrode layer (5) extends to the outer peripheral side of the cell formation region (20) in a plan view and also covers a part of the upper surface of the non-formation region (44). Further, the separation electrode layer (18) is formed on the upper surface of the non-formation region (44).

  Subsequently, as shown in FIG. 6, an intervening layer (22) made of titanium and a fixing layer (21) made of nickel of the upper electrode layer (6) are sequentially formed in the same manner as the lower electrode layer (5). It is formed on the upper surface (5a) of the lower electrode layer (5). Thereafter, as shown in FIG. 7, an etching mask (not shown) is formed on the upper surface (6a) of the upper electrode layer (6), and hydrochloric acid-based etching in which titanium and nickel are simultaneously dissolved through the opening formed in the etching mask. An unnecessary portion of the upper electrode layer (6) is removed with a metal etching solution such as a solution. Titanium and nickel may be sequentially etched with different etching solutions. Thereby, the lower electrode layer (5) and the upper electrode layer (6) are stacked on the upper surface (1a) of the lower IGBT (1). Further, a connection region (15) that is not covered by the upper electrode layer (6) is formed in the lower electrode layer (5) by the notch (36) provided in the upper electrode layer (6) by etching. At this time, the upper electrode layer (6) etches away the outer peripheral side of the lower semiconductor substrate (51) from the outer peripheral edge of the cell forming region (20), that is, the upper side of the non-formed region (44). For this reason, the upper electrode layer (6) extends to the outer peripheral side of the cell formation region (20), and covers a part of the upper surface of the non-formation region (44) as viewed in a plan view. Further, as shown in FIG. 7, the connection region (15) of the lower electrode layer (5) is formed outside the cell formation region (20) of the lower semiconductor substrate (51).

  When the upper electrode layer (6) is etched with an etching solution, the lower electrode layer (5) may be eroded together with the upper electrode layer (6). Since the etching is removed on the outer peripheral side of the lower semiconductor substrate (51) with respect to the outer peripheral edge, the electrical characteristics can be prevented from being impaired by the etching of the upper electrode layer (6). Further, etching damage of the cell (20a) in the cell formation region (20) can be prevented. That is, since the lower electrode layer (5) electrically connects the P-type base region (33) and the N-type emitter region (34) of a large number of cells (20a), the cell formation region (20) If the lower electrode layer (5) formed thereon is etched, the electrical characteristics of the lower IGBT (1) may be impaired. On the other hand, the non-formation region (44) extending outside the cell formation region (20) of the lower IGBT (1) is a portion constituting the connection region (15) to be a bonding pad, etc. Even if it is eroded by etching of the layer (6), it is very unlikely to be affected by the electrical properties. Therefore, a highly reliable semiconductor device with stable electrical characteristics can be formed.

  Next, the upper electrode layer (6), the separated electrode layer (18), and a part of the lower electrode layer (5) are covered with the protective film (9). The protective film (9) has an opening (19) in two bonding pads of the connection region (15) and the separated electrode layer (18) and a pad of the fixing region (16). As shown in FIG. 8, the upper IGBT (2) is fixed to the lower IGBT (1) by the solder (7) through the opening (19) of the fixing region (16). The solder (7) is formed higher than the protective film (9). An uppermost electrode layer (27), a protective film (29), and a collector electrode (14) are formed in advance on the upper IGBT (2). As shown in FIG. 9, the protective film (9) is annularly formed on the outer periphery of the fixing region (16) of the lower IGBT (1), and has a positioning effect when fixing the upper IGBT (2). As a result, as shown in FIG. 1, the upper IGBT (2) is soldered to a predetermined position of the lower IGBT (1) with high accuracy. Further, the protective film (9) surrounding the fixing region (16) can prevent the solder (7) from flowing out. As a result, the solder (7) is formed relatively thick on the upper surface of the upper electrode layer (6), and can efficiently dissipate heat generated when the semiconductor device (10) is operated.

  The collector electrode (13) formed on the lower surface (51b) of the lower semiconductor substrate (51) is fixed to the upper surface of the support plate (45) via solder. Further, as shown in FIG. 1, the connection regions (15, 35) of the lower IGBT (1) and the upper IGBT (2) and the separated electrode layer (18) are connected to an external element (not shown) or an external lead (not shown). The end of 8) is connected. Thereby, the semiconductor device (10) is completed.

FIG. 10 shows an embodiment of the present invention in which the H-type bridge circuit shown in FIG. 11 is constituted by a single semiconductor device by the semiconductor device (10) shown in FIG. The H-type bridge circuit includes a high-side lower IGBT (1) and another lower IGBT (3), and a low-side upper IGBT (2) and another upper IGBT (4). The first laminated body of the lower IGBT (1) and the upper IGBT (2) and the second laminated body of the other lower IGBT (3) and the other upper IGBT (4) are made of copper or aluminum having heat dissipation properties. It is fixed on a metal support plate (45). A control device (40) for controlling the switching operation from the lower IGBT (1) to another upper IGBT (4) is provided, and a plurality of devices arranged around the surface electrode or the support plate (45) of the control device (40). The external lead (42), the connection region (emitter electrode) (15, 35) of the lower IGBT (1) and the upper IGBT (2) and the separated electrode layer (gate electrode) (18) are connected by the wire (8). . As shown in FIG. 10, the control device (40) is fixed on the support plate (45) between the first laminate and the second laminate. The connection point (A ₁ ) between the lower electrode layer (emitter electrode) (5) of the lower IGBT (1) and the collector electrode (14) of the upper IGBT (2), and the lower electrode layer of the other lower IGBT (3) ( Between the connection point (A ₂ ) of the emitter electrode) and the collector electrode of the other upper IGBT (4), a load (41), for example, a cold cathode fluorescent discharge tube driven by an alternating current is connected. . The entire semiconductor device is covered with the resin sealing body (43), but the external leads (42) are led out from the resin sealing body (43).

When operating the H-bridge circuit, the lower IGBT (1) and other upper IGBT (4) and the upper IGBT (2) and other lower IGBT (3) are alternately turned on and off to perform switching. By actuating, the load (41) can be actuated by causing a reverse current to flow alternately between the connection points (A ₁ ) and (A ₂ ). In this way, the switching operation from the lower IGBT (1) to the other upper IGBT (4) is performed, and the DC voltage source is used to connect the cold connected between the connection points (A ₁ ) and (A ₂ ). The cathode fluorescent discharge tube can be lit. According to the semiconductor device (50) shown in FIG. 10, the degree of integration can be improved while reducing the area occupied by the support plate (45), and the lower IGBT (1), the upper IGBT (2), and the other lower IGBT ( 3) and other upper IGBT (4) are firmly fixed with solder (7), and each IGBT (1, 2, 3, 4) and wire (8) are firmly connected to each other for high reliability. A semiconductor device can be formed.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, instead of each IGBT (1, 2, 3, 4), a semiconductor element such as another bipolar transistor, a field effect transistor, a thyristor, or a triac may be configured. In addition, as shown in FIG. 12, after covering a part of the lower electrode layer (5) with the protective film (9), the upper electrode layer (6) is formed on the upper surface (5a) of the lower electrode layer (5). May be. In this way, since the lower electrode layer (5) is protected by the protective film (9), when the unnecessary portion of the upper electrode layer (6) is removed by etching above the protective film (9), the lower electrode layer It is possible to satisfactorily prevent the layer (5) from being eroded.

  INDUSTRIAL APPLICABILITY The present invention can be satisfactorily applied to a semiconductor device formed by stacking a plurality of semiconductor elements, a semiconductor device constituting an H bridge circuit (full bridge circuit) used for a cold cathode fluorescent discharge tube driving device, and the like. .

Sectional drawing which shows one Embodiment of the semiconductor device by this invention Partial enlarged view of FIG. Partial enlarged view of the lower semiconductor substrate of FIG. Plan view of the lower semiconductor substrate of FIG. Sectional drawing which shows the state which formed the lower electrode layer in the upper surface of a lower semiconductor substrate Sectional drawing which shows the state which formed the upper electrode layer on the upper surface of the lower electrode layer of FIG. Sectional drawing which shows the state which etched the upper electrode layer of FIG. FIG. 9 is a cross-sectional view showing a state where the upper IGBT is stacked. The top view which shows the state which coat | covered the protective film on the upper surface of the lower semiconductor substrate of FIG. 1 is a plan view showing an embodiment of the semiconductor device of FIG. Circuit diagram of FIG. Sectional drawing which shows the modification of FIG.

Explanation of symbols

  (1) ・ ・ Lower semiconductor element (lower IGBT), (1a, 2a, 5a, 6a) ・ ・ Upper surface, (2) ・ ・ Upper semiconductor element (upper IGBT), (5) ・ ・ Lower electrode layer, (6・ ・ Upper electrode layer, (7) ・ ・ Solder, (8) ・ ・ Lead wire (wire), (9) ・ Protective film, (15) ・ ・ Connection area, (19) ・ ・ Opening, ( 20) ... cell formation area, (20a) ... cell, (21) ... fixed layer, (23) ... connection layer, (36) ... notch, (40) ... control device,

Claims (3)

A lower semiconductor element, an electrode layer formed on the upper surface of the lower semiconductor element, an upper semiconductor element fixed to the upper surface of the electrode layer, and a conductive adhesive for fixing the upper semiconductor element to the upper surface of the electrode layer With agent layer,
The electrode layer has a fixing region for fixing the upper semiconductor element;
Forming a non-conductive protective film covering at least a part of the electrode layer in an annular shape along the outer periphery of the fixed region;
A semiconductor device, wherein the adhesive layer is disposed in the annular protective film.   The semiconductor device according to claim 1, wherein the adhesive layer is formed higher than the protective film.   The semiconductor device according to claim 1, wherein the adhesive layer is formed of a solder material, a brazing material, or a silver paste.

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