JP2020202313A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

To provide a semiconductor device capable of suppressing deterioration of reliability be caused by a terminal electrode.SOLUTION: Provided is a semiconductor device 1 including: a semiconductor layer 2 having a first main surface 3 and a roughened second main surface 4; a gate terminal electrode 12 and a source terminal electrode 14 formed on the first main surface 3; an organic insulating layer 18 partially covering the gate terminal electrode 12 and the source terminal electrode 14 on the first main surface 3; and a drain terminal electrode 22 directly connected to the second main surface 4 via no silicide layer.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Patent Document 1 discloses a semiconductor device including a Si substrate and a back surface electrode (terminal electrode) having a Ti ceiling layer formed on the back surface of the Si substrate.

Japanese Unexamined Patent Publication No. 2011-233643

The Ti silicide layer according to Patent Document 1 is formed by forming a Ti layer on one main surface of a semiconductor layer and then heat-treating the Ti layer. The step of forming the Ti ceiling layer is carried out after the structure on the other main surface side of the semiconductor layer is formed. Therefore, the step of forming the Ti ceiling layer causes various problems in the structure on the other main surface side of the semiconductor layer.
For example, when the organic insulating layer is formed on the other main surface side of the semiconductor layer, the organic insulating layer is carbonized by the heat generated when the Ti Missil layer is formed. As a result, the semiconductor layer cannot be appropriately protected by the organic insulating layer, so that the reliability of the semiconductor device is lowered.

Such a problem can be avoided by omitting the step of forming the Ti silicide layer and connecting the Ti layer directly to one main surface of the semiconductor layer. However, in this case, the adhesion of the Ti layer to the semiconductor layer becomes insufficient, which causes a new problem of poor connection. As a result, the reliability of the semiconductor device is lowered.
One embodiment of the present invention provides a semiconductor device capable of suppressing a decrease in reliability due to a terminal electrode and a method for manufacturing the same.

In one embodiment of the present invention, a semiconductor layer having a first main surface on one side and a second main surface on the other side that has been roughened, and a first terminal electrode formed on the first main surface. Includes an organic insulating layer that partially covers the first terminal electrode on the first main surface, and a second terminal electrode that is directly connected to the second main surface without interposing a silicide layer. Provides semiconductor devices.
According to this semiconductor device, since the second main surface is roughened, it is possible to increase the adhesion of the second terminal electrode to the second main surface. As a result, the peeling of the second terminal electrode from the second main surface can be suppressed, so that the second terminal electrode can be directly connected to the second main surface without using the silicide layer.

As a result, it is not necessary to heat the semiconductor layer at the time of forming the second terminal electrode, so that the structure on the first main surface side of the semiconductor layer can be appropriately formed. As an example, carbonization of the organic insulating layer due to the forming step of the second terminal electrode can be prevented. Therefore, it is possible to provide a semiconductor device capable of suppressing a decrease in reliability caused by the second terminal electrode.
One embodiment of the present invention includes a step of preparing a wafer layer having a first main surface on one side and a second main surface on the other side, and a step of forming a first terminal electrode on the first main surface. A step of forming an organic insulating layer that partially covers the first terminal electrode on the first main surface, and a step of roughening the second main surface after the step of forming the organic insulating layer. After the roughening step of the second main surface, a step of forming a second terminal electrode on the second main surface so as to be directly connected to the second main surface without passing through a VDD layer, and the above. Provided is a method for manufacturing a semiconductor device, which includes a step of cutting a wafer layer and cutting out a semiconductor device.

According to this method of manufacturing a semiconductor device, the second main surface is roughened, so that the adhesion of the second terminal electrode to the second main surface can be increased. As a result, the peeling of the second terminal electrode from the second main surface can be suppressed, so that the second terminal electrode can be directly connected to the second main surface without using the silicide layer.
As a result, it is not necessary to heat the semiconductor layer when the second terminal electrode is formed, so that carbonization of the organic insulating layer due to the process of forming the second terminal electrode can be prevented. Therefore, it is possible to manufacture and provide a semiconductor device capable of suppressing a decrease in reliability caused by the second terminal electrode.

FIG. 1 is a perspective view showing a semiconductor device according to the first embodiment of the present invention, and shows a form in which a second terminal electrode according to a first embodiment is incorporated. FIG. 2 is a plan view of the semiconductor device of FIG. FIG. 3 is a plan view of FIG. 2 with the structure above the first terminal electrode removed. FIG. 4 is an enlarged view of the region IV shown in FIG. 3 and is a diagram for explaining the structure of the first main surface of the semiconductor layer. FIG. 5 is a cross-sectional view taken along the line VV shown in FIG. FIG. 6A is an enlarged view of the region VI shown in FIG. FIG. 6B is a diagram showing a second terminal electrode according to a second embodiment. FIG. 6C is a diagram showing a second terminal electrode according to a third embodiment. FIG. 6D is a diagram showing a second terminal electrode according to a fourth embodiment. FIG. 6E is a diagram showing a second terminal electrode according to a fifth embodiment. FIG. 6F is a diagram showing a second terminal electrode according to a sixth embodiment. FIG. 6G is a diagram showing a second terminal electrode according to a seventh embodiment. FIG. 7 is a plan view showing a wafer used for manufacturing the semiconductor device shown in FIG. FIG. 8A is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. FIG. 8B is a diagram showing a step after FIG. 8A. FIG. 8C is a diagram showing a step after FIG. 8B. FIG. 8D is a diagram showing a step after FIG. 8C. FIG. 8E is a diagram showing a process after FIG. 8D. FIG. 8F is a diagram showing a process after FIG. 8E. FIG. 8G is a diagram showing a process after FIG. 8F. FIG. 8H is a diagram showing a process after FIG. 8G. FIG. 8I is a diagram showing a step after FIG. 8H. FIG. 8J is a diagram showing a step after FIG. 8I. FIG. 9A is a cross-sectional view showing an example of a manufacturing process of a main part of the MISFET. FIG. 9B is a diagram showing a step after FIG. 9A. FIG. 9C is a diagram showing a process after FIG. 9B. FIG. 9D is a diagram showing a process after FIG. 9C. FIG. 9E is a diagram showing a process after FIG. 9D. FIG. 9F is a diagram showing a process after FIG. 9E. FIG. 9G is a diagram showing a process after FIG. 9F. FIG. 9H is a diagram showing a process after FIG. 9G. FIG. 9I is a diagram showing a step after FIG. 9H. FIG. 10 is a perspective view showing a semiconductor package incorporating the semiconductor device shown in FIG. 1 through the package body. FIG. 11 is a perspective view showing the semiconductor device according to the second embodiment of the present invention, showing a form in which the second terminal electrode according to the first embodiment is incorporated. FIG. 12 is a plan view of the semiconductor device of FIG. FIG. 13 is a cross-sectional view taken along the line XIII-XIII shown in FIG. FIG. 14A is an enlarged view of the region XIV shown in FIG. FIG. 14B is a diagram showing a second terminal electrode according to a second embodiment. FIG. 14C is a diagram showing a second terminal electrode according to a third embodiment. FIG. 14D is a diagram showing a second terminal electrode according to a fourth embodiment. FIG. 14E is a diagram showing a second terminal electrode according to a fifth embodiment. FIG. 14F is a diagram showing a second terminal electrode according to a sixth embodiment. FIG. 14G is a diagram showing a second terminal electrode according to a seventh embodiment. FIG. 15 is a plan view showing a wafer used for manufacturing the semiconductor device shown in FIG. FIG. 16A is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. FIG. 16B is a diagram showing a step after FIG. 16A. FIG. 16C is a diagram showing a step after FIG. 16B. FIG. 16D is a diagram showing a step after FIG. 16C. FIG. 16E is a diagram showing a step after FIG. 16D. FIG. 16F is a diagram showing a step after FIG. 16E. FIG. 16G is a diagram showing a process after FIG. 16F. FIG. 16H is a diagram showing a process after FIG. 16G. FIG. 16I is a diagram showing a step after FIG. 16H. FIG. 16J is a diagram showing a step after FIG. 16I. FIG. 16K is a diagram showing a process after FIG. 16J. FIG. 16L is a diagram showing a process after FIG. 16K. FIG. 16M is a diagram showing a step after FIG. 16L. FIG. 17 is a perspective view showing a semiconductor package incorporating the semiconductor device shown in FIG. 11 through the package body.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a perspective view showing a semiconductor device 1 according to a first embodiment of the present invention (hereinafter, simply referred to as “this embodiment”), wherein the drain terminal electrode 22 according to the first embodiment is Shows the incorporated form. FIG. 2 is a plan view of the semiconductor device 1 of FIG. FIG. 3 is a plan view of FIG. 2 with the structure above the gate terminal electrode 12 and the source terminal electrode 13 removed.

FIG. 4 is an enlarged view of the region IV shown in FIG. 3 and is a diagram for explaining the structure of the first main surface 3 of the semiconductor layer 2. FIG. 5 is a cross-sectional view taken along the line VV shown in FIG. FIG. 6A is an enlarged view of the region VI shown in FIG.
The semiconductor device 1 is a switching device including a vertical MISFET (Metal Insulator Field Effect Transistor) as an example of a functional device. With reference to FIGS. 1 to 3, the semiconductor device 1 includes a semiconductor layer 2 made of a Si (silicon) single crystal. The semiconductor layer 2 is formed in the shape of a rectangular parallelepiped chip.

The semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, 5D connecting the first main surface 3 and the second main surface 4. ing. The first main surface 3 and the second main surface 4 are formed in a rectangular shape (rectangular shape in this form) in a plan view (hereinafter, simply referred to as “planar view”) viewed from their normal direction Z. ..
The first main surface 3 is a device forming surface. The first main surface 3 is a non-mounting surface. The second main surface 4 is a mounting surface. When the semiconductor device 1 is mounted on the object to be connected, the semiconductor layer 2 is mounted on the object to be connected with the second main surface 4 facing each other. Examples of the connection object include electronic components, lead frames, circuit boards, and the like.

The second main surface 4 is composed of a roughened surface. The second main surface 4 is roughened by irregularly formed unevenness (Unevenness). It is preferable that the entire area of the second main surface 4 is roughened. It is particularly preferable that the second main surface 4 is a roughened surface having no grinding marks (more specifically, grinding marks extending in a line shape). More specifically, the second main surface 4 is a crystal plane made of a Si single crystal. Therefore, the second main surface 4 is composed of a crystal roughened surface in which a Si single crystal is roughened.

The arithmetic mean roughness Ra of the second main surface 4 may exceed 0 nm and be 1000 nm or less. The arithmetic mean roughness Ra may be more than 0 nm and 50 nm or less, 50 nm or more and 100 nm or less, 100 nm or more and 200 nm or less, 200 nm or more and 400 nm or less, 400 nm or more and 600 nm or less, 600 nm or more and 800 nm or less, 800 nm or more and 1000 nm or less. The arithmetic average roughness Ra is preferably more than 0 nm and 400 nm or less.

The side surfaces 5A and 5C extend along the first direction X and face each other in the second direction Y intersecting the first direction X. The second direction Y is, more specifically, a direction orthogonal to the first direction X. The side surface 5A and the side surface 5C form a short side of the semiconductor layer 2 in a plan view.
The side surface 5B and the side surface 5D extend along the second direction Y and face each other in the first direction X. The side surface 5B and the side surface 5D form a long side of the semiconductor layer 2 in a plan view. The side surfaces 5A to 5D extend in a plane along the normal direction of the first main surface 3 and the second main surface 4, respectively.

In this form, the semiconductor layer 2 has a laminated structure including an n ⁺ type semiconductor substrate 6 and an n-type epitaxial layer 7. The second main surface 4 is formed by the semiconductor substrate 6. The first main surface 3 is formed by the epitaxial layer 7. The side surfaces 5A to 5D are formed by the semiconductor substrate 6 and the epitaxial layer 7.
The concentration of n-type impurities in the epitaxial layer 7 is less than the concentration of n-type impurities in the semiconductor substrate 6. The concentration of n-type impurities in the semiconductor substrate 6 may be 1.0 × 10 ¹⁸ cm ^-3 or more and 1.0 × 10 ²¹ cm ^-3 or less. The concentration of n-type impurities in the epitaxial layer 7 may be 1.0 × 10 ¹⁵ cm ^-3 or more and 1.0 × 10 ¹⁸ cm ^-3 or less.

The semiconductor substrate 6 is formed as a drain region 28 of the MISFET. The epitaxial layer 7 is formed as a drift region 29 of the MISFET.
The semiconductor layer 2 includes an active region 8 and an outer region 9. The active region 8 is a region in which the main part of the MISFET is formed.
The active region 8 is formed in the central portion of the semiconductor layer 2 at intervals inward from the side surfaces 5A to 5D in a plan view. The active region 8 may be formed in a quadrangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view. In this form, the active region 8 is formed in a rectangular shape in a plan view.

The outer region 9 is a region outside the active region 8. The outer region 9 is formed in the region between the side surfaces 5A to 5D and the periphery of the active region 8. The outer region 9 is formed in an annular shape (endless in this form) surrounding the active region 8 in a plan view.
A main surface insulating layer 10 is formed on the first main surface 3. The main surface insulating layer 10 is also referred to as an interlayer insulating layer. The main surface insulating layer 10 covers the active region 8 and the outer region 9. The main surface insulating layer 10 may contain at least one of silicon oxide and silicon nitride. The main surface insulating layer 10 contains silicon oxide in this form.

The main surface insulating layer 10 has insulating side surfaces 11A, 11B, 11C, and 11D. The insulating side surfaces 11A to 11D are connected to the side surfaces 5A to 5D. The insulating side surfaces 11A to 11D are formed flush with each other with respect to the side surfaces 5A to 5D.
A gate terminal electrode 12 and a source terminal electrode 13 as the first terminal electrode are formed on the first main surface 3. More specifically, the gate terminal electrode 12 and the source terminal electrode 13 are formed on the main surface insulating layer 10.

A gate voltage is applied to the gate terminal electrode 12. The gate voltage may be 0.5 V or more and 50 V or less (preferably 10 V or less). The gate terminal electrode 12 includes a gate pad 12A and gate fingers 12B and 12C.
The gate pad 12A is formed in a region along the side surface 5A in a plan view. More specifically, the gate pad 12A is formed in a region along the central portion of the side surface 5A in a plan view. The gate pad 12A may be formed in a region along a corner portion connecting any two of the side surfaces 5A to 5D in a plan view.

The gate pad 12A may be formed in a rectangular shape in a plan view. The gate pad 12A is pulled out from the outer region 9 into the active region 8 so as to cross the boundary between the outer region 9 and the active region 8 in a plan view.
The gate fingers 12B and 12C include an outer gate finger 12B and an inner gate finger 12C. The outer gate finger 12B is pulled out from the gate pad 12A into the outer region 9. The outer gate finger 12B extends in a band shape over the outer region 9. The outer gate fingers 12B are formed along the three sides 5A, 5B, 5D in this form so as to partition the active region 8 from three directions.

The inner gate finger 12C is pulled out from the gate pad 12A into the active region 8. The inner gate finger 12C extends in a band shape in the active region 8. The inner gate finger 12C extends from the side surface 5A side toward the side surface 5C side.
A source voltage is applied to the source terminal electrode 13. The source voltage may be a reference voltage (eg, GND voltage). The source terminal electrode 13 is formed in the active region 8 at a distance from the gate terminal electrode 12. The source terminal electrode 13 is formed in a C shape in a plan view and covers a region partitioned by the gate terminal electrode 12.

The gate terminal electrode 12 preferably includes at least one of a pure Al layer (an Al layer having a purity of 99% or more), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer. The source terminal electrode 13 preferably includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.
An inorganic insulating layer 14 is formed on the first main surface 3. The inorganic insulating layer 14 is also referred to as a passivation layer. More specifically, the inorganic insulating layer 14 is formed on the main surface insulating layer 10. The inorganic insulating layer 14 includes at least one of a silicon oxide layer and a silicon nitride layer.

The inorganic insulating layer 14 may have a laminated structure in which a silicon oxide layer and a silicon nitride layer are laminated in any order. The inorganic insulating layer 14 preferably contains an insulating material different from that of the main surface insulating layer 10. In this form, the inorganic insulating layer 14 has a single-layer structure composed of a silicon nitride layer.
The inorganic insulating layer 14 includes side surfaces 15A, 15B, 15C, 15D. The side surfaces 15A to 15D of the inorganic insulating layer 14 are formed at intervals inward from the side surfaces 5A to 5D of the semiconductor layer 2 in a plan view. The side surfaces 15A to 15D of the inorganic insulating layer 14 expose the peripheral edge portion of the semiconductor layer 2. The side surfaces 15A to 15D of the inorganic insulating layer 14 expose the main surface insulating layer 10.

The inorganic insulating layer 14 selectively covers the gate terminal electrode 12 and the source terminal electrode 13. The inorganic insulating layer 14 includes a gate subpad opening 16 and a source subpad opening 17. The gate subpad opening 16 exposes a part of the gate pad 12A. The source sub-pad opening 17 exposes a part of the source terminal electrode 13 as a pad region.

An organic insulating layer 18 is formed on the inorganic insulating layer 14. The inorganic insulating layer 14 and the organic insulating layer 18 form one insulating laminated structure (insulating layer). In FIG. 2, the organic insulating layer 18 is shown by hatching. The organic insulating layer 18 selectively covers the gate terminal electrode 12 and the source terminal electrode 13.
The organic insulating layer 18 may contain a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The organic insulating layer 18 preferably contains at least one of polybenzoxazole, polyimide and polyamide. In this form, the organic insulating layer 18 contains polybenzoxazole as an example of a positive type photosensitive resin.

The organic insulating layer 18 has a non-burnt outer surface. The organic insulating layer 18 has an outer surface that does not contain carbides. More specifically, the organic insulating layer 18 does not contain carbides. The organic insulating layer 18 includes side surfaces 19A, 19B, 19C, 19D. The side surfaces 19A to 19D of the organic insulating layer 18 are formed inwardly spaced from the side surfaces 5A to 5D of the semiconductor layer 2 in a plan view.

The side surfaces 19A to 19D of the organic insulating layer 18 expose the peripheral edge portion of the semiconductor layer 2 in a plan view. More specifically, the side surfaces 19A to 19D of the organic insulating layer 18 expose the main surface insulating layer 10 together with the inorganic insulating layer 14. In this form, the side surfaces 19A to 19D of the organic insulating layer 18 are formed flush with the side surfaces 15A to 15D of the inorganic insulating layer 14.
The organic insulating layer 18 includes a gate pad opening 20 and a source pad opening 21. The gate pad opening 20 exposes a part of the gate pad 12A. The source pad opening 21 exposes a part of the source terminal electrode 13 as a pad region.

The gate pad opening 20 of the organic insulating layer 18 communicates with the gate subpad opening 16 of the inorganic insulating layer 14. The inner wall of the gate pad opening 20 may be located outside the inner wall of the gate subpad opening 16. The inner wall of the gate pad opening 20 may be located inside the inner wall of the gate subpad opening 16. The organic insulating layer 18 may cover the inner wall of the gate subpad opening 16.

The source pad opening 21 of the organic insulating layer 18 communicates with the source sub pad opening 17 of the inorganic insulating layer 14. The inner wall of the source pad opening 21 may be located outside the inner wall of the source subpad opening 17. The inner wall of the source pad opening 21 may be located inside the inner wall of the source subpad opening 17. The organic insulating layer 18 may cover the inner wall of the source subpad opening 17.

The side surfaces 19A to 19D of the organic insulating layer 18 partition the dicing street 53 from the side surfaces 5A to 5D of the semiconductor layer 2. In this form, the side surfaces 15A to 15D of the inorganic insulating layer 14 also partition the dicing street 53 from the side surfaces 5A to 5D of the semiconductor layer 2.
According to the dicing street 53, it is not necessary to physically cut the organic insulating layer 18 and the inorganic insulating layer 14. As a result, the semiconductor device 1 can be smoothly cut out from the wafer, and at the same time, peeling and deterioration of the organic insulating layer 18 and the inorganic insulating layer 14 can be suppressed. As a result, the semiconductor layer 2, the gate terminal electrode 12, the source terminal electrode 13, and the like can be appropriately protected by the organic insulating layer 18 and the inorganic insulating layer 14.

The width of the dicing street 53 may be 10 μm or more and 150 μm or less. The width of the dicing street 53 is the width in the direction orthogonal to the direction in which the dicing street 53 extends.
The sides 15A to 15D of the inorganic insulating layer 14 do not necessarily partition the dicing street 53. The side surfaces 15A to 15D of the inorganic insulating layer 14 may be formed flush with the side surfaces 5A to 5D of the semiconductor layer 2.

The thickness of the organic insulating layer 18 may be 1 μm or more and 20 μm or less.
A drain terminal electrode 22 as a second terminal electrode is formed on the second main surface 4 of the semiconductor layer 2. When off, the maximum voltage that can be applied between the source terminal electrode 13 and the drain terminal electrode 22 may be 20 V or more and 10000 V or less.
The drain terminal electrode 22 forms ohmic contact with the second main surface 4. The drain terminal electrode 22 is directly connected to the roughened second main surface 4. More specifically, the drain terminal electrode 22 is directly connected to the crystal roughened surface of the second main surface 4.

More specifically, the drain terminal electrode 22 is directly connected to the second main surface 4 without forming a silicide layer containing silicide in the main configuration. The drain terminal electrode 22 does not include a region in which the material containing silicide in the main configuration is formed in layers.
Further, the drain terminal electrode 22 directly on the second main surface 4 without forming a modified layer in which the crystal state of the second main surface 4 is modified to other properties with the second main surface 4. It is connected. Examples of the modified layer include a Si melt rehardened layer, a Si polycrystalline layer, and a Si amorphous layer.

Further, the drain terminal electrode 22 is directly connected to the second main surface 4 without forming a eutectic layer containing a eutectic in the main configuration. The drain terminal electrode 22 does not include a region in which a material containing a eutectic as a main component is formed in a layer.
That is, the drain terminal electrode 22 is directly connected to the roughened second main surface 4 without the intervention of the silicide layer, the modified layer, and the eutectic layer.

With reference to FIG. 6A, the drain terminal electrode 22 has a laminated structure including a plurality of electrode layers laminated on the second main surface 4. In this form, the drain terminal electrode 22 has a laminated structure including a Ti layer 23, a Ni layer 24, an Au layer 25, and an Ag layer 26 laminated in this order from the second main surface 4 side.
The Ti layer 23 is directly connected to the roughened second main surface 4. The Ti layer 23 preferably covers the entire area of the second main surface 4. The Ti layer 23 is formed as an ohmic electrode that forms ohmic contact with the second main surface 4. The Ti layer 23 is directly connected to the second main surface 4 without the intervention of the silicide layer, the modified layer and the eutectic layer.

The Ni layer 24 covers the Ti layer 23. The Ni layer 24 preferably covers the entire area of the Ti layer 23. The Au layer 25 covers the Ni layer 24. The Au layer 25 preferably covers the entire area of the Ni layer 24. The Ag layer 26 covers the Au layer 25. The Ag layer 26 preferably covers the entire area of the Au layer 25.
The drain terminal electrode 22 may include at least one of the Ti layer 23, the Ni layer 24, the Au layer 25, and the Ag layer 26. Hereinafter, other examples of the drain terminal electrode 22 will be shown.

FIG. 6B is a cross-sectional view corresponding to FIG. 6A, showing a drain terminal electrode 22 according to a second embodiment.
With reference to FIG. 6B, the drain terminal electrode 22 has a single layer structure composed of a Ti layer 23 formed on the second main surface 4 in this form. The Ti layer 23 is formed as an ohmic electrode that forms ohmic contact with the second main surface 4. The Ti layer 23 is directly connected to the second main surface 4 without the intervention of the silicide layer, the modified layer and the eutectic layer.

FIG. 6C is a cross-sectional view corresponding to FIG. 6A, showing a drain terminal electrode 22 according to a third embodiment.
With reference to FIG. 6C, the drain terminal electrode 22 has, in this form, a single layer structure composed of an Au layer 25 formed on the second main surface 4. The Au layer 25 is formed as an ohmic electrode that forms ohmic contact with the second main surface 4. The Au layer 25 is directly connected to the second main surface 4 without the intervention of the silicide layer, the modified layer and the eutectic layer.

FIG. 6D is a cross-sectional view corresponding to FIG. 6A, showing a drain terminal electrode 22 according to a fourth embodiment.
With reference to FIG. 6D, in this embodiment, the drain terminal electrode 22 has a laminated structure including the Au layer 25 and the Ag layer 26 laminated in this order from the second main surface 4 side. The Au layer 25 is formed as an ohmic electrode that forms ohmic contact with the second main surface 4.

The Au layer 25 is directly connected to the second main surface 4 without the intervention of the silicide layer, the modified layer and the eutectic layer. The Ag layer 26 covers the Au layer 25. The Ag layer 26 preferably covers the entire area of the Au layer 25.
FIG. 6E is a cross-sectional view corresponding to FIG. 6A, showing a drain terminal electrode 22 according to a fifth embodiment.

With reference to FIG. 6E, in this embodiment, the drain terminal electrode 22 has a laminated structure including a Ti layer 23, a Ni layer 24, and an Au layer 25 laminated in this order from the second main surface 4 side. The Ti layer 23 is formed as an ohmic electrode that forms ohmic contact with the second main surface 4. The Ti layer 23 is directly connected to the second main surface 4 without the intervention of the silicide layer, the modified layer and the eutectic layer.

The Ni layer 24 covers the Ti layer 23. The Ni layer 24 preferably covers the entire area of the Ti layer 23. The Au layer 25 covers the Ni layer 24. The Au layer 25 preferably covers the entire area of the Ni layer 24.
FIG. 6F is a cross-sectional view corresponding to FIG. 6A, showing a drain terminal electrode 22 according to a sixth embodiment.

With reference to FIG. 6F, in this embodiment, the drain terminal electrode 22 includes a Ti layer 23, a Ni layer 24, a Pd layer 27, an Au layer 25, and an Ag layer 26 laminated in this order from the second main surface 4 side. It has a laminated structure. The Ti layer 23 is formed as an ohmic electrode that forms ohmic contact with the second main surface 4. The Ti layer 23 is directly connected to the second main surface 4 without the intervention of the silicide layer, the modified layer and the eutectic layer.

The Ni layer 24 covers the Ti layer 23. The Ni layer 24 preferably covers the entire area of the Ti layer 23. The Pd layer 27 covers the Ni layer 24. The Pd layer 27 preferably covers the entire area of the Ni layer 24. The Au layer 25 covers the Pd layer 27. The Au layer 25 preferably covers the entire area of the Pd layer 27. The Ag layer 26 covers the Au layer 25. The Ag layer 26 preferably covers the entire area of the Au layer 25.

FIG. 6G is a cross-sectional view corresponding to FIG. 6A, showing a drain terminal electrode 22 according to a seventh embodiment.
With reference to FIG. 6G, in this embodiment, the drain terminal electrode 22 has a laminated structure including a Ti layer 23, a Ni layer 24, a Pd layer 27, and an Au layer 25 laminated in this order from the second main surface 4 side. doing. The Ti layer 23 is formed as an ohmic electrode that forms ohmic contact with the second main surface 4. The Ti layer 23 is directly connected to the second main surface 4 without the intervention of the silicide layer, the modified layer and the eutectic layer.

The Ni layer 24 covers the Ti layer 23. The Ni layer 24 preferably covers the entire area of the Ti layer 23. The Pd layer 27 covers the Ni layer 24. The Pd layer 27 preferably covers the entire area of the Ni layer 24. The Au layer 25 covers the Pd layer 27. The Au layer 25 preferably covers the entire area of the Pd layer 27.
With reference to FIGS. 4 and 5, a p-shaped body region 30 is formed on the surface layer portion of the first main surface 3 in the active region 8. The concentration of p-type impurities in the body region 30 may be 1 × 10 ¹⁷ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less. The body region 30 defines the active region 8.

In the active region 8, a plurality of gate trenches 31 are formed on the first main surface 3. The plurality of gate trenches 31 are each formed in a band shape extending along the first direction X, and are formed at intervals along the second direction Y. The plurality of gate trenches 31 are formed in a striped shape extending along the first direction X as a whole in a plan view.
Each gate trench 31 is formed in the epitaxial layer 7 so as to penetrate the body region 30. Each gate trench 31 includes a side wall and a bottom wall. The side wall and bottom wall of each gate trench 31 are located in the epitaxial layer 7. The opening edge portion of each gate trench 31 is preferably formed in a curved shape toward the inside of the gate trench 31. As a result, the electric field concentration on the opening edge portion 32 of the gate trench 31 can be relaxed.

A gate insulating layer 35 and a gate electrode 36 are formed in each gate trench 31. In FIG. 4, the gate insulating layer 35 and the gate electrode 36 are shown by hatching.
The gate insulating layer 35 may contain at least one of silicon oxide and silicon nitride. The gate insulating layer 35 contains silicon oxide in this form. The gate insulating layer 35 is formed in a film shape along the inner wall of the gate trench 31, and partitions the recess space in the gate trench 31.

The gate insulating layer 35 includes a first region 35a, a second region 35b, and a third region 35c. The first region 35a is formed along the side wall of the gate trench 31. The second region 35b is formed along the bottom wall of the gate trench 31. The third region 35c is formed along the first main surface 3 of the semiconductor layer 2. The thickness T1 of the first region 35a is preferably less than the thickness T2 of the second region 35b and the thickness T3 of the third region 35c.

The gate electrode 36 is embedded in the gate trench 31 with the gate insulating layer 35 interposed therebetween. More specifically, the gate electrode 36 is embedded in the recess space partitioned by the gate insulating layer 35.
The gate electrode 36 may contain at least one of conductive polysilicon, tungsten, aluminum, copper, aluminum alloy and copper alloy. The gate electrode 36 is made of conductive polysilicon in this form.

In the surface layer portion of the body region 30, an n ⁺ type source region 34 is formed in a region along the side wall of the gate trench 31. The concentration of n-type impurities in the source region 34 may be 1.0 × 10 ¹⁸ cm ^-3 or more and 1.0 × 10 ²¹ cm ^-3 or less.
A plurality of source regions 34 are formed along the side wall on one side and the side wall on the other side of the gate trench 31 with respect to the second direction Y. The plurality of source regions 34 are each formed in a band shape extending along the first direction X. A portion of each source region 34 along the side wall of the gate trench 31 defines a MISFET channel in the body region 30 with the drift region 29.

A plurality of p ⁺ type contact regions 37 are formed on the surface layer portion of the body region 30. A plurality of p ⁺ type contact regions 37 are formed in regions between two source regions 34 adjacent to each other. The p-type impurity concentration in each contact region 37 may be 1.0 × 10 ¹⁸ cm ^-3 or more and 1.0 × 10 ²¹ cm ^-3 or less.
The plurality of contact regions 37 are each formed in a band shape extending along the first direction X. The plurality of contact regions 37 may be formed in a striped shape as a whole in a plan view.

The above-mentioned main surface insulating layer 10 is formed on the first main surface 3. The main surface insulating layer 10 includes a source contact hole 40. The source contact hole 40 exposes the source region 34 and the contact region 37 in the active region 8. The main surface insulating layer 10 includes a gate contact hole in a region (not shown). The gate contact hole exposes the gate electrode 36 in a region (not shown).

The above-mentioned gate terminal electrode 12 and source terminal electrode 13 are formed on the main surface insulating layer 10. The gate fingers 12B and 12C of the gate terminal electrode 12 are electrically connected to the gate electrode 36 via the gate contact hole. The source terminal electrode 13 is electrically connected to the source region 34 and the contact region 37 via the source contact hole 40.

As described above, according to the semiconductor device 1, since the second main surface 4 is roughened, the adhesion of the drain terminal electrode 22 to the second main surface 4 can be enhanced. As a result, peeling of the drain terminal electrode 22 from the second main surface 4 can be suppressed, so that the drain terminal electrode 22 can be directly connected to the second main surface 4 without going through the silicide layer. Further, the drain terminal electrode 22 can be directly connected to the second main surface 4 without going through the eutectic layer and the modified layer.

As a result, it is not necessary to heat the semiconductor layer 2 when the drain terminal electrode 22 is formed, so that the structure of the semiconductor layer 2 on the first main surface 3 side can be appropriately formed. As an example, carbonization of the organic insulating layer 18 due to the forming step of the drain terminal electrode 22 can be prevented. Therefore, it is possible to provide the semiconductor device 1 capable of suppressing the decrease in reliability caused by the drain terminal electrode 22.
Further, the semiconductor device 1 has a structure capable of forming the drain terminal electrode 22 after forming the organic insulating layer 18. It is also conceivable to form the organic insulating layer 18 after forming the drain terminal electrode 22.

However, in this case, the risk that the conductive material of the drain terminal electrode 22 adheres to the structure on the first main surface 3 side increases, which is not preferable. Further, the manufacturing process is complicated because the structure on the first main surface 3 side must be formed, the structure on the second main surface 4 side must be formed, and then the structure on the first main surface 3 side must be formed again. To become.
On the other hand, according to the semiconductor device 1, carbonization of the organic insulating layer 18 can be prevented, so that the drain terminal electrode 22 can be formed after the organic insulating layer 18 is formed. Further, since the structure on the first main surface 3 side can be protected by the organic insulating layer 18 during the forming process of the drain terminal electrode 22, there is a risk that the conductive material of the drain terminal electrode 22 adheres to the structure on the first main surface 3 side. Can be reduced. Further, the structure on the second main surface 4 side can be formed after all the structures on the first main surface 3 side have been created. Therefore, the reliability of the semiconductor device 1 can be improved, and at the same time, the complexity of the manufacturing process can be suppressed.

FIG. 7 is a plan view showing a wafer 41 used for manufacturing the semiconductor device shown in FIG.
With reference to FIG. 7, the wafer 41 is composed of a plate-shaped n ⁺ -type Si single crystal formed in a disk shape. The wafer 41 has a first wafer main surface 42 on one side, a second wafer main surface 43 on the other side, and a wafer side surface 44 connecting the first wafer main surface 42 and the second wafer main surface 43. ..

On the side surface 44 of the wafer, one or more (one in this embodiment) orientation flats 45 are formed as an example of a mark indicating the crystal orientation. The orientation flat 45 is a notch formed on the peripheral edge of the wafer 41.
A plurality of device forming regions 46 corresponding to the semiconductor devices 1 are set on the first wafer main surface 42. In this embodiment, the plurality of device forming regions 46 are arranged in a matrix along the first direction X and the second direction Y. The plurality of device forming regions 46 are partitioned by a dicing line 47. The semiconductor device 1 is cut out by cutting the wafer 41 along the peripheral edge (dicing line 47) of the plurality of device forming regions 46.

8A to 8J are cross-sectional views showing an example of a manufacturing method of the semiconductor device 1 shown in FIG. In FIGS. 8A to 8J, three device forming regions 46 are shown for convenience of explanation, and illustration of the other device forming regions 46 is omitted.
Wafer 41 is prepared with reference to FIG. 8A. Next, an n-type epitaxial layer 7 is formed on the first wafer main surface 42 by the epitaxial growth method. As a result, the wafer layer 48 including the wafer 41 and the epitaxial layer 7 is formed. The wafer layer 48 includes a first main surface 49 and a second main surface 50. The first main surface 49 and the second main surface 50 of the wafer layer 48 correspond to the first main surface 3 and the second main surface 4 of the semiconductor layer 2, respectively.

Next, with reference to FIG. 8B, the main portion 51 of the MISFET is formed on the surface layer portion of the epitaxial layer 7. The main part 51 of the MISFET is formed in the active region 8 of each device forming region 46.
Next, the main surface insulating layer 10 is formed on the first main surface 49. The main surface insulating layer 10 contains silicon oxide in this form. The main surface insulating layer 10 may be formed by a CVD (Chemical Vapor Deposition) method.

Next, referring to FIG. 8C, the gate terminal electrode 12 and the source terminal electrode 13 are formed on the main surface insulating layer 10. Here, the source terminal electrode 13 is shown in a simplified manner. The gate terminal electrode 12 and the source terminal electrode 13 are formed through a film forming step by a sputtering method and a patterning step by an etching method.
Next, with reference to FIG. 8D, the inorganic insulating layer 14 is formed on the main surface insulating layer 10. The inorganic insulating layer 14 contains silicon nitride in this form. The inorganic insulating layer 14 may be formed by a CVD method.

Next, referring to FIG. 8E, the organic insulating layer 18 is formed on the inorganic insulating layer 14. The organic insulating layer 18 collectively covers the active region 8 and the outer region 9. The organic insulating layer 18 may contain polybenzoxazole as an example of a positive type photosensitive resin.
Next, referring to FIG. 8F, the organic insulating layer 18 is selectively exposed and then developed. As a result, the pad opening 52 and the dicing street 53 are formed on the organic insulating layer 18. The pad opening 52 includes a gate pad opening 20 and a source pad opening 21. The dicing street 53 is formed along the dicing line 47.

Next, the unnecessary portion of the inorganic insulating layer 14 is removed. The unnecessary portion of the inorganic insulating layer 14 may be removed by an etching method via the organic insulating layer 18. As a result, the sub-pad opening 54 is formed in the inorganic insulating layer 14. The subpad opening 54 includes a gate subpad opening 16 and a source subpad opening 17. In addition, an inorganic insulating layer 14 that partitions a part of the dicing street 53 is formed.

Next, with reference to FIG. 8G, the second main surface 50 of the wafer layer 48 (the second wafer main surface 43 of the wafer 41) is ground. The second main surface 50 of the wafer layer 48 may be ground by a CMP (Chemical Mechanical Polishing) method. As a result, the wafer layer 48 is thinned to a desired thickness. Further, a plurality of grinding marks extending in a line are formed on the second main surface 50 of the wafer layer 48. The plurality of grinding marks may be formed in a line shape extending in an arc shape from the center of the wafer layer 48 toward the peripheral edge.

Next, referring to FIG. 8H, the second main surface 50 of the wafer layer 48 is roughened. The second main surface 50 is preferably roughened by an etching method. The second main surface 50 may be roughened to an arithmetic average roughness Ra of more than 0 nm and 1000 nm or less. The second main surface 50 is preferably roughened until the arithmetic mean roughness Ra is more than 0 nm and 400 nm or less.

Prior to the roughening step of the second main surface 50, the grinding marks may be removed from the second main surface 50. The step of removing the grinding marks may be a step of mirroring the second main surface 50. According to this step, in the roughening step of the second main surface 50, undesired etching (for example, expansion of the grinding mark) of the second main surface 50 starting from the grinding mark can be suppressed, so that the second main surface 50 can be suppressed. 50 can be appropriately roughened.

Further, in the next step of forming the drain terminal electrode 22, it is possible to prevent the drain terminal electrode 22 from entering the grinding mark. As a result, cracks in the second main surface 50 starting from the grinding marks can be suppressed, so that the drain terminal electrode 22 can be appropriately connected to the second main surface 50.
Next, with reference to FIG. 8I, the drain terminal electrode 22 is formed on the roughened second main surface 50. This step includes a step of forming the Ti layer 23, the Ni layer 24, the Au layer 25, and the Ag layer 26 in this order from the second main surface 50 side. The Ti layer 23, the Ni layer 24, the Au layer 25 and the Ag layer 26 are preferably formed by a vapor deposition method and / or a sputtering method.

The Ti layer 23 is directly connected to the roughened second main surface 50. The Ni layer 24 is directly connected to the Ti layer 23. The Au layer 25 is directly connected to the Ni layer 24. The Ag layer 26 is directly connected to the Au layer 25.
In the step of forming the drain terminal electrode 22, the silicide layer, the modified layer and the eutectic layer are not formed. Therefore, it is not necessary to heat the structure of the wafer layer 48 on the first main surface 49 side. As a result, carbonization of the organic insulating layer 18 due to the forming step of the drain terminal electrode 22 can be prevented.

Next, referring to FIG. 8J, the wafer layer 48 is cut along the dicing line 47. As a result, a plurality of semiconductor devices 1 are cut out from the wafer layer 48. The semiconductor device 1 is manufactured through the steps including the above.
9A-9I are cross-sectional views showing an example of a manufacturing process of the main part 51 of the MISFET. 9A-9I are cross-sectional views of a portion corresponding to FIG.

With reference to FIG. 9A, a wafer layer 48 including a wafer 41 and an epitaxial layer 7 is prepared. Next, a p-shaped body region 30 is formed on the surface layer portion of the first main surface 49. The body region 30 is formed by introducing p-type impurities into the first main surface 49. The p-type impurities in the body region 30 may be introduced into the surface layer portion of the first main surface 49 by an ion implantation method via an ion implantation mask (not shown).

Next, referring to FIG. 9B, an n ⁺ type source region 34 is formed on the surface layer portion of the body region 30. The source region 34 is formed by introducing an n-type impurity into the surface layer portion of the body region 30. The n-type impurities in the source region 34 may be introduced into the surface layer portion of the body region 30 by the ion implantation method via the ion implantation mask 56.
Next, with reference to FIG. 9C, a p ⁺ type contact region 37 is formed on the surface layer portion of the body region 30. The contact region 37 is formed by introducing p-type impurities into the surface layer portion of the body region 30. The p-type impurities in the contact region 37 may be introduced into the surface layer portion of the body region 30 by the ion implantation method via the ion implantation mask 57.

Next, with reference to FIG. 9D, a mask 58 having a predetermined pattern is formed on the first main surface 49. The mask 58 has a plurality of openings 59 that expose the area where the gate trench 31 should be formed.
Next, the unnecessary portion of the wafer layer 48 is removed. The unnecessary portion of the wafer layer 48 may be removed by an etching method via a mask 58. The etching method may be a wet etching method and / or a dry etching method. As a result, the gate trench 31 is formed. After that, the mask 58 is removed.

Next, with reference to FIG. 9E, the base insulating layer 60, which is the base of the gate insulating layer 35, is formed on the first main surface 49. The base insulating layer 60 may contain silicon oxide. The base insulating layer 60 may be formed by a thermal oxidation treatment method and / or a CVD method.
Next, with reference to FIG. 9F, the base conductor layer 61, which is the base of the gate electrode 36, is formed on the first main surface 49 of the wafer layer 48. The base conductor layer 61 contains conductive polysilicon. The base conductor layer 61 may be formed by a CVD method.

Next, referring to FIG. 9G, an unnecessary portion of the base conductor layer 61 is removed. Unnecessary portions of the base conductor layer 61 are removed until the base insulating layer 60 is exposed. The unnecessary portion of the base conductor layer 61 is removed by an etching method via a mask (not shown) having a predetermined pattern. The etching method may be a wet etching method and / or a dry etching method. As a result, the gate electrode 36 is formed.

Next, with reference to FIG. 9H, a main surface insulating layer 10 covering the gate electrode 36 is formed on the first main surface 49. The main surface insulating layer 10 contains silicon oxide. The main surface insulating layer 10 may be formed by a CVD method.
Next, a mask 62 having a predetermined pattern is formed on the main surface insulating layer 10. The mask 62 has a plurality of openings 63 that expose a region in which the plurality of source contact holes 40 should be formed.

Next, an unnecessary portion of the main surface insulating layer 10 and an unnecessary portion of the base insulating layer 60 are removed by an etching method via the mask 62. The unnecessary portion of the main surface insulating layer 10 and the unnecessary portion of the base insulating layer 60 are removed until the first main surface 49 is exposed. The etching method may be a wet etching method and / or a dry etching method. As a result, the gate insulating layer 35 is formed. In addition, the source contact hole 40 is formed.

Next, with reference to FIG. 9I, the gate terminal electrode 12 and the source terminal electrode 13 are formed on the main surface insulating layer 10. The gate terminal electrode 12 and the source terminal electrode 13 may be formed by a sputtering method. Through the steps including the above, the main part 51 of the MISFET is formed.
FIG. 10 is a perspective view showing the semiconductor package 64 in which the semiconductor device 1 is incorporated through the package body 65.

With reference to FIG. 10, the semiconductor package 64 is composed of a 3-terminal type TO-220 in this form. The semiconductor package 64 includes a semiconductor device 1, a pad portion 66, a heat sink portion 67, a plurality of (three in this form) lead terminals 68, a plurality of (three in this form) lead wires 69, and a package body 65.
The pad portion 66 includes a metal plate. The pad portion 66 may contain iron, gold, silver, copper, aluminum and the like. The pad portion 66 is formed in a rectangular shape in a plan view. The pad portion 66 has a plane area equal to or larger than the plane area of the semiconductor device 1.

The semiconductor device 1 is arranged on the pad portion 66 in a posture in which the drain terminal electrode 22 faces the pad portion 66. The conductive bonding material 70 is interposed in the region between the drain terminal electrode 22 and the pad portion 66. As a result, the drain terminal electrode 22 of the semiconductor device 1 is electrically connected to the pad portion 66 via the conductive bonding material 70.
The conductive bonding material 70 may be a metal paste or solder. The metal paste may be a conductive paste containing Au (gold), Ag (silver) or Cu (copper). The conductive bonding material 70 is preferably made of solder. The solder may be a lead-free type solder. The solder may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi or SnSbNi.

The heat sink portion 67 is connected to one side of the pad portion 66. In this form, the pad portion 66 and the heat sink portion 67 are formed of a single metal plate. A through hole 67a is formed in the heat sink portion 67. The through hole 67a is formed in a circular shape.
The plurality of lead terminals 68 are arranged along the side opposite to the heat sink portion 67 with respect to the pad portion 66. Each of the plurality of lead terminals 68 includes a metal plate. The lead terminal 68 may contain iron, gold, silver, copper, aluminum and the like.

The plurality of lead terminals 68 include a first lead terminal 68A, a second lead terminal 68B, and a third lead terminal 68C. The first lead terminal 68A, the second lead terminal 68B, and the third lead terminal 68C are arranged at intervals in the pad portion 66 along the side opposite to the heat sink portion 67.
The first lead terminal 68A, the second lead terminal 68B, and the third lead terminal 68C extend in a strip shape along a direction orthogonal to the arrangement direction thereof. The second lead terminal 68B and the third lead terminal 68C sandwich the first lead terminal 68A from both sides.

The plurality of lead wires 69 may be bonding wires or the like. The plurality of lead wires 69 include lead wire 69A, lead wire 69B, and lead wire 69C. The lead wire 69A is electrically connected to the first lead terminal 68A and the gate pad 12A of the semiconductor device 1. As a result, the first lead terminal 68A is electrically connected to the gate terminal electrode 12 of the semiconductor device 1 via the lead wire 69A.

The lead wire 69B is electrically connected to the second lead terminal 68B and the source terminal electrode 13. As a result, the second lead terminal 68B is electrically connected to the source terminal electrode 13 of the semiconductor device 1 via the lead wire 69B.
The lead wire 69C is electrically connected to the third lead terminal 68C and the pad portion 66. As a result, the third lead terminal 68C is electrically connected to the drain terminal electrode 22 of the semiconductor device 1 via the lead wire 69C. The third lead terminal 68C may be integrally formed with the pad portion 66.

The package body 65 contains a mold resin (sealing resin) having a filler. The package body 65 preferably contains an epoxy resin having a filler as an example of the mold resin. The package body 65 seals the semiconductor device 1, the pad portion 66, and the plurality of lead wires 69 so as to expose a part of the heat sink portion 67 and the plurality of lead terminals 68. The package body 65 is formed in a rectangular parallelepiped shape.

The semiconductor package 64 is not limited to TO-220. The semiconductor package 64 includes SOP (Small Outline Package), QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package) or SOJ (Small Outline J-leaded Package) or various forms similar thereto may be applied.

When the semiconductor device 1 is sealed by the package body 65, there is a problem that the semiconductor device 1 is damaged by the filler. This problem is called filler attack. Therefore, in the semiconductor device 1, the organic insulating layer 18 is formed on the first main surface 3 of the semiconductor layer 2.
As a result, the cushioning property of the organic insulating layer 18 can be utilized to alleviate the impact caused by the filler. As a result, the semiconductor layer 2, the gate terminal electrode 12, the source terminal electrode 13, and the like can be protected from the filler.

Further, according to the semiconductor device 1, carbonization (deterioration) of the organic insulating layer 18 is suppressed. As a result, the semiconductor layer 2, the gate terminal electrode 12, the source terminal electrode 13, and the like can be appropriately protected from the filler.
FIG. 11 is a perspective view showing the semiconductor device 101 according to the second embodiment of the present invention (hereinafter, simply referred to as “this embodiment”), wherein the cathode terminal electrode 119 according to the first embodiment is Shows the incorporated form. FIG. 12 is a plan view of the semiconductor device 101 of FIG. FIG. 13 is a cross-sectional view taken along the line XIII-XIII shown in FIG. FIG. 14A is an enlarged view of the region XIV shown in FIG.

The semiconductor device 101 is a rectifying device including an SBD (Schottky Barrier Diode) as an example of a functional device. With reference to FIGS. 11 to 13, the semiconductor device 101 includes a semiconductor layer 102 made of a Si single crystal. The semiconductor layer 102 is formed in the shape of a rectangular parallelepiped chip.
The semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, 105D connecting the first main surface 103 and the second main surface 104. ing. The first main surface 103 and the second main surface 104 are formed in a square shape (in this form, a square shape) in a plan view (hereinafter, simply referred to as "plan view") viewed from their normal direction Z. ..

The first main surface 103 is a device forming surface. The first main surface 103 is a non-mounting surface. The second main surface 104 is a mounting surface. When the semiconductor device 101 is mounted on the object to be connected, the semiconductor layer 102 is mounted on the object to be connected with the second main surface 104 facing each other. Examples of the connection object include electronic components, lead frames, circuit boards, and the like.
The second main surface 104 is composed of a roughened surface. The second main surface 104 is roughened by irregularly formed unevenness (Unevenness). It is preferable that the entire area of the second main surface 104 is roughened. It is particularly preferable that the second main surface 104 is a roughened surface having no grinding marks (more specifically, grinding marks extending in a line shape). More specifically, the second main surface 104 is a crystal plane made of a Si single crystal. Therefore, the second main surface 104 is composed of a crystal roughened surface in which a Si single crystal is roughened.

The arithmetic mean roughness Ra of the second main surface 104 may exceed 0 nm and be 1000 nm or less. The arithmetic mean roughness Ra may be more than 0 nm and 50 nm or less, 50 nm or more and 100 nm or less, 100 nm or more and 200 nm or less, 200 nm or more and 400 nm or less, 400 nm or more and 600 nm or less, 600 nm or more and 800 nm or less, 800 nm or more and 1000 nm or less. The arithmetic average roughness Ra is preferably more than 0 nm and 400 nm or less.

The side surface 105A and the side surface 105C extend along the first direction X and face each other in the second direction Y intersecting the first direction X. The side surface 105B and the side surface 105D extend along the second direction Y and face each other in the first direction X. The second direction Y is, more specifically, a direction orthogonal to the first direction X. The side surfaces 105A to 105D extend in a plane along the normal direction of the first main surface 103 and the second main surface 104, respectively.

In this form, the semiconductor layer 102 has a laminated structure including an n ⁺ type semiconductor substrate 106 and an n-type epitaxial layer 107. The second main surface 104 is formed by the semiconductor substrate 106. The first main surface 103 is formed by the epitaxial layer 107. The side surfaces 105A to 105D are formed by the semiconductor substrate 106 and the epitaxial layer 107.

The n-type impurity concentration of the epitaxial layer 107 is less than the n-type impurity concentration of the semiconductor substrate 106. The concentration of n-type impurities in the semiconductor substrate 106 may be 1.0 × 10 ¹⁸ cm ^-3 or more and 1.0 × 10 ²¹ cm ^-3 or less. The concentration of n-type impurities in the epitaxial layer 107 may be 1.0 × 10 ¹⁵ cm ^-3 or more and 1.0 × 10 ¹⁸ cm ^-3 or less.
The semiconductor layer 102 includes an active region 108 and an outer region 109. The active region 108 is the region where the main part of the SBD is formed. The active region 108 is formed in the central portion of the semiconductor layer 102 at intervals inward from the side surfaces 105A to 105D in a plan view. The active region 108 may be formed in a quadrangular shape having four sides parallel to the side surfaces 105A to 105D in a plan view.

The outer region 109 is a region outside the active region 108. The outer region 109 is formed in the region between the sides 105A-105D and the periphery of the active region 108. The outer region 109 is formed in an annular shape (endless in this form) surrounding the active region 108 in a plan view.
A main surface insulating layer 110 is formed on the first main surface 103. The main surface insulating layer 110 covers the active region 108 and the outer region 109. The main surface insulating layer 110 includes at least one of a silicon oxide layer and a silicon nitride layer.

The main surface insulating layer 110 may have a laminated structure including a silicon oxide layer and a silicon nitride layer in any order. In this form, the main surface insulating layer 110 has a single-layer structure composed of a silicon oxide layer.
The main surface insulating layer 110 has insulating side surfaces 111A, 111B, 111C, 111D. The insulating side surfaces 111A to 111D are connected to the side surfaces 105A to 105D of the semiconductor layer 102. The insulating side surfaces 111A to 111D are formed flush with the side surfaces 105A to 105D.

An anode terminal electrode 112 as a first terminal electrode is formed on the main surface insulating layer 110. The anode terminal electrode 112 is formed in the central portion of the semiconductor layer 102 at an inward distance from the side surfaces 105A to 105D in a plan view. The anode terminal electrode 112 may be formed in a quadrangular shape having four sides parallel to the side surfaces 105A to 105D of the semiconductor layer 102 in a plan view.

An inorganic insulating layer 113 is formed on the main surface insulating layer 110. The inorganic insulating layer 113 is also referred to as a passivation layer. The inorganic insulating layer 113 includes at least one of a silicon oxide layer and a silicon nitride layer.
The inorganic insulating layer 113 may have a laminated structure including a silicon oxide layer and a silicon nitride layer in any order. The inorganic insulating layer 113 preferably contains an insulating material different from that of the main surface insulating layer 110. In this form, the inorganic insulating layer 113 has a single-layer structure composed of a silicon nitride layer.

The inorganic insulating layer 113 includes side surfaces 114A, 114B, 114C, 114D. The side surfaces 114A to 114D of the inorganic insulating layer 113 are formed inwardly spaced from the side surfaces 105A to 105D of the semiconductor layer 102 in a plan view. The side surfaces 114A to 114D of the inorganic insulating layer 113 expose the peripheral edge portion of the first main surface 103 in a plan view. More specifically, the side surfaces 114A to 114D of the inorganic insulating layer 113 expose the main surface insulating layer 110.

The inorganic insulating layer 113 includes a sub-pad opening 115 that exposes a part of the anode terminal electrode 112. The sub-pad opening 115 is formed in a quadrangular shape having four sides parallel to the side surfaces 105A to 105D in a plan view.
An organic insulating layer 116 is formed on the inorganic insulating layer 113. The inorganic insulating layer 113 and the organic insulating layer 116 form one insulating laminated structure (insulating layer). In FIG. 12, the organic insulating layer 116 is shown by hatching.

The organic insulating layer 116 may contain a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The organic insulating layer 116 preferably contains at least one of polybenzoxazole, polyimide and polyamide. In this form, the organic insulating layer 116 contains polybenzoxazole as an example of a positive type photosensitive resin.

The organic insulating layer 116 has a non-burnt outer surface. The organic insulating layer 116 has a carbide-free outer surface. The organic insulating layer 116 does not contain carbides. The organic insulating layer 116 includes side surfaces 117A, 117B, 117C, 117D. The side surfaces 117A to 117D of the organic insulating layer 116 are formed at intervals inward from the side surfaces 105A to 105D in a plan view.

The side surfaces 117A to 117D of the organic insulating layer 116 expose the peripheral edge portion of the semiconductor layer 102 in a plan view. The side surfaces 117A to 117D of the organic insulating layer 116 expose the main surface insulating layer 110 together with the side surfaces 114A to 114D of the inorganic insulating layer 113. In this form, the side surfaces 117A to 117D of the organic insulating layer 116 are formed flush with the side surfaces 114A to 114D of the inorganic insulating layer 113.

The organic insulating layer 116 includes a pad opening 118 that exposes a portion of the anode terminal electrode 112. The pad opening 118 may be formed in a quadrangular shape having four sides parallel to the side surfaces 105A to 105D in a plan view.
The pad opening 118 communicates with the sub pad opening 115. The inner wall of the pad opening 118 is formed flush with the inner wall of the sub pad opening 115. The inner wall of the pad opening 118 may be located on the side surface 105A to 105D side with respect to the inner wall of the sub pad opening 115. The inner wall of the pad opening 118 may be located inward with respect to the inner wall of the sub pad opening 115. The organic insulating layer 116 may cover the inner wall of the subpad opening 115.

The side surfaces 117A to 117D of the organic insulating layer 116 partition the dicing street 143 from the side surfaces 105A to 105D of the semiconductor layer 102. In this form, the side surfaces 114A to 114D of the inorganic insulating layer 113 also partition the dicing street 143 between the side surfaces 105A to 105D of the semiconductor layer 102.
According to the dicing street 143, it is not necessary to physically cut the organic insulating layer 116 and the inorganic insulating layer 113. As a result, the semiconductor device 101 can be smoothly cut out from the wafer, and at the same time, peeling and deterioration of the organic insulating layer 116 and the inorganic insulating layer 113 can be suppressed. As a result, the semiconductor layer 102, the anode terminal electrode 112, and the like can be appropriately protected by the organic insulating layer 116 and the inorganic insulating layer 113.

The width of the dicing street 143 may be 1 μm or more and 25 μm or less. The width of the dicing street 143 is the width in the direction orthogonal to the direction in which the dicing street 143 extends. The width of the dicing street 143 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less.

The side surfaces 114A to 114D of the inorganic insulating layer 113 do not necessarily have to partition the dicing street 143. The side surfaces 114A to 114D of the inorganic insulating layer 113 may be formed flush with the side surfaces 105A to 105D of the semiconductor layer 102.
The thickness of the organic insulating layer 116 may be 1 μm or more and 20 μm or less.
A cathode terminal electrode 119 as a second terminal electrode is formed on the second main surface 104 of the semiconductor layer 102. The cathode terminal electrode 119 forms ohmic contact with the second main surface 104.

The cathode terminal electrode 119 is directly connected to the roughened second main surface 104. More specifically, the cathode terminal electrode 119 is directly connected to the crystal roughened surface of the second main surface 104.
More specifically, the cathode terminal electrode 119 is directly connected to the second main surface 104 without forming a silicide layer containing silicide in the main configuration. The cathode terminal electrode 119 does not include a region in which a material containing silicide as a main component is formed in a layer.

Further, the cathode terminal electrode 119 directly on the second main surface 104 without forming a modified layer in which the crystal state of the second main surface 104 is modified to other properties with the second main surface 104. It is connected. Examples of the modified layer include a Si melt rehardened layer, a Si polycrystalline layer, and a Si amorphous layer.
Further, the cathode terminal electrode 119 is directly connected to the second main surface 104 without forming a eutectic layer containing a eutectic substance in the main configuration. The cathode terminal electrode 119 does not include a region in which a material containing a eutectic as a main component is formed in a layer.

That is, the cathode terminal electrode 119 is directly connected to the roughened second main surface 104 without the intervention of the silicide layer, the modified layer, and the eutectic layer.
With reference to FIG. 14A, the cathode terminal electrode 119 has a laminated structure including a plurality of electrode layers laminated on the second main surface 104. In this embodiment, the cathode terminal electrode 119 has a laminated structure including a Ti layer 120, a Ni layer 121, an Au layer 122, and an Ag layer 123 laminated in this order from the second main surface 104 side.

The Ti layer 120 is directly connected to the roughened second main surface 104. The Ti layer 120 preferably covers the entire area of the second main surface 104. The Ti layer 120 is formed as an ohmic electrode that forms ohmic contact with the second main surface 104. The Ti layer 120 is directly connected to the second main surface 104 without the intervention of the silicide layer, the modified layer and the eutectic layer.

The Ni layer 121 covers the Ti layer 120. The Ni layer 121 preferably covers the entire area of the Ti layer 120. The Au layer 122 covers the Ni layer 121. The Au layer 122 preferably covers the entire area of the Ni layer 121. The Ag layer 123 covers the Au layer 122. The Ag layer 123 preferably covers the entire area of the Au layer 122.

The cathode terminal electrode 119 may include at least one of the Ti layer 120, the Ni layer 121, the Au layer 122, and the Ag layer 123. Hereinafter, other examples of the cathode terminal electrode 119 will be shown.
FIG. 14B is a cross-sectional view corresponding to FIG. 14A, showing a cathode terminal electrode 119 according to a second embodiment.

With reference to FIG. 14B, the cathode terminal electrode 119 has a single layer structure composed of a Ti layer 120 formed on the second main surface 104 in this form. The Ti layer 120 is formed as an ohmic electrode that forms ohmic contact with the second main surface 104. The Ti layer 120 is directly connected to the second main surface 104 without the intervention of the silicide layer, the modified layer and the eutectic layer.

FIG. 14C is a cross-sectional view corresponding to FIG. 14A, showing a cathode terminal electrode 119 according to a third embodiment.
With reference to FIG. 14C, the cathode terminal electrode 119 has, in this form, a monolayer structure composed of Au layers 122 formed on the second main surface 104. The Au layer 122 is formed as an ohmic electrode that forms ohmic contact with the second main surface 104. The Au layer 122 is directly connected to the second main surface 104 without the intervention of the silicide layer, the modified layer and the eutectic layer.

FIG. 14D is a cross-sectional view corresponding to FIG. 14A, showing a cathode terminal electrode 119 according to a fourth embodiment.
With reference to FIG. 14D, in this form, the cathode terminal electrode 119 has a laminated structure including Au layer 122 and Ag layer 123 laminated in this order from the second main surface 104 side. The Au layer 122 is formed as an ohmic electrode that forms ohmic contact with the second main surface 104.

The Au layer 122 is directly connected to the second main surface 104 without the intervention of the silicide layer, the modified layer and the eutectic layer. The Ag layer 123 covers the Au layer 122. The Ag layer 123 preferably covers the entire area of the Au layer 122.
FIG. 14E is a cross-sectional view corresponding to FIG. 14A, showing a cathode terminal electrode 119 according to a fifth embodiment.

With reference to FIG. 14E, in this embodiment, the cathode terminal electrode 119 has a laminated structure including a Ti layer 120, a Ni layer 121, and an Au layer 122 laminated in this order from the second main surface 104 side. The Ti layer 120 is formed as an ohmic electrode that forms ohmic contact with the second main surface 104. The Ti layer 120 is directly connected to the second main surface 104 without the intervention of the silicide layer, the modified layer and the eutectic layer.

The Ni layer 121 covers the Ti layer 120. The Ni layer 121 preferably covers the entire area of the Ti layer 120. The Au layer 122 covers the Ni layer 121. The Au layer 122 preferably covers the entire area of the Ni layer 121.
FIG. 14F is a cross-sectional view corresponding to FIG. 14A, showing a cathode terminal electrode 119 according to a sixth embodiment.

With reference to FIG. 14F, in this embodiment, the cathode terminal electrode 119 includes a Ti layer 120, a Ni layer 121, a Pd layer 124, an Au layer 122, and an Ag layer 123 laminated in this order from the second main surface 104 side. It has a laminated structure. The Ti layer 120 is formed as an ohmic electrode that forms ohmic contact with the second main surface 104. The Ti layer 120 is directly connected to the second main surface 104 without the intervention of the silicide layer, the modified layer and the eutectic layer.

The Ni layer 121 covers the Ti layer 120. The Ni layer 121 preferably covers the entire area of the Ti layer 120. The Pd layer 124 covers the Ni layer 121. The Pd layer 124 preferably covers the entire area of the Ni layer 121. The Au layer 122 covers the Pd layer 124. The Au layer 122 preferably covers the entire area of the Pd layer 124. The Ag layer 123 covers the Au layer 122. The Ag layer 123 preferably covers the entire area of the Au layer 122.

FIG. 14G is a cross-sectional view corresponding to FIG. 14A, showing a cathode terminal electrode 119 according to a seventh embodiment.
With reference to FIG. 14G, in this embodiment, the cathode terminal electrode 119 has a laminated structure including a Ti layer 120, a Ni layer 121, a Pd layer 124, and an Au layer 122 laminated in this order from the second main surface 104 side. doing. The Ti layer 120 is formed as an ohmic electrode that forms ohmic contact with the second main surface 104. The Ti layer 120 is directly connected to the second main surface 104 without the intervention of the silicide layer, the modified layer and the eutectic layer.

The Ni layer 121 covers the Ti layer 120. The Ni layer 121 preferably covers the entire area of the Ti layer 120. The Pd layer 124 covers the Ni layer 121. The Pd layer 124 preferably covers the entire area of the Ni layer 121. The Au layer 122 covers the Pd layer 124. The Au layer 122 preferably covers the entire area of the Pd layer 124.

With reference to FIG. 13, an n-type diode region 125 is formed on the surface layer portion of the first main surface 103 in the active region 108. In this form, the diode region 125 is formed in the central portion of the first main surface 103. The diode region 125 may be formed in a quadrangular shape having four sides parallel to the side surfaces 105A to 105D in a plan view.
In this form, the diode region 125 is formed by utilizing a part of the epitaxial layer 107. The diode region 125 may be formed by introducing an n-type impurity into the surface layer portion of the epitaxial layer 107.

In the outer region 109, a p ⁺ type guard region 126 is formed on the surface layer portion of the first main surface 103. The p-type impurities in the guard region 126 may or may not be activated. The guard region 126 is formed in a strip shape extending along the diode region 125 in a plan view.
More specifically, the guard region 126 is formed in an annular shape (more specifically, an endless shape) surrounding the diode region 125 in a plan view. As a result, the guard region 126 is formed as a guard ring region. The active region 108 and the diode region 125 are defined by a guard region 126.

The above-mentioned main surface insulating layer 110 is formed on the first main surface 103. The main surface insulating layer 110 includes a diode opening 127 that exposes the diode region 125. The diode opening 127 also exposes the inner peripheral edge of the guard region 126. The diode opening 127 may be formed in a quadrangular shape having four sides parallel to the side surfaces 105A to 105D in a plan view.

The above-mentioned anode terminal electrode 112 is formed on the main surface insulating layer 110. The anode terminal electrode 112 enters the diode opening 127 from above the main surface insulating layer 110. The anode terminal electrode 112 is electrically connected to the diode region 125 and the guard region 126 within the diode opening 127.
More specifically, the anode terminal electrode 112 forms a Schottky junction with the diode region 125. As a result, an SBD having the anode terminal electrode 112 as the anode and the diode region 125 as the cathode is formed.

As described above, according to the semiconductor device 101, since the second main surface 104 is roughened, the adhesion of the cathode terminal electrode 119 to the second main surface 104 can be enhanced. As a result, peeling of the cathode terminal electrode 119 from the second main surface 104 can be suppressed, so that the cathode terminal electrode 119 can be directly connected to the second main surface 104 without going through the silicide layer. Further, the cathode terminal electrode 119 can be directly connected to the second main surface 104 without going through the eutectic layer and the modified layer.

As a result, it is not necessary to heat the semiconductor layer 102 when the cathode terminal electrode 119 is formed, so that the structure of the semiconductor layer 102 on the first main surface 103 side can be appropriately formed. As an example, carbonization of the organic insulating layer 116 due to the forming step of the cathode terminal electrode 119 can be prevented. Therefore, it is possible to provide the semiconductor device 101 capable of suppressing the decrease in reliability caused by the cathode terminal electrode 119.

Further, the semiconductor device 101 has a structure capable of forming the cathode terminal electrode 119 after forming the organic insulating layer 116. It is also conceivable to form the organic insulating layer 116 after forming the cathode terminal electrode 119.
However, in this case, it cannot be said that it is preferable because the risk that the conductive material of the cathode terminal electrode 119 adheres to the structure on the first main surface 103 side increases. Further, since the structure on the first main surface 103 side must be formed, the structure on the second main surface 104 side must be formed, and then the structure on the first main surface 103 side must be formed again, which complicates the manufacturing process. To become.

On the other hand, according to the semiconductor device 101, since carbonization of the organic insulating layer 116 can be prevented, the cathode terminal electrode 119 can be formed after the organic insulating layer 116 is formed. Further, since the structure on the first main surface 103 side can be protected by the organic insulating layer 116 during the forming process of the cathode terminal electrode 119, there is a risk that the conductive material of the cathode terminal electrode 119 adheres to the structure on the first main surface 103 side. Can be reduced. Further, the structure on the second main surface 104 side can be formed after all the structures on the first main surface 103 side have been created. Therefore, the reliability of the semiconductor device 101 can be improved, and at the same time, the complexity of the manufacturing process can be suppressed.

FIG. 15 is a plan view showing a wafer 128 used for manufacturing the semiconductor device shown in FIG.
With reference to FIG. 15, the wafer 128 is composed of a plate-shaped n ⁺ -type Si single crystal formed in a disk shape. The wafer 128 has a first wafer main surface 129 on one side, a second wafer main surface 130 on the other side, and a wafer side surface 131 connecting the first wafer main surface 129 and the second wafer main surface 130. ..

On the wafer side surface 131 of the wafer 128, one or more (one in this embodiment) orientation flats 132 are formed as an example of a mark indicating the crystal orientation. The orientation flat 132 is a notch formed on the peripheral edge of the wafer 128.
A plurality of device forming regions 133 corresponding to the semiconductor devices 101 are set on the first wafer main surface 129. In this embodiment, the plurality of device forming regions 133 are arranged in a matrix along the first direction X and the second direction Y. The plurality of device forming regions 133 are partitioned by the dicing line 134. The semiconductor device 101 is cut out by cutting the wafer 128 along the peripheral edge (dicing line 134) of the plurality of device forming regions 133.

16A to 16M are cross-sectional views showing an example of a manufacturing method of the semiconductor device 101 shown in FIG. In FIGS. 16A to 16M, for convenience of explanation, only three device forming regions 133 are shown, and illustration of the other device forming regions 133 is omitted.
Wafer 128 is prepared with reference to FIG. 16A. Next, an n-type epitaxial layer 107 is formed on the first wafer main surface 129 by the epitaxial growth method. As a result, the wafer layer 135 including the wafer 128 and the epitaxial layer 107 is formed. The wafer layer 135 includes a first main surface 136 and a second main surface 137. The first main surface 136 and the second main surface 137 of the wafer layer 135 correspond to the first main surface 103 and the second main surface 104 of the semiconductor layer 102, respectively.

Next, with reference to FIG. 16B, a diode region 125 is set on the first main surface 136, and a p ⁺ type guard region 126 along the periphery of the diode region 125 is formed.
More specifically, the guard region 126 is formed on the surface layer portion of the epitaxial layer 107. The guard region 126 is formed by introducing p-type impurities into the first main surface 136. The p-type impurities in the guard region 126 may be introduced into the surface layer portion of the first main surface 136 by an ion implantation method via an ion implantation mask (not shown).

The diode region 125 may be formed by selectively introducing an n-type impurity into the surface layer portion of the first main surface 136 via an ion implantation mask (not shown).
Next, with reference to FIG. 16C, the main surface insulating layer 110 is formed on the first main surface 136. The main surface insulating layer 110 contains silicon oxide. The main surface insulating layer 110 may be formed by a thermal oxidation treatment method and / or a CVD method.

Next, with reference to FIG. 16D, a mask 138 having a predetermined pattern is formed on the main surface insulating layer 110. The mask 138 has a plurality of openings 139. The plurality of openings 139 each expose a region in the main surface insulating layer 110 where the diode opening 127 should be formed.
Next, an unnecessary portion of the main surface insulating layer 110 is removed by an etching method via a mask 138. The etching method may be a wet etching method and / or a dry etching method. As a result, the diode opening 127 is formed in the main surface insulating layer 110. After forming the diode opening 127, the mask 138 is removed.

Next, with reference to FIG. 16E, the base electrode layer 140, which is the base of the anode terminal electrode 112, is formed on the first main surface 136. The base electrode layer 140 is formed over the entire area of the first main surface 136 and covers the main surface insulating layer 110. The base electrode layer 140 may be formed by a vapor deposition method and / or a sputtering method.
Next, with reference to FIG. 16F, a mask 141 having a predetermined pattern is formed on the base electrode layer 140. The mask 141 has an opening 142 in the base electrode layer 140 that exposes a region other than the region where the anode terminal electrode 112 should be formed.

Next, an unnecessary portion of the base electrode layer 140 is removed by an etching method via the mask 141. The etching method may be a wet etching method and / or a dry etching method. As a result, the base electrode layer 140 is divided into a plurality of anode terminal electrodes 112. After forming the anode terminal electrode 112, the mask 141 is removed.
Next, with reference to FIG. 16G, the inorganic insulating layer 113 is formed on the first main surface 136. The inorganic insulating layer 113 contains silicon nitride. The inorganic insulating layer 113 may be formed by a CVD method.

Next, referring to FIG. 16H, the organic insulating layer 116 is applied on the inorganic insulating layer 113. The organic insulating layer 116 collectively covers the active region 108 and the outer region 109. The organic insulating layer 116 may contain polybenzoxazole as an example of a positive type photosensitive resin.
Next, with reference to FIG. 16I, the organic insulating layer 116 is selectively exposed and then developed. As a result, the pad opening 118 and the dicing street 143 are formed in the organic insulating layer 116. The dicing street 143 is formed along the dicing line 134.

Next, the unnecessary portion of the inorganic insulating layer 113 is removed. The unnecessary portion of the inorganic insulating layer 113 may be removed by an etching method via the organic insulating layer 116. The etching method may be a wet etching method and / or a dry etching method. As a result, the sub-pad opening 115 is formed in the inorganic insulating layer 113. In addition, an inorganic insulating layer 113 that partitions a part of the dicing street 143 is formed.

Next, with reference to FIG. 16J, the second main surface 137 of the wafer layer 135 (second wafer main surface 130 of the wafer 128) is ground. The second main surface 137 of the wafer layer 135 may be ground by a CMP (Chemical Mechanical Polishing) method. As a result, the wafer layer 135 is thinned to a desired thickness. Further, a plurality of grinding marks extending in a line shape are formed on the second main surface 137 of the wafer layer 135. The plurality of grinding marks may be formed in a line shape extending in an arc shape from the center of the wafer layer 135 toward the peripheral edge.

Next, with reference to FIG. 16K, the second main surface 137 is roughened. The second main surface 137 is roughened by an etching method. The second main surface 137 may be roughened to an arithmetic average roughness Ra of more than 0 nm and 1000 nm or less. The second main surface 137 is preferably roughened until the arithmetic average roughness Ra exceeds 0 nm and becomes 400 nm or less.
Grinding marks may be removed from the second main surface 137 prior to the roughening step of the second main surface 137. The step of removing the grinding marks may be a step of mirroring the second main surface 137. According to this step, in the roughening step of the second main surface 137, undesired etching (for example, expansion of the grinding mark) of the second main surface 137 starting from the grinding mark can be suppressed, so that the second main surface can be suppressed. The 137 can be appropriately roughened.

Further, in the next step of forming the cathode terminal electrode 119, it is possible to prevent the cathode terminal electrode 119 from entering the grinding mark. As a result, cracks on the second main surface 137 starting from the grinding marks can be suppressed, so that the cathode terminal electrode 119 can be appropriately connected to the second main surface 137.
Next, with reference to FIG. 16L, the cathode terminal electrode 119 is formed on the roughened second main surface 137. This step includes a step of forming the Ti layer 120, the Ni layer 121, the Au layer 122, and the Ag layer 123 from the second main surface 137 side in this order. The Ti layer 120, the Ni layer 121, the Au layer 122 and the Ag layer 123 are preferably formed by a vapor deposition method and / or a sputtering method.

The Ti layer 120 is directly connected to the second main surface 137 of the roughened wafer layer 135. The Ni layer 121 is directly connected to the Ti layer 120. The Au layer 122 is directly connected to the Ni layer 121. The Ag layer 123 is directly connected to the Au layer 122.
In the step of forming the cathode terminal electrode 119, the silicide layer, the modified layer and the eutectic layer are not formed. Therefore, it is not necessary to heat the structure of the wafer layer 135 on the 136 side of the first main surface. As a result, carbonization of the organic insulating layer 116 due to the forming step of the cathode terminal electrode 119 can be prevented.

Next, referring to FIG. 16M, the wafer layer 135 is cut along the peripheral edge (dicing line 134) of the plurality of device forming regions 133, and the plurality of semiconductor devices 101 are cut out from the wafer layer 135. The semiconductor device 101 is manufactured through the steps including the above.
FIG. 17 is a perspective view showing the semiconductor package 144 in which the semiconductor device 101 is incorporated through the package body 145.

With reference to FIG. 17, the semiconductor package 144 is composed of a two-terminal type TO-220 in this form. The semiconductor package 144 includes a semiconductor device 101, a pad portion 146, a heat sink portion 147, a plurality of (two in this form) lead terminals 148, a plurality of (two in this form) lead wires 149, and a package body 145.
The pad portion 146 includes a metal plate. The pad portion 146 may contain iron, gold, silver, copper, aluminum and the like. The pad portion 146 is formed in a rectangular shape in a plan view. The pad portion 146 has a plane area equal to or larger than the plane area of the semiconductor device 101.

The semiconductor device 101 is arranged on the pad portion 146 in a posture in which the cathode terminal electrode 119 faces the pad portion 146. The conductive bonding material 150 is interposed between the cathode terminal electrode 119 and the pad portion 146. As a result, the cathode terminal electrode 119 of the semiconductor device 101 is electrically connected to the pad portion 146 via the conductive bonding material 150.
The conductive bonding material 150 may be a metal paste or solder. The metal paste may be a conductive paste containing Au (gold), Ag (silver) or Cu (copper). The conductive bonding material 150 is preferably made of solder. The solder may be a lead-free type solder. The solder may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi or SnSbNi.

The heat sink portion 147 is connected to one side of the pad portion 146. In this form, the pad portion 146 and the heat sink portion 147 are formed of a single metal plate. A through hole 147a is formed in the heat sink portion 147. The through hole 147a is formed in a circular shape.
The plurality of lead terminals 148 are arranged along the side opposite to the heat sink portion 147 with respect to the pad portion 146. Each of the plurality of lead terminals 148 includes a metal plate. The lead terminal 148 may contain iron, gold, silver, copper, aluminum and the like.

The plurality of lead terminals 148 include a first lead terminal 148A and a second lead terminal 148B. The first lead terminal 148A and the second lead terminal 148B are arranged at intervals in the pad portion 146 along the side opposite to the heat sink portion 147.
The first lead terminal 148A and the second lead terminal 148B extend in a strip shape along a direction orthogonal to their arrangement direction.

The plurality of lead wires 149 may be bonding wires or the like. The plurality of lead wires 149 include lead wire 149A and lead wire 149B. The lead wire 149A is electrically connected to the first lead terminal 148A and the anode terminal electrode 112 of the semiconductor device 101. As a result, the first lead terminal 148A is electrically connected to the anode terminal electrode 112 of the semiconductor device 101 via the lead wire 149A.

The lead wire 149B is electrically connected to the second lead terminal 148B and the pad portion 146. As a result, the second lead terminal 148B is electrically connected to the cathode terminal electrode 119 of the semiconductor device 101 via the lead wire 149B. The second lead terminal 148B may be integrally formed with the pad portion 146.
The package body 145 contains a mold resin (sealing resin) having a filler. The package body 145 preferably contains an epoxy resin having a filler as an example of the mold resin. The package body 145 seals the semiconductor device 101, the pad portion 146, and the plurality of lead wires 149 so as to expose a part of the heat sink portion 147 and the plurality of lead terminals 148. The package body 145 is formed in a rectangular parallelepiped shape.

The semiconductor package 144 is not limited to TO-220. The semiconductor package 144 includes SOP (Small Outline Package), QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package) or SOJ (Small Outline J-leaded Package) or various forms similar thereto may be applied.

When the semiconductor device 101 is sealed by the package body 145, there is a problem that the semiconductor device 101 is damaged by the filler. This problem is called filler attack. Therefore, in the semiconductor device 101, the organic insulating layer 116 is formed on the first main surface 103 of the semiconductor layer 102.
Thereby, the cushioning property of the organic insulating layer 116 can be utilized to alleviate the impact caused by the filler. As a result, the semiconductor layer 102, the anode terminal electrode 112, and the like can be protected from the filler.

Further, according to the semiconductor device 101, carbonization (deterioration) of the organic insulating layer 116 due to the formation of the cathode terminal electrode 119 is prevented. As a result, the semiconductor layer 102, the anode terminal electrode 112, and the like can be appropriately protected from the filler.
The present invention can also be implemented in still other forms.
In each of the above-described embodiments, an example in which the semiconductor layers 2, 102 have a laminated structure including the semiconductor substrates 6, 106 and the epitaxial layers 7, 107 has been described. However, the semiconductor layers 2 and 102 may have a single-layer structure composed of the semiconductor substrates 6 and 106.

In each of the above-described embodiments, an example in which the semiconductor layers 2 and 102 made of a Si single crystal are adopted has been described. However, the semiconductor layers 2, 102 made of a SiC single crystal may be adopted instead of the Si single crystal. Further, the semiconductor layers 2 and 102 made of a single crystal of a compound semiconductor may be adopted instead of the Si single crystal. The single crystal of the compound semiconductor may be a single crystal of a nitride semiconductor (for example, a GaN single crystal).

In the first embodiment described above, the p ⁺ type semiconductor substrate 6 may be adopted instead of the n ⁺ type semiconductor substrate 6. According to this structure, an IGBT (Insulated Gate Bipolar Transistor) can be provided instead of the MISFET. In this case, in each of the above-described embodiments, the "source" of the MISFET is read as the "emitter" of the IGBT, and the "drain" of the MISFET is read as the "collector" of the IGBT.

In the second embodiment described above, an example in which an SBD is formed as an example of a diode has been described. However, a p-type diode region 125 may be formed instead of the n-type diode region 125. In this case, a pn junction diode can be provided instead of the SBD.
In each of the above-described embodiments, a structure in which the conductive type of each semiconductor portion is inverted may be adopted. That is, the p-type portion may be n-type and the n-type portion may be p-type.

In addition, various design changes can be made within the scope of the matters described in the claims.

1 Semiconductor device 2 Semiconductor layer 3 First main surface 4 Second main surface 12 Gate terminal electrode (first terminal electrode)
13 Source terminal electrode (1st terminal electrode)
18 Organic insulation layer 22 Drain terminal electrode (second terminal electrode)
23 Ti layer 24 Ni layer 25 Au layer 26 Ag layer 31 Gate trench (trench)
35 Gate insulating layer (insulating layer)
36 Gate electrode 48 Wafer layer 49 First main surface 50 Second main surface 64 Semiconductor package 65 Package body 66 Pad portion 68 Lead terminal 69 Lead wire 101 Semiconductor device 102 Semiconductor layer 103 First main surface 104 Second main surface 112 Anode terminal electrode (1st terminal electrode)
119 Cathode terminal electrode (second terminal electrode)
116 Organic insulation layer 120 Ti layer 121 Ni layer 122 Au layer 123 Ag layer 134 Wafer layer 135 First main surface 136 Second main surface 144 Semiconductor package 145 Package body 146 Pad portion 148 Lead terminal 149 Lead wire

Claims (21)

A semiconductor layer having a first main surface on one side and a second main surface on the other side that has been roughened,
The first terminal electrode formed on the first main surface and
An organic insulating layer that partially covers the first terminal electrode on the first main surface,
A semiconductor device including a second terminal electrode directly connected to the second main surface without a waveguide layer. The semiconductor device according to claim 1, wherein the second terminal electrode forms ohmic contact with the second main surface. The semiconductor device according to claim 1 or 2, wherein the second terminal electrode includes a Ti layer or an Au layer directly connected to the second main surface. The second terminal electrode is a Ti layer directly connected to the second main surface, a Ni layer formed on the Ti layer, an Au layer formed on the Ni layer, and the Au layer. The semiconductor device according to claim 1 or 2, which has a laminated structure including an Ag layer formed above. The second terminal electrode according to claim 1 or 2, wherein the second terminal electrode has a laminated structure including an Au layer directly connected to the second main surface and an Ag layer formed on the Au layer. Semiconductor device. The semiconductor device according to any one of claims 1 to 5, wherein the second main surface has no grinding marks. The second main surface is composed of a roughened crystal plane.
The semiconductor device according to any one of claims 1 to 6, wherein the second terminal electrode is directly connected to the crystal plane. The semiconductor device according to any one of claims 1 to 7, wherein the second main surface has an arithmetic mean roughness Ra of more than 0 nm and 400 nm or less. Any one of claims 1 to 8, wherein the second terminal electrode is directly connected to the second main surface without forming a eutectic layer and a modified layer with the second main surface. The semiconductor device according to the section. The semiconductor device according to any one of claims 1 to 9, wherein the organic insulating layer does not contain carbides. The semiconductor device according to any one of claims 1 to 10, wherein the organic insulating layer contains a photosensitive resin. The semiconductor device according to any one of claims 1 to 11, wherein the organic insulating layer contains at least one of polybenzoxazole, polyimide and polyamide. A MISFET formed on the first main surface of the semiconductor layer is further included.
The semiconductor device according to any one of claims 1 to 12, wherein the second terminal electrode is formed as a drain terminal electrode of the MISFET. A trench formed on the first main surface of the semiconductor layer and
An insulating layer formed on the inner wall of the trench and
The semiconductor device according to claim 13, further comprising a gate electrode embedded in the trench with the insulating layer interposed therebetween. Further including a diode formed on the first main surface of the semiconductor layer,
The semiconductor device according to any one of claims 1 to 14, wherein the second terminal electrode is formed as a cathode terminal electrode of the diode. A package body containing a sealing resin with a filler and
The pad part arranged in the package body and
Lead terminals arranged around the pad portion in the package body so that a part of the package body is exposed,
The semiconductor device according to any one of claims 1 to 15, which is arranged on the pad portion in a posture in which the second terminal electrode is connected to the pad portion in the package main body.
A semiconductor package including a lead wire in which the semiconductor device and the lead terminal are electrically connected in the package body. A step of preparing a wafer layer having a first main surface on one side and a second main surface on the other side, and
The step of forming the first terminal electrode on the first main surface and
A step of forming an organic insulating layer that partially covers the first terminal electrode on the first main surface, and
After the step of forming the organic insulating layer, a step of roughening the second main surface and
After the roughening step of the second main surface, a step of forming a second terminal electrode on the second main surface so as to be directly connected to the second main surface without using a silicide layer.
A method for manufacturing a semiconductor device, which comprises a step of cutting the semiconductor wafer layer and cutting out the semiconductor device. The step of forming the second terminal electrode includes a step of forming a Ti layer or an Au layer on the second main surface so as to be directly connected to the second main surface by a sputtering method or a thin film deposition method. Item 17. The method for manufacturing a semiconductor device according to item 17. The method for manufacturing a semiconductor device according to claim 17 or 18, wherein the roughening step of the second main surface includes a step of roughening the second main surface by an etching method. The method for manufacturing a semiconductor device according to any one of claims 17 to 19, further comprising a step of grinding the second main surface prior to the roughening step of the second main surface. The method for manufacturing a semiconductor device according to claim 20, further comprising a step of removing grinding marks from the second main surface prior to the roughening step of the second main surface.

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