JP2000200905A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2000200905A
JP2000200905A JP11001259A JP125999A JP2000200905A JP 2000200905 A JP2000200905 A JP 2000200905A JP 11001259 A JP11001259 A JP 11001259A JP 125999 A JP125999 A JP 125999A JP 2000200905 A JP2000200905 A JP 2000200905A
Authority
JP
Japan
Prior art keywords
power element
region
semiconductor device
integrated circuit
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11001259A
Other languages
Japanese (ja)
Inventor
Toru Miyazaki
透 宮崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP11001259A priority Critical patent/JP2000200905A/en
Publication of JP2000200905A publication Critical patent/JP2000200905A/en
Pending legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with superior radiating characteristics which can be formed in a few manufacturing processes, and a semiconductor device in which the reliability of a circuit operation can be improved, by reducing effects of noise generated in the operation of a power element on the circuit operation. SOLUTION: In a semiconductor device 1 of an intelligent power device, pads 311-315, 321-325, etc., for an integrated circuit are arranged in addition to pads 212, 213, 222, 223, etc., for a power element in each power element area 21-24. Also, a shield layer is formed between each power element area 21-24 and each of pads 311-315, 321-325, etc., for the integrated circuit.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置に関
し、特にパワー素子が配設されたパワー素子領域と、パ
ワー素子を駆動制御する回路や保護回路が配設された集
積回路領域とを同一基板上に形成する半導体装置に関す
る。さらに詳細には、本発明は、基板としてSOI（Silic
on on Insulator）基板が使用され、パワー素子領域の
周囲がトレンチ構造体で囲まれた構造を有し、放熱性能
に優れた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which a power element region provided with a power element and an integrated circuit region provided with a circuit for controlling and driving the power element and a protection circuit are provided on the same substrate. The present invention relates to a semiconductor device formed thereon. More particularly, the present invention is SOI (S Ilic as substrate
on o n I nsulator) substrate is used, the periphery of the power device region has a enclosed structure trench structure relates to a semiconductor device with excellent heat radiation performance.

【０００２】[0002]

【従来の技術】パワー素子とこのパワー素子を駆動制御
する回路や保護回路とを同一基板上に形成したインテリ
ジェントパワーデバイスの開発が進められている。この
種の半導体装置においては、パワー素子の動作で発生す
る熱を外部に放出させ、漏洩電流を減少させることが重
要な技術的課題の１つになっている。2. Description of the Related Art An intelligent power device in which a power element and a circuit for controlling and driving the power element and a protection circuit are formed on the same substrate has been developed. In this type of semiconductor device, it is one of the important technical issues to release heat generated by the operation of the power element to the outside and reduce leakage current.

【０００３】一般的に、パワー素子が配設されたパワー
素子領域内にはパワー素子用パッド（ボンディングパッ
ド）が配設されており、パワー素子用パッドはワイヤー
を通して配線基板、他のデバイス等の外部装置に電気的
に接続される。このパワー素子用パッド及びワイヤーは
パワー素子からの熱を外部装置側に逃がす放熱経路とし
ても使用されていた。Generally, a power element pad (bonding pad) is provided in a power element area in which a power element is provided, and the power element pad is connected to a wiring board, another device, or the like through a wire. It is electrically connected to an external device. These power element pads and wires have also been used as heat radiation paths for releasing heat from the power element to the external device side.

【０００４】特開平８−２３６６１８号公報には、パワ
ー素子の動作で発生する熱を効率良く外部に放出できる
発明が開示されている。この公開公報に開示された半導
体装置は、パワー素子部上の最上層に新たに上層配線層
を配設し、この上層配線層をヒートシンクとして使用す
るものである。Japanese Patent Laid-Open Publication No. Hei 8-236618 discloses an invention capable of efficiently releasing heat generated by the operation of a power element to the outside. In the semiconductor device disclosed in this publication, an upper wiring layer is newly provided in the uppermost layer on the power element section, and the upper wiring layer is used as a heat sink.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら、公開公
報に開示された半導体装置においては、以下の点につい
て配慮がなされていない。 （１）ヒートシンクとして使用される最上層の上層配線
層とパワー素子との間には上下配線層間を絶縁分離する
層間絶縁膜が数多く介在されてしまう。例えば、２層配
線構造の半導体装置においては、基板と第１層目配線層
との間、第１層目配線層と第２層目配線層との間、そし
て第２層目配線層と新たに追加された上層配線層との間
にそれぞれ層間絶縁膜が形成され、少なくとも合計３枚
の層間絶縁膜が必要になる。層間絶縁膜には一般的にシ
リコン酸化膜やシリコン窒化膜が使用されており、これ
らの無機材料は熱伝導性が低い。従って、パワー素子で
発生した熱は層間絶縁膜が熱抵抗となって上層配線層ま
で伝わりにくく、充分な放熱特性を得ることができなか
った。However, in the semiconductor device disclosed in the official gazette, the following points are not considered. (1) Many interlayer insulating films for insulating and separating the upper and lower wiring layers are interposed between the upper wiring layer and the power element used as the heat sink. For example, in a semiconductor device having a two-layer wiring structure, between a substrate and a first wiring layer, between a first wiring layer and a second wiring layer, and between a second wiring layer and a new wiring layer. An interlayer insulating film is formed between each of the layers and the additional upper wiring layer, and a total of at least three interlayer insulating films are required. Generally, a silicon oxide film or a silicon nitride film is used for the interlayer insulating film, and these inorganic materials have low thermal conductivity. Therefore, the heat generated by the power element is hardly transmitted to the upper wiring layer due to the thermal resistance of the interlayer insulating film, and sufficient heat radiation characteristics cannot be obtained.

【０００６】（２）さらに、最上層の上層配線層の形成
工程を半導体装置の製造プロセスに新たに組み込む必要
があり、この上層配線層の形成工程に伴い、下地の層間
絶縁膜を形成する工程やこの層間絶縁膜に接続孔を形成
する工程を追加する必要があるので、製造工程数が増大
してしまう。本発明は上記課題を解決するためになされ
たものである。従って、本発明の目的は、少ない製造工
程で形成することができ、かつ放熱特性に優れた半導体
装置を提供することである。特に、本発明の目的は、配
線形成工程数を減少させ全体の製造工程数を減少させる
ことができ、かつパワー素子からの熱を効率良く外部に
放出させ、放熱特性を向上させることができるインテリ
ジェントパワーデバイスを提供することである。さら
に、本発明の目的は、上記目的に加えて、パワー素子の
動作で発生するノイズの回路動作に及ぼす影響を減少さ
せ、回路動作の信頼性を向上させることができる半導体
装置を提供することである。(2) In addition, it is necessary to newly incorporate a step of forming an upper wiring layer on the uppermost layer into a manufacturing process of a semiconductor device. With the step of forming the upper wiring layer, a step of forming a base interlayer insulating film is required. It is necessary to add a step of forming a connection hole in the interlayer insulating film, and the number of manufacturing steps increases. The present invention has been made to solve the above problems. Therefore, an object of the present invention is to provide a semiconductor device which can be formed in a small number of manufacturing steps and has excellent heat dissipation characteristics. In particular, an object of the present invention is to reduce the number of wiring forming steps and the number of overall manufacturing steps, and to efficiently release heat from a power element to the outside to improve heat radiation characteristics. It is to provide a power device. Still another object of the present invention is to provide a semiconductor device capable of reducing the influence of noise generated by the operation of a power element on a circuit operation and improving the reliability of the circuit operation, in addition to the above objects. is there.

【０００７】[0007]

【課題を解決するための手段】上記課題を解決するため
に、この発明の第１の特徴は、半導体装置において、同
一基板上のパワー素子領域及び集積回路領域と、パワー
素子領域の周囲を取り囲むトレンチ構造体と、パワー素
子領域内のパワー素子用パッドと、パワー素子領域内又
はトレンチ構造体上のパワー素子用パッドと同一配線層
の集積回路用パッドと、を備えたことである。このよう
に構成される半導体装置においては、パワー素子の動作
で発生した熱をパワー素子用パッドで外部に放出させる
ことができ、さらに加えてパワー素子領域内又はトレン
チ構造体上の集積回路用パッドを通して外部に熱を放出
させることができるので、放熱特性を向上させることが
できる。さらに、集積回路用パッドは、パワー素子用パ
ッドと同一配線層で形成されており、集積回路用パッド
の配置位置をパワー素子領域内又はトレンチ構造体上に
変えただけなので、新たに配線層を追加することなく、
少ない製造工程数で放熱特性を向上させることができ
る。さらに、新たに配線層を追加することがなく、パワ
ー素子用パッド及び集積回路用パッドが最上層となり、
パワー素子用パッド及び集積回路用パッドとパワー素子
領域との間の層間絶縁膜の枚数を減少させることができ
るので、パワー素子領域からパワー素子用パッド、集積
回路用パッドのそれぞれに至る放熱経路の熱抵抗を減少
させることができ、放熱特性をより一層向上させること
ができる。In order to solve the above problems, a first feature of the present invention is to provide a semiconductor device which surrounds a power element region and an integrated circuit region on the same substrate and a periphery of the power element region. A trench structure, a power element pad in the power element region, and an integrated circuit pad in the same wiring layer as the power element pad in the power element region or on the trench structure are provided. In the semiconductor device configured as described above, the heat generated by the operation of the power element can be released to the outside by the power element pad. In addition, the integrated circuit pad in the power element region or on the trench structure Since heat can be released to the outside through the fin, heat radiation characteristics can be improved. Further, the integrated circuit pads are formed in the same wiring layer as the power element pads, and the arrangement position of the integrated circuit pads is merely changed in the power element area or on the trench structure. Without adding
The heat radiation characteristics can be improved with a small number of manufacturing steps. Furthermore, without adding a new wiring layer, the power element pad and the integrated circuit pad become the uppermost layer,
Since the number of interlayer insulating films between the power element pad and the integrated circuit pad and the power element area can be reduced, the heat radiation path from the power element area to the power element pad and the integrated circuit pad can be reduced. Thermal resistance can be reduced, and heat radiation characteristics can be further improved.

【０００８】この発明の第２の特徴は、第１の特徴の半
導体装置において、パワー素子用パッド、集積回路用パ
ッドはいずれもワイヤーを通して外部装置に電気的に接
続されたことである。このように構成される半導体装置
においては、パワー素子用パッドからワイヤーを通して
外部に至る放熱経路と、集積回路用パッドからワイヤー
を通して外部に至る放熱経路との２系統の放熱経路を形
成し、しかもワイヤーは熱伝導に優れているので、効率
良く外部に熱を放出させることができ、より一層放熱特
性を向上させることができる。A second feature of the present invention is that in the semiconductor device according to the first feature, both the power element pad and the integrated circuit pad are electrically connected to external devices through wires. In the semiconductor device thus configured, two heat radiation paths are formed: a heat radiation path from the power element pad to the outside through the wire, and a heat radiation path from the integrated circuit pad to the outside through the wire. Since is excellent in heat conduction, heat can be efficiently released to the outside, and the heat radiation characteristics can be further improved.

【０００９】この発明の第３の特徴は、第１の特徴又は
第２の特徴の半導体装置において、パワー素子領域と集
積回路用パッドとの間にさらにシールド層を備えたこと
である。このように構成される半導体装置においては、
パワー素子の動作で発生するノイズをシールド層で遮蔽
し、集積回路用パッドに伝達される信号にノイズが乗る
ことを防止することができるので、動作信頼性を向上さ
せることができる。A third feature of the present invention is that, in the semiconductor device according to the first feature or the second feature, a shield layer is further provided between the power element region and the integrated circuit pad. In the semiconductor device configured as described above,
Noise generated by the operation of the power element is shielded by the shield layer, and the noise transmitted to the signal transmitted to the integrated circuit pad can be prevented, so that the operation reliability can be improved.

【００１０】[0010]

【発明の効果】本発明は、少ない製造工程で形成するこ
とができ、かつ放熱特性に優れた半導体装置を提供する
ことができる。さらに、本発明は、上記効果に加えて、
パワー素子の動作で発生するノイズの回路動作に及ぼす
影響を減少させ、回路動作の信頼性を向上させることが
できる半導体装置を提供することができる。The present invention can provide a semiconductor device which can be formed in a small number of manufacturing steps and has excellent heat radiation characteristics. Furthermore, the present invention, in addition to the above effects,
It is possible to provide a semiconductor device capable of reducing the influence of noise generated by the operation of a power element on a circuit operation and improving the reliability of the circuit operation.

【００１１】[0011]

【発明の実施の形態】（第１の実施の形態）以下、本発
明の実施の形態を図面を参照して説明する。図１は本発
明の第１の実施の形態に係る半導体装置の平面図、図２
は図１のＦ２−Ｆ２切断線で切った部分の半導体装置の
拡大断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention, and FIG.
FIG. 2 is an enlarged cross-sectional view of a portion of the semiconductor device taken along a line F2-F2 in FIG.

【００１２】図１に示すように、第１の実施の形態に係
る半導体装置１はインテリジェントパワーデバイスであ
る。この半導体装置１は、図１中、中央部分に集積回路
（IC）領域３を配設し、図１中、左側にパワー素子領域
２１及び２２、図１中、右側にパワー素子領域２３及び
２４のそれぞれを配設する。パワー素子領域２１の周囲
はトレンチ構造体４１で取り囲まれ、同様に、パワー素
子領域２２の周囲はトレンチ構造体４２で、パワー素子
領域２３の周囲はトレンチ構造体４３で、パワー素子領
域２４の周囲はトレンチ構造体４４でそれぞれ取り囲ま
れる。As shown in FIG. 1, a semiconductor device 1 according to the first embodiment is an intelligent power device. In this semiconductor device 1, an integrated circuit (IC) region 3 is provided at a central portion in FIG. 1, and power device regions 21 and 22 are provided on the left in FIG. 1, and power device regions 23 and 24 are provided on the right in FIG. Arrange each of the. The periphery of the power element region 21 is surrounded by a trench structure 41. Similarly, the periphery of the power element region 22 is a trench structure 42, the periphery of the power element region 23 is a trench structure 43, and the periphery of the power element region 24. Are each surrounded by a trench structure 44.

【００１３】パワー素子領域２１の中央部分にはパワー
素子２１１が配設される。パワー素子２１１はパワート
ランジスタ（パワートランジスタセル）を複数個電気的
に並列に接続して構成される。第１の実施の形態におい
て、パワートランジスタには、トレンチ（図２において
符号７１で示す断面U字型の溝。）を利用し、このトレ
ンチ内にゲート電極（図２において符号７３で示す。）
を埋設した絶縁ゲート型電界効果トランジスタ（一般的
にUMOSと呼ばれているが、本発明はゲート絶縁膜に単層
のSiO2膜以外の絶縁膜、例えばSiO2膜及びSi3N4膜から
なる複合膜やSiNO膜を使用するトランジスタも含む。）
が実用的に使用できる。A power element 211 is provided at the center of the power element area 21. The power element 211 is configured by electrically connecting a plurality of power transistors (power transistor cells) electrically in parallel. In the first embodiment, a trench (a U-shaped cross section indicated by reference numeral 71 in FIG. 2) is used for the power transistor, and a gate electrode (indicated by reference numeral 73 in FIG. 2) is provided in the trench.
Embedded insulated gate field effect transistor (generally referred to as UMOS, but the present invention uses a gate insulating film made of an insulating film other than a single-layer SiO 2 film, such as an SiO 2 film and a Si 3 N 4 film. (Including transistors using composite films and SiNO films.)
Can be used practically.

【００１４】同様に、パワー素子領域２２の中央部分に
はパワー素子２２１が配設され、パワー素子領域２３の
中央部分にはパワー素子２３１が配設され、パワー素子
領域２４の中央部分にはパワー素子２４１が配設され
る。これらのパワー素子２２１、２３１、２４１はいず
れもパワー素子領域２１のパワー素子２１１と同様の複
数個のパワートランジスタで構成される。Similarly, a power element 221 is provided at the center of the power element area 22, a power element 231 is provided at the center of the power element area 23, and a power element is provided at the center of the power element area 24. An element 241 is provided. Each of these power elements 221, 231 and 241 is constituted by a plurality of power transistors similar to the power element 211 in the power element area 21.

【００１５】なお、詳細には説明しないが、集積回路領
域３には、パワー素子２１１、２２１、２３１、２４１
のそれぞれを駆動する駆動回路、駆動の制御を行う論理
回路、サージによる破壊を防止するための保護回路等が
配設される。Although not described in detail, the power elements 211 221 231 241 and 241
Are provided, a driving circuit for driving each of them, a logic circuit for controlling the driving, a protection circuit for preventing destruction by a surge, and the like are provided.

【００１６】図２に示すように、第１の実施の形態に係
る半導体装置１はSOI構造の基板１０で構成される。す
なわち、基板１０は、単結晶シリコンからなる低い不純
物密度のp型半導体基板１０１と、半導体基板１０１上
に形成された絶縁体層１０２と、絶縁体層１０２に張り
合わされた半導体層１０３とを備えて構成される。この
半導体層１０３は素子が形成されるアクティブ領域とし
て使用され、第１の実施の形態において半導体層１０３
の少なくともパワー素子領域２１〜２４には低い不純物
密度のn型ウエル領域が形成される。As shown in FIG. 2, the semiconductor device 1 according to the first embodiment includes a substrate 10 having an SOI structure. That is, the substrate 10 includes a low-impurity-density p-type semiconductor substrate 101 made of single-crystal silicon, an insulator layer 102 formed over the semiconductor substrate 101, and a semiconductor layer 103 attached to the insulator layer 102. It is composed. This semiconductor layer 103 is used as an active region where an element is formed, and is used in the first embodiment.
In at least the power element regions 21 to 24, an n-type well region having a low impurity density is formed.

【００１７】図２にはパワー素子領域２２の一部の断面
構造を示しているが、基本的にはパワー素子領域２１〜
２４のそれぞれの断面構造は同一である。すなわち、ま
ずパワー素子領域２１〜２４のそれぞれの周囲を取り囲
むトレンチ構造体４１〜４４は、いずれもトレンチ４０
１、埋込絶縁体４０２、埋込充填材４０３、キャップ材
４０４を備えて構築される。トレンチ４０１は、半導体
層１０３の表面から深さ方向に、底面が絶縁体層１０２
の表面に達するように形成され、パワー素子領域２１〜
２４のそれぞれと集積回路領域３との間を分離するよう
に構成される。通常、トレンチ４０１の形成には、微細
加工を目的として、反応性イオンエッチング（RIE）等
の異方性の強いエッチングが使用される。埋込絶縁体４
０２はトレンチ４０１の側壁及び底面に沿って形成さ
れ、埋込絶縁体４０２には例えば熱酸化法や化学的気相
析出（VCD）法で成膜されたSiO2膜が実用的に使用でき
る。埋込充填材４０３はトレンチ４０１内部に埋込絶縁
体４０２を介在させて埋め込まれ、埋込充填材４０３に
は例えばCVD法で成膜された多結晶シリコン膜が実用的
に使用できる。通常、この多結晶シリコン膜はトレンチ
４０１内部に完全に埋め込むために、トレンチ４０１の
周囲の半導体層１０３上にも余分に成膜されるが、これ
らの余分に成膜された多結晶シリコン膜は全面エッチン
グにより取り除かれる。キャップ材４０４はトレンチ４
０１上に配設され、このキャップ材４０４には例えば熱
酸化法で形成されたSiO2膜が実用的に使用できる。FIG. 2 shows a partial cross-sectional structure of the power element region 22.
24 have the same sectional structure. That is, first, the trench structures 41 to 44 surrounding the periphery of each of the power element regions 21 to 24 are
1. A buried insulator 402, a buried filler 403, and a cap 404 are provided. The trench 401 has a bottom surface extending from the surface of the semiconductor
And the power element regions 21 to
24 and the integrated circuit region 3. Usually, in forming the trench 401, highly anisotropic etching such as reactive ion etching (RIE) is used for the purpose of fine processing. Embedded insulator 4
Numeral 02 is formed along the side wall and bottom surface of the trench 401, and for the buried insulator 402, for example, a SiO 2 film formed by a thermal oxidation method or a chemical vapor deposition (VCD) method can be practically used. The buried filler 403 is buried inside the trench 401 with a buried insulator 402 interposed therebetween. For the buried filler 403, for example, a polycrystalline silicon film formed by a CVD method can be used practically. Usually, this polycrystalline silicon film is additionally formed on the semiconductor layer 103 around the trench 401 to completely bury the inside of the trench 401. The entire surface is removed by etching. Cap material 404 is trench 4
For example, a SiO 2 film formed by a thermal oxidation method can be practically used as the cap material 404.

【００１８】図１に示すトレンチ構造体４１は、パワー
素子領域２１と集積回路領域３との間を完全に絶縁分離
しており、双方の間で寄生トランジスタの発生を防止す
ることができる。同様に、トレンチ構造体４２はパワー
素子領域２２と集積回路領域３との間を完全に絶縁分離
し、トレンチ構造体４３はパワー素子領域２３と集積回
路領域３との間を完全に絶縁分離し、トレンチ構造体４
４はパワー素子領域２４と集積回路領域３との間を完全
に絶縁分離することができる。In the trench structure 41 shown in FIG. 1, the power element region 21 and the integrated circuit region 3 are completely insulated and separated from each other, so that a parasitic transistor can be prevented from being generated therebetween. Similarly, the trench structure 42 completely insulates the power device region 22 from the integrated circuit region 3, and the trench structure 43 completely insulates the power device region 23 from the integrated circuit region 3. , Trench structure 4
4 can completely insulate and isolate the power element region 24 and the integrated circuit region 3.

【００１９】パワー素子領域２１のパワー素子２１１、
パワー素子領域２２のパワー素子２２１、パワー素子領
域２３のパワー素子２３１、パワー素子領域２４のパワ
ー素子２４１のそれぞれのパワートランジスタ（UMOS）
は、図２に示すように、いずれも、トレンチ７１、ゲー
ト絶縁膜７２、ゲート電極７３、ドレイン領域、ソース
領域及びベース領域を主体として構築される。The power element 211 in the power element area 21;
Each power transistor (UMOS) of the power element 221 in the power element area 22, the power element 231 in the power element area 23, and the power element 241 in the power element area 24
As shown in FIG. 2, each of them is constructed mainly of a trench 71, a gate insulating film 72, a gate electrode 73, a drain region, a source region, and a base region.

【００２０】このパワートランジスタのドレイン領域は
半導体層１０３のn型ウエル領域を主体に形成される。
このドレイン領域には半導体層１０３の絶縁体層１０２
側に形成された高い不純物密度のn型埋込層５、半導体
層１０３の表面からn型埋込層５に達する高い不純物密
度のn型半導体領域６、n型半導体領域６の表面部分に形
成されコンタクト領域として使用される高い不純物密度
のn型半導体領域９１のそれぞれが順次電気的に接続さ
れており、これらの領域を通してドレイン領域にドレイ
ン電流が供給される。The drain region of the power transistor is formed mainly on the n-type well region of the semiconductor layer 103.
In this drain region, the insulator layer 102 of the semiconductor layer 103 is formed.
The n-type buried layer 5 having a high impurity density formed on the side, the n-type semiconductor region 6 having a high impurity density reaching the n-type buried layer 5 from the surface of the semiconductor layer 103, and the surface portion of the n-type semiconductor region 6 are formed. Each of the n-type semiconductor regions 91 having a high impurity density used as a contact region is electrically connected sequentially, and a drain current is supplied to the drain region through these regions.

【００２１】ベース領域は、ドレイン領域の表面部分に
形成され、中間の不純物密度のp型半導体領域８で形成
される。このベース領域のゲート絶縁膜７２に近接する
領域には、ゲート電極７３に供給されるゲート電圧に応
じてドレイン領域とソース領域との間に主電流を流すた
めのチャネル領域が形成される。The base region is formed on the surface of the drain region, and is formed of a p-type semiconductor region 8 having an intermediate impurity density. In a region of the base region adjacent to the gate insulating film 72, a channel region for flowing a main current between the drain region and the source region according to a gate voltage supplied to the gate electrode 73 is formed.

【００２２】ソース領域は、ベース領域の表面部分に形
成され、高い不純物密度のn型半導体領域９０で形成さ
れる。The source region is formed on the surface of the base region, and is formed of an n-type semiconductor region 90 having a high impurity density.

【００２３】さらに、ソース領域の中央部分には半導体
層１０３（n型ウエル領域）の表面からベース領域に達
するバックゲート領域（又はベースコンタクト領域）が
形成され、このバックゲート領域は高い不純物密度のp
型半導体領域９５で形成される。Further, a back gate region (or a base contact region) extending from the surface of the semiconductor layer 103 (n-type well region) to the base region is formed at a central portion of the source region, and the back gate region has a high impurity density. p
It is formed in the type semiconductor region 95.

【００２４】ゲート絶縁膜７２は、ソース領域の周囲を
取り囲み、半導体層１０３の表面からベース領域を突き
抜けるように形成されたトレンチ７１の内壁及び底面に
沿って形成される。ゲート絶縁膜７２には、例えば熱酸
化法で成膜されたSiO2膜が実用的に使用できる。勿論、
前述のように、ゲート絶縁膜７２はSiO2膜以外のものを
使用することができる。ゲート電極７３はトレンチ７１
内においてゲート絶縁膜７２を介在して埋設される。ゲ
ート電極７３には例えばCVD法で成膜された多結晶シリ
コン膜が実用的に使用できる。この多結晶シリコン膜に
は抵抗値を調節する不純物、例えばAs若しくはPのn型不
純物、又はB等のp型不純物が導入される。トレンチ７１
上部にはゲート電極７３とその上層の配線との短絡を防
止するためにキャップ材７４が形成される。The gate insulating film 72 is formed along the inner wall and the bottom of the trench 71 formed so as to surround the source region and penetrate the base region from the surface of the semiconductor layer 103. As the gate insulating film 72, for example, an SiO 2 film formed by a thermal oxidation method can be practically used. Of course,
As described above, a material other than the SiO 2 film can be used for the gate insulating film 72. The gate electrode 73 is a trench 71
Embedded in the inside with a gate insulating film 72 interposed therebetween. For the gate electrode 73, for example, a polycrystalline silicon film formed by a CVD method can be practically used. An impurity for adjusting the resistance value, for example, an n-type impurity such as As or P, or a p-type impurity such as B is introduced into the polycrystalline silicon film. Trench 71
A cap material 74 is formed on the upper portion to prevent a short circuit between the gate electrode 73 and the wiring above it.

【００２５】同図２に示すように、パワートランジスタ
のドレイン領域に接続されたn型半導体領域９１にはド
レイン電極２０１が電気的に接続される。第１の実施の
形態に係る半導体装置１は２層配線構造で構成されてお
り、ドレイン電極２０１は第１層目配線層（下層配線
層）に配置される。すなわち、ドレイン電極２０１は、
半導体層１０３表面上の層間絶縁膜１１上に配設され、
この層間絶縁膜１１に形成された接続孔（符号は付けな
い。）を通してn型半導体領域９１に接続される。ドレ
イン電極２０１は例えばアルミニウムにSiやCuを数%添
加したアルミニウム合金膜を主体に形成される。As shown in FIG. 2, a drain electrode 201 is electrically connected to an n-type semiconductor region 91 connected to the drain region of the power transistor. The semiconductor device 1 according to the first embodiment has a two-layer wiring structure, and the drain electrode 201 is disposed in a first wiring layer (lower wiring layer). That is, the drain electrode 201
Disposed on the interlayer insulating film 11 on the surface of the semiconductor layer 103;
It is connected to the n-type semiconductor region 91 through a connection hole (not numbered) formed in the interlayer insulating film 11. The drain electrode 201 is mainly formed of, for example, an aluminum alloy film obtained by adding several percent of Si or Cu to aluminum.

【００２６】このドレイン電極２０１はさらに上層の第
２層目配線層（上層配線層）に配置された配線に電気的
に接続され、この配線には図２に示すパワー素子２２１
においては同一の第２層目配線層に配置されるパワー素
子用パッド（ボンディングパッド）２２３に電気的に接
続される。図１に示すパワー素子２１１のドレイン電極
２０１は同図１に示すパワー素子用パッド２１３に、同
様にパワー素子２３１のドレイン電極２０１はパワー素
子用パッド２３３に、パワー素子２４１のドレイン電極
２０１はパワー素子用パッド２４３にそれぞれ電気的に
接続される。パワー素子用パッド２１３はパワー素子領
域２１内、好ましくはパワー素子２１１上に配置され
る。同様に、パワー素子用パッド２２３はパワー素子領
域２２内において好ましくはパワー素子２２１上に配置
され、パワー素子用パッド２３３はパワー素子領域２３
内において好ましくはパワー素子２３１上に配置され、
パワー素子用パッド２４３はパワー素子領域２４内にお
いて好ましくはパワー素子２４１上に配置される。パワ
ー素子用パッド２１３、２２３、２３３、２４３は、い
ずれも第１層目配線層上の層間絶縁膜１２上に配設さ
れ、ドレイン電極２０１と同様に例えばアルミニウム合
金膜を主体に形成される。さらに、パワー素子用パッド
２１３、２２３、２３３、２４３はいずれも例えば100
μｍ×100μｍ程度の平面寸法で形成される。なお、第
２層目配線層の上層には保護膜１３が形成されるが、パ
ワー素子用パッド２１３、２２３、２３３、２４３のそ
れぞれの領域において保護膜１３にはボンディング開口
が形成される。The drain electrode 201 is electrically connected to a wiring disposed in a second upper wiring layer (upper wiring layer), and the wiring is connected to the power element 221 shown in FIG.
Is electrically connected to a power element pad (bonding pad) 223 disposed in the same second wiring layer. The drain electrode 201 of the power element 211 shown in FIG. 1 is the power element pad 213 shown in FIG. 1, the drain electrode 201 of the power element 231 is the power element pad 233, and the drain electrode 201 of the power element 241 is the power electrode. Each is electrically connected to the element pad 243. The power element pad 213 is disposed in the power element area 21, preferably on the power element 211. Similarly, the power element pad 223 is preferably disposed on the power element 221 in the power element area 22, and the power element pad 233 is
Is preferably arranged on the power element 231,
The power element pad 243 is preferably arranged on the power element 241 in the power element region 24. Each of the power element pads 213, 223, 233, and 243 is provided on the interlayer insulating film 12 on the first wiring layer, and is formed mainly of, for example, an aluminum alloy film like the drain electrode 201. Further, each of the power element pads 213, 223, 233, and 243 is, for example, 100
It is formed with a plane dimension of about μm × 100 μm. The protective film 13 is formed above the second wiring layer, and a bonding opening is formed in the protective film 13 in each region of the power element pads 213, 223, 233, and 243.

【００２７】一方、図２に示すパワートランジスタのソ
ース領域として使用されるn型半導体領域９０及びバッ
クゲート電極として使用されるp型半導体領域９５には
ソース電極２０２が電気的に接続される。ソース電極２
０２は、ドレイン電極２０１と同一の第１層目配線層に
配置され、層間絶縁膜１１に形成された接続孔を通して
n型半導体領域９０及びp型半導体領域９５に接続され
る。On the other hand, a source electrode 202 is electrically connected to an n-type semiconductor region 90 used as a source region and a p-type semiconductor region 95 used as a back gate electrode of the power transistor shown in FIG. Source electrode 2
Numeral 02 is disposed in the same first wiring layer as the drain electrode 201 and passes through a connection hole formed in the interlayer insulating film 11.
It is connected to the n-type semiconductor region 90 and the p-type semiconductor region 95.

【００２８】このソース電極２０２はさらに上層の第２
層目配線層に配置された配線に電気的に接続され、この
配線には図２に示すパワー素子２２１においては図１に
示す同一の第２層目配線層に配置されるパワー素子用パ
ッド２２２に電気的に接続される。図１に示すパワー素
子２１１のソース電極２０２は同図１に示すパワー素子
用パッド２１２に、同様にパワー素子２３１のソース電
極２０２はパワー素子用パッド２３２に、パワー素子２
４１のソース電極２０２はパワー素子用パッド２４２に
それぞれ電気的に接続される。パワー素子用パッド２１
２はパワー素子領域２１内、好ましくはパワー素子２１
１上に配置される。同様に、パワー素子用パッド２２２
はパワー素子領域２２内において好ましくはパワー素子
２２１上に配置され、パワー素子用パッド２３２はパワ
ー素子領域２３内において好ましくはパワー素子２３１
上に配置され、パワー素子用パッド２４２はパワー素子
領域２４内において好ましくはパワー素子２４１上に配
置される。パワー素子用パッド２１２、２２２、２３
２、２４２は、いずれもパワー素子用パッド２１３、２
２３、２３３又は２４３と同等の平面寸法で形成され
る。また、パワー素子用パッド２１２、２２２、２３
２、２４２のそれぞれの領域において保護膜１３にはボ
ンディング開口が形成される。The source electrode 202 is formed on a second upper layer.
The power element 221 shown in FIG. 2 is electrically connected to the wiring arranged in the first wiring layer. The power element pad 222 arranged in the same second wiring layer shown in FIG. Is electrically connected to The source electrode 202 of the power element 211 shown in FIG. 1 is connected to the power element pad 212 shown in FIG. 1, and the source electrode 202 of the power element 231 is connected to the power element pad 232.
The 41 source electrodes 202 are electrically connected to the power element pads 242, respectively. Power element pad 21
2 is within the power element region 21, preferably the power element 21
1 above. Similarly, the power element pad 222
Is preferably arranged on the power element 221 in the power element area 22, and the power element pad 232 is preferably arranged in the power element area 23.
The power element pad 242 is disposed on the power element 241 in the power element region 24. Power element pads 212, 222, 23
2, 242 are power element pads 213, 2
23, 233 or 243. In addition, the power element pads 212, 222, 23
Bonding openings are formed in the protective film 13 in the respective regions 2 and 242.

【００２９】図２に示すように、パワー素子領域２２に
おいてはパワー素子２２１とトレンチ構造体４２との間
に放熱領域２２５が配設される。同様に、図１に示すパ
ワー素子領域２１においてはパワー素子２１１とトレン
チ構造体４１との間に放熱領域２１５が配設され、パワ
ー素子領域２３においてはパワー素子２３１とトレンチ
構造体４３との間に放熱領域２３５が配設され、パワー
素子領域２４においてはパワー素子２４１とトレンチ構
造体４４との間に放熱領域２４５が配設される。放熱領
域２１５は、サージ等の発生で短時間にパワー素子２１
１が発熱し温度が上昇する場合において、SOI構造の基
板１０の絶縁体層１０２でパワー素子領域２１の底面
を、トレンチ構造体４１でパワー素子領域２１の側面を
完全に覆い、放熱経路を遮断してしまうと、漏洩電流が
増加する恐れがあるので、放熱性を高めるために放熱面
積を稼ぐことを主目的として配設される。例えば、パワ
ー素子２１１の面積を30000μｍ2に設定した場合、パワ
ー素子２１１の面積に放熱領域２１５の面積を加えたパ
ワー素子領域２１の全体の面積は約4倍の120000μｍ2に
設定することが、SOI構造の基板１及びトレンチ構造体
４１を採用しない場合と同等の放熱性を確保する上で好
ましい。この場合、パワー素子領域２１は縦横の長さで
約180μｍは大きくなる。他の放熱領域２２５、２３
５、２４５のそれぞれにおいても同様である。As shown in FIG. 2, in the power element region 22, a heat radiation region 225 is provided between the power element 221 and the trench structure 42. Similarly, in the power element region 21 shown in FIG. 1, a heat dissipation region 215 is provided between the power element 211 and the trench structure 41, and in the power element region 23, between the power element 231 and the trench structure 43. In the power element region 24, a heat radiation region 235 is provided between the power element 241 and the trench structure 44. The heat dissipating region 215 is provided with the power element 21
In the case where the temperature rises due to the heat generation of 1, the bottom surface of the power element region 21 is completely covered with the insulator layer 102 of the SOI structure substrate 10, and the side surface of the power element region 21 is completely covered with the trench structure 41, and the heat radiation path is cut off. In such a case, the leakage current may be increased. Therefore, the antenna is mainly provided to increase a heat radiation area in order to enhance heat radiation. For example, when the area of the power element 211 is set to 30,000 μm 2 , the total area of the power element area 21 obtained by adding the area of the heat dissipation area 215 to the area of the power element 211 can be set to about 40000 × 120,000 μm 2 . It is preferable to ensure the same heat dissipation as when the SOI structure substrate 1 and the trench structure 41 are not used. In this case, the length of the power element region 21 is about 180 μm in length and width. Other heat dissipation areas 225, 23
The same applies to each of 5, 245.

【００３０】そして、第１の実施の形態に係る半導体装
置１においては、図１及び図２に示すように、パワー素
子領域２１の放熱領域２１５、パワー素子領域２２の放
熱領域２２５、パワー素子領域２３の放熱領域２３５、
パワー素子領域２４の放熱領域２４５のそれぞれのデッ
ドスペースを空間的に有効に活用し、この放熱領域２１
５に集積回路用パッド（ボンディングパッド）３１１〜
３１５が配設され、放熱領域２２５に集積回路用パッド
３２１〜３２５が配設され、放熱領域２３５に集積回路
用パッド３３１〜３３５が配設され、さらに放熱領域２
４５に集積回路用パッド３４１〜３４５が配設される。
集積回路用パッド３１１〜３１５、３２１〜３２５、３
３１〜３３５、３４１〜３４５はいずれもパワー素子用
パッド２１２、２１３、２２２、２２３、２３２、２３
３、２４２、２４３のそれぞれと同一配線層の第２層目
配線層に配置されており、第１層目配線層に配置される
配線３０１又は第２層目配線層に配置される配線を通し
て集積回路領域３との間で信号の入出力が行われる。In the semiconductor device 1 according to the first embodiment, as shown in FIGS. 1 and 2, the heat dissipation area 215 of the power element area 21, the heat dissipation area 225 of the power element area 22, and the power element area 23 heat dissipation areas 235,
The dead space of each heat dissipation area 245 of the power element area 24 is effectively utilized spatially, and the heat dissipation area 21
5 shows integrated circuit pads (bonding pads) 311 to 31.
315 are provided, the integrated circuit pads 321 to 325 are provided in the heat dissipation area 225, the integrated circuit pads 331 to 335 are provided in the heat dissipation area 235, and the heat dissipation area 2 is provided.
At 45, integrated circuit pads 341 to 345 are provided.
Integrated circuit pads 311 to 315, 321 to 325, 3
Reference numerals 31 to 335 and 341 to 345 denote power element pads 212, 213, 222, 223, 232, and 23, respectively.
3, 242 and 243, are arranged in the second wiring layer of the same wiring layer, and are integrated through the wiring 301 arranged in the first wiring layer or the wiring arranged in the second wiring layer. Signal input / output is performed with the circuit area 3.

【００３１】集積回路用パッド３１１〜３１５は発熱源
となるパワー素子２１１に近接したパワー素子領域２１
内に配設されることが放熱効率を高める点で好ましい
が、集積回路用パッド３１１〜３１５の一部がトレンチ
構造体４１上に配置されていても充分な放熱効率の向上
が期待できる。その他の集積回路用パッド３２１〜３２
５、３３１〜３３５、３４１〜３４５のそれぞれも同様
である。The integrated circuit pads 311 to 315 are located in the power element region 21 close to the power element 211 serving as a heat source.
Although it is preferable to dispose it in the inside in order to enhance the heat radiation efficiency, even if a part of the integrated circuit pads 311 to 315 are arranged on the trench structure 41, a sufficient improvement in the heat radiation efficiency can be expected. Other integrated circuit pads 321 to 32
5, 331 to 335, and 341 to 345 are the same.

【００３２】図３は半導体装置１を実装した配線基板の
概略断面図（図１に示すＦ３−Ｆ３切断線部分で切った
概略断面図）である。図３に示すように、半導体装置１
は配線基板１５上に実装される。配線基板１５にはエポ
キシ系樹脂配線基板、セラミックス配線基板のいずれか
が実用的に使用できる。配線基板１５の表面上には配線
１６１、１６２のそれぞれが配設される。配線１６１、
１６２のそれぞれは、例えばエポキシ系樹脂配線基板に
おいてはCu配線やAl配線で形成され、セラミックス配線
基板においてはMoペーストやWペーストを焼き固めたメ
タライズ配線で形成される。FIG. 3 is a schematic sectional view (schematic sectional view taken along the line F3-F3 shown in FIG. 1) of the wiring board on which the semiconductor device 1 is mounted. As shown in FIG.
Are mounted on the wiring board 15. Either an epoxy-based resin wiring board or a ceramic wiring board can be practically used for the wiring board 15. On the surface of the wiring board 15, each of the wirings 161 and 162 is provided. Wiring 161,
Each of the reference numerals 162 is formed of, for example, a Cu wiring or an Al wiring on an epoxy resin wiring substrate, and is formed of a metallized wiring obtained by sintering a Mo paste or a W paste on a ceramic wiring substrate.

【００３３】図３に示すように、半導体装置１のパワー
素子用パッド２２３、２４３のそれぞれ（２１２、２１
３、２２２、２３２、２３３、２４２のそれぞれも同
様）は、ワイヤー（ボンディングワイヤー）１４１を通
して配線１６１に電気的に接続される。一方、集積回路
用パッド３２２、３４２のそれぞれ（３１１〜３１５、
３２１、３２３〜３２５、３３１〜３３５、３４１、３
４３〜３４５のそれぞれも同様）は、ワイヤー１４２を
通して配線１６２に電気的に接続される。ワイヤー１４
１、１４２は、いずれも、電気伝導性を有し、かつ熱伝
導性に優れた例えばCuワイヤー、Alワイヤー、Auワイヤ
ーのいずれかが実用的に使用できる。As shown in FIG. 3, each of the power element pads 223 and 243 of the semiconductor device 1 (212 and 21)
3, 222, 232, 233, and 242) are electrically connected to the wiring 161 through wires (bonding wires) 141. On the other hand, each of the integrated circuit pads 322 and 342 (311 to 315,
321, 323-325, 331-335, 341, 3
43 to 345) are electrically connected to the wiring 162 through the wires 142. Wire 14
As for Nos. 1 and 142, any of Cu wire, Al wire, and Au wire having electric conductivity and excellent heat conductivity can be practically used.

【００３４】このように構成される半導体装置１におい
ては、パワー素子２１１、２２１、２３１、２４１のそ
れぞれの動作で発生した熱をパワー素子用パッド２１
２、２１３、２２２、２２３、２３２、２３３、２４
２、２４３のそれぞれで外部に放出させることができ、
さらに加えてパワー素子領域２１〜２４内又はトレンチ
構造体４１〜４４上の集積回路用パッド３１１〜３１
５、３２１〜３２５、３３１〜３３５、３４１〜３４５
のそれぞれを通して外部に放出させることができるの
で、放熱特性を向上させることができる。さらに、集積
回路用パッド３１１〜３１５、３２１〜３２５、３３１
〜３３５、３４１〜３４５のそれぞれは、パワー素子用
パッド２１２、２１３、２２２、２２３、２３２、２３
３、２４２、２４３のそれぞれと同一配線層で形成され
ており、集積回路用パッド３１１〜３１５、３２１〜３
２５、３３１〜３３５、３４１〜３４５のそれぞれの配
置位置をパワー素子領域２１〜２４内又はトレンチ構造
体４１〜４４上に変えただけなので、新たに配線層を追
加することなく、少ない製造工程数で形成することがで
き、かつ放熱特性を向上させることができる。さらに、
新たに配線層を追加することがなく、パワー素子用パッ
ド２１２、２１３、２２２、２２３、２３２、２３３、
２４２、２４３のそれぞれ及び集積回路用パッド３１１
〜３１５、３２１〜３２５、３３１〜３３５、３４１〜
３４５のそれぞれが最上層となり、パワー素子用パッド
２１２、２１３、２２２、２２３、２３２、２３３、２
４２、２４３のそれぞれ及び集積回路用パッド３１１〜
３１５、３２１〜３２５、３３１〜３３５、３４１〜３
４５のそれぞれとパワー素子領域２１〜２４との間を層
間絶縁膜１１及び１２の２層に減少させることができる
ので、パワー素子領域２１〜２４からパワー素子用パッ
ド２１２、２１３、２２２、２２３、２３２、２３３、
２４２、２４３のそれぞれ及び集積回路用パッド３１１
〜３１５、３２１〜３２５、３３１〜３３５、３４１〜
３４５のそれぞれに至る放熱経路の熱抵抗を減少させる
ことができ、放熱特性をより一層向上させることができ
る。In the semiconductor device 1 thus configured, the heat generated by the operation of each of the power elements 211, 221, 231 and 241 is transferred to the power element pad 21.
2,213,222,223,232,233,24
2, 243 can be released to the outside,
In addition, integrated circuit pads 311 to 31 in power element regions 21 to 24 or on trench structures 41 to 44
5, 321-325, 331-335, 341-345
Can be released to the outside through each of them, so that the heat radiation characteristics can be improved. Further, integrated circuit pads 311 to 315, 321 to 325, 331
To 335, 341 to 345 are the power element pads 212, 213, 222, 223, 232, 23, respectively.
3, 242, and 243, and are formed in the same wiring layer as the integrated circuit pads 311 to 315 and 321 to 3
25, 331 to 335, and 341 to 345 are merely arranged in the power element regions 21 to 24 or on the trench structures 41 to 44. Therefore, the number of manufacturing steps is small without adding a new wiring layer. And heat dissipation characteristics can be improved. further,
The power element pads 212, 213, 222, 223, 232, 233,
242, 243 and integrated circuit pad 311
315, 321-325, 331-335, 341-
345 is the uppermost layer, and the power element pads 212, 213, 222, 223, 232, 233, 2
42, 243 and the integrated circuit pads 311-
315, 321-325, 331-335, 341-3
45 and the power element regions 21 to 24 can be reduced to two layers of the interlayer insulating films 11 and 12, so that the power element pads 212, 213, 222, 223, 232, 233,
242, 243 and integrated circuit pad 311
315, 321-325, 331-335, 341-
345, the heat resistance of the heat radiation path leading to each of them can be reduced, and the heat radiation characteristics can be further improved.

【００３５】さらに、このように構成される半導体装置
１においては、パワー素子用パッド２１２、２１３、２
２２、２２３、２３２、２３３、２４２、２４３のそれ
ぞれからワイヤー１４１を通して外部に至る放熱経路
と、集積回路用パッド３１１〜３１５、３２１〜３２
５、３３１〜３３５、３４１〜３４５のそれぞれからワ
イヤー１４２を通して外部に至る放熱経路との２系統の
放熱経路を形成し、しかもワイヤー１４１、１４２のそ
れぞれは熱伝導に優れているので、効率良く外部に熱を
放出させることができ、より一層放熱特性を向上させる
ことができる。Further, in the semiconductor device 1 thus configured, the power element pads 212, 213, and 2
22, 223, 232, 233, 242, and 243, a heat radiation path from the respective wires to the outside through the wire 141, and the integrated circuit pads 311 to 315 and 321 to 32
5, 331 to 335, and 341 to 345 form two systems of heat radiating paths including a heat radiating path extending to the outside through the wire 142. Further, since each of the wires 141 and 142 is excellent in heat conduction, it is efficiently connected to the outside. Heat can be released, and the heat radiation characteristics can be further improved.

【００３６】さらに、このように構成される半導体装置
１においては、パワー素子領域２１〜２４のそれぞれの
面積を実質的に変化させない場合には、集積回路用パッ
ド３１１〜３１５、３２１〜３２５、３３１〜３３５、
３４１〜３４５のそれぞれの占有面積をパワー素子領域
２１〜２４のそれぞれの占有面積に重複させ減少させる
ことができるので、全体面積（チップ面積）を減少させ
ることができる。Furthermore, in the semiconductor device 1 thus configured, when the respective areas of the power element regions 21 to 24 are not substantially changed, the integrated circuit pads 311 to 315, 321 to 325, 331 ~ 335,
Since the occupied area of each of the power element regions 21 to 24 can be reduced by overlapping the occupied area of each of the power element regions 21 to 24, the entire area (chip area) can be reduced.

【００３７】さらに、このように構成される半導体装置
１においては、全体面積（チップ面積）を実質的に変化
させない場合には、集積回路用パッド３１１〜３１５、
３２１〜３２５、３３１〜３３５、３４１〜３４５のそ
れぞれの配置でパワー素子領域２１〜２４のそれぞれの
面積を増加させることができるので、その分放熱面積が
増加でき、放熱特性を向上させることができる。Furthermore, in the semiconductor device 1 thus configured, when the entire area (chip area) is not substantially changed, the integrated circuit pads 311 to 315,
Since the respective areas of the power element regions 21 to 24 can be increased by the respective arrangements of 321 to 325, 331 to 335, and 341 to 345, the heat radiation area can be increased accordingly, and the heat radiation characteristics can be improved. .

【００３８】（第２の実施の形態）第２の実施の形態
は、第１の実施の形態に係る半導体装置１において、さ
らにパワー素子から集積回路用パッドへのノイズの影響
を減少させる場合を説明するものである。図４は本発明
の第２の実施の形態に係る半導体装置の拡大断面図であ
る。(Second Embodiment) The second embodiment is directed to a case where the influence of noise from a power element to a pad for an integrated circuit is further reduced in the semiconductor device 1 according to the first embodiment. It is for explanation. FIG. 4 is an enlarged sectional view of a semiconductor device according to the second embodiment of the present invention.

【００３９】図４に示すように、第２の実施の形態に係
る半導体装置１は、パワー素子領域２２において、パワ
ー素子２２１と集積回路用パッド３２２との間にシール
ド層３０２を備える。シールド層３０２は、第２の実施
の形態において第１層目配線層に配置され、例えばアル
ミニウム合金膜で形成される。シールド層３０２には固
定電位、例えばグランド電位が供給される。As shown in FIG. 4, the semiconductor device 1 according to the second embodiment includes a shield layer 302 between the power element 221 and the integrated circuit pad 322 in the power element region 22. The shield layer 302 is disposed on the first wiring layer in the second embodiment, and is formed of, for example, an aluminum alloy film. A fixed potential, for example, a ground potential is supplied to the shield layer 302.

【００４０】図示しないが、このようなシールド層３０
２は、パワー素子領域２２において、パワー素子２２１
と他の集積回路用パッド３２１、３２３〜３２５のそれ
ぞれとの間に、さらには他のパワー素子領域２１、２
３、２４のそれぞれにおいても同様に配設される。Although not shown, such a shield layer 30
2 denotes a power element 221 in the power element region 22.
And each of the other integrated circuit pads 321, 323 to 325, and the other power element regions 21, 2
Also in each of 3 and 24, it is arrange | positioned similarly.

【００４１】このように構成される半導体装置１におい
ては、第１の実施の形態に係る半導体装置１で得られる
効果に加えて、パワー素子２１１、２２１、２３１、２
４１のそれぞれの動作で発生するノイズをシールド層３
０２で遮蔽し、ノイズが集積回路用パッド３１１〜３１
５、３２１〜３２５、３３１〜３３５、３４１〜３４５
のそれぞれに伝達される信号に乗ることを防止すること
ができるので、動作信頼性を向上させることができる。In the semiconductor device 1 thus configured, in addition to the effects obtained by the semiconductor device 1 according to the first embodiment, the power elements 211, 221, 231, 2
The noise generated by each operation of the shield layer 3
02, and the noise is reduced to the integrated circuit pads 311 to 31.
5, 321-325, 331-335, 341-345
Can be prevented from riding on the signal transmitted to each of them, so that the operation reliability can be improved.

【００４２】（第３の実施の形態）第３の実施の形態
は、第２の実施の形態に係る半導体装置１のシールド層
の変形例を説明するものである。図５は本発明の第３の
実施の形態に係る半導体装置の拡大断面図である。(Third Embodiment) A third embodiment describes a modification of the shield layer of the semiconductor device 1 according to the second embodiment. FIG. 5 is an enlarged sectional view of a semiconductor device according to the third embodiment of the present invention.

【００４３】図５に示すように、第３の実施の形態に係
る半導体装置１は、パワー素子領域２２において、パワ
ー素子２２１と集積回路用パッド３２２との間にシール
ド層１０６を備える。シールド層１０６は、第３の実施
の形態において半導体層１０３に形成された低い不純物
密度のp型ウエル領域（p型半導体領域）で形成される。
このシールド層１０６の表面部分にはコンタクト領域と
して形成された高い不純物密度のp型半導体領域９６が
形成されており、このp型半導体領域９６を通してシー
ルド層１０６には固定電位、例えばグランド電位が供給
される。As shown in FIG. 5, the semiconductor device 1 according to the third embodiment includes a shield layer 106 between the power element 221 and the integrated circuit pad 322 in the power element region 22. The shield layer 106 is formed of a low impurity density p-type well region (p-type semiconductor region) formed in the semiconductor layer 103 in the third embodiment.
A high impurity density p-type semiconductor region 96 formed as a contact region is formed on a surface portion of the shield layer 106, and a fixed potential, for example, a ground potential is supplied to the shield layer 106 through the p-type semiconductor region 96. Is done.

【００４４】図示しないが、このようなシールド層１０
６は、パワー素子領域２２において、パワー素子２２１
と他の集積回路用パッド３２１、３２３〜３２５のそれ
ぞれとの間に、さらには他のパワー素子領域２１、２
３、２４のそれぞれにおいても同様に配設される。Although not shown, such a shield layer 10
6 denotes a power element 221 in the power element region 22.
And each of the other integrated circuit pads 321, 323 to 325, and the other power element regions 21, 2
Also in each of 3 and 24, it is arrange | positioned similarly.

【００４５】このように構成される半導体装置１におい
ては、前述の第２の実施の形態に係る半導体装置１と同
様の効果を得ることができ、さらにシールド層１０６は
第１層目配線層とは異なる半導体層１０３に形成されて
いるので、第１層目配線層の配線レイアウト、特に集積
回路用パッド３１１〜３１５、３２１〜３２５、３３１
〜３３５、３４１〜３４５のそれぞれの下層の配線レイ
アウトの自由度を向上させることができる。In the semiconductor device 1 configured as described above, the same effects as those of the semiconductor device 1 according to the above-described second embodiment can be obtained. Further, the shield layer 106 is formed with the first wiring layer. Are formed in different semiconductor layers 103, so that the wiring layout of the first wiring layer, in particular, the integrated circuit pads 311 to 315, 321 to 325, 331
To 335 and 341 to 345 can be improved in the degree of freedom of the wiring layout of the lower layer.

【００４６】（第４の実施の形態）第４の実施の形態
は、第１の実施の形態に係る半導体装置１のパワー素子
の変形例を説明するものである。図６は本発明の第４の
実施の形態に係る半導体装置の拡大断面図である。(Fourth Embodiment) The fourth embodiment describes a modification of the power element of the semiconductor device 1 according to the first embodiment. FIG. 6 is an enlarged sectional view of a semiconductor device according to the fourth embodiment of the present invention.

【００４７】図６に示すように、第４の実施の形態に係
る半導体装置１においては、パワー素子２１１、２２
１、２３１、２４１のそれぞれのパワートランジスタが
横型２重拡散構造の絶縁ゲート型電界効果トランジスタ
で構成される。すなわち、このパワートランジスタは、
n型ウエル領域（半導体層１０３）で形成されるドレイ
ン領域と、p型半導体領域８で形成されるベース領域
と、n型半導体領域９０で形成されたソース領域と、半
導体層１０３上のゲート絶縁膜１７と、ゲート絶縁膜１
７上のゲート電極１８とを備えて構成される。As shown in FIG. 6, in the semiconductor device 1 according to the fourth embodiment, the power devices 211 and 22
Each of the power transistors 1, 231, and 241 is constituted by an insulated gate field effect transistor having a lateral double diffusion structure. That is, this power transistor
a drain region formed by an n-type well region (semiconductor layer 103); a base region formed by a p-type semiconductor region 8; a source region formed by an n-type semiconductor region 90; Film 17 and gate insulating film 1
7 on the gate electrode 18.

【００４８】ゲート絶縁膜１７は例えば熱酸化法で成膜
したSiO2膜で形成される。ゲート電極１８には例えば多
結晶シリコン膜が実用的に使用できる。この多結晶シリ
コン膜には抵抗値を調節する不純物、例えばAs、P、Bの
いずれかが導入される。ベース領域、ソース領域のそれ
ぞれはゲート電極１８を同一の不純物導入のマスクとし
て使用する２重拡散法で形成される。The gate insulating film 17 is formed of, for example, an SiO 2 film formed by a thermal oxidation method. For the gate electrode 18, for example, a polycrystalline silicon film can be practically used. Impurities for adjusting the resistance value, for example, any of As, P, and B are introduced into the polycrystalline silicon film. Each of the base region and the source region is formed by a double diffusion method using the gate electrode 18 as a mask for introducing the same impurity.

【００４９】このように構成される半導体装置１におい
ては、前述の第１の実施の形態に係る半導体装置１と同
様の効果を得ることができる。In the semiconductor device 1 thus configured, the same effects as those of the semiconductor device 1 according to the first embodiment can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施の形態に係る半導体装置の
平面図である。FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.

【図２】本発明の第１の実施の形態に係る半導体装置の
拡大断面図（図１のＦ２−Ｆ２切断線で切った拡大断面
図）である。FIG. 2 is an enlarged cross-sectional view (an enlarged cross-sectional view taken along a line F2-F2 in FIG. 1) of the semiconductor device according to the first embodiment of the present invention;

【図３】本発明の第１の実施の形態に係る半導体装置１
を実装した配線基板の概略断面図（図１に示すＦ３−Ｆ
３切断線部分で切った概略断面図）である。FIG. 3 is a semiconductor device 1 according to the first embodiment of the present invention.
1 is a schematic cross-sectional view of a wiring board on which is mounted (F3-F shown in FIG. 1).
FIG. 3 is a schematic cross-sectional view taken along a line 3.

【図４】本発明の第２の実施の形態に係る半導体装置の
拡大断面図である。FIG. 4 is an enlarged cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

【図５】本発明の第３の実施の形態に係る半導体装置の
拡大断面図である。FIG. 5 is an enlarged sectional view of a semiconductor device according to a third embodiment of the present invention.

【図６】本発明の第４の実施の形態に係る半導体装置の
拡大断面図である。FIG. 6 is an enlarged sectional view of a semiconductor device according to a fourth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ 半導体装置 ３ 集積回路領域 ５ 埋込層 ６，８，９０，９１，９５ 半導体領域 １０ 基板 １５ 配線基板 ２１〜２４ パワー素子領域 ４１〜４４ トレンチ構造体 ７１，４０１ トレンチ ７２，１７ ゲート絶縁膜 ７３，１８ ゲート電極 ２０１ ドレイン電極 ２０２ ソース電極 ２１１，２２１，２３１，２４１ パワー素子 ２１５，２２５，２３５，２４５ 放熱領域 ２１２，２１３，２２２，２２３，２３２，２３３，２
４２，２４３ パワー素子用パッド ３１１〜３１５，３２１〜３２５，３３１〜３３５，３
４１〜３４５ 集積回路用パッド １４１，１４２ ワイヤー １０６，３０２ シールド層 ４０２ 埋込絶縁体 ４０３ 埋込充填材REFERENCE SIGNS LIST 1 semiconductor device 3 integrated circuit area 5 buried layer 6, 8, 90, 91, 95 semiconductor area 10 substrate 15 wiring board 21 to 24 power element area 41 to 44 trench structure 71, 401 trench 72, 17 gate insulating film 73 , 18 Gate electrode 201 Drain electrode 202 Source electrode 211, 221, 231, 241 Power element 215, 225, 235, 245 Heat dissipation area 212, 213, 222, 223, 232, 233, 2
42,243 Power element pads 311 to 315,321 to 325,331 to 335,3
41 to 345 Pad for integrated circuit 141, 142 Wire 106, 302 Shield layer 402 Embedded insulator 403 Embedded filler

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 29/78 ６５３Ｄ ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 653D

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 同一基板上のパワー素子領域及び集積回
路領域と、 前記パワー素子領域の周囲を取り囲むトレンチ構造体
と、 前記パワー素子領域内のパワー素子用パッドと、 前記パワー素子領域内又は前記トレンチ構造体上の前記
パワー素子用パッドと同一配線層の集積回路用パッド
と、 を備えたことを特徴とする半導体装置。A power element region and an integrated circuit region on the same substrate; a trench structure surrounding a periphery of the power element region; a power element pad in the power element region; And a pad for an integrated circuit in the same wiring layer as the pad for the power element on the trench structure. 【請求項２】 前記パワー素子用パッド、集積回路用パ
ッドはいずれもワイヤーを通して外部装置に電気的に接
続されることを特徴とする請求項１に記載の半導体装
置。2. The semiconductor device according to claim 1, wherein both the power element pad and the integrated circuit pad are electrically connected to an external device through a wire. 【請求項３】 前記パワー素子領域と前記集積回路用パ
ッドとの間にはさらにシールド層を備えたことを特徴と
する請求項１又は請求項２に記載の半導体装置。3. The semiconductor device according to claim 1, further comprising a shield layer between the power element region and the integrated circuit pad.
JP11001259A 1999-01-06 1999-01-06 Semiconductor device Pending JP2000200905A (en)

Priority Applications (1)

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JP11001259A JP2000200905A (en) 1999-01-06 1999-01-06 Semiconductor device

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JP11001259A JP2000200905A (en) 1999-01-06 1999-01-06 Semiconductor device

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JP2000200905A true JP2000200905A (en) 2000-07-18

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Cited By (9)

* Cited by examiner, † Cited by third party
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JP2004228172A (en) * 2003-01-20 2004-08-12 Fuji Electric Device Technology Co Ltd Semiconductor device
JP2007048853A (en) * 2005-08-09 2007-02-22 Matsushita Electric Ind Co Ltd Semiconductor device
JP2008053313A (en) * 2006-08-22 2008-03-06 Denso Corp Semiconductor integrated circuit device
CN100463153C (en) * 2005-01-05 2009-02-18 国际商业机器公司 On-chip circuit pad structure and method of manufacture
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US8164197B2 (en) 2007-08-07 2012-04-24 Rohm Co., Ltd. Semiconductor device having multilayer interconnection structure
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US7944059B2 (en) 2005-08-09 2011-05-17 Panasonic Corporation Semiconductor device having a probing region
JP2008053313A (en) * 2006-08-22 2008-03-06 Denso Corp Semiconductor integrated circuit device
US8164197B2 (en) 2007-08-07 2012-04-24 Rohm Co., Ltd. Semiconductor device having multilayer interconnection structure
JP2011109074A (en) * 2009-10-22 2011-06-02 Seiko Epson Corp Integrated circuit device and electronic apparatus
JP2011187650A (en) * 2010-03-08 2011-09-22 Renesas Electronics Corp Semiconductor device
JP2014191854A (en) * 2013-03-28 2014-10-06 Rohm Co Ltd Motor drive device
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