US20120202342A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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US20120202342A1
US20120202342A1 US13/450,329 US201213450329A US2012202342A1 US 20120202342 A1 US20120202342 A1 US 20120202342A1 US 201213450329 A US201213450329 A US 201213450329A US 2012202342 A1 US2012202342 A1 US 2012202342A1
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layer
gate
electrode
semiconductor device
metal layer
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Kouji Nakajima
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof.
  • a gate lead-out electrode for leading out a gate electrode of a MOSFET cell so-called a gate finger is disposed to the outer periphery of a cell region where a number of MOSFET cells are arranged.
  • JP-A Japanese Unexamined Patent Application Publication (JP-A) No. 9-139496 (Reference 1) describes a cell region in which plural MOSFET cells 10 each having an N ⁇ type epitaxial layer 2 that functions as a drain formed on an N-semiconductor substrate 1 , a P-type well 3 and a ring-like rectangular N′ type source region 4 formed in the surface layer portion thereof and a gate electrode 6 formed via a gate oxide film 5 above the substrate so as to ride over an MOSFET cell 10 arranged in a matrix as a vertical MOSFET (refer to FIG. 6A and FIG. 6B ).
  • a source electrode 8 made of aluminum for connecting the source regions 4 of each of the MOSFET cells 10 is formed on the surface of the chip, and the source electrode 8 is connected with a source pad 11 .
  • a gate finger 13 is disposed about at the outer periphery of the cell region.
  • the gate finger 13 is disposed on the gate oxide film 5 formed above the surface of the semiconductor substrate 1 , composed of a polysilicon layer 6 a for leading out a gate formed indivisibly with the gate electrode 6 made of polysilicon and an aluminum layer 13 a disposed thereon, and is connected to a gate pad 12 .
  • the gate electrode 6 and the polysilicon layer 6 a are covered with an interlayer insulation film 7 so as not to short circuit with the source electrode 8 . Further, a drain electrode 9 made of aluminum is formed on the rear face of the semiconductor substrate 1 .
  • JP-A Japanese Unexamined Patent Application Publication
  • JP-A No. 2001-36081 Reference 2
  • JP-A and FIG. 8B Japanese Unexamined Patent Application Publication
  • a wiring pattern portion 21 is connected to the gate signal wirings 25 of the upper layer made of aluminum through plural contact vias 29 formed in a first interlayer insulation film (not illustrated). Further, the gate signal wiring 25 has a pad portion 25 a and an extension portion 25 b extending from the pad portion 25 a along a gate connection wiring portion 24 .
  • the gate signal wiring 25 is covered with a second interlayer insulation film (not illustrated).
  • a source lead-out wiring 26 and a drain lead-out wiring 27 of the upper layer made of aluminum are formed over the second interlayer insulation film.
  • an interlayer connection pad (not illustrated) is formed in the same layer with a gate signal wiring 25 for electrically connecting a source lead-out wiring 26 and a drain lead-out wiring 27 with a source region 22 and a drain region 23 , respectively.
  • FIG. 7 is a plan view schematically showing a flow of an electric current of the semiconductor device shown in FIG. 6A and FIG. 6B .
  • the source lead-out wiring 26 (source electrode) and the gate signal wiring (gate finger) 25 are formed in different layers, pattern layout for each of them can be designed flexibly.
  • a semiconductor device comprises a substrate containing a cell region in which a plurality of transistor cells are arranged; a gate electrode formed in the cell region above the substrate and made of a first conductive material; a gate lead-out electrode formed in a gate finger region different from the cell region and composed of a laminate structure including a first layer made of the first conductive material and a wiring metal layer formed on the first layer; an interlayer insulation film compose of a single layer and covering the gate electrode and the gate lead-out electrode; and a source electrode formed above the interlayer insulation film, in which an entire area of the wiring metal layer is bonded to the first layer without intervening an interlayer insulation film.
  • a method of manufacturing a semiconductor includes a cell region in which plural transistor cells are arranged, a gate electrode, and a gate lead-out electrode formed in a gate finger region different from the region where the cell region is formed.
  • the method comprises (a) forming a gate electrode and a first layer of a gate lead-out electrode with a first conductive material above a semiconductor layer; (b) forming a photoresist layer over the entire surface above the gate electrode and the first layer; (c) forming an opening in the photoresist layer so that a portion of the first layer of the gate lead-out electrode is exposed; (d) depositing a wiring metal layer on the photoresist layer and the portion of the first layer of the gate lead-out electrode which is exposed via the opening; (e) lifting-off the wiring metal layer formed on the photoresist layer with the photoresist layer; (f) forming an interlayer insulation film over the entire surface including the first layer and the wiring metal layer; (g) selectively removing the interlayer
  • the metal wiring layer of the gate lead-out electrode pattern is formed by a lift-off method using the photoresist layer as a mask, it is not necessary to form the interlayer insulation film for protecting the gate electrode upon patterning the metal wiring layer. Accordingly, the gate electrode and the gate lead-out electrode can be covered by the formation of a single interlayer insulation film. This can dispose the gate lead-out electrode and the source electrode in different layers without increasing the number of interlayer insulation films.
  • the gate lead-out electrode and the source electrode can be formed in different layers without increasing the chip thickness and the pattern lay out for each of them can be designed flexibly. Accordingly, increase of the on-resistance of the semiconductor device can also be prevented. Further, potential for increasing the cracking or peeling of the interlayer insulation film can also be prevented.
  • FIG. 1A is a perspective view showing a semiconductor device 100 in one embodiment of the present invention.
  • FIG. 1B is a cross sectional view along line I-I in FIG. 1A ;
  • FIG. 2 is a perspective view schematically showing each of the layers in the semiconductor device 100 ;
  • FIGS. 3A to 3D and FIGS. 4A and 4B are cross sectional views for the steps showing a method of manufacturing the semiconductor device 100 ;
  • FIG. 5 is a cross sectional view showing a semiconductor device 200 as a modified example in one embodiment of the present invention.
  • FIG. 6A is a perspective view showing a semiconductor device of the prior art disclosed in Reference 1;
  • FIG. 6B is a cross sectional view along line II-II in FIG. 6A ;
  • FIG. 7 is a plan view schematically showing a problem in the semiconductor device of the prior art disclosed in Reference 1;
  • FIGS. 8A and 8B are plan views showing the semiconductor device of the prior art disclosed in Reference 2.
  • FIG. 9 is a cross sectional view showing a semiconductor device 300 as another modified example of one embodiment of the present invention.
  • FIG. 1A is a perspective view showing a semiconductor device 100 in one embodiment of the present invention and FIG. 1B is a cross sectional view along line I-I in FIG. 1A .
  • FIG. 2 is a perspective view schematically showing each of layers in the semiconductor device 100 .
  • a lattice-lines illustrated to the inside of a polysilicon layer 6 a in FIG. 2 are schematic sketch for plural electrodes 6 arranged in a lattice in a cell region.
  • the semiconductor device 100 includes a semiconductor substrate 1 including a cell region where plural MOSFET cells 10 are arranged, and a gate electrode 6 formed of a polysilicon (first conductive material) formed in the cell region above the semiconductor substrate 1 .
  • a gate finger region is formed in a region different from the region formed with the cell region above the semiconductor substrate 1 , and a polysilicon layer (first layer) 6 a of a material identical with the gate electrode 6 is formed.
  • a wiring metal layer 103 b is laminated on the polysilicon layer 6 a and the polysilicon layer 6 a and the wiring metal layer 103 b constitute a gate lead-out electrode 103 .
  • An interlayer insulation film 7 (for example, BPSG film (silicon oxide film containing boron glass and phosphor glass)) is formed so as to cover the gate electrode 6 and the gate lead-out electrode 103 and a source electrode 108 is formed on the interlayer insulation film 7 .
  • BPSG film silicon oxide film containing boron glass and phosphor glass
  • the gate lead-out electrode 103 may further contain an adhesion metal layer 103 a between the polysilicon layer 6 a and the wiring metal layer 103 b in contact with them.
  • the bottom face of the adhesion metal layer 103 a is in close contact at the entire surface thereof with the polysilicon layer 6 a and no interlayer insulation film is formed therebetween.
  • a cell region where a number of MOSFET cells 10 are arranged in a matrix is formed above the semiconductor substrate 1 .
  • the N + type source region 4 in each MOSFET cell 10 is connected to the source electrode 108 .
  • the source electrode 108 is connected with a source pad 11 .
  • an N ⁇ type epitaxial layer 2 is formed on the N-type semiconductor substrate 1 and functions as a drain region of the MOSFET.
  • a P-type well (base region) 3 is formed in the surface layer portion of the N ⁇ type epitaxial layer 2
  • an N + type source region 4 is formed in the surface layer portion of the P-type well 3 .
  • the gate electrode 6 is formed so as to override the MOSFET cells 10 via the gate oxide film 5 .
  • the source electrode 108 is formed over the entire surface of the cell region when viewed in a plane. That is, the source electrode 108 is formed as a wide pattern covering the upper surface of the gate lead-out electrode 103 , which does not cause division and round about of the current path as has been described for FIG. 7 . This can lower the on-resistance.
  • the material for the source electrode 108 is not particularly restricted and formed, for example, of aluminum.
  • a recess 108 a is formed to a portion of the source electrode 108 at a position where the gate pad 12 is formed.
  • a contact via 107 a is formed to a portion of the interlayer insulation film 7 at a position where the gate pad 12 is formed.
  • the gate pad 12 is exposed through the contact via 107 a and the recess 108 a .
  • plural contact vias 7 a are formed in the interlayer insulation film 7 for electrically connecting the source region 4 , the well 3 , and the source electrode 108 .
  • the material for the gate electrode 6 is not particularly restricted and for example, formed of polysilicon.
  • the gate electrode 6 is formed of a polysilicon layer 6 a (first layer).
  • the gate electrode 6 and the polysilicone layer 6 a of the gate lead-out electrode 103 are formed of a single layer. That is, since the gate electrode 6 and the polysilicon layer 6 a of the gate lead-out electrode 103 are formed indivisibly, they are connected electrically.
  • the gate electrode 6 and the polysilicon layer 6 a of the gate lead-out electrode 103 are disposed on the gate oxide film 5 formed on the epitaxial layer 2 .
  • the gate electrode 6 and the polysilicon layer 6 a of the gate lead-out electrode 103 have the same layer structure in the cross section.
  • the gate lead-out electrode 103 is formed in the gate finger region different from the cell region.
  • the gate electrode 6 is formed in the cell region. That is, the gate lead-out electrode 103 may be disposed so as to cross or transverse the cell region such that a gate voltage is distributed uniformly over the entire cell region.
  • the gate pad 12 is connected to the gate lead-out electrode 103 and they are formed indivisibly in one common layer.
  • the gate lead-out electrode 103 has a laminate structure where the polysilicon layer 6 a , the adhesion metal layer 103 a , and the wiring metal layer 103 b are laminated successively. That is, the entire bottom surface of the adhesion metal layer 103 a is in close contact with the polysilicon layer 6 a . Accordingly, the interlayer insulation film 7 is not formed between the wiring metal layer 103 b and the polysilicon layer 6 a , but covers the wiring metal layer 103 b , the adhesion metal layer 103 a and the polysilicon layer 6 a . That is, there is no need for forming the first interlayer insulation film or making contact vias 29 in the first interlayer insulation film as described above with referring to FIG. 8A .
  • the adhesion metal layer 103 a is disposed between the polysilicon layer 6 a and the wiring metal layer 103 b in contact with them. That is, the adhesion metal layer 103 a has the same pattern as the wiring metal layer 103 b.
  • the material for the wiring metal layer 103 b is not particularly restricted and it is preferably a material of a resistance lower than that of the polysilicon (first conductive material).
  • the wiring metal layer 103 b is formed, for example, of aluminum.
  • the material for the adhesion metal layer 103 a is not particularly restricted.
  • the adhesion metal layer 103 a includes, for example, a laminate film where a titanium film 103 ab and a titanium nitride film 103 aa are laminated in this order above the polysilicon layer 6 a.
  • the titanium nitride film 103 aa in the upper layer can function as a barrier for suppressing junction breakage (alloy spike failure) and/or conduction failure caused by leaching of silicon in the polysilicon layer (a into aluminum of the wiring metal layer 103 b . This can further ensure the adhesiveness between the polysilicon layer 6 a and the wiring metal 103 b . Further, the titanium film 103 ab in the lower layer can prevent nitrogen (N) in the titanium nitride film 103 aa from introducing into silicon in the polysilicon layer 6 a.
  • the adhesion metal layer 103 a is in direct contact over the entire area of the bottom face thereof not by way of a contact plug, etc. with the polysilicon layer 6 a and the wiring metal layer 103 being laminated therebetween. Accordingly, even when the electric conductivity of the adhesion metal layer 103 a is somewhat high, increase of the wiring resistance is offset by the increase of the contact area. Accordingly, increase of the contact resistance between the wiring metal layer 103 b and the polysilicon layer 6 a can be suppressed.
  • the thickness of the laminate film is not particularly restricted, the thickness may be, for example, about 3 nm for the titanium nitride film 103 aa and about 13 nm for the titanium film 103 ab .
  • the thickness of the wiring metal layer 103 b is preferably about 1 ⁇ m. This can inhibit formation of evenness in the source electrode 108 of the upper layer.
  • the interlayer insulation film 7 is a single layer formed above the gate electrode 6 and the gate lead-out gate 103 for covering the gate electrode 6 and the gate lead-out gate 103 . Since the source electrode 108 can be formed above the gate lead-out gate 103 via the interlayer insulation film 7 , the source electrode 108 and the gate lead-out gate 103 can be disposed in different layers. Further, the interlayer insulation film 7 can suppress short circuit between the gate electrode 6 and the gate lead-out electrode 103 and the source electrode 108 .
  • a drain electrode 9 is formed to the semiconductor substrate 1 on the side of the rear face.
  • the drain electrode 9 is formed, for example, of aluminum.
  • the MOSFET cell 10 is not disposed but a P-type second well 14 is formed.
  • the gate pad 12 has a laminate structure where the polysilicon layer 6 a , the adhesion metal layer 103 a , and the wiring metal layer 103 b are laminated successively (not illustrated).
  • Provision of the P-type second well 14 serves as a diode with the N ⁇ type epitaxial layer 2 to improve the breakdown voltage by enhancing the expansion of a depletion layer from the junction between the N ⁇ type epitaxial layer 2 and the P-type second well 14 below the gate pad 12 and the gate lead-out electrode 103 , when an inverse or reverse voltage is applied between the drain and the source.
  • FIGS. 3A to 3D and FIGS. 4A and 4B are cross sectional views for the steps showing the method of manufacturing the semiconductor device in this embodiment.
  • a P-type second well 14 is formed in a predetermined region of an N ⁇ type epitaxial layer 2 by using a photolithographic method and an ion implantation method. Then, a gate oxide film 5 of a predetermined pattern is formed on the epitaxial layer 2 by using a photolithographic method and etching treatment.
  • a polysilicon layer (first conductive material) is formed on the gate oxide film 5 .
  • the polysilicon layer is selectively removed by using a photolithographic method and a dry etching method (patterning) to form a gate electrode 6 and a polysilicon layer 6 a of a gate lead-out electrode 103 .
  • the gate electrode 6 and the polysilicon layer 6 a for the gate lead-out electrode 103 are formed indivisibly.
  • a P-type well 3 and an N + type source region 4 are formed by an ion implantation and diffusion method.
  • a cross sectional structure shown in FIG. 3A is formed.
  • a gate oxide film 5 is formed by thermal oxidation or chemical vapor deposition (CVD). Then, a polysilicon layer (first conductive material) is formed on the gate oxide film 5 . Then, the gate electrode 6 and the polysilicon layer 6 a of the gate lead-out gate 103 are patterned by using a photolithographic method and a dry etching method, and the gate oxide film 5 is etched selectively by using a polysilicon pattern as a mask.
  • a photoresist layer PR is formed over the entire surface above the gate electrode 6 , and the polysilicon layer 6 a (first layer) of the gate lead-out electrode 103 , and an opening is formed in the photoresist layer PR for partially opening the gate lead-out electrode 103 . That is, a portion of the polysilicon layer 6 a is exposed and other regions than described above are covered with the photoresist layer PR.
  • a adhesion metal layer 103 a such as a titanium film 103 ab and a titanium nitride film 103 aa is formed over the entire surface while leaving the photoresist layer PR, and the adhesion metal layer 103 a is deposited on the polysilicon layer 6 a exposed through the opening in the photoresist layer PR.
  • a titanium film 103 ab and a titanium nitride film 103 aa are deposited in this order.
  • the film thickness can be made as about 13 nm for the titanium film 103 ab and about 3 nm for the titanium nitride film 103 aa.
  • a wiring metal layer 103 b is formed over the entire surface and a wiring metal layer 103 b is deposited just above the adhesion metal layer 103 a .
  • the adhesion metal layer 103 a and the wiring metal layer 103 b are formed by a sputtering method or a vapor deposition method.
  • An aluminum film is deposited, for example, as the wiring metal layer 103 b and the film thickness thereof can be made to about 1 ⁇ m.
  • the photoresist layer PR is removed by a lift-off method, and the adhesion metal layer 103 a and the wiring metal layer 103 b deposited above the photoresist layer PR are removed.
  • the adhesion metal layer 103 a and the wiring metal layer 103 b of a predetermined pattern are left on the polysilicon layer 6 a , to form a gate lead-out electrode 103 having a laminate structure composed of the polysilicon layer 6 a , the adhesion metal layer 103 a , and the wiring metal layer 103 b.
  • An interlayer insulation film 7 is formed over the entire surface including the gate electrode 6 and the gate lead-out electrode 103 (polysilicon layer 6 a , adhesion metal layer 103 a , and wiring metal layer 103 b ) so as to cover them.
  • the interlayer insulation film 7 is removed selectively to form contact via 7 a reaching the source region 4 and the well 3 .
  • a contact via 107 a corresponding to the gate pad 12 shown in FIG. 2 is formed.
  • a source electrode 108 is formed over the interlayer insulation film 7 , and the source electrode 108 is connected electrically with the source region 4 and the well 3 .
  • the drain electrode 9 shown in FIG. 1B is formed to the semiconductor substrate 1 on the side of the rear face to obtain a semiconductor device 100 as a vertical power MOSFET.
  • the effect of this embodiment is to be described.
  • the method of manufacturing the semiconductor device 100 since the pattern for the wiring metal layer 103 b of the gate lead-out electrode 103 is formed by the lift-off method using the photoresist layer PR as a mask, it is not necessary to form an interlayer insulation film for protecting the gate electrode 6 upon patterning the wiring metal layer 103 b and it may suffice that only the interlayer insulation film 7 covering the gate electrode 6 and the gate lead-out electrode 103 may be formed as the interlayer insulation film.
  • the gate lead-out electrode 103 and the source electrode 108 can be disposed in different layers without increasing the number of layers for the interlayer insulation film.
  • the source electrode 108 can be formed so as to cover the gate lead-out electrode 103 from above without increasing the thickness of the chip and a design flexibility for a patterning layout can be enhanced. Therefore, this dose not cause branching or round about of the current path as has been described for FIG. 7 and increase of the on-resistance of the semiconductor device 100 can also be prevented. Further, increase of the potential for the cracking or peeling of the interlayer insulation film 7 can also be prevented.
  • the design flexibility for the patterning layout of the gate lead-out electrode 103 and the source electrode 108 can be enhanced without increasing the thickness of the semiconductor device 100 .
  • a vertical power MOSFET in which the gate electrode is disposed above the substrate, it may be a semiconductor device 200 as a vertical power MOSFET having a trench gate structure as shown, for example, in FIG. 5 . Since other structures of the semiconductor device 200 are identical with those of the semiconductor device 100 , descriptions therefor are to be omitted.
  • a gate electrode 6 is buried in the inside of a trench, a polysilicon layer constituting the gate electrode 6 is led out above the epitaxial layer 2 in a not illustrated region and formed as one pattern formed indivisibly in a common layer with polysilicon layer 6 a of a gate lead-out electrode 103 . That is, also in the trench gate structure, the gate electrode 6 and the polysilicon layer 6 a of the gate lead-out electrode 103 are formed in one identical step.
  • the design flexibility of the patterning layout can be improved and the same effect as in the semiconductor device 100 can be obtained also in the semiconductor device 200 .
  • the interlayer insulation film 7 may also be a laminate film made of plural different materials.
  • the insulation material for the interlayer insulation film 7 may include, for example, as shown in a semiconductor device 300 in FIG. 9 , a laminate film formed by laminating a BPSG (Boron Phosphorus Silicate Glass) film with good planarity as an upper layer and an NSG (Non-doped Silicate Glass) film as a barrier layer for preventing downward diffusion of boron or phosphorus from the BPSG film as a lower layer. Since other structures of the semiconductor device 300 are identical with those of the semiconductor device 100 , descriptions therefor are to be omitted.
  • BPSG Bipolar Phosphorus Silicate Glass
  • the wiring metal layer 103 b may also be a material containing at least one of aluminum, copper, and tungsten.
  • the wiring metal layer may be formed of an alloy film containing aluminum or an alloy film containing copper. Use of tungsten can prevent occurrence of migration and/or aluminum spike. However, in a case of using tungsten, it is desirable that increase in the wiring resistance may be permitted.
  • the channel type may also be the P-channel type. That is, the conduction type may be reversed for all impurities.
  • IGBT Insulated Gate Bipolar Transistor
  • An IGBT can be constituted, for example, by using a P-type semiconductor substrate as the semiconductor substrate 1 in FIG. 1B .

Abstract

A method of manufacturing a semiconductor device includes depositing a wiring metal layer on a photoresist layer and a portion of a first layer of a gate lead-out electrode which is exposed via an opening, lifting-off a wiring metal layer formed on the photoresist layer forming an interlayer insulation film over the entire surface including the first layer and the wiring metal layer, selectively removing the interlayer insulation film thereby forming a contact via reaching a source region formed in a cell region, and forming a source electrode on the interlayer insulation film and electrically connecting a source electrode with the source region.

Description

  • The present application is a Divisional Application of U.S. patent application Ser. No. 12/588,392, filed on Oct. 14, 2009, which is based on Japanese patent application No. 2008-267840, filed on Oct. 16, 2008, and Japanese patent application No. 2009-138631, filed on Jun. 9, 2009, the entire contents of which is incorporated herein by reference.
    • BACKGROUND
  • 1. Field of the Invention
  • The present invention relates to a semiconductor device and a manufacturing method thereof.
  • 2. Description of Related Art
  • In semiconductor devices such as a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor), a gate lead-out electrode for leading out a gate electrode of a MOSFET cell, so-called a gate finger is disposed to the outer periphery of a cell region where a number of MOSFET cells are arranged.
  • Japanese Unexamined Patent Application Publication (JP-A) No. 9-139496 (Reference 1) describes a cell region in which plural MOSFET cells 10 each having an N− type epitaxial layer 2 that functions as a drain formed on an N-semiconductor substrate 1, a P-type well 3 and a ring-like rectangular N′ type source region 4 formed in the surface layer portion thereof and a gate electrode 6 formed via a gate oxide film 5 above the substrate so as to ride over an MOSFET cell 10 arranged in a matrix as a vertical MOSFET (refer to FIG. 6A and FIG. 6B).
  • As shown in FIG. 6B, a source electrode 8 made of aluminum for connecting the source regions 4 of each of the MOSFET cells 10 is formed on the surface of the chip, and the source electrode 8 is connected with a source pad 11.
  • Further, as shown in FIG. 6A, a gate finger 13 is disposed about at the outer periphery of the cell region.
  • Further, the gate finger 13 is disposed on the gate oxide film 5 formed above the surface of the semiconductor substrate 1, composed of a polysilicon layer 6 a for leading out a gate formed indivisibly with the gate electrode 6 made of polysilicon and an aluminum layer 13 a disposed thereon, and is connected to a gate pad 12.
  • Further, the gate electrode 6 and the polysilicon layer 6 a are covered with an interlayer insulation film 7 so as not to short circuit with the source electrode 8. Further, a drain electrode 9 made of aluminum is formed on the rear face of the semiconductor substrate 1.
  • On the other hand, Japanese Unexamined Patent Application Publication (JP-A) No. 2001-36081 (Reference 2) describes a constitution in which gate signal wirings made of aluminum extending in the direction where plural gate electrode portions are arranged by way of an interlayer insulation film above a polysilicon wirings of a DMOSFET formed in a ladder-shape, and the gate signal wirings thereof are electrically connected with the polysilicon wirings through plural contact vias (refer to FIG. 8A and FIG. 8B).
  • As shown in FIG. 8A, a wiring pattern portion 21 is connected to the gate signal wirings 25 of the upper layer made of aluminum through plural contact vias 29 formed in a first interlayer insulation film (not illustrated). Further, the gate signal wiring 25 has a pad portion 25 a and an extension portion 25 b extending from the pad portion 25 a along a gate connection wiring portion 24.
  • As shown in FIG. 8B, the gate signal wiring 25 is covered with a second interlayer insulation film (not illustrated). A source lead-out wiring 26 and a drain lead-out wiring 27 of the upper layer made of aluminum are formed over the second interlayer insulation film.
  • Further, reference 2 describes that an interlayer connection pad (not illustrated) is formed in the same layer with a gate signal wiring 25 for electrically connecting a source lead-out wiring 26 and a drain lead-out wiring 27 with a source region 22 and a drain region 23, respectively.
  • However, the present inventor considers that the prior art described above involves the following problems and a further improvement is necessary therefor. The problems in the technique described for FIG. 6A and FIG. 6B to be described with reference to FIG. 7. FIG. 7 is a plan view schematically showing a flow of an electric current of the semiconductor device shown in FIG. 6A and FIG. 6B.
  • In the vertical power MOSFET described above, current flows to a source electrode 8 as shown in FIG. 7. In this case, since the source electrode 8 and a gate finger 13 are formed in a common layer, it is necessary that the source electrode 8 is arranged so as not to overlap the gate finger 13. Since the gate finger 13 is arranged in a state of intruding into the cell region so as to traverse the cell region, the current branches into a current Iinside flowing in the source electrode 8 inside of the gate finger 13 and a current Ioutside flowing in the outside source electrode 8 of the gate finger 13. As shown in FIG. 7, since the current Ioutside has to flow through a path round about the gate finger 13 and the current path is made longer by so much when compared with the current Iinside. As a result, this increases the entire on-resistance of the vertical power MOSFET.
  • On the other hand, in the technique described for FIG. 8A and FIG. 8B, since the source lead-out wiring 26 (source electrode) and the gate signal wiring (gate finger) 25 are formed in different layers, pattern layout for each of them can be designed flexibly. However, this involves a problem that the number of steps of forming the interlayer insulation film increases more compared with the semiconductor device shown in FIG. 6A and FIG. 6B. That is, when the gate signal wiring 25 made of aluminum is patterned, it is necessary to form an interlayer insulation film for protecting the polysilicon wiring in the lower layer and an interlayer insulation film for insulating the gate signal wiring 25 and the source lead-out wiring 26. Further, increase in the number of the layers for the interlayer insulation film is not preferred since this increases the chip thickness and may possibly increase the frequency for the occurrence of cracking or peeling in the interlayer insulation film.
    • SUMMARY
  • In one aspect of the present invention, a semiconductor device comprises a substrate containing a cell region in which a plurality of transistor cells are arranged; a gate electrode formed in the cell region above the substrate and made of a first conductive material; a gate lead-out electrode formed in a gate finger region different from the cell region and composed of a laminate structure including a first layer made of the first conductive material and a wiring metal layer formed on the first layer; an interlayer insulation film compose of a single layer and covering the gate electrode and the gate lead-out electrode; and a source electrode formed above the interlayer insulation film, in which an entire area of the wiring metal layer is bonded to the first layer without intervening an interlayer insulation film.
  • In another aspect of the present invention, a method of manufacturing a semiconductor includes a cell region in which plural transistor cells are arranged, a gate electrode, and a gate lead-out electrode formed in a gate finger region different from the region where the cell region is formed. The method comprises (a) forming a gate electrode and a first layer of a gate lead-out electrode with a first conductive material above a semiconductor layer; (b) forming a photoresist layer over the entire surface above the gate electrode and the first layer; (c) forming an opening in the photoresist layer so that a portion of the first layer of the gate lead-out electrode is exposed; (d) depositing a wiring metal layer on the photoresist layer and the portion of the first layer of the gate lead-out electrode which is exposed via the opening; (e) lifting-off the wiring metal layer formed on the photoresist layer with the photoresist layer; (f) forming an interlayer insulation film over the entire surface including the first layer and the wiring metal layer; (g) selectively removing the interlayer insulation film thereby forming a contact via reaching the source region formed in the cell region; and (h) forming a source electrode on the interlayer insulation film and electrically connecting the source electrode with the source region.
  • According to the present invention, since the metal wiring layer of the gate lead-out electrode pattern is formed by a lift-off method using the photoresist layer as a mask, it is not necessary to form the interlayer insulation film for protecting the gate electrode upon patterning the metal wiring layer. Accordingly, the gate electrode and the gate lead-out electrode can be covered by the formation of a single interlayer insulation film. This can dispose the gate lead-out electrode and the source electrode in different layers without increasing the number of interlayer insulation films.
  • Since the number of layers for the interlayer insulation films is not increased by the constitution of covering the gate electrode and the gate lead-out electrode by the single interlayer insulation film, the gate lead-out electrode and the source electrode can be formed in different layers without increasing the chip thickness and the pattern lay out for each of them can be designed flexibly. Accordingly, increase of the on-resistance of the semiconductor device can also be prevented. Further, potential for increasing the cracking or peeling of the interlayer insulation film can also be prevented.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
  • FIG. 1A is a perspective view showing a semiconductor device 100 in one embodiment of the present invention,
  • FIG. 1B is a cross sectional view along line I-I in FIG. 1A;
  • FIG. 2 is a perspective view schematically showing each of the layers in the semiconductor device 100;
  • FIGS. 3A to 3D and FIGS. 4A and 4B are cross sectional views for the steps showing a method of manufacturing the semiconductor device 100;
  • FIG. 5 is a cross sectional view showing a semiconductor device 200 as a modified example in one embodiment of the present invention;
  • FIG. 6A is a perspective view showing a semiconductor device of the prior art disclosed in Reference 1;
  • FIG. 6B is a cross sectional view along line II-II in FIG. 6A;
  • FIG. 7 is a plan view schematically showing a problem in the semiconductor device of the prior art disclosed in Reference 1;
  • FIGS. 8A and 8B are plan views showing the semiconductor device of the prior art disclosed in Reference 2; and
  • FIG. 9 is a cross sectional view showing a semiconductor device 300 as another modified example of one embodiment of the present invention.
    •  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The invention will now be described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.
  • Prefer embodiments of a semiconductor device and a manufacturing method thereof according to the present invention are to be described specifically with reference to the drawings. In the description for the drawings, identical elements carry identical reference numerals for which duplicate descriptions am to be omitted.
  • FIG. 1A is a perspective view showing a semiconductor device 100 in one embodiment of the present invention and FIG. 1B is a cross sectional view along line I-I in FIG. 1A. FIG. 2 is a perspective view schematically showing each of layers in the semiconductor device 100. A lattice-lines illustrated to the inside of a polysilicon layer 6 a in FIG. 2 are schematic sketch for plural electrodes 6 arranged in a lattice in a cell region.
  • The semiconductor device 100 includes a semiconductor substrate 1 including a cell region where plural MOSFET cells 10 are arranged, and a gate electrode 6 formed of a polysilicon (first conductive material) formed in the cell region above the semiconductor substrate 1. A gate finger region is formed in a region different from the region formed with the cell region above the semiconductor substrate 1, and a polysilicon layer (first layer) 6 a of a material identical with the gate electrode 6 is formed. A wiring metal layer 103 b is laminated on the polysilicon layer 6 a and the polysilicon layer 6 a and the wiring metal layer 103 b constitute a gate lead-out electrode 103. An interlayer insulation film 7 (for example, BPSG film (silicon oxide film containing boron glass and phosphor glass)) is formed so as to cover the gate electrode 6 and the gate lead-out electrode 103 and a source electrode 108 is formed on the interlayer insulation film 7.
  • Further, the gate lead-out electrode 103 may further contain an adhesion metal layer 103 a between the polysilicon layer 6 a and the wiring metal layer 103 b in contact with them.
  • The bottom face of the adhesion metal layer 103 a is in close contact at the entire surface thereof with the polysilicon layer 6 a and no interlayer insulation film is formed therebetween.
  • As shown in FIG. 1A, a cell region where a number of MOSFET cells 10 are arranged in a matrix is formed above the semiconductor substrate 1. The N+ type source region 4 in each MOSFET cell 10 is connected to the source electrode 108. Further, the source electrode 108 is connected with a source pad 11.
  • As shown in FIG. 1B, an N− type epitaxial layer 2 is formed on the N-type semiconductor substrate 1 and functions as a drain region of the MOSFET. A P-type well (base region) 3 is formed in the surface layer portion of the N− type epitaxial layer 2, and an N+ type source region 4 is formed in the surface layer portion of the P-type well 3. The gate electrode 6 is formed so as to override the MOSFET cells 10 via the gate oxide film 5.
  • The source electrode 108 is formed over the entire surface of the cell region when viewed in a plane. That is, the source electrode 108 is formed as a wide pattern covering the upper surface of the gate lead-out electrode 103, which does not cause division and round about of the current path as has been described for FIG. 7. This can lower the on-resistance. The material for the source electrode 108 is not particularly restricted and formed, for example, of aluminum.
  • As shown in FIG. 2, a recess 108 a is formed to a portion of the source electrode 108 at a position where the gate pad 12 is formed.
  • Further, a contact via 107 a is formed to a portion of the interlayer insulation film 7 at a position where the gate pad 12 is formed. The gate pad 12 is exposed through the contact via 107 a and the recess 108 a. Further, plural contact vias 7 a are formed in the interlayer insulation film 7 for electrically connecting the source region 4, the well 3, and the source electrode 108.
  • The material for the gate electrode 6 is not particularly restricted and for example, formed of polysilicon. In the semiconductor device 100, the gate electrode 6 is formed of a polysilicon layer 6 a (first layer). Further, as shown in FIG. 2, the gate electrode 6 and the polysilicone layer 6 a of the gate lead-out electrode 103 are formed of a single layer. That is, since the gate electrode 6 and the polysilicon layer 6 a of the gate lead-out electrode 103 are formed indivisibly, they are connected electrically.
  • In the semiconductor device 100, as shown in FIG. 1B, the gate electrode 6 and the polysilicon layer 6 a of the gate lead-out electrode 103 are disposed on the gate oxide film 5 formed on the epitaxial layer 2. The gate electrode 6 and the polysilicon layer 6 a of the gate lead-out electrode 103 have the same layer structure in the cross section.
  • As shown in FIG. 2, the gate lead-out electrode 103 is formed in the gate finger region different from the cell region. On the other hand, the gate electrode 6 is formed in the cell region. That is, the gate lead-out electrode 103 may be disposed so as to cross or transverse the cell region such that a gate voltage is distributed uniformly over the entire cell region. Further, the gate pad 12 is connected to the gate lead-out electrode 103 and they are formed indivisibly in one common layer.
  • The gate lead-out electrode 103 has a laminate structure where the polysilicon layer 6 a, the adhesion metal layer 103 a, and the wiring metal layer 103 b are laminated successively. That is, the entire bottom surface of the adhesion metal layer 103 a is in close contact with the polysilicon layer 6 a. Accordingly, the interlayer insulation film 7 is not formed between the wiring metal layer 103 b and the polysilicon layer 6 a, but covers the wiring metal layer 103 b, the adhesion metal layer 103 a and the polysilicon layer 6 a. That is, there is no need for forming the first interlayer insulation film or making contact vias 29 in the first interlayer insulation film as described above with referring to FIG. 8A.
  • The adhesion metal layer 103 a is disposed between the polysilicon layer 6 a and the wiring metal layer 103 b in contact with them. That is, the adhesion metal layer 103 a has the same pattern as the wiring metal layer 103 b.
  • The material for the wiring metal layer 103 b is not particularly restricted and it is preferably a material of a resistance lower than that of the polysilicon (first conductive material). In the semiconductor device 100, the wiring metal layer 103 b is formed, for example, of aluminum.
  • On the other hand, the material for the adhesion metal layer 103 a is not particularly restricted. In the semiconductor device 100, the adhesion metal layer 103 a includes, for example, a laminate film where a titanium film 103 ab and a titanium nitride film 103 aa are laminated in this order above the polysilicon layer 6 a.
  • The effect due to the laminate film of the adhesion metal layer 103 a in the semiconductor device 100 is to be described below.
  • In the adhesion metal layer 103 a the titanium nitride film 103 aa in the upper layer can function as a barrier for suppressing junction breakage (alloy spike failure) and/or conduction failure caused by leaching of silicon in the polysilicon layer (a into aluminum of the wiring metal layer 103 b. This can further ensure the adhesiveness between the polysilicon layer 6 a and the wiring metal 103 b. Further, the titanium film 103 ab in the lower layer can prevent nitrogen (N) in the titanium nitride film 103 aa from introducing into silicon in the polysilicon layer 6 a.
  • Further, the adhesion metal layer 103 a is in direct contact over the entire area of the bottom face thereof not by way of a contact plug, etc. with the polysilicon layer 6 a and the wiring metal layer 103 being laminated therebetween. Accordingly, even when the electric conductivity of the adhesion metal layer 103 a is somewhat high, increase of the wiring resistance is offset by the increase of the contact area. Accordingly, increase of the contact resistance between the wiring metal layer 103 b and the polysilicon layer 6 a can be suppressed.
  • Further, while the thickness of the laminate film is not particularly restricted, the thickness may be, for example, about 3 nm for the titanium nitride film 103 aa and about 13 nm for the titanium film 103 ab. In this case, the thickness of the wiring metal layer 103 b is preferably about 1 μm. This can inhibit formation of evenness in the source electrode 108 of the upper layer.
  • The interlayer insulation film 7 is a single layer formed above the gate electrode 6 and the gate lead-out gate 103 for covering the gate electrode 6 and the gate lead-out gate 103. Since the source electrode 108 can be formed above the gate lead-out gate 103 via the interlayer insulation film 7, the source electrode 108 and the gate lead-out gate 103 can be disposed in different layers. Further, the interlayer insulation film 7 can suppress short circuit between the gate electrode 6 and the gate lead-out electrode 103 and the source electrode 108.
  • A drain electrode 9 is formed to the semiconductor substrate 1 on the side of the rear face. The drain electrode 9 is formed, for example, of aluminum.
  • Further, in the region where the gate pad 12 and the gate lead-out electrode 103 are disposed, the MOSFET cell 10 is not disposed but a P-type second well 14 is formed. The gate pad 12 has a laminate structure where the polysilicon layer 6 a, the adhesion metal layer 103 a, and the wiring metal layer 103 b are laminated successively (not illustrated).
  • Provision of the P-type second well 14 serves as a diode with the N− type epitaxial layer 2 to improve the breakdown voltage by enhancing the expansion of a depletion layer from the junction between the N− type epitaxial layer 2 and the P-type second well 14 below the gate pad 12 and the gate lead-out electrode 103, when an inverse or reverse voltage is applied between the drain and the source.
  • An example of a method of manufacturing the semiconductor device 100 is to be described with reference to FIGS. 3A to 3D and FIGS. 4A and 4B. FIGS. 3A to 3D and FIGS. 4A and 4B are cross sectional views for the steps showing the method of manufacturing the semiconductor device in this embodiment.
  • At first, a P-type second well 14 is formed in a predetermined region of an N− type epitaxial layer 2 by using a photolithographic method and an ion implantation method. Then, a gate oxide film 5 of a predetermined pattern is formed on the epitaxial layer 2 by using a photolithographic method and etching treatment.
  • Then, a polysilicon layer (first conductive material) is formed on the gate oxide film 5.
  • Then, the polysilicon layer is selectively removed by using a photolithographic method and a dry etching method (patterning) to form a gate electrode 6 and a polysilicon layer 6 a of a gate lead-out electrode 103. Thus, the gate electrode 6 and the polysilicon layer 6 a for the gate lead-out electrode 103 are formed indivisibly.
  • Subsequently, a P-type well 3 and an N+ type source region 4 are formed by an ion implantation and diffusion method. Thus, a cross sectional structure shown in FIG. 3A is formed.
  • From the step for forming the gate oxide film 5 to the patterning step for the polysilicon layer may also be effected as described below. After forming a P-type second well 14 in a predetermined region of an epitaxial layer 2, a gate oxide film 5 is formed by thermal oxidation or chemical vapor deposition (CVD). Then, a polysilicon layer (first conductive material) is formed on the gate oxide film 5. Then, the gate electrode 6 and the polysilicon layer 6 a of the gate lead-out gate 103 are patterned by using a photolithographic method and a dry etching method, and the gate oxide film 5 is etched selectively by using a polysilicon pattern as a mask.
  • Then, as shown in FIG. 3B, a photoresist layer PR is formed over the entire surface above the gate electrode 6, and the polysilicon layer 6 a (first layer) of the gate lead-out electrode 103, and an opening is formed in the photoresist layer PR for partially opening the gate lead-out electrode 103. That is, a portion of the polysilicon layer 6 a is exposed and other regions than described above are covered with the photoresist layer PR.
  • Then, as shown in FIG. 3C, a adhesion metal layer 103 a such as a titanium film 103 ab and a titanium nitride film 103 aa is formed over the entire surface while leaving the photoresist layer PR, and the adhesion metal layer 103 a is deposited on the polysilicon layer 6 a exposed through the opening in the photoresist layer PR. As the adhesion metal layer 103 a, for example, a titanium film 103 ab and a titanium nitride film 103 aa are deposited in this order. The film thickness can be made as about 13 nm for the titanium film 103 ab and about 3 nm for the titanium nitride film 103 aa.
  • Successively, a wiring metal layer 103 b is formed over the entire surface and a wiring metal layer 103 b is deposited just above the adhesion metal layer 103 a. The adhesion metal layer 103 a and the wiring metal layer 103 b are formed by a sputtering method or a vapor deposition method. An aluminum film is deposited, for example, as the wiring metal layer 103 b and the film thickness thereof can be made to about 1 μm.
  • Then, as shown in FIG. 3D, the photoresist layer PR is removed by a lift-off method, and the adhesion metal layer 103 a and the wiring metal layer 103 b deposited above the photoresist layer PR are removed. Thus, the adhesion metal layer 103 a and the wiring metal layer 103 b of a predetermined pattern are left on the polysilicon layer 6 a, to form a gate lead-out electrode 103 having a laminate structure composed of the polysilicon layer 6 a, the adhesion metal layer 103 a, and the wiring metal layer 103 b.
  • An interlayer insulation film 7 is formed over the entire surface including the gate electrode 6 and the gate lead-out electrode 103 (polysilicon layer 6 a, adhesion metal layer 103 a, and wiring metal layer 103 b) so as to cover them.
  • Successively, as shown in FIG. 4A, the interlayer insulation film 7 is removed selectively to form contact via 7 a reaching the source region 4 and the well 3. At the same time, a contact via 107 a corresponding to the gate pad 12 shown in FIG. 2 is formed.
  • Then, as shown in FIG. 4B, a source electrode 108 is formed over the interlayer insulation film 7, and the source electrode 108 is connected electrically with the source region 4 and the well 3.
  • Then, the drain electrode 9 shown in FIG. 1B is formed to the semiconductor substrate 1 on the side of the rear face to obtain a semiconductor device 100 as a vertical power MOSFET.
  • The effect of this embodiment is to be described. According to the method of manufacturing the semiconductor device 100, since the pattern for the wiring metal layer 103 b of the gate lead-out electrode 103 is formed by the lift-off method using the photoresist layer PR as a mask, it is not necessary to form an interlayer insulation film for protecting the gate electrode 6 upon patterning the wiring metal layer 103 b and it may suffice that only the interlayer insulation film 7 covering the gate electrode 6 and the gate lead-out electrode 103 may be formed as the interlayer insulation film. Thus, the gate lead-out electrode 103 and the source electrode 108 can be disposed in different layers without increasing the number of layers for the interlayer insulation film.
  • Further, for the number of layers, since only the interlayer insulation film 7 may be formed for covering the gate lead-out electrode 103 and the gate electrode 6 as the interlayer insulation film for the semiconductor device 100, that is, a single layer may suffice as in the case of reference 1, the source electrode 108 can be formed so as to cover the gate lead-out electrode 103 from above without increasing the thickness of the chip and a design flexibility for a patterning layout can be enhanced. Therefore, this dose not cause branching or round about of the current path as has been described for FIG. 7 and increase of the on-resistance of the semiconductor device 100 can also be prevented. Further, increase of the potential for the cracking or peeling of the interlayer insulation film 7 can also be prevented.
  • According to this embodiment, the design flexibility for the patterning layout of the gate lead-out electrode 103 and the source electrode 108 can be enhanced without increasing the thickness of the semiconductor device 100.
  • The semiconductor device and the manufacturing method thereof according to the present invention are not restricted to the embodiment described above but various modifications are possible.
  • In the embodiment described above, while description has been made to a vertical power MOSFET in which the gate electrode is disposed above the substrate, it may be a semiconductor device 200 as a vertical power MOSFET having a trench gate structure as shown, for example, in FIG. 5. Since other structures of the semiconductor device 200 are identical with those of the semiconductor device 100, descriptions therefor are to be omitted.
  • In a case of the vertical power MOSFET having the trench gate structure, a gate electrode 6 is buried in the inside of a trench, a polysilicon layer constituting the gate electrode 6 is led out above the epitaxial layer 2 in a not illustrated region and formed as one pattern formed indivisibly in a common layer with polysilicon layer 6 a of a gate lead-out electrode 103. That is, also in the trench gate structure, the gate electrode 6 and the polysilicon layer 6 a of the gate lead-out electrode 103 are formed in one identical step.
  • Also in the semiconductor device 200, since the gate lead-out electrode 103 and the source electrode 108 are formed in different layers, the design flexibility of the patterning layout can be improved and the same effect as in the semiconductor device 100 can be obtained also in the semiconductor device 200.
  • Further, in the semiconductor device 100, while the description has been made to the interlayer insulation film 7 with respect to a layer made of a single material such as BPSG, the interlayer insulation film 7 may also be a laminate film made of plural different materials.
  • That is, while the insulation material for the interlayer insulation film 7 is not particularly restricted, it may include, for example, as shown in a semiconductor device 300 in FIG. 9, a laminate film formed by laminating a BPSG (Boron Phosphorus Silicate Glass) film with good planarity as an upper layer and an NSG (Non-doped Silicate Glass) film as a barrier layer for preventing downward diffusion of boron or phosphorus from the BPSG film as a lower layer. Since other structures of the semiconductor device 300 are identical with those of the semiconductor device 100, descriptions therefor are to be omitted.
  • Further, in the embodiment described above, while description has been made to a case of using aluminum as the material for the wiring metal layer 103 b, it may also be a material containing at least one of aluminum, copper, and tungsten. Further, the wiring metal layer may be formed of an alloy film containing aluminum or an alloy film containing copper. Use of tungsten can prevent occurrence of migration and/or aluminum spike. However, in a case of using tungsten, it is desirable that increase in the wiring resistance may be permitted.
  • While all of the semiconductor devices 100 to 300 have been explained with respect to the N channel type MOSFET as the example, the channel type may also be the P-channel type. That is, the conduction type may be reversed for all impurities.
  • Further, the present invention is not restricted to the MOSFET but is applicable also to IGBT (Insulated Gate Bipolar Transistor). An IGBT can be constituted, for example, by using a P-type semiconductor substrate as the semiconductor substrate 1 in FIG. 1B.
  • Although the invention has been described above in connection with several preferred embodiments thereof, it will be appreciated by those skilled in the art that those embodiments are provided solely for illustrating the invention, and should not be relied upon to construe the appended claims in a limiting sense.

Claims (8)

1. A method of manufacturing a semiconductor device including a cell region in which a plurality of transistor cells are arranged, a gate electrode, and a gate lead-out electrode formed in a gate finger region different from the region where the cell region is formed, the method comprising:
(a) forming a gate electrode and a first layer of a gate lead-out electrode with a first conductive material above a semiconductor layer;
(b) forming a photoresist layer over the entire surface above the gate electrode and the first layer;
(c) forming an opening in the photoresist layer so that a portion of the first layer of the gate lead-out electrode is exposed;
(d) depositing a wiring metal layer on the photoresist layer and the portion of the first layer of the gate lead-out electrode which is exposed via the opening;
(e) lifting-off the wiring metal layer formed on the photoresist layer with the photoresist layer;
(f) forming an interlayer insulation film over the entire surface including the first layer and the wiring metal layer;
(g) selectively removing the interlayer insulation film thereby forming a contact via reaching the source region formed in the cell region; and
(h) forming a source electrode on the interlayer insulation film and electrically connecting the source electrode with the source region.
2. The method of manufacturing the semiconductor device according to claim 1, wherein
the lowermost layer of the wiring metal layer comprises an adhesion metal layer.
3. The method of manufacturing the semiconductor device according to claim 2, wherein
the adhesion metal layer comprises a titanium film and a titanium nitride film deposited in this order.
4. The method of manufacturing the semiconductor device according to claim 1, wherein
the first conductive material comprises a polysilicon.
5. The method of manufacturing the semiconductor device according to claim 1, wherein
the wiring metal layer comprises at least one of aluminum, copper, and tungsten.
6. The method of manufacturing the semiconductor device according to claim 1, wherein
the source electrode is formed over the entire surface above the cell region and the gate lead-out electrode when viewed in a plane.
7. The method of manufacturing a semiconductor device according to claim 1, wherein
the interlayer insulation film comprises a laminate film made of a plurality of different materials.
8. The method of manufacturing a semiconductor device according to claim 7, wherein
the interlayer insulation film comprises a non-doped silicate glass film and a boron-phosphorus silicate glass film formed in a layer thereabove.
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