JP6086360B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device.

  Conventionally, a silicon carbide semiconductor device having a MOS (metal-oxide-semiconductor-insulated gate) structure made of silicon carbide (SiC) is known as a power semiconductor device capable of greatly reducing power loss (for example, (See Patent Document 1 below.) In Patent Document 1 below, when a low temperature oxidation (LTO) film is formed as an interlayer insulating film formed on a gate electrode, cracks are generated in the subsequent heat treatment process, and the film is formed on the LTO film. In order to solve the problem that the surface electrode has a defective shape, a method has been proposed in which a BPSG (Boron Phosphorus Silicon Glass) film is formed as an interlayer insulating film to prevent the occurrence of cracks and defective electrode formation.

  In Patent Document 1 below, when an electrode material such as nickel (Ni) that exhibits ohmic properties with respect to an n-type semiconductor is used as an electrode material of a source electrode formed as a front surface electrode, this electrode material is It has been confirmed that the BPSG film diffuses into the BPSG film and the insulating property of the BPSG film decreases. As a method for solving such a problem, in Patent Document 1 below, after reflowing a BPSG film, a TEOS (Tetra Ethyl Oxide Silicate) film that becomes a nickel diffusion barrier layer is formed on the BPSG film. There has been proposed a method for preventing nickel, which is an electrode material of the front surface electrode formed on the film, from diffusing into the BPSG film.

JP 2009-4573 A

  However, in the above-mentioned Patent Document 1, the following problem occurs. FIG. 7 is a cross-sectional view schematically showing a part of the configuration of a conventional MOS type silicon carbide semiconductor device. FIG. 8 is a characteristic diagram showing the relationship between the phosphorus concentration and boron concentration in the interlayer insulating film and the taper angle of the interlayer insulating film. FIG. 9 is a characteristic diagram showing the relationship between the reflow temperature of a conventional interlayer insulating film and the interface state density at the gate insulating film / silicon carbide semiconductor interface. When the impurity concentration of phosphorus (P) and boron (B) in the BPSG film is low, the softening point of the BPSG film becomes high, and the reflow property of the interlayer insulating film 104 formed of the BPSG film is deteriorated.

  When the reflow property of the interlayer insulating film 104 deteriorates, the taper angle θ of the interlayer insulating film 104 becomes, for example, 90 ° or less as shown in FIG. 8, and therefore the step coverage of the TEOS film formed on the interlayer insulating film 104 is increased. Getting worse. Deterioration of the step coverage of the TEOS film may cause electrode formation defects. The taper angle θ of the interlayer insulating film 104 refers to the main part of the silicon carbide substrate 101 at the step portion 105 formed in the interlayer insulating film 104 by the gate electrode 103 formed on the silicon carbide substrate 101 through the gate insulating film 102. It is the inclination with respect to the angle to the surface.

  The flatness of the interlayer insulating film 104 can be improved by increasing the reflow temperature. However, in the manufacture (manufacturing) of a silicon carbide semiconductor device having a MOS structure, when heat treatment is performed at a temperature of 900 ° C. or higher after forming the gate insulating film 102, the gate insulating film 102, the silicon carbide substrate 101, and There is a problem that the interface state density of the interface (gate insulating film / silicon carbide semiconductor interface) increases and the channel mobility decreases.

  As another method for preventing diffusion of the electrode material of the source electrode into the interlayer insulating film, a titanium nitride (TiN) film or a titanium (Ti) and titanium nitride film is used as a barrier metal film between the interlayer insulating film and the source electrode. A method for forming a laminated film is known. However, when a BPSG film is formed as an interlayer insulating film, there is a problem in that the boron in the BPSG film has poor adhesion to titanium, so that the source electrode is easily peeled off.

  When a barrier metal film mainly composed of titanium is formed between the interlayer insulating film and the source electrode, the adhesion between the interlayer insulating film and the source electrode is reduced by lowering the boron concentration in the BPSG film formed as the interlayer insulating film. Can improve sex. However, when the boron concentration in the BPSG film is lowered as described above, there is a problem that the flatness of the interlayer insulating film is deteriorated and the step coverage of the barrier metal film is deteriorated as the boron concentration in the BPSG film is lowered. Arise.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device having an interlayer insulating film having a high insulating property in order to solve the above-described problems caused by the prior art. Another object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device capable of preventing electrode formation defects in order to eliminate the above-described problems caused by the prior art. Another object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device capable of preventing deterioration in interface characteristics at the bonding interface between an insulating film and a semiconductor in order to eliminate the above-described problems caused by the prior art. To do.

  In order to solve the above-described problems and achieve the object, a method for manufacturing a silicon carbide semiconductor device according to the present invention includes a first conductivity type having a lower impurity concentration than the silicon carbide substrate on a first main surface of a silicon carbide substrate. A step of growing a silicon carbide epitaxial layer, a step of forming an insulated gate structure made of a metal-oxide film-semiconductor on the surface of the first conductivity type silicon carbide epitaxial layer, and a first step made of an impurity containing no phosphorus and boron. A step of covering the gate conductive film constituting the insulated gate structure with one interlayer insulating film, a step of covering the first interlayer insulating film with a second interlayer insulating film made of an impurity containing phosphorus and boron, and heat treatment, Planarizing the second interlayer insulating film; forming a contact hole penetrating through the first interlayer insulating film and the second interlayer insulating film in the depth direction; A step of covering the second interlayer insulating film with a cap insulating film for preventing diffusion of boron in the interlayer insulating film; a step of covering the cap insulating film with a barrier metal film containing at least titanium; and a surface of the barrier metal film And forming the input electrode so as to cover the contact hole and forming the output electrode on the second main surface of the silicon carbide substrate.

  The method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the total impurity concentration of impurities contained in the second interlayer insulating film is not less than 4 wt% and less than 12 wt%.

  In the method of manufacturing a silicon carbide semiconductor device according to the present invention, the boron concentration in the second interlayer insulating film is 2 wt% or more and less than 5.5 wt% in the above-described invention.

  In the method for manufacturing a silicon carbide semiconductor device according to the present invention, the cap insulating film is any one of TEOS, NSG, HTO, silicon nitride, LTO, PSG, and BPSG having a boron concentration of less than 1 wt%. It is characterized by comprising a single layer film containing two main components or a laminated film in which two or more layers are laminated.

  In the method for manufacturing a silicon carbide semiconductor device according to the present invention as set forth in the invention described above, the temperature of the heat treatment is 750 ° C. or higher and lower than 900 ° C.

  In the method for manufacturing a silicon carbide semiconductor device according to the present invention as set forth in the invention described above, the thickness of the cap insulating film is 30% or less of the thickness of the second interlayer insulating film.

  The method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the gate conductive film is formed under a reduced pressure lower than atmospheric pressure by a chemical vapor deposition method.

  In the method for manufacturing a silicon carbide semiconductor device according to the present invention as set forth in the invention described above, the heat treatment is performed in an atmosphere containing 4 mol% of hydrogen.

  In the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the step of forming the insulated gate structure may include forming a first second conductive layer on a surface layer of the first conductive type silicon carbide epitaxial layer. A step of selectively forming a type semiconductor region, and an impurity concentration in the surfaces of the first conductive type silicon carbide epitaxial layer and the first second conductive type semiconductor region than in the first second conductive type semiconductor region. A step of growing a second conductivity type silicon carbide epitaxial layer having a low conductivity, and a first first conductivity type semiconductor region having an impurity concentration higher than that of the silicon carbide substrate on the surface layer of the second conductivity type silicon carbide epitaxial layer. A step of forming and contacting the first first conductivity type semiconductor region and penetrating the second conductivity type silicon carbide epitaxial layer to contact the first second conductivity type semiconductor region Forming a second second conductivity type semiconductor region having an impurity concentration higher than that of the second conductivity type silicon carbide epitaxial layer, and penetrating through the second conductivity type silicon carbide epitaxial layer, the first conductivity type silicon carbide. Forming a first conductivity type channel region having an impurity concentration higher than that of the first conductivity type silicon carbide epitaxial layer and lower than that of the first first conductivity type semiconductor region so as to reach the epitaxial layer; And the gate conductive layer on the surface of the second conductive type silicon carbide epitaxial layer sandwiched between the first first conductive type semiconductor region and the first conductive type channel region via a gate insulating film. Forming a film.

  According to the above-described invention, it is possible to prevent the electrode material constituting the input electrode from diffusing into the interlayer insulating film by forming the barrier metal film on the interlayer insulating film. Thereby, it can prevent that the insulation of an interlayer insulation film falls.

  Further, according to the above-described invention, by forming at least the outermost surface layer of the interlayer insulating film (first interlayer insulating film) with an insulator made of impurities that do not contain phosphorus and boron, phosphorus in the interlayer insulating film and The impurity concentration of boron can be lowered. As a result, the barrier metal film formed on the interlayer insulating film can be prevented from peeling off. In addition, since at least the outermost surface layer (second interlayer insulating film) of the interlayer insulating film is made of an insulator made of impurities including phosphorus and boron, the interlayer insulating film can be softened by heat treatment. Good flatness can be realized. Thereby, good coverage of the barrier metal film formed on the interlayer insulating film can be realized.

  According to the above-described invention, the lowermost layer (first interlayer insulating film) of the interlayer insulating film is formed of an insulator made of impurities not containing phosphorus and boron, and the cap film is formed on the surface of the interlayer insulating film. Thus, it is possible to prevent boron in the interlayer insulating film from diffusing. Thereby, it is possible to prevent the softening point of the interlayer insulating film from increasing. Further, at least the outermost surface layer (second interlayer insulating film) of the interlayer insulating film is made of an insulator made of an impurity containing phosphorus and boron to such an extent that it can be softened by heat treatment at a low temperature of 700 ° C. or higher and lower than 900 ° C. Therefore, an increase in interface state density at the gate insulating film-silicon carbide semiconductor interface constituting the insulated gate structure can be prevented. Accordingly, it is possible to prevent the channel mobility from decreasing.

  According to the method for manufacturing a silicon carbide semiconductor device of the present invention, it is possible to provide a silicon carbide semiconductor device having a highly insulating interlayer insulating film. Moreover, according to the manufacturing method of the silicon carbide semiconductor device concerning this invention, there exists an effect that the electrode formation defect can be prevented. In addition, according to the method for manufacturing a silicon carbide semiconductor device of the present invention, it is possible to prevent deterioration in interface characteristics at the bonding interface between the insulating film and the semiconductor.

It is sectional drawing which shows an example of the semiconductor device manufactured by the manufacturing method of the silicon carbide semiconductor device concerning embodiment. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment. It is sectional drawing which shows typically a part of structure of the conventional MOS type silicon carbide semiconductor device. It is a characteristic view showing the relationship between the phosphorus concentration and boron concentration in the interlayer insulating film and the taper angle of the interlayer insulating film. It is a characteristic view which shows the relationship between the reflow temperature of the conventional interlayer insulation film, and the interface state density of a gate insulation film and a silicon carbide semiconductor interface.

  Exemplary embodiments of a method for manufacturing a silicon carbide semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment)
First, a silicon carbide semiconductor device manufactured (manufactured) by the method for manufacturing a silicon carbide semiconductor device according to the embodiment will be described using a silicon carbide MOSFET (insulated gate field effect transistor) as an example. FIG. 1 is a cross-sectional view showing an example of a semiconductor device manufactured by the method for manufacturing a silicon carbide semiconductor device according to the embodiment. As shown in FIG. 1, in the silicon carbide semiconductor device according to the embodiment, an n-type silicon carbide epitaxial layer (first conductivity type) is formed on the front surface (first main surface) of n ⁺ -type silicon carbide substrate 1. A silicon carbide epitaxial layer) 2 is deposited.

On the surface of n-type silicon carbide epitaxial layer 2, a MOS (metal-oxide film-insulated gate made of semiconductor) structure is formed. Specifically, ap ⁺ type base region (first second conductivity type semiconductor region) 3 is formed on the surface layer of n type silicon carbide epitaxial layer 2 opposite to the n ⁺ type silicon carbide substrate 1 side. It is provided selectively. A p ⁻ type silicon carbide epitaxial layer (second conductivity type silicon carbide epitaxial layer) 4 is deposited on the surfaces of n type silicon carbide epitaxial layer 2 and p ⁺ type base region 3. p ⁻ type silicon carbide epitaxial layer 4 constitutes a base region together with p ⁺ type base region 3.

A portion of p ⁻ type silicon carbide epitaxial layer 4 on p ⁺ type base region 3 is provided with an n ⁺ type source region (first first conductivity) on a surface layer opposite to p ⁺ type base region 3 side. Type semiconductor region) 5 and p ⁺ type contact region (second second conductivity type semiconductor region) 6 are selectively provided. P ⁺ type contact region 6 penetrates p ⁻ type silicon carbide epitaxial layer 4 in the depth direction and reaches p ⁺ type base region 3. Further, p ⁺ -type contact region 6, the n ⁺ -type source region 5, on the opposite side with respect to the n-type channel region 7 side, which will be described later, is provided in contact with the n ⁺ -type source regions 5.

p ^- type in the n-type portion of the silicon carbide epitaxial layer 2 of the silicon carbide epitaxial layer 4, p in the depth direction ^- -type silicon carbide epitaxial layer 4 penetrates reaching the n-type silicon carbide epitaxial layer 2 n-type channel region 7 is provided. N-type channel region 7 is not in contact with n ⁺ -type source region 5. N type channel region 7 forms a drift region together with n type silicon carbide epitaxial layer 2. A gate conductive film (gate electrode) 9 is provided on the surface of the portion of p ⁻ type silicon carbide epitaxial layer 4 sandwiched between n ⁺ type source region 5 and n type channel region 7 via gate insulating film 8. It has been. The gate conductive film 9 is covered with an interlayer insulating film 10.

The interlayer insulating film 10 is formed by laminating a first interlayer insulating film (not shown) and a second interlayer insulating film (not shown) in order from the gate conductive film 9 side. The first interlayer insulating film is made of an insulator made of impurities not containing phosphorus and boron. Specifically, the first interlayer insulating film is made of, for example, silicon oxide (SiO ₂ ) -based glass (NSG: Non-Doped Silicon Glass) that does not contain impurities. The first interlayer insulating film has a function of preventing diffusion of boron (B) in the interlayer insulating film 10. The second interlayer insulating film is made of an insulator made of impurities including phosphorus and boron. Specifically, the second interlayer insulating film is made of, for example, a BPSG film that can be softened by heat treatment.

  The interlayer insulating film 10 is covered with a cap insulating film 11. The cap insulating film 11 is, for example, a TEOS film, an NSG film, a thermal oxidation (HTO: Hot Thermal Oxide) film, a silicon nitride (SiN) film, an LTO film, a PSG (Phosphorus Silicon Glass) film, and a boron concentration of less than 1 wt%. It may be a single layer film of any of the BPSG films or a stacked film formed by stacking two or more of these. The cap insulating film 11 has a function of preventing the diffusion of boron (B) in the interlayer insulating film 10. The cap insulating film 11 is covered with a barrier metal film 12 containing at least titanium (Ti). The barrier metal film 12 may be made of, for example, titanium nitride (TiN). The barrier metal film 12 has a function of preventing the electrode material constituting the source electrode 13 and the front electrode layer 14 from diffusing into the interlayer insulating film 10.

A contact hole penetrating the barrier metal film 12, the cap insulating film 11, and the interlayer insulating film 10 in the depth direction is provided. A source electrode (first electrode) 13 that covers a part of the surface of the barrier metal film 12 and the contact hole and is in contact with the n ⁺ type source region 5 and the p ⁺ type contact region 6 through the contact hole is provided. The source electrode 13 is electrically insulated from the gate conductive film 9 by the interlayer insulating film 10. The source electrode 13 is made of nickel, for example.

On the surfaces of the barrier metal film 12 and the source electrode 13, a front electrode layer 14 made of, for example, aluminum silicide (Al—Si) is provided. n ⁺ -type silicon carbide rear surface of the substrate 1 in the (second main surface) entirely, the backside ohmic electrode 15 is provided made of, for example, nickel to form an n ⁺ -type silicon carbide substrate 1 and the ohmic junction (Ni) and titanium (Ti) It has been. On the surface of the backside ohmic electrode 15, a backside electrode layer 16 is provided in which, for example, titanium, nickel, and gold (Au) are sequentially stacked from the backside ohmic electrode 15 side. The back ohmic electrode 15 and the back electrode layer 16 are drain electrodes (output electrodes).

Next, a method for manufacturing the silicon carbide semiconductor device according to the embodiment will be described. FIGS. 2-6 is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment. First, as shown in FIG. 2, for example, an n ⁺ type silicon carbide substrate 1 having a thickness of 340 μm is prepared. The n ⁺ type silicon carbide substrate 1 is a silicon carbide single crystal substrate made of, for example, a four-layered periodic hexagonal crystal (4H—SiC) of silicon carbide. The front surface of n ⁺ type silicon carbide substrate 1 may be, for example, a (000-1) plane. In the present specification, in the Miller index notation, “−” means a bar attached to the index immediately after that, and “−” is added before the index to indicate a negative index.

Next, n type silicon carbide epitaxial layer 2 is formed on the front surface of n ⁺ type silicon carbide substrate 1. The impurity concentration and thickness of n-type silicon carbide epitaxial layer 2 may be, for example, 5 × 10 ¹⁵ cm ⁻³ and 10 μm, respectively. Next, the p ⁺ type base region 3 is selectively formed on the surface layer of the n-type silicon carbide epitaxial layer 2 by ion implantation of aluminum (Al), for example. The impurity concentration of the p ⁺ type base region 3 may be 2 × 10 ¹⁸ cm ⁻³ .

Next, p ⁻ type silicon carbide epitaxial layer 4 is formed on the surfaces of n type silicon carbide epitaxial layer 2 and p ⁺ type base region 3. The impurity concentration and thickness of p ⁻ type silicon carbide epitaxial layer 4 may be, for example, 5 × 10 ¹⁵ cm ⁻³ and 0.5 μm, respectively. Next, the n ⁺ type source region 5 is selectively formed in the surface layer of the p ⁻ type silicon carbide epitaxial layer 4 by ion implantation of phosphorus (P), for example. The impurity concentration of the n ⁺ -type source region 5 may be 2 × 10 ²⁰ cm ⁻³ , for example.

Next, as shown in FIG. 3, by ion implantation of aluminum, the p ⁺ -type base region 3 is reached by contacting the n ⁺ -type source region 5 and penetrating the p ⁻ -type silicon carbide epitaxial layer 4 in the depth direction. ^{A +} -type contact region 6 is selectively formed. The impurity concentration of the p ⁺ -type contact region 6 may be 8 × 10 ²⁰ cm ⁻³ , for example. Next, an n-type channel region 7 that penetrates the p ⁻ -type silicon carbide epitaxial layer 4 in the depth direction and reaches the n-type silicon carbide epitaxial layer 2 is selectively formed by ion implantation of nitrogen (N). Next, a heat treatment is performed at a temperature of 1600 ° C. for 3 minutes to activate the impurities introduced by ion implantation.

Next, as shown in FIG. 4, for example, thermal oxidation is performed at a temperature of 1100 ° C. in a dry atmosphere, so that the p ⁻ type silicon carbide epitaxial layer 4 extends from a part of the n ⁺ type source region 5 to the n type channel region 7. A gate insulating film 8 is formed to a thickness of 50 nm on the surface of the portion sandwiched between the n ⁺ type source region 5 and the n type channel region 7. Next, a gate conductive film 9 made of phosphorus-doped polysilicon (poly-Si) is formed on the gate insulating film 8 to a thickness of 500 nm. The gate conductive film 9 may be formed by, for example, low pressure CVD (LP-CVD) in which a thin film is subjected to chemical vapor deposition under a reduced pressure lower than atmospheric pressure.

  Next, a first interlayer insulating film 10 a made of, for example, NSG is formed as an interlayer insulating film 10 on the gate conductive film 9 to a thickness of 200 nm. Further, on the first interlayer insulating film 10a, a second interlayer insulating film 10b made of, for example, BPSG having a phosphorus concentration of 2.7 wt% and a boron concentration of 3.6 wt% is formed as an interlayer insulating film 10 with a thickness of 700 nm. The total impurity concentration of impurities contained in the second interlayer insulating film 10b is preferably 4 wt% or more and less than 12 wt%. The boron concentration in the second interlayer insulating film 10b is preferably 2 wt% or more and less than 5.5 wt%. Thereby, the interlayer insulating film 10 with good flatness can be formed at a reflow temperature of about 750 ° C. or higher and 900 ° C. or lower.

Next, as shown in FIG. 5, for example, thermal annealing treatment (reflow) is performed at a temperature of 800 ° C. for 10 minutes in a gas atmosphere in which hydrogen (H ₂ ) is diluted to 4 mol% with nitrogen (N ₂ ), The insulating film 10 is planarized. Next, interlayer insulating film 10 is selectively removed by dry etching to form a contact hole in which n ⁺ type source region 5 and p ⁺ type contact region 6 are exposed. Next, as shown in FIG. 6, a cap insulating film 11 covering the interlayer insulating film 10 is formed with a thickness of 160 nm. The thickness of the cap insulating film 11 is preferably 30% or less of the thickness of the second interlayer insulating film 10b. The reason is to prevent the cap film from cracking during the subsequent sintering annealing.

Next, the cap insulating film 11 is selectively removed by dry etching, and contact holes that expose the n ⁺ type source region 5 and the p ⁺ type contact region 6 are formed again. Next, a barrier metal film 12 made of titanium nitride is formed with a thickness of 100 nm so as to cover the cap insulating film 11. Next, the barrier metal film 12 is patterned to expose the n ⁺ type source region 5 and the p ⁺ type contact region 6 in the contact hole. Next, a source electrode 13 covering a part of the surface of the barrier metal film 12 and the contact hole is formed with a thickness of 60 μm so as to be embedded in the contact hole.

Next, for example, the (0001) plane which is the back surface of the n ⁺ type silicon carbide substrate 1 is cleaned. Next, a nickel film and a titanium film are sequentially laminated to form a back ohmic electrode 15. Next, heat treatment is performed for 2 minutes at a temperature of 975 ° C. in an atmosphere containing hydrogen to sinter (sinter) the backside ohmic electrode 15. Next, a front electrode layer 14 made of, for example, aluminum silicide is formed so as to cover the barrier metal film 12 and the source electrode 13. Next, the back electrode layer 16 is formed by sequentially laminating a titanium film, a nickel film, and a gold film on the back ohmic electrode 15. Thereby, the silicon carbide semiconductor device shown in FIG. 1 is completed.

  As described above, according to the embodiment, it is possible to prevent the electrode material constituting the source electrode from diffusing into the interlayer insulating film by forming the barrier metal film on the interlayer insulating film. Thereby, it can prevent that the insulation of an interlayer insulation film falls.

  In addition, according to the embodiment, by forming at least the outermost surface layer (first interlayer insulating film) of the interlayer insulating film with an insulator made of impurities not containing phosphorus and boron, phosphorus in the interlayer insulating film and The impurity concentration of boron can be lowered. As a result, the barrier metal film formed on the interlayer insulating film can be prevented from peeling off. In addition, since at least the outermost surface layer (second interlayer insulating film) of the interlayer insulating film is made of an insulator made of impurities including phosphorus and boron, the interlayer insulating film can be softened by heat treatment. Good flatness can be realized. Thereby, good coverage of the barrier metal film formed on the interlayer insulating film can be realized. Therefore, it is possible to prevent a source electrode formation failure.

  According to the embodiment, the lowermost layer (first interlayer insulating film) of the interlayer insulating film is formed of an insulator made of impurities not containing phosphorus and boron, and the cap film is formed on the surface of the interlayer insulating film. Thus, it is possible to prevent boron in the interlayer insulating film from diffusing. Thereby, it is possible to prevent the softening point of the interlayer insulating film from increasing. Further, since at least the outermost surface layer of the interlayer insulating film is formed of an insulator made of an impurity containing phosphorus and boron to such an extent that it can be softened by heat treatment at a low reflow temperature of 700 ° C. or higher and lower than 900 ° C., an insulating gate structure An increase in the interface state density at the interface between the gate insulating film and the silicon carbide semiconductor to be formed can be prevented. Accordingly, it is possible to prevent the channel mobility from decreasing.

In the above description, the MOSFET is described as an example in the present invention. However, the present invention is not limited to the above-described embodiment, but can be applied to a semiconductor device in which an electrode is formed on an interlayer insulating film such as IGBT. For example, when the present invention is applied to an IGBT, a p ⁺ type semiconductor substrate may be used instead of an n ⁺ type semiconductor substrate. In the above-described embodiment, an interlayer insulating film in which two insulating films are stacked is described as an example. However, three or more insulating films are stacked without departing from the gist of the present invention. An interlayer insulating film may be formed. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the method for manufacturing a silicon carbide semiconductor device according to the present invention is useful for a power semiconductor device used for a power supply device such as a power conversion device or various industrial machines.

1 n ⁺ type silicon carbide substrate 2 n type silicon carbide epitaxial layer 3 p ⁺ base region 4 p ⁻ type silicon carbide epitaxial layer 5 n ⁺ source region 6 p ⁺ contact region 7 n type channel region 8 gate insulating film 9 gate conductive film DESCRIPTION OF SYMBOLS 10 Interlayer insulating film 10a 1st interlayer insulating film 10b 2nd interlayer insulating film 11 Cap insulating film 12 Barrier metal film 13 Source electrode 14 Front surface electrode layer 15 Back surface ohmic electrode 16 Back surface electrode layer

Claims (8)

Growing a first conductivity type silicon carbide epitaxial layer having an impurity concentration lower than that of the silicon carbide substrate on the first main surface of the silicon carbide substrate;
Forming an insulated gate structure made of a metal-oxide film-semiconductor on the surface of the first conductivity type silicon carbide epitaxial layer;
Covering the gate conductive film constituting the insulated gate structure with a first interlayer insulating film made of impurities not containing phosphorus and boron;
Covering the first interlayer insulating film with a second interlayer insulating film made of an impurity containing phosphorus and boron;
Flattening the second interlayer insulating film by heat treatment;
Forming a contact hole penetrating through the first interlayer insulating film and the second interlayer insulating film in a depth direction;
The proof technique boron diffusion of the second interlayer insulating film, TEOS, NSG, HTO, LTO , single-layer film composed mainly of any one of the BPSG than PSG and boron concentration 1 wt%, or 2 or more Covering the second interlayer insulating film with a cap insulating film made of a laminated film in which
Covering the cap insulating film with a barrier metal film containing at least titanium;
Forming an input electrode so as to cover part of the surface of the barrier metal film and the contact hole;
Forming an output electrode on the second main surface of the silicon carbide substrate;
The manufacturing method of the silicon carbide semiconductor device characterized by the above-mentioned.   2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein a total impurity concentration of impurities contained in the second interlayer insulating film is not less than 4 wt% and less than 12 wt%.   3. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein a boron concentration in the second interlayer insulating film is not less than 2 wt% and less than 5.5 wt%. The temperature of the said heat processing is 750 degreeC or more and less than 900 degreeC, The manufacturing method of the silicon carbide semiconductor device as described in any one of Claims 1-3 characterized by the above-mentioned. 5. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein a thickness of the cap insulating film is 30% or less of a thickness of the second interlayer insulating film. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the gate conductive film is formed by a chemical vapor deposition method under a reduced pressure lower than an atmospheric pressure. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the heat treatment is performed in an atmosphere containing 4 mol% of hydrogen. Forming the insulated gate structure comprises:
Selectively forming a first second conductivity type semiconductor region on a surface layer of the first conductivity type silicon carbide epitaxial layer;
A second conductivity type silicon carbide epitaxial layer having an impurity concentration lower than that of the first second conductivity type semiconductor region is grown on the surfaces of the first conductivity type silicon carbide epitaxial layer and the first second conductivity type semiconductor region. A process of
Forming a first first conductivity type semiconductor region having an impurity concentration higher than that of the silicon carbide substrate on a surface layer of the second conductivity type silicon carbide epitaxial layer;
The second conductivity type silicon carbide epitaxial layer is in contact with the first first conductivity type semiconductor region and passes through the second conductivity type silicon carbide epitaxial layer and in contact with the first second conductivity type semiconductor region. Forming a second second-conductivity-type semiconductor region having a higher impurity concentration than
The impurity concentration is higher than that of the first conductivity type silicon carbide epitaxial layer and penetrates the second conductivity type silicon carbide epitaxial layer and reaches the first conductivity type silicon carbide epitaxial layer, and the first first conductivity type. Forming a first conductivity type channel region having an impurity concentration lower than that of the type semiconductor region;
The gate conductive film is formed on the surface of the second conductive type silicon carbide epitaxial layer sandwiched between the first first conductive type semiconductor region and the first conductive type channel region via a gate insulating film. Forming, and
The manufacturing method of the silicon carbide semiconductor device as described in any one of Claims 1-7 characterized by the above-mentioned.

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