JP2010272676A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem wherein, although a titanium-based barrier metal film formed of titanium and titanium nitride is widely used as an aluminum diffusion barrier metal film under an aluminum-based source electrode in a power MOSFET, according to an examination, when the titanium-based barrier metal is used, warpage of a wafer is increased, wafer handling becomes difficult, it becomes obvious that problems of a wafer fracture, a wafer chip and the like become inevitable, and this trend is particularly noticeable in a product having a minimum dimension ≤0.35 μm. <P>SOLUTION: When forming, by sputtering film formation, a tungsten-based barrier metal film (an alloy film containing tungsten such as TiW as a main constituent) as a barrier metal layer between an aluminum-based metal layer and a lower-layer silicon-based semiconductor layer, the barometric pressure of a sputtering film formation chamber is set ≤1.2 Pa. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technique effective when applied to a metal film forming technique in a method for manufacturing a semiconductor device (or a semiconductor integrated circuit device).

  Japanese Unexamined Patent Publication No. 2000-223708 (Patent Literature 1), Japanese Unexamined Patent Publication No. 2007-165663 (Patent Literature 2), Japanese Unexamined Patent Publication No. 2001-267469 (Patent Literature 3), or Japanese Unexamined Patent Publication No. 2006-32598. The gazette (Patent Document 4) discloses a technique of using TiW as a barrier metal of an aluminum source electrode of a trench gate type power MOSFET (Metal Oxide Field Effect Transistor).

  Japanese Patent Application Laid-Open No. 2003-318395 (Patent Document 5), US Patent Publication No. 2003-0199156 (Patent Document 6), or US Patent Publication No. 2005-0145899 (Patent Document 7) discloses an aluminum power MOSFET. A technique is disclosed in which TiW is used as a barrier metal for a source electrode, and an aluminum source electrode is formed thereon by reflowing.

JP 2000-223708 A JP 2007-165663 A JP 2001-267469 A JP 2006-32598 A JP 2003-318395 A US Patent Publication No. 2003-0199156 US Patent Publication No. 2005-0145899

  In power MOSFETs, a titanium-based barrier metal film made of titanium and titanium nitride is widely used as an aluminum diffusion barrier metal film under an aluminum-based source electrode. However, according to a study by the present inventors, when a titanium-based barrier metal film is used, the warpage of the wafer increases and wafer handling becomes difficult, and problems such as wafer cracking and wafer chipping are unavoidable. It became clear. This tendency is particularly prominent in products having a minimum dimension of 0.35 micrometer or less.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a manufacturing process of a highly reliable semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, in one invention of the present application, a tungsten-based barrier metal film (alloy film containing tungsten as a main component such as TiW) is used as a barrier metal layer between an aluminum-based metal layer and a lower silicon-based semiconductor layer. When forming by sputtering film formation, the atmospheric pressure of the sputtering film formation chamber is set to 1.2 Pascal or less.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, as a barrier metal layer between the aluminum metal layer and the underlying silicon semiconductor layer, a tungsten barrier metal film (an alloy film containing tungsten such as TiW as a main component) is formed by sputtering film formation. By setting the atmospheric pressure of the sputtering film formation chamber to 1.2 Pascal or less, a tungsten-based barrier metal film having a stress that counteracts the stress of the aluminum-based metal layer can be formed. It is possible to prevent an increase in warpage of the wafer due to.

It is a plane block diagram of the multi-chamber type wafer processing apparatus used for the manufacturing method of the semiconductor device of one embodiment of this application. 1 is a schematic cross-sectional view of a sputtering film forming chamber used in a tungsten-based barrier metal film forming process in a method for manufacturing a semiconductor device according to an embodiment of the present application. It is a device top view which shows an example of power MOSFET manufactured by the manufacturing method of the semiconductor device of one embodiment of this application. FIG. 5 is a device cross-sectional flow diagram (source / contact groove forming resist pattern forming step) of a trench / gate / cell portion in the method of manufacturing a semiconductor device according to an embodiment of the present application; FIG. 5 is a device cross-sectional flow diagram (source contact groove forming step) of a trench gate cell portion in a method for manufacturing a semiconductor device according to an embodiment of the present application; FIG. 5 is a device cross-sectional flow diagram (source / contact trench forming resist pattern removal step) of a trench / gate / cell portion in the method of manufacturing a semiconductor device according to an embodiment of the present application; FIG. 6 is a device cross-sectional flow diagram (source contact groove extending step) of a trench gate cell portion in a method for manufacturing a semiconductor device according to an embodiment of the present application; It is a device top view (p + body contact region introduction | transduction process) of the trench gate cell part in the manufacturing method of the semiconductor device of one embodiment of this application. FIG. 10 is a device cross-sectional flow diagram (p + body contact region introducing step) of a trench gate cell portion (corresponding to the X-X ′ cross section of FIG. 8) in the method for manufacturing a semiconductor device of one embodiment of the present application; It is a device top view (contact groove 2 step structure formation process) of a trench gate gate cell part in a manufacturing method of a semiconductor device of one embodiment of this application. FIG. 11 is a device cross-sectional flow diagram (contact groove two-stage structure forming step) of a trench gate cell portion (corresponding to the X-X ′ cross section of FIG. 10) in the method for manufacturing a semiconductor device of one embodiment of the present application; FIG. 6 is a device cross-sectional flow diagram (barrier metal film forming step) of a trench, gate, and cell portion in the method for manufacturing a semiconductor device according to an embodiment of the present application. FIG. 5 is a device cross-sectional flow diagram (aluminum-based metal film forming step) of a trench, a gate, and a cell portion in the method for manufacturing a semiconductor device according to an embodiment of the present application. FIG. 5 is a device cross-sectional flow diagram (rear surface metal film forming step) of a trench, a gate, and a cell portion in the method for manufacturing a semiconductor device of one embodiment of the present application. FIG. 13 is a data plot diagram showing the relationship between TiW sputtering pressure and wafer warpage after the barrier metal film forming step corresponding to FIG. 12. FIG. 15 is a data plot diagram showing the relationship between wafer thickness and wafer warpage for the embodiment and the comparative example after the back surface metal film forming step corresponding to FIG. 14.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A semiconductor device manufacturing method including the following steps:
(A) forming a recess from the upper surface of the first insulating film on the first main surface of the semiconductor wafer downward;
(B) forming a tungsten-based barrier metal film by sputtering film formation on the inner surface of the recess and the upper surface of the first insulating film;
(C) after the step (b), forming an aluminum-based metal layer so as to cover the tungsten-based barrier metal film on the inner surface of the recess and the upper surface of the first insulating film;
Here, the step (b) is performed in a sputtering film forming chamber having an atmospheric pressure of 1.2 Pa or less.

  2. In the method of manufacturing a semiconductor device according to the item 1, in the step (b), the tungsten-based barrier metal film contains tungsten as a main component and titanium as a secondary component.

  3. In the method for manufacturing a semiconductor device according to the item 2, the composition weight ratio of the target used in the step (b) is approximately Ti: W = 1: 9.

  4). 4. In the method for manufacturing a semiconductor device according to any one of items 1 to 3, the step (b) is usually performed by sputtering.

  5. In the method for manufacturing a semiconductor device according to any one of 1 to 4, the film thickness of the tungsten-based barrier metal film is 100 nm or more and 300 nm or less.

  6). 6. In the method for manufacturing a semiconductor device according to any one of 1 to 5, the thickness of the aluminum-based metal layer is not less than 3 micrometers and not more than 7 micrometers.

  7). In the method for manufacturing a semiconductor device according to any one of 1 to 6, the atmospheric pressure is 0.3 Pascal or more.

  8). 7. In the method for manufacturing a semiconductor device according to any one of 1 to 6, the atmospheric pressure is 1.0 Pascal or less.

  9. In the method for manufacturing a semiconductor device according to any one of 1 to 6, the atmospheric pressure is 0.4 Pascal or more.

  10. In the method for manufacturing a semiconductor device according to any one of 1 to 6, the atmospheric pressure is 0.3 Pascal or more and 1.0 Pascal or less.

  11. In the method for manufacturing a semiconductor device according to any one of 1 to 6, the atmospheric pressure is 0.4 Pascal or more and 1.0 Pascal or less.

  12 12. In the method for manufacturing a semiconductor device as described above in any one of 1 to 11, the final thickness of the semiconductor wafer is not less than 80 micrometers and not more than 160 micrometers.

  13. 13. The method for manufacturing a semiconductor device according to any one of items 1 to 12, wherein the semiconductor wafer is a 200φ silicon-based wafer.

  14 14. The method for manufacturing a semiconductor device according to any one of 1 to 13, wherein the semiconductor device includes a power MOSFET.

  15. 15. In the method for manufacturing a semiconductor device as described above in any one of 1 to 14, the recess has a two-stage structure.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Furthermore, in the present application, the term “semiconductor device” mainly refers to a single device such as various transistors (active elements), and mainly a resistor, a capacitor, etc. on a semiconductor chip or the like (for example, a single crystal silicon substrate). It is a collection. In addition, even if it is called a single unit, there are actually a plurality of small elements integrated. Here, as a typical example of various transistors, a MISFET (Metal Insulator Semiconductor Transistor which can be a MISFET represented by a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a transistor, an IGB transistor which can be an IGBT transistor, an IBB transistor, an IGB transistor, an IBB transistor, an IGB transistor, an IGB transistor, an IB transistor, an IGB transistor, an IGBT, and an IGBT. . Also, “MOS” does not limit the insulating film to oxide.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or Carbon-doped Silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NSC), etc., coated silicon oxide, silica-based low-k insulating film (porous) with pores introduced in the same materials Needless to say, it includes a composite insulating film and other silicon-based insulating films having these as main components.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. "Wafer" usually refers to a single crystal silicon wafer on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but is an insulating substrate such as an epitaxial wafer, an SOI substrate, or an LCD glass substrate. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). In the present application, an example is described in which barrier metal is formed mainly by normal sputtering (not directional sputtering), and an aluminum-based metal layer is formed mainly by ionized sputtering. Is explained. However, in the present invention, ionization sputtering or long throw sputtering may be used for barrier metal film formation, and normal sputtering or long throw sputtering is used for film formation of an aluminum-based metal layer. May be.

  Here, “ionized sputtering” is a type of directional sputtering (long throw sputtering or LT sputtering is directional sputtering, but is generally not ionized sputtering). Whereas the film (for example, usually sputter deposition) is mainly due to electrically neutral sputtered atoms, molecules, or clusters thereof, ionized metal ions, etc. have sheath voltage (and additional bias). Thus, sputtering film formation with good coverage is realized by utilizing the fact that it is incident on the wafer surface with a relatively large vertical velocity component. Although there are various types of ionization sputtering methods, the PCM method will be specifically described here, but it is needless to say that the ionization sputtering method is not limited to this method. Therefore, the name of “ionizing sputtering” is not limited as long as it is a method in which the ionization-target metal atoms substantially contribute to film formation. In the present embodiment, an example in which ILC1060 manufactured by Canon Anelva is used as a normal sputtering apparatus has been specifically described, but it is needless to say that other normal sputtering apparatuses may be used.

  Moreover, although the example which used I-1080 PCM by Canon Anelva company of a PCM system as an ionization sputtering apparatus was demonstrated concretely, as other ionization sputtering apparatuses, SIP of Applied Materials (Applied Materials) is mentioned. -There is a PVD (Self-Ionized Plasma Physical Vapor Deposition) device. ULVAC also provides a similar device.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

  Regarding power MOSFETs and the like, for details of the technology for forming aluminum-based metal electrodes using various sputter depositions, see Japanese Patent Application No. 2008-002993 (Japan filing date: January 10, 2008) or Japanese Patent Application. Since it is described in detail in No. 2009-092973 (Japan filing date: April 7, 2009), the description thereof will not be repeated in principle in the present application.

1. Description of a metal film forming apparatus used in the method of manufacturing a semiconductor device according to an embodiment of the present application (mainly FIGS. 1 and 2)
First, a metal film forming apparatus and the like used in the method for manufacturing a semiconductor device according to an embodiment of the present application will be briefly described. FIG. 1 is a plan configuration diagram of a multi-chamber type (cluster type) wafer processing apparatus used in a method of manufacturing a semiconductor device according to an embodiment of the present application.

  As shown in FIG. 1, a sputtering apparatus (preliminary chamber 58, AlSi sputtering chamber 61, TiW normal sputtering film forming chamber 59), a heat treatment apparatus (preheat processing chamber 56), and an etching apparatus (sputtering / sputtering chamber) used in the manufacturing process are used. The etching chamber 57) and the like are integrated in the cluster apparatus 51. This cluster apparatus 51 has a load port 52 (or front chamber) for accommodating four wafer cassettes 53 under normal pressure. The wafer accommodated in the load port 52 is converted into a vacuum via one of the two load lock chambers 54 and supplied to each processing chamber through the vacuum transfer chamber 55. The opposite is true when discharging.

  In this embodiment, the silicidation / annealing step after forming the TiW film is performed by an external batch processing furnace different from the multi-chamber type wafer processing apparatus 51. By using 58 as a single wafer RTA (Rapid Thermal Annealing) chamber, the wafer 1 may be executed without exposing it to the atmosphere in a series of processes.

  FIG. 2 is a schematic cross-sectional view of a sputtering chamber 59 (ordinary non-directivity sputtering chamber) used in the tungsten-based barrier metal film forming step in the semiconductor device manufacturing method according to the embodiment of the present application. is there. This sputtering chamber (sputtering apparatus) is also included in the magnetron sputtering system, as is the case with other general-purpose metal sputtering apparatuses. As shown in FIG. 2, a lower electrode (wafer stage) 62 is provided at the lower portion of the chamber 59, and a device surface 1a (a surface opposite to the back surface 1b) is formed on the wafer stage 62 during film formation. The wafer 1 is set facing up. The lower electrode 62 is normally grounded. An electrostatic chuck electrode is provided in the wafer stage 62 and can be turned on and off by an electrostatic chuck control system.

  An upper electrode (target backing plate) 66 is provided on the upper portion of the chamber 59 so as to face the wafer stage 62, and a tungsten-based barrier metal target 67 (here, for example, TiW target containing about 10 wt% titanium) is set. A DC power (DC bias) is normally applied to the upper electrode 66 by an upper electrode DC bias power source 74.

  A gas supply control system is provided outside the chamber 59 so that argon gas and other gases can be supplied into the chamber 61 through the gas supply path 78. Further, the inside of the chamber 59 is evacuated by an evacuation system through an exhaust port 81 provided below, and can maintain a high vacuum necessary for sputtering.

2. Description of an example of a device upper surface structure of a power MOSFET manufactured by a method of manufacturing a semiconductor device according to an embodiment of the present application (mainly FIG. 3)
FIG. 3 is a device top view showing an example of a power MOSFET manufactured by the method of manufacturing a semiconductor device according to the embodiment of the present application. As shown in FIG. 3, a power MOSFET element chip 8 (trench gate power MOS type) in which elements are formed on a square or rectangular plate-like silicon-based semiconductor substrate (wafer before being divided into individual chips). In the semiconductor device, the source pad region 11 (aluminum-based pad) in the center occupies the main area. Below that, a strip-like repetitive device pattern region R (a plurality of strip-like source contact regions and strip-like gate electrodes (corresponding to columnar trench gate electrodes) extending sufficiently longer than their width (or pitch) and strip-like source contact regions are formed. Linear cell region). More precisely, the linear cell region R extends almost entirely below the source pad region 11, and a portion surrounded by a broken line is a part thereof. In the periphery of the linear cell region R, there is a gate pad region 13 for leading the gate electrode from the periphery to the outside. Further, an aluminum guard ring 19 is provided therearound. The outermost peripheral portion of the chip 8 is an area when the wafer is divided by dicing or the like, that is, a scribe area 14.

3. Outline of device cross-section process flow in manufacturing method of semiconductor device of one embodiment of the present application (mainly FIGS. 4 to 14)
In this section, an example of a linear trench gate type power MOSFET of 0.15 micrometer process is shown in FIG. 4 to FIG. A process flow will be described for a device cross section (XX ′ cross section of FIG. 3, FIG. 8, or FIG. 10) corresponding to the trench gate cell section 12 and the like.

  FIG. 4 is a device cross-sectional flow diagram (source / contact trench forming resist pattern forming step) of the trench gate cell portion in the method of manufacturing a semiconductor device according to the embodiment of the present application. Here, an n-type epitaxial wafer 1 in which an n-type epitaxial layer (for example, the thickness of the epitaxial layer is about 4 micrometers) is formed on a 200 phi n + -type silicon single crystal wafer (silicon-based wafer) is used as a raw material wafer. An example of use will be described, but the diameter of the wafer may be 300 phi, 450 phi, or the like. Further, the conductivity type of the wafer may be p-type. Further, the type of wafer is not limited to an epitaxial wafer, and may be another semiconductor substrate, an insulating substrate, or the like. Further, if necessary, it may be a semiconductor wafer or substrate other than silicon.

  As shown in FIG. 4, the semiconductor wafer 1 is mainly composed of an n + silicon substrate portion 1s and an epitaxial layer 1e. In the epitaxial layer 1e, there is an n-type drift region 2 which is an original n-type epitaxial layer. In the upper part, a p-type channel region (p-type base region) 3, an n + source region 4 and the like are formed. A plurality of trench gate electrodes (polysilicon electrodes) 6 are periodically provided so that the upper portion protrudes from the epitaxial layer 1 e, and a gate insulating film 7 is formed around the middle and lower portions of each trench gate electrode 6. Is provided. An interlayer insulating film 21 is formed on the device surface side 1 a of the semiconductor wafer 1 to completely cover each trench / gate electrode 6. As the interlayer insulating film 21, from the lower layer, for example, a silicon nitride film (silicon nitride insulating film) having a thickness of approximately 60 nm, a PSG film (silicon oxide insulating film) having a thickness of approximately 300 nm, A multilayer insulating film composed of a thick SOG film (silicon oxide insulating film) or the like can be exemplified.

  A resist film 9 for processing is formed on the interlayer insulating film 21. When dry etching is performed using the resist film 9 as an etching mask, a recess (source contact groove) 22 is formed as shown in FIG. Next, when the resist film 9 that has become unnecessary is removed, the state shown in FIG. 6 is obtained.

  Next, when dry etching is further performed using the patterned interlayer insulating film 21 as an etching mask, the recess (source contact groove) 22 is extended to the upper end of the p-type channel region 3 as shown in FIG. The

  A device upper surface (wafer upper surface) corresponding to FIG. 7 (corresponding to FIG. 9) at this time is shown in FIG. In FIG. 8, the cell repetition unit region G is also shown corresponding to FIG.

  Following FIG. 7, as shown in FIG. 9, the source contact groove 22 (for example, the groove bottom width is about 300 nm, the depth is about 850 nm, the aspect ratio is about 2 or more and about 5 or less, and the average is about 2.8. P + body contact region 5 is introduced into the surface region of p-type channel region 3 by ion implantation.

  Next, as shown in FIG. 11, the width of the interlayer insulating film 21 is reduced by performing isotropic oxide film etching on the front side 1 a of the wafer 1. As a result, a recess (source contact groove) 22 having a two-stage structure constituted by the recess bottom upper stage 25 and the recess bottom lower stage 26 is completed. FIG. 10 shows a device upper surface (wafer upper surface) corresponding to FIG. 11 at this time.

  In the state of FIG. 11, as shown in FIG. 12, a TiW film as a barrier metal film 23 is formed on almost the entire device surface side 1 a of the semiconductor wafer 1 by sputtering (FIG. 2).

  The TiW film 23 is formed by sputtering in the following procedure, for example. That is, the wafer 1 is accommodated in the wafer transfer container (wafer cassette) 53 of FIG. 1 and set in the load port 52 of the multi-chamber type wafer processing apparatus 51. From there, the wafer 1 is first set on the wafer stage in the degas chamber 56, and a pre-heating process for removing moisture on the surface is executed. Examples of conditions for the pre-heat treatment include a stage temperature setting of about 250 degrees Celsius, a pressure of about 266 Pascal, an argon flow rate of about 200 sccm, and a processing time of about 45 seconds.

  Next, the wafer 1 is set on the wafer stage of the sputter etch chamber 57 of FIG. 1, and a sputter etch process for removing the oxide film on the surface is performed as necessary. As the conditions of the sputter etching process, for example, the stage temperature is not controlled, the pressure is about 0.5 Pascal, the argon flow rate is about 37.5 sccm, and the plasma excitation method is, for example, the CCP (Capacitively Coupled Plasma) method, high frequency power 400 W (for example, 60 MHz). ), A processing time of about 25 seconds, and an etching amount of about 10 nm can be exemplified.

  Next, the wafer 1 is set on the wafer stage of the TiW sputter deposition chamber 59 shown in FIGS. 1 and 2, and a TiW sputter deposition process is performed by, for example, a normal sputtering method. Here, ILC1060 manufactured by Canon Anelva, which is a normal sputtering apparatus, was used as the sputtering film forming apparatus for TiW. The film forming conditions are, for example, a film thickness of about 200 nm (preferably, for example, about 100 nm or more and 300 nm or less), a processing time of about 60 seconds, a vacuum degree of about 0.5 Pascal, an argon flow rate of about 40 sccm, and a stage temperature About 100 degrees Celsius (wafer is off electrostatic chuck), target side DC power is about 3000 watts, wafer side ground, target composition titanium 10% tungsten 90% (% by weight). This step can also be performed by an ionization sputtering method such as a PCM method.

  Next, when silicidation annealing is performed, in FIG. 12, the surface of the silicon member in contact with the TiW film 23 becomes thin titanium silicide due to titanium supplied from the lower surface and inside of the TiW film 23. Since the illustration becomes complicated, these changes are not displayed in FIGS.

  This silicidation annealing is performed by the following procedure, for example. That is, the wafer 1 is unloaded from the multi-chamber type wafer processing apparatus of FIG. And it accommodates in the wafer container 53, for example, is transferred to a batch-type annealing apparatus, and a silicidation annealing process is performed. As conditions for this silicidation annealing treatment, for example, a temperature of about 650 degrees Celsius, an atmospheric pressure, for example, a normal pressure, a nitrogen gas flow rate of about 15 liters / minute, and a processing time of about 10 minutes can be exemplified. This step can also be performed by a single wafer RTA apparatus provided in the multi-chamber type wafer processing apparatus 51 or at another place.

  When the silicidation annealing is completed, as shown in FIG. 13, a seed aluminum-based metal film 24s is formed on almost the entire surface of the TiW film 23b by, for example, PCM sputtering film formation. The seed / aluminum-based metal film portion 24s and the main body-based aluminum-based metal film 24 can also be executed using other ionized sputtering film forming apparatuses. Further, in a situation where the embedding characteristics are not so severe, a normal non-ionized sputtering film forming apparatus similar to the normal sputtering film forming chamber 59 (FIG. 1) can also be used.

  The seed aluminum film 24s is formed by the following procedure, for example. That is, the wafer 1 is discharged from the batch type annealing apparatus, is accommodated in the wafer transfer container (wafer cassette) 53 of FIG. 1, and is set in the load port 52 of the multi-chamber type wafer processing apparatus 51. From there, the wafer 1 is set again on the wafer stage in the degas chamber 56, and a pre-heating process for removing moisture and the like on the surface is executed. Examples of conditions for the pre-heat treatment include a stage temperature setting of about 375 degrees Celsius, a pressure of about 266 Pascal, an argon flow rate of about 200 sccm, and a processing time of about 50 seconds.

  Thereafter, the wafer 1 is set on the wafer stage 62 in the aluminum-based metal film sputtering chamber 61 shown in FIGS. 1 and 2, and the sputter film forming process of the seed aluminum-based metal film 24s is executed. The conditions of the seed / aluminum-based metal film formation process include, for example, a stage temperature setting of about 420 degrees Celsius (the electrostatic chuck is off), a pressure of about 5 Pascal, an argon flow rate of about 20 sccm, and an upper electrode high frequency power of 4 kW (for example, 60 MHz). ), The upper electrode DC power 1 kW, the lower electrode high frequency power 200 W (for example, 13.56 MHz), the processing time is about 14 minutes, and the film formation amount is about 2750 nm. A suitable range for setting the stage temperature is about 400 degrees Celsius to 440 degrees Celsius. Here, by turning off the electrostatic chuck, the wafer temperature rises excessively during the seed / aluminum-based metal film forming process, and the reflow of the deposited aluminum-based metal member proceeds excessively, and the source contact groove 22 It is possible to avoid closing the top of the. That is, in the first half of the formation of the aluminum-based metal member film, the final embedding characteristic is achieved by forming a sufficiently thick aluminum-based metal member film on the bottom surface portion of the source contact groove 22 rather than flattening by reflow. The contribution of is large. Therefore, the bias of the lower electrode is particularly effective in this first half portion in that metal ions penetrate more vertically onto the wafer.

  Next, as shown in FIG. 13, a concave portion (source contact groove) 22 is formed integrally with the seed / aluminum-based metal film 24s by PCM sputtering deposition on almost the entire surface of the seed / aluminum-based metal film 24s. Then, an aluminum-based metal film 24 is formed so as to fill the inside and further cover the TiW film 23 b outside the recess (source contact groove) 22. That is, by this process, the aluminum-based metal film 24 to be the source electrode 24 (emitter electrode in the case of IGBT) is formed.

  The latter sputter deposition process (second half) of the aluminum-based metal film 24 is performed, for example, in the following procedure. That is, the wafer 1 is continuously set on the wafer stage 62 in the film forming chamber 61 when the seed / aluminum-based metal film 24s is formed (with various conditions substantially unchanged), Shift to the following processing conditions. That is, as the conditions for the sputtering process of the latter aluminum-based metal film 24, for example, the stage temperature setting is about 420 degrees Celsius (electrostatic chuck is on), the pressure is about 5 Pascal, the argon flow rate is about 20 sccm, the upper electrode high frequency power For example, 4 kW (for example, 60 MHz), upper electrode DC power 1 kW, lower electrode high-frequency power is off, processing time is about 14 minutes, and the amount of film formation is about 2750 nm. A suitable range for setting the stage temperature is about 400 degrees Celsius to 440 degrees Celsius. A preferable thickness range of the entire aluminum-based metal film 24 is, for example, about 3 μm or more and 7 μm or less.

In addition, if the stage temperature setting during the sputter deposition process (first half and second half) is less than 400 degrees Celsius, the reflow does not proceed sufficiently, and if it exceeds 440 degrees Celsius, undesired metal agglomeration tends to occur. Become. Further, if the lower electrode high-frequency power is turned on in the sputter film formation process (second half), a similar aggregation phenomenon tends to occur due to an undesired rise in wafer temperature.
As a source electrode material, AlCu, pure Al, a copper metal member, etc. can be used in addition to the silicon-added aluminum metal (AlSi) described here.

  Thereafter, the aluminum-based metal film 24 is patterned, and a final passivation insulating film (for example, an organic insulating film such as a coating-based polyimide resin film having a thickness of about 2 micrometers) is formed thereon. A clear opening. Thereafter, the back surface of the wafer 1 is processed by grinding or wet etching, so that the wafer has a desired final thickness (for example, about 80 μm or more and 160 μm or less). That is, the wafer 1 is thinned.

  Next, as shown in FIG. 14, when the drain electrode metal layer 20 is formed on the back surface of the wafer 1 by sputtering and divided into individual chips, the device shown in FIG. 3 is obtained.

  In this example, as shown in FIG. 11, the head portion of the trench gate electrode 6 is covered with a relatively thick interlayer insulating film 21, and a space between adjacent interlayer insulating films 21 is a two-stage structure. The concave portion (source contact groove) 22 is formed. Such a structure has an advantage that the area of the contact portion is increased and the contact characteristics can be improved. On the other hand, there is a demerit that the structure becomes complicated at the boundary between the lowermost stage (the concave bottom face 26) and the upper part (the concave bottom face upper stage 25) by using the concave portion (source contact groove) 22 having a two-stage structure. Therefore, when it is desired to avoid such disadvantages, a structure having a flat bottom surface can be used.

4). Explanation of data showing warpage of wafer manufactured by manufacturing method of semiconductor device of one embodiment of the present application, consideration on the entire present application, etc. (mainly FIG. 15 and FIG. 16)
In this section, a mechanism for reducing the warpage of the wafer according to the above embodiment will be described.

  FIG. 15 is a data plot diagram showing the relationship between the TiW sputtering pressure and the wafer warp after the barrier metal film forming step corresponding to FIG. FIG. 16 is a data plot diagram showing the relationship between the wafer thickness and the wafer warpage in the embodiment and the comparative example after the back surface metal film forming step corresponding to FIG. Here, geometrically, the amount of warpage substantially corresponds to the length of a normal line standing from the plane including the outer periphery of the wafer toward the center of the wafer. The sign of the amount of warpage is such that the device surface 1a is up and the down is convex.

  As shown in FIG. 15, when the pressure in the chamber at the time of sputter deposition is in the general-purpose pressure region A, the amount of warpage of the wafer at the completion of TiW sputter deposition is a relatively small positive or negative value. On the other hand, when the pressure in the chamber at the time of sputter deposition is in the pressure region B effective for warpage reduction corresponding to the above-described embodiment, the amount of warpage of the wafer at the completion of TiW sputter deposition is relatively large. It turns out that the value of is shown. As described above, the warping stress changes relatively greatly depending on the pressure in the chamber during TiW sputtering film formation. Argon constituting the atmosphere is taken in during film formation and voids are removed when it later escapes. It is presumed that it is formed.

  As shown in FIG. 16, the warp amount of the wafer after the backside metal film formation (final thickness) corresponding to this (the warp amount in the final thickness of the wafer) is reduced in the comparative example as shown in FIG. It can be seen that the amount of warpage of the wafer rapidly increases. On the other hand, at the film forming pressure corresponding to the above-described embodiment, the final thickness is within the range of 0.5 mm. This is because the warp due to the aluminum-based alloy film as the source electrode metal shows a relatively large positive value, but the warp stress in the positive direction and the relatively large warp stress in the negative direction of the TiW film are balanced. It is thought that it is because. Since this is a major problem in handling such as conveyance after the thinning process, it is very advantageous in mass production that there is little warpage at the time after the thinning process.

  The pressure (degree of vacuum) in the chamber at the time of sputtering film formation is generally preferably 1.2 Pascal or less from FIG. However, considering process stability, 1.0 Pa or less is more preferable. The lower limit of the preferable atmospheric pressure range may be lowered as necessary (depending on the final thickness of the wafer), and although there is no particular limit, if the final thickness is up to about 80 micrometers, 0.3 Pascal (or 0 .4 Pascal) or higher. Therefore, as a preferable range, 0.3 Pascal or more, 1.2 Pascal or less (or 0.4 Pascal or more, 1.0 Pascal or less), or a range corresponding to each combination of these upper and lower limits Can do.

  Note that titanium-based materials that are widely used as barrier metals have a warping stress in the same direction as that of the aluminum-based alloy film, and thus it is difficult to obtain the same effect as the TiW film. In addition, in a device with a built-in SBD (Schottky Barrier Diode), there is an additional advantage that a tungsten-based barrier metal film such as a TiW film is effective from the viewpoint of securing diode characteristics.

5). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. .

  For example, in the above-described embodiment, the power MOSFET has been specifically described as an example. However, the invention of the present application is not limited thereto, and is widely applied to other single units such as IGBTs, integrated circuit elements including them, and the like. Needless to say, you can.

  In the above-described embodiment, the N-channel type device such as the N-channel type power MOSFET has been specifically described. However, the invention of the present application is not limited thereto, and the P-channel type device such as the P-channel type power MOSFET is used. Needless to say, it can also be applied. In that case, what is necessary is just to perform PN inversion operation which carries out total exchange of P and N in the said embodiment.

  Further, in the above-described embodiment, the description has mainly focused on the sputtering film forming method as the metal member film forming method. However, the invention of the present application is not limited thereto, and the CVD method, plating may be performed as necessary. Needless to say, law can be applied.

1 Semiconductor wafer (epitaxial wafer)
1a Device surface of the wafer (first main surface)
1b Wafer backside 1e Epitaxial layer (n-type epitaxial layer)
1s n + silicon substrate part 2 n-type drift region 3 p-type channel region (p-type base region)
4 n + source region 5 p + body contact region 6 trench gate electrode (polysilicon electrode)
7 Gate insulating film 8 Chip or chip region 9 Resist film 11 Source pad 12 Cell region (trench gate gate cell part)
13 Gate pad 14 Scribe area (dicing area)
19 Guard ring 20 Drain electrode 21 Interlayer insulating film 22 Recessed portion (source contact groove)
23 Barrier metal film 24 Aluminum metal film (source electrode)
24 s Seed aluminum-based metal film part 25 Upper part of recess bottom part 26 Lower part of recess bottom part 51 Multi-chamber type wafer processing apparatus 52 Load port (or front chamber)
53 Wafer transfer container (wafer cassette)
54 Load lock chamber 55 Vacuum transfer chamber 56 Degassing chamber 57 Sputtering / etching chamber 58 Preliminary chamber 59 Conventional sputtering film forming chamber for TiW 61 Aluminum-based metal film sputtering chamber 62 Lower electrode (wafer stage)
66 Upper electrode (target backing plate)
67 Target 78 Gas supply path 81 Exhaust port A General-purpose pressure area B Pressure area effective for warping reduction G Cell repeat unit area R Strip-like repeat device / pattern area cut-out portion

Claims (15)

A semiconductor device manufacturing method including the following steps:
(A) forming a recess from the upper surface of the first insulating film on the first main surface of the semiconductor wafer downward;
(B) forming a tungsten-based barrier metal film by sputtering film formation on the inner surface of the recess and the upper surface of the first insulating film;
(C) after the step (b), forming an aluminum-based metal layer so as to cover the tungsten-based barrier metal film on the inner surface of the recess and the upper surface of the first insulating film;
Here, the step (b) is performed in a sputtering film forming chamber having an atmospheric pressure of 1.2 Pa or less.     In the method of manufacturing a semiconductor device according to the item 1, in the step (b), the tungsten-based barrier metal film contains tungsten as a main component and titanium as a secondary component.     In the method for manufacturing a semiconductor device according to the item 2, the composition weight ratio of the target used in the step (b) is approximately Ti: W = 1: 9.     In the method for manufacturing a semiconductor device according to the item 1, the step (b) is usually performed by sputtering.     In the method for manufacturing a semiconductor device according to the item 1, the tungsten-based barrier metal film has a thickness of 100 nm or more and 300 nm or less.     In the method of manufacturing a semiconductor device according to the item 1, the thickness of the aluminum-based metal layer is not less than 3 micrometers and not more than 7 micrometers.     In the method for manufacturing a semiconductor device according to the item 1, the atmospheric pressure is 0.3 Pascal or more.     In the method for manufacturing a semiconductor device according to the item 1, the atmospheric pressure is 1.0 Pascal or less.     In the method for manufacturing a semiconductor device according to the item 1, the atmospheric pressure is 0.4 Pascal or more.     In the method for manufacturing a semiconductor device according to the item 1, the atmospheric pressure is 0.3 Pascal or more and 1.0 Pascal or less.     In the method for manufacturing a semiconductor device according to the item 1, the atmospheric pressure is 0.4 Pascal or more and 1.0 Pascal or less.     In the method for manufacturing a semiconductor device according to the item 1, the final thickness of the semiconductor wafer is not less than 80 micrometers and not more than 160 micrometers.     In the method for manufacturing a semiconductor device according to the item 1, the semiconductor wafer is a 200φ silicon-based wafer.     In the method for manufacturing a semiconductor device according to the item 1, the semiconductor device includes a power MOSFET.     In the method for manufacturing a semiconductor device according to the item 1, the concave portion has a two-stage structure.

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