JP2013134998A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process a rear face while protecting an element formation face without limiting a temperature of a semiconductor substrate during a rear face processing step, in a semiconductor device manufacturing method having the rear face processing step.SOLUTION: The semiconductor device manufacturing method includes: a surface processing step of forming at least one part of a semiconductor element on one side of a semiconductor substrate; and a rear face processing step of processing a rear face opposed to one face after the surface processing step. The method also includes: an inorganic film formation step of forming an inorganic protective film across an entire face of one face after the surface processing step and before the rear face processing step; an organic film formation step for forming an organic protective film across an entire face of the inorganic protective film and then patterning the organic protective film after the inorganic film formation step and before the rear face processing step; and an inorganic film removing step of removing one part of the inorganic protective film with the organic protective film as a mask after the rear face processing step.

Description

  The present invention relates to a method for manufacturing a semiconductor device including a back surface treatment step, and a semiconductor device manufactured by the method.

  As a method for manufacturing a semiconductor device, a surface treatment process for manufacturing a semiconductor substrate having a semiconductor element formed on a first main surface (hereinafter referred to as an element formation surface), and a second main surface on the opposite side of the element formation surface of the semiconductor substrate There is a method for manufacturing a semiconductor device including a back surface processing step for performing processing such as back grinding and ion implantation on a surface (hereinafter referred to as a back surface).

  In such a back surface processing step, the back surface of the semiconductor substrate is processed with the element formation surface in contact with the stage. For this reason, the semiconductor element formed on the element formation surface is damaged, and there is a concern that the quality of the semiconductor device may be degraded.

  In order to solve this problem, Patent Document 1 proposes a method of performing a back surface treatment step after applying a peelable protective tape to the element formation surface. According to this method, the element forming surface can be prevented from coming into direct contact with the stage during the back surface processing step, and the back surface can be processed without damaging the element forming surface.

JP 2002-270676 A

  However, when the method of Patent Document 1 is used, a process in which the temperature of the semiconductor substrate is equal to or higher than the heat-resistant temperature of the protective tape cannot be performed in the back surface treatment process. In Patent Document 1, it is proposed to perform the process while cooling the semiconductor substrate in the process at which the temperature exceeds the above-mentioned heat resistance temperature. However, in processes such as ashing and sputtering, it is considered that the temperature of the semiconductor substrate reaches a temperature exceeding the generally known heat resistance temperature of the protective tape (about 150 ° C.) even while cooling. . In addition, problems such as the need for cooling equipment arise.

  The present invention has been made in view of the above problems, and in a method for manufacturing a semiconductor device including a back surface processing step, while protecting the element formation surface without limiting the temperature of the semiconductor substrate during the back surface processing step. The purpose is to perform backside processing. Another object of the present invention is to provide a semiconductor device manufactured by the manufacturing method.

In order to achieve the above object, the invention described in claim 1
A surface treatment step of forming at least a part of the semiconductor element on one surface side of the semiconductor substrate;
After the surface treatment step, a back surface treatment step for processing the back surface opposite to the one surface, and a method for manufacturing a semiconductor device,
After the surface treatment step, before the back surface treatment step, an inorganic film forming step for forming an inorganic protective film over the entire surface of one surface;
After the inorganic film forming step, before the back surface treatment step, after forming the organic protective film over the entire surface of the inorganic protective film, an organic film forming step of patterning the organic protective film;
And an inorganic film removing step of removing a part of the inorganic protective film using the organic protective film as a mask after the back surface treatment process.

  According to this method, the inorganic protective film is formed over the entire surface on the one surface side of the semiconductor substrate by the inorganic film forming step before the back surface treatment step. And an organic protective film is formed in a part on an inorganic protective film by an organic film formation process. For this reason, even when the semiconductor substrate is placed on a stage or the like so that the one surface side comes into contact during the back surface treatment process, the semiconductor element formed on one surface side of the semiconductor substrate is not damaged over the entire surface of the one surface side. Can be processed. In addition, this method is a method that does not use a protective tape, and the temperature of the semiconductor substrate during the back surface treatment step can be prevented from being limited by the heat-resistant temperature of the protective tape. In addition, the semiconductor device manufactured by the manufacturing method according to the present invention includes an inorganic protective film and an organic protective film as a film for protecting one surface side of the semiconductor element. As a result, it is possible to suppress the deterioration of the protective film over time due to the load on the back surface treatment process and the use environment of the semiconductor element. In general, inorganic materials have higher hardness and melting point than organic materials. That is, the progress of scratches that the organic protective film has received during the back surface treatment process can be suppressed by the inorganic protective film. Therefore, it can suppress that a damage | wound reaches | attains the part covered with the inorganic protective film among semiconductor elements.

The above-described invention can be applied particularly to a method for manufacturing an insulated gate bipolar transistor (hereinafter referred to as IGBT). That is, as described in claim 2,
As a semiconductor element, an insulated gate bipolar transistor is formed,
As a surface treatment process,
Forming a second conductivity type base layer on a surface layer of one surface of the first conductivity type semiconductor substrate;
Forming a plurality of first conductivity type emitter layers on the surface of the base layer;
A diffusion layer and a gate forming step for forming a plurality of gate electrodes through a gate insulating film on one surface side of the semiconductor substrate;
Forming an insulating film on one surface of the semiconductor substrate so as to cover the gate electrode and forming a plurality of contact holes in the insulating film corresponding to each gate electrode;
Forming a gate line so as to be electrically connected to a plurality of gate electrodes through each contact hole; and
An emitter electrode forming step for forming an emitter electrode so as to be electrically connected to the base layer and the emitter layer and to cover a portion of the insulating film excluding the gate line forming portion;
As a backside treatment process,
A back-grinding process to thin the semiconductor substrate by grinding it from the backside;
A collector electrode forming step of forming a collector layer of the second conductivity type on the back surface side surface of the ground semiconductor substrate and forming a collector electrode electrically connected to the collector layer on the back surface of the semiconductor substrate; And
In the organic film forming step, the organic protective film is patterned so as to overlap with the entire edge line and the gate line except the pad area exposed to the outside of the emitter electrode,
In the inorganic film removing step, a part of the inorganic protective film can be removed using the organic protective film as a mask, and the pad region of the emitter electrode can be exposed to the outside.

  According to this, in the back surface treatment step, the insulating film, the gate line, and the emitter electrode on the gate electrode can be prevented from directly contacting the stage or the like by the inorganic protective film and the organic protective film. In other words, the back surface treatment process can be performed without damaging the insulating film, the gate line, and the emitter electrode. For this reason, it is possible to suppress a decrease in breakdown voltage due to scratches on the insulating film and disconnection of the gate line and the emitter electrode, and it is possible to suppress a change in resistivity. Further, the inorganic protective film is removed by the inorganic film removing step, and the pad region of the emitter electrode exposed on the one surface side becomes an adhesive surface with solder or the like for connecting to an external circuit. According to the present invention, since the scratch caused by the back surface treatment process can be prevented from occurring in the pad region of the emitter electrode, the connection strength between the emitter electrode and the solder can be increased, and the connection reliability is improved. be able to. Moreover, IGBT manufactured with the manufacturing method which concerns on this invention has an inorganic protective film so that a gate line may be covered, and will have an organic protective film on an inorganic protective film. For this reason, the progress of the damage | wound which the organic protective film received at the time of a back surface process can be suppressed by an inorganic protective film. Therefore, it is possible to suppress the scratch from reaching the gate line. In the vertical IGBT, in connecting the emitter electrode and the external circuit, for example, solder is introduced onto the emitter electrode to fix the terminal of the external circuit and the like. And when fixing a terminal etc., a solder may be located on the protective film which covers a gate line. As described above, by suppressing the progress of the scratches that the organic protective film received during the back surface treatment process with the inorganic protective film, the solder on the protective film can be prevented from entering the protective film, and the gate line and the emitter A short circuit via solder with the electrode can be suppressed.

  Preferably, the semiconductor wafer is made of silicon, the inorganic protective film is a silicon nitride film or a silicon oxide film, and the organic protective film is made of a polyimide resin.

  By adopting such a method, the present invention can be realized in the current manufacturing process of a semiconductor device. In other words, the manufacturing method of the semiconductor device according to the present invention can be realized by diverting the current manufacturing line.

The invention according to claim 4
A semiconductor device manufactured by the manufacturing method according to claim 2 or 3,
As a semiconductor element, there is a trench type insulated gate bipolar transistor in which a gate electrode and a gate insulating film are formed through a base layer from a surface on one surface side of a semiconductor substrate.

  Since the operational effects of the semiconductor device according to the present invention are the same as the operational effects described in claim 2 or claim 3, the description thereof is omitted.

1 is a top view illustrating a schematic configuration of a semiconductor device according to a first embodiment. It is a cross-sectional perspective view of the area | region II shown with a dashed-dotted line in FIG. 3A and 3B are cross-sectional views showing a diffusion layer and a gate forming step, where FIG. 2A shows a yz cross section in FIG. 2 and FIG. 2B shows an xz cross section in FIG. 3A and 3B are cross-sectional views showing a gate line forming step and an emitter electrode forming step, where FIG. 2A shows a yz cross section in FIG. 2 and FIG. It is sectional drawing which shows an inorganic film formation process, (a) shows the yz cross section in FIG. 2, (b) shows the xz cross section in FIG. It is sectional drawing which shows an organic film formation process, (a) shows the yz cross section in FIG. 2, (b) shows the xz cross section in FIG. It is sectional drawing which shows a back surface process, (a) shows yz cross section in FIG. 2, (b) shows xz cross section in FIG. It is sectional drawing which shows an inorganic film removal process, (a) shows the yz cross section in FIG. 2, (b) shows the xz cross section in FIG. It is a perspective view which shows schematic structure of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows a diffusion layer and a gate formation process, (a) shows yz cross section in FIG. 9, (b) shows xz cross section in FIG. It is sectional drawing which shows a gate line formation process and an emitter electrode formation process, (a) shows yz cross section in FIG. 9, (b) shows xz cross section in FIG. It is sectional drawing which shows an inorganic film formation process, (a) shows the yz cross section in FIG. 9, (b) shows the xz cross section in FIG. It is sectional drawing which shows an organic film formation process, (a) shows the yz cross section in FIG. 9, (b) shows the xz cross section in FIG. It is sectional drawing which shows a back surface process, (a) shows yz cross section in FIG. 9, (b) shows xz cross section in FIG. It is sectional drawing which shows an inorganic film removal process, (a) shows the yz cross section in FIG. 9, (b) shows the xz cross section in FIG. It is a top view which shows schematic structure of the semiconductor device which concerns on 3rd Embodiment. FIG. 17 is a cross-sectional perspective view of a region XVII indicated by a dashed line in FIG. 16.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same reference numerals are given to the same or equivalent parts. Moreover, in each figure, the xy plane prescribed | regulated by the mutually orthogonal x direction and y direction, and z direction orthogonal to an xy plane are defined.

(First embodiment)
First, a schematic configuration of the semiconductor device according to the present embodiment will be described with reference to FIGS. 1 and 2.

  The semiconductor device 10 according to the present embodiment includes a vertical insulated gate bipolar transistor (IGBT) having a trench gate structure as a semiconductor element formed on the semiconductor substrate 11. The IGBT is formed in the central element formation region 11c in the semiconductor substrate 11 (chip) whose planar shape along the xy plane is substantially rectangular. A breakdown voltage structure such as a guard ring (not shown) is formed in the outer peripheral region 11e surrounding the element forming region 11c.

In the present embodiment, an n conductivity type (n ⁻ ) single crystal bulk silicon substrate having an impurity concentration of about 1 × 10 ¹⁴ cm ⁻³ is used as the semiconductor substrate 11. In the element formation region 11c, a p-conductivity type (p) base layer 12 having an impurity concentration of about 2 × 10 ¹⁷ cm ⁻³ is formed on the surface layer on the one surface 11a side of the semiconductor substrate 11. The base layer 12 is selectively formed with a trench 20 that penetrates the base layer 12 and extends in the y direction. Then, a conductive material (for example, polysilicon having an impurity concentration of about 1 × 10 ²⁰ cm ⁻³ ) is filled in the trench 20 through the gate insulating film 21 formed on the wall surface of the trench 20, and the gate electrode having the trench structure A plurality of 22 are formed. Each gate electrode 22 extends in the y direction and is repeatedly formed at a predetermined pitch along the x direction. As described above, the base layer 12 is arranged in parallel along the x direction by the gate electrodes 22 provided in stripes, and is partitioned into a plurality of regions that are electrically separated from each other.

An n conductivity type (n ⁺ ) emitter layer 13 adjacent to the side surface portion of the gate insulating film 21 is selectively formed as a region having a higher impurity concentration than the semiconductor substrate 11 on the surface layer on the one surface 11 a side of the base layer 12. ing. The emitter layer 13 has an impurity concentration of about 1 × 10 ²⁰ cm ⁻³ .

  In the element formation region 11 c, an insulating film 24 for electrically separating a gate line 23, which will be described later, the base layer 12 and the emitter layer 13, is selectively formed on the one surface 11 a of the semiconductor substrate 11. The insulating film 24 includes a striped portion (stripe portion 24a) formed along the trench 20 (that is, along the y direction) so as to cover the gate insulating film 21 and the gate electrode 22, and along the x direction. And a connecting portion that connects the stripe portions 24a.

  The gate line 23 is formed on the connecting portion of the insulating film 24 in the element formation region 11c. And it is electrically connected to the gate pad 25 formed in one outer peripheral region 11e in the y direction through the gate line 23 formed in the outer peripheral region 11e. The gate line 23 and the gate pad 25 are integrally formed. Further, the gate line 23 is electrically connected to the gate electrode 22 through the contact hole 26 at a point where the stripe portion 24a of the insulating film 24 and the connecting portion intersect in the element formation region 11c.

  The emitter electrode 30 is formed in almost all the element formation region 11c. Specifically, it is provided in contact with the portion of the base layer 12 and the emitter layer 13 exposed on the one surface 11 a of the semiconductor substrate 11 and is also integrated with a part on the insulating film 24 so as not to contact the gate line 23. Provided.

  A protective film 40 is formed so as to cover the gate line 23 and the edge region 30b excluding the pad region 30a exposed to the outside in the emitter electrode 30. In other words, only the pad region 30 a and the gate pad 25 of the emitter electrode 30 are exposed from the protective film 40 on the one surface 11 a side of the semiconductor substrate 11. The protective film 40 includes an inorganic protective film 41 and an organic protective film 42, the inorganic protective film 41 is formed on one surface 11 a of the semiconductor substrate 11, and the organic protective film 42 is formed on the inorganic protective film 41. . In the present embodiment, the inorganic protective film 41 is, for example, a silicon nitride (SiN) film, and the organic protective film 42 can be, for example, a polyimide resin.

On the other hand, a p conductivity type (p ⁺ ) collector layer 14 is formed on the surface layer of the semiconductor substrate 11 on the back surface 11b side opposite to the one surface 11a. A collector electrode 31 is formed on the entire back surface 11 b, and the collector electrode 31 is electrically connected to the collector layer 14. The collector layer 14 has an impurity concentration of about 7 × 10 ¹⁷ cm ⁻³ .

  Next, a method for manufacturing the semiconductor device 10 according to the present embodiment will be described with reference to FIGS. 3 to 8, (a) shows the yz section in FIG. 2, and (b) shows the xz section.

First, a diffusion layer and gate formation process is performed. As shown in FIGS. 3A and 3B, a p-type base layer 12 is formed by doping an impurity such as boron in the surface layer on the one surface 11 a side of the semiconductor substrate 11. Then, the trench 20 is formed so as to penetrate the base layer 12 from the surface on the one surface 11a side of the semiconductor substrate 11 and extend in the y direction. Then, after forming a gate insulating film 21 made of, for example, silicon oxide (SiO ₂ ) on the inner wall of the trench 20, the gate electrode 22 is formed by filling the trench 20 with, for example, doped polysilicon. Then, a plurality of n ⁺ -type emitter layers 13 are formed by doping impurities such as phosphorus adjacent to the side surface portion of the trench 20 in the x direction and extending in the y direction on the surface layer of the base layer 12. The order of forming the trench 20 and the emitter layer 13 is not limited to the above. That is, the emitter layer 13 is formed so as to be exposed to the one surface 11a and surrounded by the base layer 12, and then the trench 20 is formed so as to penetrate the emitter layer 13 and the base layer 12, and then the gate insulating film 21, the gate The electrode 22 may be formed.

  Next, an insulating film forming step is performed. As shown in FIGS. 3A and 3B, an insulating film 24 is formed so as to cover one surface 11a corresponding to the formation position of the gate electrode 22 and a gate line 23 described later. Thereby, the stripe part 24a and the connection part of the insulating film 24 are formed. Then, a contact hole 26 is formed in the insulating film 24 at a point where the stripe portion 24a and the connecting portion intersect.

  Next, a gate line formation step and an emitter electrode formation step are performed. As shown in FIGS. 4A and 4B, the gate line 23 is formed on the connecting portion in the insulating film 24 and the outer peripheral region 11e. At this time, the gate line 23 is connected to the gate electrode 22 through the contact hole 26. In this gate line formation step, the gate pad 25 is also formed integrally with the gate line 23. Further, the emitter electrode 30 is formed so as to cover a part (connecting portion) of the insulating film 24 so as to be in contact with the base layer 12 and the emitter layer 13 exposed on the one surface 11a but not to be in contact with the gate line 23. In addition, the emitter electrode 30 and the gate line 23 in this embodiment can use aluminum as those constituent materials, and can be formed by sputtering method.

  The above process corresponds to the surface treatment process in the present embodiment.

  Next, an inorganic film forming step is performed. As shown in FIGS. 5A and 5B, the inorganic protective film 41 covers the entire surface of the emitter electrode 30, the gate line 23, and the insulating film 24, that is, covers the entire surface of the one surface 11 a of the semiconductor substrate 11. Form. In the present embodiment, for example, silicon nitride (SiN) is formed by deposition using a plasma CVD method.

  Next, an organic film forming step is performed. As shown in FIGS. 6A and 6B, an organic protective film 42 is applied using a spin coater over the entire surface of the inorganic protective film 41 formed by the inorganic film forming step. Then, the organic protective film 42 is patterned so as to overlap the entire surface of the gate line 23 and the edge region 30 b of the emitter electrode 30. In the present embodiment, as a constituent material of the organic protective film 42, for example, a polyimide resin can be used.

  Next, a back surface treatment process is performed. As shown in FIGS. 7A and 7B, in the back surface processing step, the one surface 11a side of the semiconductor substrate 11 is placed on the stage 100 and the back surface 11b side opposite to the one surface 11a is processed. That is, the back surface 11 b is processed while the organic protective film 42 is in contact with the stage 100. In the present embodiment, as the back surface processing step, a back grinding step in which the semiconductor substrate 11 is ground and thinned from the back surface 11b side, and a collector electrode 31 that contacts the back surface 11b after forming the collector layer 14 on the surface layer of the back surface 11b. An example having a collector forming step of forming In the back grinding process, while the organic protective film 42 is in contact with the stage 100, grinding is performed using a grindstone (not shown) while applying pressure from the back surface 11b side, so that the semiconductor substrate 11 is thinned. In the collector forming step, the back surface 11b is doped with an impurity such as boron, and the collector layer 14 is formed on the entire back surface 11b. And the collector electrode 31 which consists of aluminum is formed in the surface of the back surface 11b by sputtering method. Note that another element may be formed together with the IGBT as the semiconductor element configured on the semiconductor substrate 11. For example, an RC-IGBT in which a free wheel diode is integrally formed with an IGBT may be manufactured. In this case, in the collector forming step, the back surface 11b is doped with impurities such as boron, and the collector layer 14 is formed on the entire back surface 11b. Then, a resist mask (not shown) is formed, and a cathode layer (not shown) is selectively formed by doping impurities such as phosphorus. Thereafter, the resist mask is removed by ashing, and a collector electrode 31 made of aluminum is formed by sputtering.

  Next, an inorganic film removing step is performed. As shown in FIGS. 8A and 8B, the inorganic protective film 41 formed on the one surface 11a side of the semiconductor substrate 11 is anisotropically dry-etched using the organic protective film 42 as a mask, and a pad region of the emitter electrode 30 is obtained. 30a is exposed.

  The semiconductor device 10 according to this embodiment can be manufactured through the above steps.

  Next, functions and effects of the semiconductor device 10 and the manufacturing method thereof according to the present embodiment will be described.

  In the manufacturing method of the semiconductor device 10 according to the present embodiment, the semiconductor substrate 11 is disposed so that the one surface 11a side on which the inorganic protective film 41 and the organic protective film 42 are formed is in contact with the stage 100 in the back surface treatment process.

  Among the back surface processing steps, in the back grinding step, when the back surface 11b is ground with a grindstone, the presence of the organic protective film 42 can prevent the portion where the organic protective film 42 is not formed from being damaged. In other words, it can suppress that the part in which only the inorganic protective film 41 was formed was damaged. However, depending on the pressure during grinding, the semiconductor substrate 11 may be deformed so as to bend toward the stage 100, and the inorganic protective film 41 may come into contact with the stage 100. Even in this case, since the semiconductor substrate 11 has the inorganic protective film 41, a portion of the semiconductor element formed on the one surface 11a side of the semiconductor substrate 11, that is, the emitter electrode 30, the gate line 23, and the insulating film 24 is staged. It is possible to prevent damage due to contact with 100.

  In the collector forming step of the back surface treatment step, a resist mask is formed and impurities are doped to form the collector layer 14 (or the cathode layer). Thereafter, ashing is performed to remove the resist mask. Ashing in the present embodiment is plasma ashing, in which oxygen gas is converted into oxygen plasma by non-ionizing radiation, and the resist mask is combined with oxygen radicals generated in the plasma to change into carbon dioxide and water. For this reason, the resist mask is evaporated and peeled off. When this ashing is performed, the temperature of the semiconductor substrate 11 rises. As shown in Patent Document 1, in an example in which a protective tape is used as a member for protecting the surface 11a, the temperature of the semiconductor substrate 11 is considered to be equal to or higher than the heat resistance temperature of the protective tape. I can't do it. Or the equipment for cooling is needed. On the other hand, as shown in this embodiment, in the example using the inorganic protective film 41 and the organic protective film 42 as a member for protecting the one surface 11a, it is not necessary to use a protective tape. Therefore, ashing can be performed without being restricted by the heat-resistant temperature of the protective tape.

  Also, in the collector forming step of the back surface processing step, aluminum is deposited on the back surface 11 b of the semiconductor substrate 11 by sputtering to form the collector electrode 31. Also by this sputtering method, the temperature of the semiconductor substrate 11 rises. For this reason, as with ashing, it may be difficult to use a protective tape. On the other hand, as shown in this embodiment, in the example using the inorganic protective film 41 and the organic protective film 42 as a member for protecting the one surface 11a, it is not necessary to use a protective tape. Therefore, the collector electrode 31 can be formed by the sputtering method without being restricted by the heat resistance temperature of the protective tape.

  Further, the semiconductor device 10 manufactured by the manufacturing method shown in the present embodiment includes the inorganic protective film 41 and the organic protective film 42 as the protective film 40 on the one surface 11a side of the semiconductor device 10. For this reason, the inorganic protective film 41 can suppress the progress of scratches received by the organic protective film 42 from the stage 100 during the back surface treatment process. Therefore, it is possible to suppress the scratch from reaching the gate line 23. In the vertical IGBT, when connecting the emitter electrode 30 and an external circuit (not shown), for example, solder is introduced onto the pad region 30a of the emitter electrode 30 to fix the terminal of the external circuit. In bonding, the solder may be located on the protective film 40 that covers the gate line 23. As described above, it is possible to suppress the solder on the protective film 40 from entering the protective film 40 by suppressing the progress of scratches received by the organic protective film 42 during the back surface treatment process by the inorganic protective film 41. A short circuit through the solder between the gate line 23 and the emitter electrode 30 can be suppressed.

(Second Embodiment)
In 1st Embodiment, the example which manufactures vertical IGBT as a semiconductor element was shown. However, the semiconductor element is not limited to the vertical IGBT. In the present embodiment, for example, a vertical MOSFET, specifically, a double diffusion MOS (hereinafter referred to as DMOS) is shown as an example. The semiconductor device 10 in this embodiment has a general planar type DMOS configuration, and detailed description thereof is omitted. Below, the structure and manufacturing method of the semiconductor device 10 in this embodiment are demonstrated easily.

  First, the configuration of the semiconductor device 10 according to the present embodiment will be described with reference to FIG.

In the present embodiment, the semiconductor device 10 includes a p-type base formed by doping boron or the like as an impurity into the surface layer on the one surface 11a side of the n ⁻ -type semiconductor substrate 11 doped with phosphorus or the like as impurities in silicon. It has a layer 12. In this embodiment, the base layer 12 is formed to extend in the y direction, and is repeatedly formed at a predetermined pitch along the x direction. In addition, it has an n ⁺ -type source region 15 formed so as to be exposed to the surface layer on the one surface 11 a side while being surrounded by the base layer 12. The source region 15 is formed along the base layer 12 (extending in the y direction).

  Then, on the surface on the one surface 11a side of the semiconductor substrate 11, the gate insulating film 21 covers the region between the adjacent base layers 12, and at least a part of the base layer 12 and the source region 15 is exposed to the one surface 11a. It is formed extending in the y direction. Further, a gate electrode 22 is formed on the gate insulating film 21 so as to extend in the y direction, and electrically separates a gate line 23 (to be described later) from the base layer 12 and the source region 15 so as to cover the gate electrode 22. An insulating film 24 is formed. As in the first embodiment, the insulating film 24 is formed in a stripe-shaped portion (stripe portion 24a) formed along the gate electrode 22 and a connecting portion that is formed along the x direction and connects the stripe portion 24a. And have.

  In the insulating film 24, the gate line 23 electrically connected to the gate electrode 22 through the contact hole 26 formed at the point where the stripe portion 24 a and the connecting portion intersect is on the connecting portion of the insulating film 24. (Ie, along the x direction). The gate line 23 is electrically connected to the gate pad 25 through the gate line 23 formed in the outer peripheral region 11e of the semiconductor substrate 11 as in the first embodiment.

  Further, the source electrode 32 is formed at a position corresponding to the emitter electrode 30 in the first embodiment. Specifically, it is provided in contact with the portion of the base layer 12 and the source region 15 exposed on the one surface 11 a of the semiconductor substrate 11 and is also integrated with a part on the insulating film 24 so as not to contact the gate line 23. Provided.

  Then, the protective film 40 is formed so as to cover the gate line 23 and the edge region 32b excluding the pad region 32a exposed to the outside in the source electrode 32. In other words, only the pad region 32 a and the gate pad 25 of the source electrode 32 are exposed from the protective film 40 on the one surface 11 a side of the semiconductor substrate 11. The protective film 40 includes an inorganic protective film 41 and an organic protective film 42, the inorganic protective film 41 is formed on one surface 11 a of the semiconductor substrate 11, and the organic protective film 42 is formed on the inorganic protective film 41. . In the present embodiment, the inorganic protective film 41 is, for example, a silicon nitride (SiN) film, and the organic protective film 42 can be, for example, a polyimide resin.

On the other hand, an n ⁺ -type drain layer 16 having an impurity concentration higher than that of the semiconductor substrate 11 is formed on the surface layer on the back surface 11 b side of the semiconductor substrate 11, and a drain electrode 33 is formed so as to be in contact with the drain layer 16. . As a constituent material of the gate insulating film 21 and the insulating film 24 in the present embodiment, for example, silicon oxide (SiO ₂ ) can be used. As the gate electrode 22, for example, polysilicon can be used. Moreover, as the gate line 23, the source electrode 32, and the drain electrode 33, for example, aluminum can be used.

  Next, a method for manufacturing the semiconductor device 10 according to the present embodiment will be described with reference to FIGS. 10 to 15, (a) shows the yz section in FIG. 9, and (b) shows the xz section.

First, a diffusion layer and gate formation process is performed. As shown in FIGS. 10A and 10B, the surface layer on the one surface 11a side of the semiconductor substrate 11 is doped with an impurity such as boron to form a plurality of p-type base layers 12 extending in the y direction. Then, an n ⁺ -type source region 15 is formed along the y direction so as to be exposed inside the base layer 12 and on the surface 11a. Then, the gate insulating film 21 is formed so as to cover at least part of the base layer 12 and the source region 15 while covering the region between the adjacent base layers 12 in the surface of the surface 11a. Then, the gate electrode 22 is formed on the gate insulating film 21.

  Next, an insulating film forming step is performed. As shown in FIGS. 10A and 10B, an insulating film 24 is formed so as to cover the one surface 11a corresponding to the formation position of the gate electrode 22 and a gate line 23 described later. Thereby, the stripe part 24a and the connection part of the insulating film 24 are formed. Then, a contact hole 26 is formed at a point in the insulating film 24 where the stripe portion 24a and the connecting portion intersect.

  Next, a gate line formation step and a source electrode formation step are performed. As shown in FIGS. 11A and 11B, this step is the same as the gate line forming step and the emitter electrode forming step in the first embodiment, respectively. That is, by replacing the emitter layer 13 in the first embodiment with the source region 15 and replacing the emitter electrode 30 with the source electrode 32, the gate line forming process and the source electrode forming process in the present embodiment can be performed.

  The above process corresponds to the surface treatment process in the present embodiment.

  Next, an inorganic film forming step is performed. As shown in FIGS. 12A and 12B, this step is the same step as the inorganic film forming step in the first embodiment. That is, the inorganic protective film 41 is formed so as to cover the entire surface on the one surface 11a side of the semiconductor substrate 11 by the surface treatment process. In the present embodiment, for example, silicon nitride (SiN) is formed by deposition using a plasma CVD method.

  Next, an organic film forming step is performed. As shown in FIGS. 13A and 13B, this process is the same as the organic film forming process in the first embodiment. That is, the organic protective film 42 is formed by patterning so as to overlap the entire surface of the gate line 23 and the edge region 32 b of the source electrode 32. In the present embodiment, as a constituent material of the organic protective film 42, for example, a polyimide resin can be used.

Next, a back surface treatment process is performed. As shown in FIGS. 14A and 14B, this step is the same step as the back surface treatment step in the first embodiment. That is, by replacing the p ⁺ -type collector layer 14 in the first embodiment with the n ⁺ -type drain layer 16 and replacing the collector electrode 31 with the drain electrode 33, the back surface processing step in this embodiment can be performed.

  Next, an inorganic film removing step is performed. As shown in FIGS. 15A and 15B, this step is the same step as the inorganic film removing step in the first embodiment. That is, the inorganic protective film 41 formed on the one surface 11a side of the semiconductor substrate 11 is dry-etched using the organic protective film 42 as a mask to expose the pad region 32a of the source electrode 32.

  The semiconductor device 10 according to this embodiment can be manufactured through the above steps.

  Next, functions and effects of the semiconductor device 10 and the manufacturing method thereof according to the present embodiment will be described.

  Also in the manufacturing method of the semiconductor device 10 according to the present embodiment, as in the first embodiment, in the back surface treatment process, the one surface 11a side on which the inorganic protective film 41 and the organic protective film 42 are formed is in contact with the stage 100. A semiconductor substrate 11 is disposed. For this reason, also in this embodiment, there can exist an effect similar to 1st Embodiment. That is, the back surface treatment process can be performed without scratching the components of the semiconductor element formed on the one surface 11 a side of the semiconductor substrate 11. In addition, the back surface treatment step can be performed without being restricted by the heat resistance temperature of the protective tape.

  Moreover, the semiconductor device 10 manufactured by the manufacturing method shown in the present embodiment includes an inorganic protective film 41 and an organic protective film 42 as the protective film 40 on the one surface 11a side of the semiconductor device 10 as in the first embodiment. Will have. For this reason, also in this embodiment, there can exist an effect similar to 1st Embodiment. That is, the inorganic protective film 41 can suppress the progress of scratches received by the organic protective film 42 from the stage 100 during the back surface treatment process. Therefore, it is possible to suppress the scratch from reaching the gate line 23.

(Third embodiment)
In the first embodiment, an IGBT as a semiconductor element and a manufacturing method thereof are shown as examples. In this embodiment, a configuration including an IGBT and a temperature sensor is shown as an example of the semiconductor element.

  As shown in FIGS. 16 and 17, the semiconductor device 10 in the present embodiment is provided with a temperature sensor 200 in addition to the IGBT as the semiconductor element in the first embodiment. The temperature sensor 200 is a temperature-sensitive diode, and is electrically connected to a pn diode (not shown) formed by being electrically separated through the semiconductor substrate 11 and the insulating film 24, and an n-type region of the pn diode. The n-type side wiring 210 and the p-type side wiring 220 electrically connected to the p-type region of the pn diode. The pn diode is disposed substantially at the center of the element formation region 11c, and the n-type side wiring 210 and the p-type side wiring 220 are formed on the insulating film 24 so as to extend from the pn diode to the outer peripheral region 11e of the semiconductor substrate 11, Each is connected to the n-type side pad 230 and the p-type side pad 240 exposed from the protective film 40. The temperature sensor 200 causes a current to flow in the forward direction between the n-type side pad 230 and the p-type side pad 240, and based on the resistance value of the pn diode obtained from the current-voltage characteristics, Detect temperature. Further, the temperature sensor 200 is covered with an inorganic protective film 41 as shown in FIG. That is, the n-type side wiring 210 and the p-type side wiring 220 are covered with the inorganic protective film 41 over the entire area and overlap the organic protective film 42 formed on the inorganic protective film 41. The n-type side wiring 210 and the p-type side wiring 220 can be formed by depositing the same material as the emitter electrode 30 and the gate line 23, for example, aluminum by a sputtering method.

  The semiconductor device 10 according to the present embodiment can be manufactured as follows. That is, in the emitter electrode forming step and the gate line forming step in the first embodiment, the step of forming the n-type side wiring 210 and the p-type side wiring 220 can be performed simultaneously. Then, in the inorganic film forming step, the entire surface of the semiconductor substrate 11 including the n-type side wiring 210 and the p-type side wiring 220 is covered with the inorganic protective film 41. Next, in the organic film formation step, the organic protective film 42 is formed so as to overlap the entire area of the gate line 23 and the edge region 30 b of the emitter electrode 30, and the n-type side wiring 210 and the p-type side wiring 220 are formed. Are also formed to overlap. And after implementing a back surface treatment process, the semiconductor device 10 which concerns on this embodiment can be manufactured by implementing an inorganic film removal process.

  By adopting the semiconductor device 10 and its manufacturing method according to the present embodiment, in addition to the effects described in the first embodiment, the n-type side wiring 210 and the p-type side wiring 220 of the temperature sensor 200 are subjected to back surface processing. It is possible to prevent the process from being damaged. Therefore, changes in the wiring resistance of the n-type side wiring 210 and the p-type side wiring 220 can be suppressed, and the temperature can be detected with high accuracy. In the semiconductor device 10 according to the present embodiment, the inorganic protective film 41 and the organic protective film 42 are formed so as to cover the entire area of the n-type side wiring 210 and the p-type side wiring 220. For this reason, the inorganic protective film 41 can suppress the progress of scratches received by the organic protective film 42 from the stage 100 during the back surface treatment process. Therefore, it is possible to suppress the damage from reaching the n-type side wiring 210 and the p-type side wiring 220. As in the first embodiment, solder may be located on the protective film 40 when the pad region 30a of the emitter electrode 30 is connected to an external circuit. As described above, it is possible to suppress the solder on the protective film 40 from entering the protective film 40 by suppressing the progress of scratches received by the organic protective film 42 during the back surface treatment process by the inorganic protective film 41. Short-circuiting between the n-type side wiring 210 and the p-type side wiring 220 and the emitter electrode 30 via solder can be suppressed.

(Other embodiments)
The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

In each of the above-described embodiments, an example in which silicon nitride (SiN) is used as a constituent material of the inorganic protective film 41 has been described, but the present invention is not limited to the above example. For example, silicon oxide (SiO ₂ ) can be used.

  In each of the above-described embodiments, an example in which a polyimide resin is used as a constituent material of the organic protective film 42 has been described. However, the present invention is not limited to the above example. For example, polybenzoxazole or silicon resin can be used.

  In the first embodiment, an example in which the semiconductor element is a vertical IGBT having a trench structure has been described. However, the present invention is not limited to an IGBT having a trench structure, and may be applied to a planar IGBT or an RC-IGBT in which an IGBT and a free wheel diode are integrally formed. Good. In the second embodiment, an example in which the semiconductor element is a planar type DMOS has been described. However, the present invention is not limited to the planar type, and may be applied to a DMOS having a trench structure.

  Furthermore, in the above-described embodiments, the semiconductor elements are IGBTs or DMOSs, but the present invention is not limited to these examples. The present invention can be applied to any semiconductor device including a semiconductor element that needs to process the one surface 11a and the back surface 11b of the semiconductor substrate 11.

  In the embodiment described above, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. Good.

DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate, 12 ... Base layer, 13 ... Emitter layer, 14 ... Collector layer 20 ... Trench, 21 ... Gate insulating film, 22 ... Gate electrode 23 ...・ Gate line 24... Insulating film 30... Emitter electrode 31. Collector electrode 41. Inorganic protective film 42.

Claims (4)

A surface treatment step of forming at least a part of the semiconductor element on one surface side of the semiconductor substrate;
After the surface treatment step, a back surface treatment step of processing the back surface side opposite to the one surface, and a manufacturing method of a semiconductor device comprising:
After the surface treatment step and before the back surface treatment step, an inorganic film forming step for forming an inorganic protective film over the entire surface of the one surface;
After the inorganic film forming step, before the back surface treatment step, after forming the organic protective film over the entire surface of the inorganic protective film, an organic film forming step of patterning the organic protective film;
A method of manufacturing a semiconductor device, comprising: an inorganic film removing step of removing a part of the inorganic protective film using the organic protective film as a mask after the back surface treatment step. As the semiconductor element, an insulated gate bipolar transistor is formed,
As the surface treatment step,
A second conductivity type base layer is formed on a surface layer of the first conductivity type semiconductor substrate, a plurality of first conductivity type emitter layers are formed on the surface layer of the base layer, and one surface side of the semiconductor substrate is formed. And a diffusion layer and a gate forming step for forming a plurality of gate electrodes through the gate insulating film,
Forming an insulating film on one surface of the semiconductor substrate so as to cover the gate electrode, and forming a plurality of contact holes in the insulating film corresponding to each gate electrode;
Forming a gate line so as to be electrically connected to the plurality of gate electrodes through each contact hole; and
An emitter electrode forming step of forming an emitter electrode so as to cover the portion excluding the gate line forming portion in the insulating film, which is electrically connected to the base layer and the emitter layer;
As the back surface treatment step,
A back grinding process for grinding and thinning the semiconductor substrate from the back surface;
A collector electrode forming step of forming a collector layer of a second conductivity type on the back surface side layer of the semiconductor substrate after grinding, and forming a collector electrode electrically connected to the collector layer on the back surface of the semiconductor substrate; Have
In the organic film forming step, the organic protective film is patterned so as to overlap with the entire edge line and the entire gate line except the pad area exposed to the outside of the emitter electrode,
2. The semiconductor device according to claim 1, wherein in the inorganic film removing step, a part of the inorganic protective film is removed using the organic protective film as a mask to expose a pad region of the emitter electrode to the outside. Production method.   3. The semiconductor according to claim 1, wherein the semiconductor substrate is made of silicon, the inorganic protective film is a silicon nitride film or a silicon oxide film, and the organic protective film is made of a polyimide-based resin. Device manufacturing method. A semiconductor device manufactured by the manufacturing method according to claim 2 or 3,
A semiconductor device comprising a trench type insulated gate bipolar transistor in which the gate electrode and the gate insulating film are formed through the base layer from the surface on one surface side of the semiconductor substrate as the semiconductor element.

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