JP2007329279A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device being capable of activating impurities introduced to the second main surface of a semiconductor substrate, preventing the characteristic deterioration of an element while machining the second main surface side, and accurately forming a contact hole on the first main surface side. <P>SOLUTION: The method for manufacturing the semiconductor device has a process for forming an interlayer insulating film 107 on the first main surface of the semiconductor substrate 101, the process for removing the interlayer insulating film 107 while leaving a specified thickness in a contact-hole forming predetermined region, and the process for thinning the semiconductor substrate 101 by removing the specified thickness from the second main surface side of the semiconductor substrate 101. The manufacturing method further has the process for introducing impurities to the surface layer of the second main surface of the thinned semiconductor substrate 101, and the process for thermally treating the semiconductor substrate 101 at a temperature higher than the melting point of a material configuring a metal electrode 108 after introducing impurities. The manufacturing method further has the process for forming the contact hole 109 by removing the left interlayer insulating film 107 after a heat treatment, and the process for forming the metal electrode 108 in the contact hole 109 and on the interlayer insulating film 107. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention provides a semiconductor device in which a contact hole is formed on a first main surface side of a semiconductor substrate, and an impurity layer is formed on a surface layer of a second main surface of the semiconductor substrate after the thickness of the semiconductor substrate is reduced. It is about the method.

  Conventionally, as a method for manufacturing a semiconductor device, a contact hole is formed on a first main surface side of a semiconductor substrate, and an impurity layer is formed on a surface layer of a second main surface of the semiconductor substrate after the thickness of the semiconductor substrate is reduced. For example, Patent Document 1 is disclosed.

Patent Document 1 discloses a method for manufacturing an insulated gate bipolar transistor (IGBT) having a structure having a field stop layer (FS layer). Specifically, first, contact holes are formed in an interlayer insulating film provided on the surface (first main surface) of a semiconductor wafer (semiconductor substrate), and surface electrodes such as emitters are formed. That is, a surface structure is formed. Thereafter, the back surface (second main surface) of the semiconductor substrate is removed by grinding to thin the semiconductor substrate, and ion implantation is performed on the second main surface of the semiconductor substrate after the grinding and removal, and heat treatment is performed, whereby the impurity layer (FS layer). And a collector layer).
JP 2004-103982 A

  However, in the manufacturing method disclosed in Patent Document 1, since the surface electrode is formed before the heat treatment, the heat treatment must be performed at a relatively low temperature (eg, 500 ° C. or less) that is equal to or lower than the melting point of the material constituting the surface electrode. I do not get. Therefore, activation of the ion-implanted impurity may be insufficient.

  Further, as a manufacturing method different from Patent Document 1, for example, a manufacturing method shown in FIGS. 5 and 6 is also conceivable. FIGS. 5A and 5B are cross-sectional views showing a manufacturing method of a semiconductor device different from Patent Document 1, wherein FIG. 5A is a contact hole forming step, FIG. 5B is a grinding removal step, and FIG. 5C is an impurity introduction step. is there. 6A and 6B are cross-sectional views showing the manufacturing method of the semiconductor device subsequent to FIG. 5, in which FIG. 6A is a heat treatment step, FIG. 6B is a front surface electrode formation step, and FIG. 5 and 6, as in the embodiments described later, an FS type IGBT having a trench gate structure is manufactured, and for convenience, the trench, the gate insulating film, the gate electrode, and the emitter region are omitted. . Moreover, about a code | symbol, the same code | symbol shall be provided about the same structure as embodiment mentioned later.

  First, a contact hole 109 is formed in the interlayer insulating film 107 provided on the first main surface of the semiconductor substrate 101 by photolithography (see FIG. 5A). Then, the second main surface of the semiconductor substrate 101 is ground and removed to thin the semiconductor substrate 101 (see FIG. 5B). After grinding and removal, ion implantation (see FIG. 5C) is performed on the second main surface of the semiconductor substrate, and heat treatment is performed to form impurity layers (collector layer 110 and FS layer 112) (see FIG. 6A). ). Then, after forming the impurity layer, a front surface electrode (emitter electrode 108) is formed (see FIG. 6B), and after forming a passivation film (not shown), a back surface electrode (collector electrode 111) is formed (see FIG. 6C). ). According to such a manufacturing method, since the heat treatment is performed before the surface electrode is formed, the heat treatment temperature can be set to a temperature sufficient for activating the ion-implanted impurities. Reference numeral 121 shown in FIG. 5B is a first protective member that protects the surface on the first main surface side of the semiconductor substrate 101 when grinding and removing. Reference numeral 122 shown in FIG. The second protective member protects the surface of the semiconductor substrate 101 on the first main surface side when introducing impurities.

  However, in the manufacturing method shown in FIGS. 5 and 6, the semiconductor substrate 101 is ground and removed after the contact hole 109 is formed and before the surface electrode 108 is formed, so that the first main substrate 101 exposed from the contact hole 109 is removed. There is a possibility that the surface layer on the surface side is contaminated by fine particles, processing liquid, or the like generated by grinding, thereby causing deterioration of characteristics of the elements formed on the semiconductor substrate 101 or a decrease in yield. Even if the first protective member 121 is protected as described above, the first protective member 121 is removed before the surface electrode is formed. is there.

  Note that it is also conceivable to grind and remove the second main surface of the semiconductor substrate 101 before the contact hole 109 is formed in the manufacturing method shown in FIGS. However, in this case, a photolithography process for forming the contact hole 109 must be performed on the semiconductor substrate 101 having a small thickness, and the contact hole 109 is accurately formed by warping of the semiconductor substrate 101. It becomes difficult.

  In view of the above problems, the present invention can activate impurities introduced into the second main surface of the semiconductor substrate, prevent deterioration of element characteristics while processing the second main surface side of the semiconductor substrate, and An object of the present invention is to provide a method of manufacturing a semiconductor device capable of accurately forming a contact hole on one main surface side.

  In order to achieve the above object, the invention described in claim 1 includes a step of forming an interlayer insulating film on the first main surface of the semiconductor substrate and a predetermined thickness of the interlayer insulating film in the region where the contact hole is to be formed. A step of removing the remaining part of the semiconductor substrate, a step of removing the semiconductor substrate by a predetermined thickness from the second main surface side, which is the back surface of the first main surface, and a step of thinning the semiconductor substrate; A step of introducing impurities into the surface layer of the main surface; a step of heat-treating the semiconductor substrate after the introduction of impurities; and a step of removing a remaining interlayer insulating film of a predetermined thickness after the heat treatment to form a contact hole; And a step of forming a metal electrode in the contact hole and on the interlayer insulating film, and in the heat treatment step, the semiconductor substrate is heated to a temperature equal to or higher than the melting point of the material constituting the metal electrode. Heat treatment in And wherein the Rukoto.

  Thus, according to the present invention, the metal electrode is formed on the first main surface side of the semiconductor substrate after performing the heat treatment after the introduction of the impurities. Therefore, in the heat treatment step, the semiconductor substrate can be heat treated at a temperature equal to or higher than the melting point of the material constituting the metal electrode. That is, the impurities introduced into the second main surface of the semiconductor substrate can be activated. Further, before the heat treatment, the interlayer insulating film is removed partway from the surface (that is, a part of the contact hole is formed), so that the open end (shoulder) of the contact hole is gently curved by the subsequent heat treatment. It can be a shape.

  Further, the second main surface side of the semiconductor substrate is removed to a predetermined thickness with a part of the interlayer insulating film remaining. Therefore, it is possible to prevent the surface layer of the semiconductor substrate from being contaminated by the fine particles or the processing liquid generated by the removal. That is, it is possible to prevent deterioration of the characteristics of the element while processing the second main surface side of the semiconductor substrate.

  Furthermore, before removing the second main surface side of the semiconductor substrate to a predetermined thickness, the interlayer insulating film is removed partway from the surface (that is, a part of the contact hole is formed). That is, a photolithography process for forming contact holes is performed on a thick semiconductor substrate. Therefore, the contact hole can be formed with high accuracy on the first main surface side of the semiconductor substrate.

  According to a second aspect of the present invention, in the step of forming the contact hole, the entire surface of the interlayer insulating film including the interlayer insulating film having a predetermined thickness exposed in the thickness direction of the semiconductor substrate may be etched. For example, the entire surface may be etched by wet etching or isotropic dry etching, and the etching may be terminated when a contact hole is formed. According to this, the manufacturing method can be simplified.

  Next, as claimed in claim 3, a step of forming a protective film on the first main surface of the semiconductor substrate, a step of forming an interlayer insulating film on the protective film, and a contact hole formation scheduled region The step of removing the interlayer insulating film leaving the protective film, the step of removing the semiconductor substrate by a predetermined thickness from the second main surface side which is the back surface of the first main surface, and the step of thinning the semiconductor substrate, A step of introducing impurities into the surface layer of the second main surface with respect to the semiconductor substrate; a step of heat-treating the semiconductor substrate after the introduction of impurities; and a step of removing the protective film after the heat treatment to form a contact hole; A step of exposing from the interlayer insulating film and a step of forming a metal electrode in the contact hole and on the interlayer insulating film, and in the step of heat treatment, the semiconductor substrate is heated at a temperature equal to or higher than the melting point of the material constituting the metal electrode. Heat treatment And butterflies.

  Thus, according to the present invention, the metal electrode is formed on the first main surface side of the semiconductor substrate after performing the heat treatment after the introduction of the impurities. Therefore, in the heat treatment step, the semiconductor substrate can be heat treated at a temperature equal to or higher than the melting point of the material constituting the metal electrode. That is, the impurities introduced into the second main surface of the semiconductor substrate can be activated. Further, before the heat treatment, the interlayer insulating film is removed while leaving the protective film (that is, a part of the contact hole is formed), so that the opening end (shoulder) of the contact hole is loosened by the subsequent heat treatment. It can be a curved shape.

  Further, the second main surface side of the semiconductor substrate is removed to a predetermined thickness with the protective film remaining. Therefore, it is possible to prevent the surface layer of the semiconductor substrate from being contaminated by the fine particles or the processing liquid generated by the removal. That is, it is possible to prevent deterioration of the characteristics of the element while processing the second main surface side of the semiconductor substrate.

  Further, before removing the second main surface side of the semiconductor substrate to a predetermined thickness, the interlayer insulating film is removed (that is, a part of the contact hole is formed). That is, a photolithography process for forming contact holes is performed on a thick semiconductor substrate. Therefore, the contact hole can be formed with high accuracy on the first main surface side of the semiconductor substrate.

  According to a fourth aspect of the present invention, in the step of forming the contact hole, the entire surface of the protective part and the interlayer insulating film exposed in the thickness direction of the semiconductor substrate may be etched. Since the operational effects of the present invention are the same as the operational effects of the invention described in claim 2, the description thereof is omitted.

  When the temperature is lower than 800 ° C., the effect of making the shoulder shape of the contact hole into a curved shape is small, and the step coverage of the metal electrode is deteriorated. Further, if the temperature is equal to or higher than the diffusion temperature of the impurity diffusion layer formed on the surface layer of the first main surface of the semiconductor substrate, desired element characteristics cannot be ensured. Therefore, as described in claim 5, in the heat treatment step, the heat treatment temperature is preferably in a range of 800 ° C. or more and less than the diffusion temperature of the impurity diffusion layer formed on the surface layer of the first main surface of the semiconductor substrate. .

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a cross-sectional view illustrating a schematic configuration of a main part of a semiconductor device to which the manufacturing method according to the first embodiment is applied.

  As shown in FIG. 1, a semiconductor device 100 according to the present embodiment includes a field stop type IGBT (Insulated Gate Bipolar Transistor) having a trench gate structure as an element formed on a semiconductor substrate 101.

The semiconductor substrate 101 is an N-conductivity (N−) FZ wafer serving as an IGBT drift layer, and has a concentration of about 1 × 10 ¹⁴ cm ⁻³ , for example. On the first main surface side surface layer of the semiconductor substrate 101, a P conductivity type (P) base region 102 which is a first semiconductor region is selectively formed in the IGBT formation region.

In the base region 102, a trench 103 that penetrates the base region 102 from the first main surface of the semiconductor substrate 101 and whose bottom surface reaches the semiconductor substrate 101 is selectively formed. In the present embodiment, a trench 103 having a diameter of about 1 μm and a depth of about 5 μm is formed. Then, via a gate insulating film 104 (for example, an oxide film) formed on the bottom and side surfaces of the trench, the trench 103 is filled with, for example, polysilicon having a concentration of about 1 × 10 ²⁰ cm ⁻³ , and the gate electrode 105 is formed. It is configured.

Further, in the base region 102, an N conductivity type (N +) emitter region 106, which is a second semiconductor region, is selectively formed on the first main surface side surface layer adjacent to the side surface portion of the trench 103 (gate electrode 105). Is formed. In the present embodiment, the emitter region 106 has a thickness of about 0.5 μm and a concentration of about 1 × 10 ¹⁹ cm ⁻³ . An interlayer insulating film 107 is formed on the first main surface of the semiconductor substrate 101 including the gate electrode 105. On this interlayer insulating film 107, an emitter electrode 108 made of, for example, an aluminum-based material is formed. The emitter electrode 108 is connected to an emitter region via a contact hole 109 formed in the interlayer insulating film 107. 106 is electrically connected. The interlayer insulating film 107 is an insulating film disposed between the first main surface of the semiconductor substrate 101 (the surfaces of the base region 102 and the emitter region 106) and the emitter electrode 108. In the present embodiment, At least a BPSG film is included. The emitter electrode 108 corresponds to the metal electrode recited in the claims.

A P conductivity type (P +) collector layer 110 is selectively formed on the surface of the semiconductor substrate 101 on the second main surface side. In the present embodiment, the collector layer 110 has a thickness of about 0.5 μm and a concentration of about 1 × 10 ¹⁸ cm ⁻³ . The collector layer 110 is electrically connected to a collector electrode 111 made of, for example, an aluminum material.

  In the present embodiment, as shown in FIG. 1, an N conductivity type (N) field stop layer 112 (hereinafter referred to as an FS layer 112) between a semiconductor substrate 101 as a drift layer and a collector layer 110. Is formed. When the IGBT having the FS layer 112 that stops the depletion layer is employed as the IGBT having the trench gate structure as described above, the semiconductor substrate 101 (semiconductor device 100) is compared with other trench structures (punch-through type and non-punch-through type). ) Can be made thinner. Accordingly, the SW loss can be reduced because there are few excess carriers and the remaining width of the neutral region in the state where the depletion layer is fully extended is small. Note that the thickness from the surface of the base region 102 (first main surface of the semiconductor substrate 101) shown in FIG. 1 to the surface of the collector layer 110 (second main surface of the semiconductor substrate 101) is approximately 130 μm.

  Next, the operation of the IGBT in the semiconductor device 100 having the above configuration will be described. When a predetermined collector voltage is applied between the emitter electrode 108 and the collector electrode 111 and a predetermined gate voltage is applied between the emitter electrode 108 and the gate electrode 105 (that is, the gate is turned on), the emitter region 106 of the base region 102 and the semiconductor A channel is formed by inverting the portion between the substrate 101 and the substrate 101 to N-type. Through this channel, electrons are injected from the emitter electrode 108 into the semiconductor substrate 101. Then, the injected electrons cause the collector layer 110 and the semiconductor substrate 101 to be forward-biased, whereby holes are injected from the collector layer 110, the resistance of the semiconductor substrate 101 is greatly reduced, and the current capacity of the IGBT is increased. Further, when the gate voltage applied between the emitter electrode 108 and the gate electrode 105 is 0 V or reverse bias (that is, the gate is turned off), the channel region inverted to the N type is a P type region. Then, the injection of electrons from the emitter electrode 108 stops. By stopping the injection, the injection of holes from the collector layer 110 is also stopped. Thereafter, carriers (electrons and holes) accumulated in the semiconductor substrate 101 are discharged from the collector electrode 111 and the emitter electrode 108, respectively, or recombine with each other and disappear.

  Next, a method for manufacturing the semiconductor device 100 having the above configuration will be described with reference to FIGS. 2A and 2B are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment, wherein FIG. 2A is an interlayer insulating film forming step, FIG. 2B is a first removal step, and FIG. 2C is a grinding removal step. , (D) is an impurity introduction step. FIG. 3 is a cross-sectional view showing a method for manufacturing a semiconductor device following FIG. 2, wherein (a) is a heat treatment step, (b) is a second removal step, (c) is a surface electrode formation step, and (d). Is a back electrode forming step. In FIGS. 2A to 2D and FIGS. 3A to 3D, the trench 103, the gate insulating film 104, the gate electrode 105, and the emitter region 106 are omitted for convenience.

  First, the base region 102 is formed on the surface of the first main surface side of the semiconductor substrate 101 having a thickness of 400 to 800 μm, and surface structure portions of elements such as the gate insulating film 104, the gate electrode 105, and the emitter region 106 are formed.

  Next, as shown in FIG. 2A, an interlayer insulating film 107 made of BPSG having a thickness of about 800 nm is formed on the first main surface of the semiconductor substrate 101, that is, on the base region 102, the emitter region 106, and the gate electrode 105. Form. Note that a CVD method can be employed as a forming method. This step corresponds to the step of forming the interlayer insulating film 107 shown in the claims.

  After the formation of the interlayer insulating film 107, as shown in FIG. 2B, a photoresist 120 is formed on the interlayer insulating film 107, and a first removal process by photolithography is performed. Specifically, as shown in FIG. 2B, portions of the photoresist 120 located on the base region 102 and the emitter region 106 are opened. Then, for example, reactive ion etching or plasma etching is performed in the contact hole formation scheduled region on the base region 102 and the emitter region 106 in the interlayer insulating film 107 using the photoresist 120 as a mask. In the first removal step, the interlayer insulating film 107 is partially removed in the thickness direction of the semiconductor substrate 101, and the interlayer insulating film 107 having a predetermined thickness (for example, about 200 nm) is left in the contact hole formation scheduled region. State. That is, an incomplete contact hole 109a is formed. This step corresponds to the step of removing the interlayer insulating film 107 shown in the claims to the middle.

  As described above, in this embodiment, the interlayer insulating film 107 is removed from the surface partway (forms an incomplete contact hole 109a) before the grinding removal step, so that the semiconductor substrate 101 is thick. Thus, the position of the contact hole 109 can be determined. Therefore, the contact hole 109 can be accurately formed on the first main surface side of the semiconductor substrate 101.

  After the first removal step, as shown in FIG. 2C, the semiconductor substrate 101 is removed by a predetermined thickness from the second main surface side, which is the back surface of the first main surface, to reduce the thickness of the semiconductor substrate 101. A removal step is performed. Specifically, as shown in FIG. 2C, the semiconductor substrate 101 is mounted with the first protective member 121 for preventing scratches attached to the surface of the semiconductor substrate 101 on the first main surface side. A predetermined thickness is removed by grinding from the second main surface side, so that the thickness of the semiconductor substrate 101 is 200 μm or less. This step corresponds to the step of thinning the semiconductor substrate 101 shown in the claims. Note that the first protective member 121 is peeled off after grinding and removal. Further, grinding removal can be performed without arranging the first protective member 121.

  In the present embodiment, since the first main surface of the semiconductor substrate 101 is protected by the remaining interlayer insulating film 107, the first main surface of the semiconductor substrate 101 is caused by fine particles, processing liquid, or the like generated by grinding and removing. It is possible to prevent the side surface layer from being contaminated. That is, it is possible to prevent deterioration of element characteristics while processing the second main surface side of the semiconductor substrate 101.

  After the grinding and removing step, as shown in FIG. 2D, an impurity introducing step for introducing impurities into the surface layer of the second main surface is performed on the thinned semiconductor substrate 101. Specifically, as shown in FIG. 2D, a second protective member 122 that protects the first main surface of the semiconductor substrate 101 due to impurities is disposed on the surface on the first main surface side of the semiconductor substrate 101. In this state, N conductivity type impurity (for example, phosphorus) is ion-implanted into the second main surface of the semiconductor substrate 101, and further P conductivity type impurity (for example, boron) is ion-implanted. As a result, an ion implantation layer 112a made of N conductivity type impurities and an ion implantation layer 110a made of P conductivity type impurities are formed in the surface layer on the second main surface side of the semiconductor substrate 101. The introduction of impurities is not limited to ion implantation. This step corresponds to the step of introducing impurities shown in the claims. Note that the second protective member 122 is removed after the ion implantation. Further, the grinding removal can be performed without arranging the second protection member 122.

  After the impurity introduction step, a heat treatment step for heat treating the semiconductor substrate 101 is performed as shown in FIG. There are two purposes of this heat treatment process. The first purpose is to activate the implanted ions by annealing the semiconductor substrate 101 and to recover the damaged region. The open end (shoulder) of the completed contact hole 109a has a gently curved shape (increasing the radius of curvature). The first purpose is the main purpose. Specifically, the semiconductor substrate 101 is heat-treated at a temperature equal to or higher than the melting point of the material constituting the emitter electrode 108. Thus, when heat treatment is performed at a temperature equal to or higher than the melting point of the material constituting the emitter electrode 108, the ion-implanted impurity is activated and has a desired diffusion depth and peak concentration, as shown in FIG. A collector layer 110 and an FS layer 112 are formed. Further, the open end (shoulder) of the incomplete contact hole 109a has a gently curved shape. Further, in the present embodiment, since the first main surface of the semiconductor substrate 101 is protected by the remaining interlayer insulating film 107, the intrusion of impurities can be prevented.

  If the heat treatment temperature is less than 800 ° C., the fluidization effect of the interlayer insulating film 107 (that is, the effect of making the shoulder portion of the unfinished contact hole 109a in a curved shape) is small, and the step coverage of the emitter electrode 108 is poor. Become. Further, when the temperature is equal to or higher than the diffusion temperature of the impurity diffusion layer (the emitter region 106 in the present embodiment) formed in the surface layer of the first main surface of the semiconductor substrate 101, desired element characteristics cannot be ensured. Therefore, in the heat treatment step, it is preferable that the heat treatment temperature is 800 ° C. or more and less than the diffusion temperature of the impurity diffusion layer (emitter region 106) formed in the surface layer of the first main surface of the semiconductor substrate 101. In this embodiment, the heat treatment temperature is 900 ° C.

  After the heat treatment process, as shown in FIG. 3B, the remaining interlayer insulating film 107 having a predetermined thickness is removed, and the incomplete contact hole 109a becomes a complete contact hole 109, and the semiconductor substrate 101 is interlayer-insulated. A second removal step of exposing from the film 107 is performed. In this embodiment, the entire surface of the interlayer insulating film 107 including the interlayer insulating film 107 having a predetermined thickness exposed in the thickness direction of the semiconductor substrate 101 is wet-etched, for example. As a result, the thickness of the interlayer insulating film 107 is about 600 nm. Note that the complete contact hole 109 means that the first main surface of the semiconductor substrate 101 is exposed through the contact hole 109.

  As described above, in this embodiment, since the incomplete contact hole 109a is formed in the first removal step, the interlayer insulating film 107 is entirely etched to form the contact hole 109 in the second removal step. That is, the contact hole 109 is formed by the first removal step and the second removal step. According to this, since photolithography is unnecessary, the manufacturing method can be simplified. In addition to wet etching, isotropic dry etching can also be employed. Although photolithography is required, the contact hole 109 can be formed by removing the remaining interlayer insulating film 107 having a predetermined thickness from the interlayer insulating film 107.

  After the second removing step, as shown in FIG. 3C, an aluminum material is deposited in the contact hole 109 and on the interlayer insulating film 107 by, eg, sputtering, and patterned to form the emitter electrode 108. An electrode forming step is performed. Then, after the passivation film forming step (not shown), as shown in FIG. 3D, a back electrode forming step for forming the collector electrode 111 on the second main surface (on the collector layer 110) of the semiconductor substrate 101 is performed. . Thus, the semiconductor device 100 shown in FIG. 1 can be formed.

  As described above, according to the method for manufacturing the semiconductor device 100 according to the present embodiment, the emitter electrode 108 (surface electrode) is formed on the first main surface side of the semiconductor substrate 101 after performing the heat treatment after introducing the impurities. Therefore, in the heat treatment step, the semiconductor substrate 101 can be heat treated at a temperature equal to or higher than the melting point of the material constituting the emitter electrode 108. That is, the impurities introduced into the second main surface of the semiconductor substrate 101 can be activated. Further, before the heat treatment, the interlayer insulating film 107 is removed partway from the surface (that is, an incomplete contact hole 109a is formed), so that the opening end portion (shoulder) of the contact hole 109a (109) is formed by the subsequent heat treatment. Part) can have a gentle curve shape.

  Further, since the second main surface side of the semiconductor substrate 101 is ground and removed with a part of the interlayer insulating film 107 left, the surface layer of the semiconductor substrate 101 is contaminated by fine particles, processing liquid, etc. generated by the removal. Can be prevented. That is, it is possible to prevent deterioration of element characteristics while processing the second main surface side of the semiconductor substrate 101.

  Further, before grinding and removing the second main surface side of the semiconductor substrate 101, the interlayer insulating film 107 is removed partway from the surface while the semiconductor substrate 101 is thick, and the position of the contact hole 109 (109a) Therefore, the contact hole 109 can be accurately formed on the first main surface side of the semiconductor substrate 101.

(Second Embodiment)
Next, a second embodiment of the present invention will be described based on FIG. 4A and 4B are cross-sectional views showing a part of the method for manufacturing the semiconductor device 100 according to the second embodiment of the present invention, where FIG. This is the first removal step.

  Since the manufacturing method of the semiconductor device 100 according to the second embodiment is often in common with the manufacturing method of the semiconductor device 100 according to the first embodiment, the detailed description of the common parts will be omitted below, and different parts will be emphasized. Explained.

  In the first embodiment, in the contact hole formation scheduled region, the interlayer insulating film 107 is removed partway and a predetermined thickness is left, so that the first main surface of the semiconductor substrate 101 is protected during grinding removal and heat treatment. An example to do. In contrast, the present embodiment is characterized in that a protective film is provided between the semiconductor substrate 101 and the interlayer insulating film 107, and the interlayer insulating film 107 is removed while leaving the protective film. The other points are basically the same as the method shown in the first embodiment.

  Specifically, as shown in FIG. 4A, first, a protective film 130 having a thickness of about 200 nm is formed on the first main surface of the semiconductor substrate 101, that is, on the base region 102, the emitter region 106, and the gate electrode 105. Form. This step corresponds to the formation step of the protective film 130 shown in the claims. As the protective film 130, for example, a silicon nitride film can be employed. This protective film 130 not only performs the same function as the remaining predetermined thickness of the interlayer insulating film 107 shown in the first embodiment, but also serves as an etching stopper in the first removal step according to the present embodiment. Fulfills the function. Then, an interlayer insulating film 107 made of BPSG having a thickness of about 600 nm is formed on the protective film 130.

  After the interlayer insulating film 107 is formed, as shown in FIG. 4B, a photoresist 120 is formed on the interlayer insulating film 107, and a first removal process by photolithography is performed. Specifically, as shown in FIG. 4B, portions of the photoresist 120 located on the base region 102 and the emitter region 106 are opened. Then, for example, reactive ion etching or plasma etching is performed in the contact hole formation scheduled region on the base region 102 and the emitter region 106 in the interlayer insulating film 107 using the photoresist 120 as a mask. In this first removal step, the interlayer insulating film 107 is removed in the thickness direction of the semiconductor substrate 101 using the protective film 130 as an etching stopper. That is, the incomplete contact hole 109a in which the protective film 130 is left is formed in the contact hole formation scheduled region.

  After the first removal step, as in the first embodiment, the semiconductor device 100 is formed through a grinding removal step, an impurity introduction step, a heat treatment step, a second removal step, and a surface electrode formation step. In this embodiment, since the protective film 130 remains in the first removal step, the protective film 130 is removed in the second removal step, whereby the incomplete contact hole 109a is replaced with the complete contact hole 109. And Note that the complete contact hole 109 means that the first main surface of the semiconductor substrate 101 is exposed through the contact hole 109.

  As described above, also in the method for manufacturing the semiconductor device 100 according to the present embodiment, the emitter electrode 108 (surface electrode) is formed on the first main surface side of the semiconductor substrate 101 after performing the heat treatment after introducing the impurities. Therefore, in the heat treatment step, the semiconductor substrate 101 can be heat treated at a temperature equal to or higher than the melting point of the material constituting the emitter electrode 108. That is, the impurities introduced into the second main surface of the semiconductor substrate 101 can be activated. Further, since the incomplete contact hole 109a with the protective film 130 left is formed before the heat treatment, the opening end portion (shoulder portion) of the contact hole 109a (109) is made into a gently curved shape by the subsequent heat treatment. be able to.

  Further, since the second main surface side of the semiconductor substrate 101 is ground and removed with the protective film 130 left, it is possible to prevent the surface layer of the semiconductor substrate 101 from being contaminated by fine particles, processing liquid, or the like generated by the removal. Can do. That is, it is possible to prevent deterioration of element characteristics while processing the second main surface side of the semiconductor substrate 101.

  Further, before grinding and removing the second main surface side of the semiconductor substrate 101, the position of the contact hole 109 (109a) is determined by removing the interlayer insulating film 107 with the semiconductor substrate 101 thick. The contact hole 109 can be accurately formed on the first main surface side of the semiconductor substrate 101.

  Furthermore, in this embodiment, the interlayer insulating film 107 is removed using the protective film 130 as an etching stopper, so that the protective film 130 having a predetermined thickness can be reliably left after the first removal step.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  In this embodiment, the example which applies the manufacturing method of this invention to FS type IGBT of the trench gate structure included in the semiconductor device 100 was shown. However, the scope of application of the manufacturing method of the present invention is not limited to the above elements. On the first main surface side of the semiconductor substrate, an interlayer insulating film having a contact hole formed on the first main surface is provided, and the metal electrode formed on the interlayer insulating film is electrically connected to the semiconductor substrate through the contact hole. Has been. The semiconductor substrate can be applied as long as the semiconductor substrate is thinly processed by grinding and removing from the second main surface side and impurities are introduced into the processed surface and heat-treated. In other words, any element can be applied as long as it has electrodes on both surfaces (first main surface and second main surface) of the semiconductor substrate 101 and a current flows between the electrodes. For example, the present invention can be applied to IGBTs other than those described above, power MOS transistors, diodes, thyristors, and the like.

It is sectional drawing which shows schematic structure of the principal part of the semiconductor device to which the manufacturing method concerning 1st Embodiment is applied. FIG. 6 is a cross-sectional view showing a method of manufacturing the semiconductor device according to the first embodiment, wherein (a) is an interlayer insulating film forming step, (b) is a first removal step, (c) is a grinding removal step, and (d). Is an impurity introduction step. FIGS. 3A and 3B are cross-sectional views illustrating a method for manufacturing a semiconductor device following FIG. 2, wherein FIG. 3A is a heat treatment step, FIG. 2B is a second removal step, FIG. It is a process. It is sectional drawing according to process which shows a part of manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention, (a) is the process of forming a protective film and an interlayer insulation film, (b) is a 1st removal process. is there. It is sectional drawing according to process which shows the manufacturing method of the conventional semiconductor device, (a) is a contact hole formation process, (b) is a grinding removal process, (c) is an impurity introduction process. FIGS. 6A and 6B are cross-sectional views illustrating a semiconductor device manufacturing method following FIG. 5, wherein FIG. 5A is a heat treatment step, FIG. 5B is a front surface electrode formation step, and FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Semiconductor device 101 ... Semiconductor substrate 102 ... Base region 106 ... Emitter region 107 ... Interlayer insulating film 108 ... Emitter electrode (surface electrode)
109 ... contact hole 109a ... unfinished contact hole 110 ... collector layer 111 ... collector electrode (back electrode)
112 ... Field stop layer (FS layer)

Claims (5)

Forming an interlayer insulating film on the first main surface of the semiconductor substrate;
In the contact hole formation scheduled region, the step of removing the interlayer insulating film halfway leaving a predetermined thickness; and
Removing the semiconductor substrate by a predetermined thickness from the second main surface side, which is the back surface of the first main surface, and thinning the semiconductor substrate;
Introducing impurities into a surface layer of the second main surface with respect to the thinned semiconductor substrate;
A step of heat-treating the semiconductor substrate after the introduction of the impurities;
Removing the interlayer insulating film having a predetermined thickness after the heat treatment to form a contact hole, and exposing the semiconductor substrate from the interlayer insulating film;
Forming a metal electrode in the contact hole and on the interlayer insulating film,
In the heat treatment step, the semiconductor substrate is heat-treated at a temperature equal to or higher than a melting point of a material constituting the metal electrode.   2. The semiconductor according to claim 1, wherein in the step of forming the contact hole, the entire surface of the interlayer insulating film including the interlayer insulating film having a predetermined thickness exposed in the thickness direction of the semiconductor substrate is etched. Device manufacturing method. Forming a protective film on the first main surface of the semiconductor substrate;
Forming an interlayer insulating film on the protective film;
A step of removing the interlayer insulating film leaving the protective film in a contact hole formation planned region;
Removing the semiconductor substrate by a predetermined thickness from the second main surface side, which is the back surface of the first main surface, and thinning the semiconductor substrate;
Introducing impurities into a surface layer of the second main surface with respect to the thinned semiconductor substrate;
A step of heat-treating the semiconductor substrate after the introduction of the impurities;
After the heat treatment, removing the protective film to form a contact hole, exposing the semiconductor substrate from the interlayer insulating film,
Forming a metal electrode in the contact hole and on the interlayer insulating film,
In the heat treatment step, the semiconductor substrate is heat-treated at a temperature equal to or higher than a melting point of a material constituting the metal electrode.   4. The method of manufacturing a semiconductor device according to claim 3, wherein, in the step of forming the contact hole, the entire surface of the protection portion and the interlayer insulating film exposed in the thickness direction of the semiconductor substrate is etched.   5. The heat treatment temperature in the heat treatment step is in a range of 800 ° C. or more and less than a diffusion temperature of an impurity diffusion layer formed on a surface layer of the first main surface of the semiconductor substrate. A manufacturing method of a semiconductor device given in any 1 paragraph.

Images