JP2008270681A - Silicon carbide semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly integrated silicon carbide semiconductor device that is not only manufactured without using complex technology but also durable against the use for a long period of time. <P>SOLUTION: The semiconductor device includes an active region and peripheral voltage withstanding structure 20b surrounding the active region. A gate electrode is formed in a trench of the active region through a gate insulating film, and a p<SP>+</SP>region 6 is formed on a bottom portion thereof. On the other hand, not only a trench isolation film 12 is loaded in the trench of the peripheral voltage withstanding structure 20b but also p<SP>+</SP>region 6 is formed on a bottom of the trench closest to the active region. Of the trenches of the voltage withstanding structure, the p<SP>+</SP>region 6 is preferably formed on the bottom of the trench closest to the active region and on the bottom of the trench second closest thereto. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a silicon carbide semiconductor device using silicon carbide (SiC) as a semiconductor material.

  Conventionally, power semiconductor devices that control a high breakdown voltage and a large current have been developed. There are several types of power semiconductor devices, and each type of power semiconductor device is properly used according to the application. For example, bipolar transistors and IGBTs (Insulated Gate Bipolar Transistors) can have a large current density but cannot be switched at high speed. For this reason, the use limit frequency of the bipolar transistor is several kHz, and the use limit frequency of the IGBT is about 20 kHz.

  On the other hand, although the power MOSFET cannot take a large current density, it can perform high-speed switching and can be used even at a high frequency of about several MHz. Two types of power MOSFET structures are known, a planar gate type and a trench gate type.

  In addition, in order to further improve the performance of the power semiconductor device, the semiconductor material is being improved. Conventionally, a silicon (silicon) single crystal has been used as a semiconductor material for power semiconductor devices, but in recent years, silicon carbide (SiC) excellent in low on-voltage, high-speed and high-temperature characteristics has attracted attention. (For example, see the following non-patent document 1.) Silicon carbide is a chemically very stable material, has a wide band gap of 3 eV, and can be used very stably even at high temperatures. Further, the maximum value of the electric field strength allowable for silicon carbide is one digit or more larger than the maximum value of the electric field strength allowable for silicon. For this reason, a semiconductor device using silicon carbide can withstand a large current.

  However, it is very difficult to selectively form a p-type region with respect to an n-type silicon carbide substrate. Although it has been reported that a p-type region can be formed by ion implantation at a high temperature, it has been found that a sufficient p-type region cannot be obtained because the resistance is actually too high (see, for example, Patent Document 1 below). ).

Therefore, a bevel structure shown in FIG. 12 is widely adopted in a semiconductor device using silicon carbide instead of the guard ring. FIG. 12 is an explanatory diagram illustrating a structure of a semiconductor device having a bevel structure. The semiconductor device 100 of FIG. 12 is formed by an n ⁺ drain substrate 101, an n ⁻ base layer 102, a p base layer 103, a p ⁺ contact region 104, an insulating layer 105, a source electrode 106, and a drain electrode 107. The inclined surface formed in the p base layer 103 is formed by selectively removing the p base layer 103 by performing dry etching after epitaxially growing the p base layer 103 on the n ⁻ base layer 102. .

In addition, a plurality of trenches are formed so as to surround the periphery of the main junction of the semiconductor device (that is, in the peripheral breakdown voltage structure), and p ⁺ layers or Schottky contacts are provided between the bottoms of the trenches and the trenches, respectively. By forming an n ⁻ layer between trenches so that a depletion layer spreads between the p ⁺ layer at the bottom and the p ⁺ layer between the trenches, the termination part is configured to reduce the area occupied by the termination part and achieve high breakdown voltage A known semiconductor device is known (for example, see Patent Document 2 below).

JP-A-6-314791 ([Problems to be Solved by the Invention]) Japanese Patent Laid-Open No. 11-087698 Krishna Shenai and 2 other authors, Optim Semiconductors for High-Power Electronics, Itripe Transactions on Electronic E Devices), 1989, Vol 36, p1811.

  However, when manufacturing a semiconductor device having the above-described bevel structure, complicated techniques such as a technique for controlling the taper angle of the inclined surface that affects the withstand voltage and a technique for preventing damage to the surface of the semiconductor device due to dry etching are used. There is a problem that it is necessary. In addition, a semiconductor device having a bevel structure has a problem in that it lacks reliability for long-term use.

Further, as in Patent Document 2 described above, if the p ⁺ layer is provided at the bottom of all the trenches in the peripheral breakdown voltage structure, there is a problem that the peripheral breakdown voltage structure becomes large. When the ratio of the peripheral breakdown voltage structure portion in the semiconductor device increases, the degree of integration of the semiconductor device decreases. For this reason, there is a problem that it is necessary to increase the integration degree of the semiconductor device by reducing the area occupied by the peripheral breakdown voltage structure in the semiconductor device, widening the active region.

  In order to eliminate the above-described problems caused by the conventional technology, the present invention can reduce the proportion of the peripheral breakdown voltage structure portion in the entire semiconductor device to increase the degree of integration, and can be manufactured without using complicated technology. A further object is to provide a silicon carbide semiconductor device that can withstand long-term use.

  In order to solve the above-described problems and achieve the object, a silicon carbide device according to the invention of claim 1 is a silicon carbide semiconductor device having an active region and a breakdown voltage structure portion surrounding the periphery of the active region. A first conductivity type semiconductor substrate having a high impurity concentration formed of silicon carbide, and a first impurity concentration lower than that of the first conductivity type semiconductor substrate formed on the first main surface of the first conductivity type semiconductor substrate. A conductive semiconductor layer; a second conductive semiconductor layer formed on a surface of the first conductive semiconductor layer; and a depth so as to penetrate the second conductive semiconductor layer and reach the first conductive semiconductor layer. A plurality of trenches formed in a direction, a first conductivity type source region selectively formed on a surface of the second conductivity type semiconductor layer of the active region, the first conductivity type source region, and the second conductivity First main electrically connected to the semiconductor layer A pole, a second main electrode formed on the second main surface of the first conductivity type semiconductor substrate, and a surface electrode covering the semiconductor region between the trenches of the breakdown voltage structure, A control electrode is formed in the trench through a gate insulating film. The trench of the breakdown voltage structure is filled with an insulating material, and a second conductivity type is formed at the bottom of the trench closest to the active region. A region is formed.

  A silicon carbide semiconductor device according to a second aspect of the present invention is a silicon carbide semiconductor device having an active region and a breakdown voltage structure portion surrounding the periphery of the active region, and having an impurity concentration formed of silicon carbide. A high second conductivity type semiconductor substrate; a first first conductivity type semiconductor layer formed on a first main surface of the second conductivity type semiconductor substrate; and a surface of the first first conductivity type semiconductor layer. A second first conductivity type semiconductor layer having an impurity concentration lower than that of the first conductivity type semiconductor substrate, a second conductivity type semiconductor layer formed on the surface of the second first conductivity type semiconductor layer, A plurality of trenches formed in a depth direction so as to penetrate the second conductive type semiconductor layer and reach the second first conductive type semiconductor layer; and a surface of the second conductive type semiconductor layer in the active region. A selectively formed first conductivity type source region and the first conductivity A first main electrode electrically connected to the source region and the second conductivity type semiconductor layer; a second main electrode formed on a second main surface of the first conductivity type semiconductor substrate; and the breakdown voltage structure portion A surface electrode covering the semiconductor region between the trenches, a control electrode is formed in the trench in the active region through a gate insulating film, and an insulating material is formed in the trench in the breakdown voltage structure portion A second conductivity type region is formed at the bottom of the trench closest to the active region while being filled.

  According to a third aspect of the present invention, there is provided the silicon carbide semiconductor device according to the first or second aspect of the invention, wherein, among the trenches of the breakdown voltage structure portion, the bottom portion of the trench closest to the active region and the second active portion are provided. The second conductivity type region is formed at the bottom of the trench close to the region.

  According to the first to third aspects of the invention, the bottom of the trench closest to the active region, or the bottom of the trench closest to the active region and the second closest to the active region among the trenches of the breakdown voltage structure portion. A second conductivity type region is formed at the bottom. By this second conductive region, an electric field generated around the active region can be relaxed. In addition, since the breakdown voltage is borne by the insulating film of the trench in which the second conductive region is not formed among the trenches in the breakdown voltage structure portion, compared with the case where the second conductive region is formed in all of the trenches in the breakdown voltage structure portion. Thus, the distance between the pressure-resistant structures can be shortened.

  According to the silicon carbide semiconductor device of the present invention, it is possible to increase the degree of integration by reducing the ratio of the peripheral breakdown voltage structure portion to the entire semiconductor device, and to manufacture without using a complicated technology, and for a longer period of use. It is possible to obtain a silicon carbide semiconductor device that can withstand the above.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

(Embodiment 1)
FIG. 1 is a cross-sectional view illustrating the configuration of the active region of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing the configuration of the peripheral breakdown voltage structure portion of the semiconductor device according to the first embodiment. In the first embodiment, a case where the present invention is applied to a trench MOSFET will be described. As shown in FIG. 1, an n ⁻ base layer 2 and a p base layer 3 are provided in this order on the first main surface side of an n ⁺ semiconductor substrate 1 in the active region 20a of the semiconductor device. An n ⁺ source region 4 and a p ⁺ contact region 5 are selectively provided on the surface of the p base layer 3.

The active region 20 a is provided with a trench that penetrates the n ⁺ source region 4 and the p base layer 3 and reaches the n ⁻ base layer 2. A p ⁺ region 6 is provided at the bottom of the trench of the active region 20a. The trench is filled with a gate electrode 8 via a gate insulating film 7 and an insulating film 9 is provided on the upper surface thereof. A source electrode 10 made of a nickel (Ni) layer 10a and an aluminum (Al) layer 10b is provided so as to cover the n ⁺ source region 4, the p contact layer 5, the gate insulating film 7 and the insulating film 9. A drain electrode 11 made of nickel is provided on the second main surface side of the n ⁺ semiconductor substrate 1.

On the other hand, as shown in FIG. 2, the peripheral breakdown voltage structure portion 20b of the semiconductor device includes an n ⁻ base layer 2 and a p base layer 3 on the first main surface side of the n ⁺ semiconductor substrate 1 in the same manner as the active region 20a. It is provided in order. The n ⁺ source region 4 is not provided on the surface of the p base layer 3 of the peripheral breakdown voltage structure 20b, and only the p ⁺ contact region 5 is provided. Further, the gate electrode 8 is not filled in the trench of the peripheral breakdown voltage structure portion 20b, but the trench insulating film 12 is filled, and the upper surface of the trench insulating film 12 is covered with the insulating film 9.

In the peripheral breakdown voltage structure 20b, ap ⁺ region 6 is provided at the trench closest to the active region 20a and the bottom of the trench closest to the next. Note that the p + region 6 may be provided only in the trench closest to the active region 20a.

The p ⁺ region 6 is provided to prevent the electric field from concentrating on the bottom of the trench when a high voltage is applied between the source electrode 10 and the drain electrode 11. When the electric field is concentrated on the bottom of the trench, for example, the bottom of the trench of the gate insulating film 7 may be destroyed. By providing the p ⁺ region 6, it is possible to prevent the electric field from concentrating on the bottom of the trench and to prevent the gate insulating film 7 from being destroyed.

Further, a surface electrode 13 made of a nickel (Ni) layer 13a and an aluminum layer 13b is provided so as to cover a part of the trench insulating film 12 and the insulating film 9 of the peripheral breakdown voltage structure portion 20b and the p contact layer 5. Further, a back electrode 14 made of nickel is provided on the second main surface side of the n ⁺ semiconductor substrate 1 of the peripheral breakdown voltage structure 20b.

  Next, a manufacturing process of the semiconductor device according to the first embodiment will be described. 3 to 6 are explanatory diagrams for explaining a manufacturing process of the semiconductor device according to the first embodiment. 3 to 6, the active region 20 a and the peripheral voltage withstanding structure 20 b are shown in one drawing.

First, an n-type silicon carbide semiconductor substrate (hereinafter referred to as “n ⁺ semiconductor substrate”) 1 containing a sufficiently high concentration of impurities is prepared. The n ⁺ semiconductor substrate 1 includes, for example, about 2 × 10 ¹⁸ cm ^{−3 of} nitrogen. Next, on the first main surface side of the n ⁺ semiconductor substrate 1, for example, an n ⁻ base layer 2 having a thickness of about 10 μm containing about 1.0 × 10 ¹⁶ cm ^{−3 of} nitrogen is epitaxially grown. Subsequently, a 2.5 μm thick p base layer 3 containing about 2.1 × 10 ¹⁷ cm ^{−3 of} aluminum, for example, is epitaxially grown on the surface of the n ⁻ base layer 2 (FIG. 3). The n ⁻ base layer 2 and the p base layer 3 are formed in both the active region 20a and the peripheral voltage withstanding structure portion 20b.

Next, the n ⁺ source region 4 is selectively formed on the surface of the p base layer 3 in the active region 20a. A p ⁺ contact region 5 is formed in a region where the n ⁺ source region 4 is not formed in the surface of the p base layer 3 of the active region 20a. Further, only the p ⁺ contact region 5 is formed on the surface of the p base layer 3 of the peripheral breakdown voltage structure 20b (FIG. 4). The n ⁺ source region 4 is formed by performing heat treatment after ion implantation of phosphorus, and the p ⁺ contact region 5 is formed by performing heat treatment after ion implantation of aluminum. The heat treatment temperature is, for example, 1700 ° C., and the heat treatment time is, for example, 1 minute.

Next, a 1.6 μm thick silicon oxide film 15 is formed on the surfaces of the n ⁺ source region 4 and the p ⁺ contact region 5. Subsequently, the silicon oxide film 15 is selectively removed by photolithography and etching, and an oxide film mask having a width of 1.2 μm is formed, for example, every 5 μm. Then, a part of the n ⁺ source region 4, the p ⁺ contact region 5 and the p base layer 3 is selectively removed by etching to form a trench reaching the n ⁻ base layer 2 (FIG. 5). The depth of the trench is 3 μm, for example.

Next, a thermal oxide film is formed in the trench and patterned. Then, for example, aluminum is ion-implanted into the bottom of the trench at about 2.0 × 10 ¹⁹ cm ⁻³ and activated by heating at 1700 ° C. for 1 minute, for example. As a result, ap ⁺ region 6 is formed at the bottom of the trench. Thereafter, the silicon oxide film 15 is removed (FIG. 6). Here, in the active region 20a, the p ⁺ region 6 is formed in all the trenches. On the other hand, in the peripheral voltage withstanding structure portion 20b, the p ⁺ region 6 is formed only in the trench closest to the active region 20a, or only in the trench closest to the active region 20a and the trench closest to the second.

  Next, a gate insulating film 7 having a thickness of, for example, 100 nm is formed inside the trench of the active region 20a. Thereafter, the gate electrode 8 is buried in the trench, and the insulating film 9, the source electrode 10, and the drain electrode 11 are formed, thereby completing the active region 20a of the semiconductor device shown in FIG. The source electrode 10 is formed of a nickel (Ni) layer 10a and an aluminum layer 10b. The drain electrode 11 is made of nickel. Thus, the reason why the source electrode 10 and the drain electrode 11 are made of nickel is to bring each electrode into contact with the semiconductor with low resistance.

On the other hand, the trench insulating film 12 is filled in the trench of the peripheral breakdown voltage structure 20b. Trench insulating film 12 may be formed of a silicon nitride film in addition to an oxide film, for example. Subsequently, the insulating film 9 is formed in the same manner as the active region 20a. Then, a contact hole is formed in the insulating film 9, and simultaneously with the formation of the source electrode 10 in the active region 20a, the surface electrode 13 composed of the nickel layer 13a and the aluminum layer 13b is formed. Thereby, the surface electrode 13 covers each of the p base layers 3 separated by the trench. Further, a back electrode 14 is formed of nickel on the second main surface of the n ⁺ semiconductor substrate 1. Thereby, the peripheral breakdown voltage structure 20b of the semiconductor device shown in FIG. 2 is completed.

  FIG. 7 is a graph showing electrical characteristics of the semiconductor device of the semiconductor device according to the first embodiment. In FIG. 7, the horizontal axis represents the drain-source voltage Vds (V), and the vertical axis represents the drain current Ids (A). In FIG. 7, white circles (◯) indicate characteristic values of the semiconductor device according to the first embodiment, and black circles (●) indicate characteristic values of the semiconductor device having the bevel structure shown in FIG. As shown in FIG. 7, the semiconductor device according to the first embodiment has substantially the same electrical characteristics as a semiconductor device having a bevel structure.

The semiconductor device according to the first embodiment used for measuring the characteristic values in FIG. 7 had a chip size of 3 mm square and an active region area of 7.85 mm ² . Also, 40 μm is sufficient for the length of the peripheral breakdown voltage structure portion of the semiconductor device according to the first embodiment (the length from the end of the active region to the end of the semiconductor device). This is because most of the drain voltage is borne by the p ⁺ region 6 formed at the bottom of the trench in the peripheral breakdown voltage structure. Note that the chip size of the beveled semiconductor device used for comparison was 3 mm square, and the length of the peripheral breakdown voltage structure portion was 260 μm.

FIG. 8 is a graph showing the results of a long-term reliability test of the semiconductor device according to the first embodiment. In FIG. 8, the horizontal axis represents elapsed time (h), and the vertical axis represents device breakdown voltage (V) when the drain current is 1 mA / cm ² . In FIG. 8, white triangles (Δ) indicate characteristic values (p = 1) in the case where the p ⁺ region 6 is formed only in the trench closest to the active region in the semiconductor device according to the first embodiment, a black triangle. (▲) indicates the characteristic value (p = 2) in the case where the p ⁺ region 6 is formed in the trench closest to the active region and the second closest trench in the semiconductor device according to the first embodiment. Also, the black squares (■) in FIG. 8 indicate the characteristic values of the semiconductor device having the bevel structure shown in FIG. 12 measured for comparison.

  In the long-term reliability test, a high temperature applied voltage test was adopted. First, the semiconductor device according to the first embodiment or a semiconductor device having a bevel structure is molded and assembled. Thereafter, a voltage of 1200 V was continuously applied between the drain and the source in an atmosphere at 125 ° C., and a change in device breakdown voltage was measured.

The initial device withstand voltage of the semiconductor device according to the first embodiment is 1250V, which is sufficient as a device with a withstand voltage of 1200V. The on-resistance of the semiconductor device according to the first embodiment (Ron) was 2.49Emuomegacm ² For 2.47mΩcm ^2, p = ² in p = 1. The reason why there is almost no difference in on-resistance between p = 1 and p = 2 is because the design of the active region is the same. The initial device breakdown voltage of the semiconductor device having the bevel structure used for comparison was 1265 V, and the on-resistance (Ron) was 2.47 mΩcm ² .

  As shown in FIG. 8, the element breakdown voltages of the semiconductor device according to the first embodiment and the semiconductor device of the bevel structure are almost the same immediately after the start of the experiment. However, in the semiconductor device according to the first embodiment, neither p = 1 nor p = 2 showed any change in breakdown voltage after 3000 hours from the start of the experiment. On the other hand, the breakdown voltage of the beveled semiconductor device started to deteriorate after 96 hours from the start of the experiment, and then the breakdown voltage suddenly decreased.

Thus, if the p ⁺ region 6 is formed at least at the bottom of the trench closest to the active region among the trenches in the peripheral breakdown voltage structure portion of the semiconductor device, a sufficient breakdown voltage can be obtained over a long period of time. Further, if the p ⁺ region 6 is formed in the trench closest to the active region and the second closest trench, the breakdown voltage of the semiconductor device can be ensured more reliably. Here, the breakdown voltage of the semiconductor device is lowered because the electric field concentrates at the bottom of the trench closest to the active region among the trenches in the peripheral breakdown voltage structure, causing avalanche breakdown. In the semiconductor device according to the first embodiment, the p ⁺ region 6 is provided at the bottom of the trench closest to the active region, thereby relaxing the electric field and preventing avalanche breakdown. For this reason, the semiconductor device according to the first embodiment can obtain a sufficient breakdown voltage over a long period of time.

Further, in the semiconductor device according to the first embodiment, as compared with the case where all of the trench near the breakdown voltage structure portion provided p ⁺ region 6, since the number of trenches to provide a p ⁺ region 6 is small, the peripheral voltage withstanding structure portion The length of can be reduced.

FIG. 9 is an explanatory diagram illustrating a simulation result of electric lines of force in the peripheral withstand voltage structure portion of the semiconductor device (p = 2) according to the first embodiment. FIG. 9 shows a simulation result when the drain-source voltage Vds is 1500V. In FIG. 9, ap ⁺ region is formed at the bottom of trenches T1 and T2 close to the active region. On the other hand, the p ⁺ region is not formed at the bottom of the trenches T3 to T5 away from the active region, and is filled with an insulating film.

As shown in FIG. 9, almost no electric lines of force are collected at the bottoms of the trenches T1 and T2. On the other hand, electric lines of force are concentrated at the bottom of the trenches T3 to T5. This is the p ⁺ region no voltage is borne by the bottom of the trench T1 and T2 are formed, the voltage at the bottom of the p ⁺ region 6 trench T3 is not formed T5 is borne Show.

Thus, because most voltages at the bottom of the trench p ⁺ region is formed is not burden to all of the trench near the breakdown voltage structure portion when forming the p ⁺ regions, the peripheral voltage withstanding structure portion in order to secure a withstand voltage The length must be increased. However, in the semiconductor device according to the first embodiment, the p ⁺ region is formed only in the trenches (T1, T2) in the vicinity of the active region where the electric field is concentrated among the trenches in the peripheral breakdown voltage structure portion, and the trench separated from the active region. A p ⁺ region is not formed in (T3 to T5). For this reason, in the semiconductor device according to the first embodiment, the voltage can be borne at the bottom of the trench (T3 to T5) where the p ⁺ region is not formed, and the length of the peripheral breakdown voltage structure can be shortened. it can.

More specifically, in the semiconductor device according to the first embodiment, a breakdown voltage of 1500 V can be obtained with a total of six trenches (only five appear in the figure) as shown in the simulation results of FIG. Therefore, 40 μm is sufficient for the length of the peripheral pressure-resistant structure. On the other hand, when the p ⁺ region is formed in all the trenches of the peripheral breakdown voltage structure portion, the length of the peripheral breakdown voltage structure portion must be about 85 μm in order to ensure a breakdown voltage of 1500V.

As described above, according to the semiconductor device according to the first embodiment, by forming the p ⁺ region 6 only at the bottom of the trench close to the active region, the length of the peripheral breakdown voltage structure portion can be reduced and long-term A high breakdown voltage can be ensured over a wide range. Further, according to the semiconductor device according to the first embodiment, a semiconductor device having the same electrical characteristics as a beveled semiconductor device can be obtained without using a complicated technique.

(Embodiment 2)
FIG. 10 is a cross-sectional view illustrating the configuration of the active region of the semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view showing the configuration of the peripheral voltage withstanding structure portion of the semiconductor device according to the second embodiment. In the second embodiment, a case where the present invention is applied to a trench IGBT will be described. In the following description, components similar to those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

The semiconductor device (active region 40a, the peripheral voltage withstanding structure portion 40b) according to the second embodiment, instead of the n ⁺ semiconductor substrate 1 of the semiconductor device according to the first embodiment (see FIGS. 1 and 2), p ⁺ semiconductor It is formed by the substrate 31. In the semiconductor device according to the second embodiment, an n buffer layer 32 is formed between the n ⁻ base layer 2 and the p ⁺ semiconductor substrate 31. The electrodes on the second main surface side of the p ⁺ semiconductor substrate 31 (the drain electrode 11 and the back electrode 14) have a low contact resistance with the p ⁺ semiconductor substrate 31 and are an intermetallic compound of titanium and aluminum (hereinafter “Ti”). -Al ").

A method for manufacturing the semiconductor device according to the second embodiment will be described. First, a p-type silicon carbide semiconductor substrate (hereinafter referred to as “p ⁺ semiconductor substrate”) 31 containing a sufficiently high concentration of impurities is prepared. The p ⁺ semiconductor substrate 31 includes, for example, about 2 × 10 ¹⁸ cm ^{−3 of} aluminum. Next, on the first main surface side of the p ⁺ semiconductor substrate 31, an n buffer layer 32 having a thickness of about 1 μm and containing, for example, about 2.0 × 10 ¹⁷ cm ^{−3 of} nitrogen is epitaxially grown. Thereafter, the semiconductor device is manufactured by the same process as in the first embodiment (see FIGS. 3 to 6). However, the electrodes (drain electrode 11 and back electrode 14) on the second main surface side of the p ⁺ semiconductor substrate 31 are made of Ti—Al instead of nickel.

The semiconductor device according to the second embodiment thus formed was subjected to the same long-term reliability test as that of the semiconductor device according to the first embodiment. In the semiconductor device according to the second embodiment used for the test, it is sufficient that the chip size is 3 mm square, the area of the active region is 7.85 mm ² , and the length of the peripheral breakdown voltage structure is 40 μm. For comparison, the same test was performed on the beveled semiconductor device shown in FIG. Note that the on-voltage of the semiconductor device according to the second embodiment used for the test at the time of 10A conduction is 3.60 V, the initial element breakdown voltage is 1250 V, the bevel structure semiconductor device on-voltage (3.62 V) and the initial voltage It was almost the same as the device breakdown voltage (1265V).

  In the semiconductor device according to the second embodiment, as with the semiconductor device according to the first embodiment, no change in withstand voltage was observed after 3000 hours from the start of the experiment. On the other hand, the breakdown voltage of the beveled semiconductor device began to deteriorate after 96 hours, as in the result shown in FIG.

  As described above, the present invention can be applied not only to the trench MOSFET shown in the first embodiment but also to the trench IGBT shown in the second embodiment. The same effect as in the first mode can be obtained.

  As described above, the silicon carbide semiconductor device according to the present invention is useful for silicon carbide semiconductor devices such as MOSFETs and IGBTs having a trench gate structure, and is particularly suitable for MOS power silicon carbide semiconductor devices.

3 is a cross-sectional view showing a configuration of an active region of the semiconductor device according to the first exemplary embodiment; FIG. 3 is a cross-sectional view showing a configuration of a peripheral voltage withstanding structure portion of the semiconductor device according to the first exemplary embodiment; FIG. 6 is an explanatory diagram for explaining a manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is an explanatory diagram for explaining a manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is an explanatory diagram for explaining a manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is an explanatory diagram for explaining a manufacturing process of the semiconductor device according to the first embodiment; FIG. 3 is a graph showing electrical characteristics of the semiconductor device of the semiconductor device according to the first embodiment; 4 is a graph showing the results of a long-term reliability test of the semiconductor device according to the first embodiment. FIG. 6 is an explanatory diagram illustrating a simulation result of electric lines of force in a peripheral withstand voltage structure portion of the semiconductor device (p = 2) according to the first embodiment; 6 is a cross-sectional view showing a configuration of an active region of a semiconductor device according to a second exemplary embodiment; FIG. FIG. 6 is a cross-sectional view showing a configuration of a peripheral voltage withstanding structure portion of a semiconductor device according to a second embodiment; It is explanatory drawing which shows the structure of the semiconductor device of a bevel structure.

Explanation of symbols

1 n ⁺ semiconductor substrate (first conductivity type semiconductor substrate)
2 n ^- base layer (first conductivity type semiconductor layer)
3 p base layer (second conductivity type semiconductor layer)
4 n ⁺ source region 5 p ⁺ contact region 6 p ⁺ region (second conductivity type region)
7 Gate insulating film 8 Gate electrode (control electrode)
9 Insulating film 10 Source electrode (first main electrode)
10a Nickel layer 10b Aluminum layer 11 Drain electrode (second main electrode)
12 Trench insulating film 13 Surface electrode 13a Nickel layer 13b Aluminum layer 14 Back electrode 20a Active region 20b Peripheral breakdown voltage structure

Claims (3)

A silicon carbide semiconductor device having an active region and a breakdown voltage structure surrounding the periphery of the active region,
A first conductivity type semiconductor substrate having a high impurity concentration formed of silicon carbide;
A first conductivity type semiconductor layer having a lower impurity concentration than the first conductivity type semiconductor substrate formed on the first main surface of the first conductivity type semiconductor substrate;
A second conductivity type semiconductor layer formed on a surface of the first conductivity type semiconductor layer;
A plurality of trenches formed in a depth direction so as to penetrate the second conductivity type semiconductor layer and reach the first conductivity type semiconductor layer;
A first conductivity type source region selectively formed on a surface of the second conductivity type semiconductor layer of the active region;
A first main electrode electrically connected to the first conductivity type source region and the second conductivity type semiconductor layer;
A second main electrode formed on a second main surface of the first conductivity type semiconductor substrate;
A surface electrode covering a semiconductor region between the trenches of the pressure-resistant structure;
With
A control electrode is formed in the active region trench through a gate insulating film,
A silicon carbide semiconductor device, wherein a trench of the breakdown voltage structure portion is filled with an insulating material, and a second conductivity type region is formed at the bottom of the trench closest to the active region. A silicon carbide semiconductor device having an active region and a breakdown voltage structure surrounding the periphery of the active region,
A second conductivity type semiconductor substrate made of silicon carbide and having a high impurity concentration;
A first first conductivity type semiconductor layer formed on a first main surface of the second conductivity type semiconductor substrate;
A second first conductivity type semiconductor layer having an impurity concentration lower than that of the first conductivity type semiconductor substrate formed on the surface of the first first conductivity type semiconductor layer;
A second conductivity type semiconductor layer formed on the surface of the second first conductivity type semiconductor layer;
A plurality of trenches formed in a depth direction so as to penetrate the second conductivity type semiconductor layer and reach the second first conductivity type semiconductor layer;
A first conductivity type source region selectively formed on a surface of the second conductivity type semiconductor layer of the active region;
A first main electrode electrically connected to the first conductivity type source region and the second conductivity type semiconductor layer;
A second main electrode formed on a second main surface of the first conductivity type semiconductor substrate;
A surface electrode covering a semiconductor region between the trenches of the pressure-resistant structure;
With
A control electrode is formed in the active region trench through a gate insulating film,
A silicon carbide semiconductor device, wherein a trench of the breakdown voltage structure portion is filled with an insulating material, and a second conductivity type region is formed at the bottom of the trench closest to the active region.   2. The second conductivity type region is formed at a bottom of a trench closest to the active region and a bottom of a trench closest to the active region among the trenches of the breakdown voltage structure portion. Or the silicon carbide semiconductor device of 2.

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