JPH0878619A - Semiconductor device for electric power - Google Patents

Abstract

PURPOSE: To provide a compact, high-reliability semiconductor device by using metal wires having an almost equal length independently from the area of semiconductor chip. CONSTITUTION: In a semiconductor device for electric power with semiconductor chips 2 and 14 and electrode pattern arranged on a supporting substrate, which has semiconductor chips 2 and 14 with a plurality of bonding pads 17, a plurality of electrode patterns, and a plurality of metal wires 8 for connecting by bridging a plurality of pads 17 to electrode patterns, the pads 17 in a plurality of rows are arranged in parallel on the semiconductor chips 2 and 14. And first and second electrode patterns 15a and 15b are arranged almost in parallel to each row of the pads 17 at both the sides of the semiconductor chips 2 and 14, and metal wires 8 are respectively connected by bridging between the first electrode pattern 15a and the pads 17 in one or more rows adjacent to said patterns 15a and between the second electrode patterns 15b and the pads 17 in one or more rows adjacent to said patterns 15b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and more particularly, it can be used in a high frequency band and
The present invention relates to a power semiconductor device having a module structure capable of processing a large amount of power.

[0002]

2. Description of the Related Art Conventionally, IGBTs have been used for power semiconductor devices.
There is known a module structure in which a power semiconductor switching element such as (insulated gate bipolar transistor), diode, GTO thyristor (gate turn-off thyristor), and power transistor is sealed in an insulating container. This power semiconductor device having a module structure is used in various inverter devices and the like in accordance with the withstand voltage and current capacity characteristics of a built-in power semiconductor switching element. Among them, as a power semiconductor switching element, an IGBT is used. A power semiconductor device having a module structure including a power supply is used as a control circuit for various power devices from the viewpoint that the IGBT is a voltage-controlled type, and therefore is easy to control and can process a large current in a high frequency region. Many are used.

Most of the power semiconductor devices having such a module structure have a structure in which a supporting substrate and a circuit component are electrically insulated from each other for convenience of use, and an insulating plate is provided on the supporting substrate. Are welded and laminated, and a circuit component portion including a semiconductor chip, an electrode pattern and the like is provided on the insulating plate. In addition, this power semiconductor device having a module structure employs a pressure welding method or a joining method when conductively connecting a semiconductor chip or an electrode pattern forming a circuit component and an external lead terminal. Here, the pressure contact method is a structure in which the lead electrode of the semiconductor chip and the external lead terminal are mechanically pressed to bond them, and this pressure contact method does not cause deterioration at the bonding interface between the lead electrode of the semiconductor chip and the external lead terminal. Although it has the advantage that it hardly occurs, the mechanical structure is complicated due to the pressure contact structure. On the other hand, the bonding method is a structure in which a semiconductor chip or an electrode pattern and an external lead terminal are conductively connected by solder or a metal wire,
This joining method has the advantage of being relatively easy to assemble, but it may cause deterioration of the joining portion of the metal wire or the solder layer depending on the use conditions.

Like an IGBT or the like, a semiconductor chip is prepared by cutting out one silicon (Si) wafer,
Moreover, in a power semiconductor device having a module structure in which a plurality of semiconductor chips are connected in parallel in one structure,
When a semiconductor chip or electrode pattern is electrically conductively connected to an external lead terminal, a joining method is usually adopted. Further, in a power semiconductor device having a module structure in which the entire surface of the semiconductor chip constitutes a common electrode such as a diode, when conductively connecting the semiconductor chip and the electrode pattern, direct conductive connection is usually made by soldering or the like. Has been adopted. On the other hand, in a power semiconductor device having a module structure in which an emitter lead-out terminal and a gate lead-out terminal are mixed on the surface of a semiconductor chip, such as an IGBT, an emitter lead-out terminal or a gate lead-out terminal and an emitter electrode pattern corresponding thereto are provided. When conductively connecting the gate electrode pattern and the gate electrode pattern, metal wires are mainly connected between the emitter electrode lead terminal and the emitter electrode pattern, and between the gate electrode lead terminal and the gate electrode pattern, respectively. However, when the connecting means by the metal wire is used in the power semiconductor device having the module structure, the joint portion of the metal wire or the joint portion of the solder layer is deteriorated as described above. The cause of such deterioration is temperature change due to energization, that is, deterioration due to temperature rise and fall of the metal wire joint, and deterioration due to changes in the ambient environment (for example, application of vibration, occurrence of corrosion, etc.). In this case, in order to suppress deterioration due to temperature change due to energization, a means for increasing the diameter of the metal wire used and increasing the time until disconnection,
In order to reduce the amount of flowing current per metal wire, a means for connecting a plurality of metal wires in parallel may be adopted.
Further, in order to suppress deterioration due to vibration or corrosion, a means for covering the metal wire to be used with a gel-like elastic agent containing extremely few ionic impurities may be adopted.

By the way, in a power semiconductor device having a module structure, the withstand voltage when a plurality of semiconductor chips are connected in parallel is determined by the number of termination rings (FLR) provided on the outer periphery of each semiconductor chip. In order to increase the breakdown voltage of the semiconductor chip, the number of FLRs may be increased and the electric field between the rings may be evenly distributed. On the other hand, the current capacity of the semiconductor chip is substantially proportional to the effective area of the semiconductor chip, that is, the area of the semiconductor chip excluding the FLR forming portion. Therefore, if the area of the FLR forming portion increases, the semiconductor chip's current capacity increases accordingly. The effective area becomes small. Here, in order to secure the amount of current of the semiconductor chips, it is sufficient to increase the number of semiconductor chips connected in parallel or increase the area of one semiconductor chip. When the value is increased, the amount of current flowing through the semiconductor chip becomes unbalanced, and therefore a means for preventing such an amount of current imbalance is required.

Here, FIG. 8 is a block diagram showing an example of a known means for preventing the imbalance of the current amount in the semiconductor chip, showing an example in which the semiconductor chip constitutes an IGBT. Yes, (a) shows the case where the semiconductor chip is small, and (b) shows the case where the semiconductor chip is large.

As shown in FIGS. 8A and 8B, the semiconductor chip 51 is divided into a plurality of cells (IGBT cells) 52, and each of the divided cells 52 is provided with an emitter bonding pad 53. . Further, a gate bonding pad 54 common to each cell 52 is provided in the central portion of the semiconductor chip 51. Then, each of the emitter bonding pads 53 is connected to a common emitter electrode pattern (also not shown) via a metal wire (not shown) separately so that the cells 52 are connected in parallel and the current flowing through each cell 52 is It is intended to be uniform. In this configuration, if the number of cells 52 to be divided is increased, that is, the number of cells 52 connected in parallel is increased, the imbalance of the amount of current in the semiconductor chip 51 can be effectively eliminated. Increasing the number causes various problems as described below.

The first problem is that the overall structure of the power semiconductor device having a module structure becomes complicated, the inductance of the wiring portion including the metal wire increases, and the loss increases when performing the switching operation. is there. The second problem is that due to variations in characteristics between the cells 52 connected in parallel, and imbalance between the arrangement positions of the emitter bonding pads 53 of each cell 52 and the emitter electrode pattern (not shown), This is a point where an imbalance occurs in the amount of current between 52. The third problem is that each cell 52
As the number of divisions increases, the semiconductor chip 51 becomes larger,
The point is that the power semiconductor device having a module structure also becomes larger. The fourth problem is that as the number of divisions of the cell 52 increases, the manufacturing yield of the power semiconductor device having a module structure decreases.

In order to solve these problems, a power semiconductor device having a module structure, which solves the second problem of imbalance in the amount of current, has already been disclosed in Japanese Patent Laid-Open No.
No. 1-13905 and the like. Also, the third
As a device that solves the problem of large size, which is a problem of (1), a power semiconductor device having a module structure as shown in FIG. 9 is known. Among these, the power semiconductor device having a module structure disclosed in Japanese Patent Laid-Open No. 61-13905 is equivalent to each semiconductor chip from these semiconductor chips to the external lead terminals of the module when a plurality of semiconductor chips are connected in parallel. It is connected so that it will be in a proper state. In a power semiconductor device having a module structure as shown in FIG. 9, an insulating plate 62 is laminated on a supporting substrate 61, and a collector electrode pattern 63, an emitter electrode pattern 64, and a gate electrode pattern 65 are formed on the insulating plate 62. The diode chip 66 and the IGBT chip 67 are provided side by side on the collector electrode pattern 63. Then, the diode chip 66 and the IGB arranged side by side
The emitter electrode pattern 64 is arranged on one side of the T chip 67, and the gate electrode pattern 65 is arranged on the other side of the IGBT chip 67. A collector external lead terminal 69 is provided at one corner of the collector electrode pattern 63, an emitter external lead terminal 70 is provided in the middle of the emitter electrode pattern 64, and a gate external lead terminal 71 is provided at the end of the gate electrode pattern 65. Further, four anode pads (not shown) are provided on the diode chip 66,
Four emitter pads 72 and one gate pad 73 are provided on the T chip 67. Metal wires 74 are respectively connected between the four anode pads and the four emitter pads 72 and the emitter electrode pattern 64.
The metal wire 74 is also connected between one gate pad 73 and the gate electrode pattern 65.

[0010]

By the way, the power semiconductor device having the module structure disclosed in Japanese Patent Laid-Open No. 61-13905 has a problem in that when a plurality of semiconductor chips are connected in parallel,
Although it is possible to avoid the occurrence of an imbalance in the current amount of multiple semiconductor chips, what is considered when increasing the area of each semiconductor chip in order to reduce the total number of multiple semiconductor chips connected in parallel. Not not. In particular, when a semiconductor chip has a large area, a plurality of metal wires connecting one semiconductor chip and one electrode pattern have different lengths, which causes various vibrations in each metal wire. Alternatively, the metal wire self-heats due to energization, or the inductance value is different among the metal wires, so that many adverse effects occur during the operation of the power semiconductor device having the module structure. The power semiconductor device having the module structure disclosed in No. -13905 has a problem that no consideration has been given to the occurrence of such an adverse effect.

Further, the power semiconductor device having the module structure as shown in FIG. 9 can be reduced in size to some extent as compared with the power semiconductor device having the module structure before that, but the IGBT chip 67 has the same structure. As shown in the state of the connected metal wire 74, the metal wire 74 connected between the emitter pad 72 and the emitter electrode pattern 64, the gate pad 73 and the gate electrode pattern 65.
When the metal wires 74 connected between them are arranged so as to extend in directions opposite to each other, the same IGBT chip 67 is provided.
As for the length of the metal wire 74 connected to the long wire, the difference between the long wire and the short wire is about three times. The longer the metal wire 74 is, the faster the joint interface strength deteriorates due to vibration or self-heating due to energization, and once the joint area becomes small due to deterioration, current concentration concentrates on the smaller portion. Occurs, and the life is shortened in an accelerated state.
However, there is a problem in that there is an imbalance in life between the four.

The present invention eliminates such a problem, and its object is to achieve small size and high reliability by using connecting metal wires having substantially the same length regardless of the area of the semiconductor chip. It is to provide a power semiconductor device having the same.

[0013]

In order to achieve the above object, the present invention provides one or more semiconductor chips having a plurality of bonding pads, and one or more electrode patterns provided in the vicinity of the semiconductor chips. And a plurality of metal wires bridge-connected between the plurality of bonding pads of the semiconductor chip and the corresponding electrode patterns, wherein the one or more semiconductor chips and the one or more electrode patterns are In a power semiconductor device arranged on a common support substrate, a plurality of rows of bonding pads are arranged and formed in parallel on the semiconductor chip, and the semiconductors are provided on both sides of the semiconductor chip substantially parallel to the bonding pads of each row. First and second electrode patterns corresponding to the chip are respectively arranged, and the first electrode pattern and the first electrode pattern are arranged close to each other. Between one row bonding pads even without, and comprises means to bridge connecting the metal wires respectively between said second at least one row bonding pad of the electrode patterns adjacent the second electrode pattern.

[0014]

According to the above means, a plurality of rows of bonding pads are arranged and formed in parallel on the semiconductor chip, and the semiconductor chips are arranged on both sides of the semiconductor chip so as to be substantially parallel to the plurality of rows of bonding pads. And a second electrode pattern between the first electrode pattern and at least one row of bonding pads arranged in proximity to the first electrode pattern. Since the metal wires are bridge-connected to the semiconductor chip and at least one row of bonding pads arranged close to the second electrode pattern, the metal wires are led out to both sides of the semiconductor chip when viewed from the semiconductor chip. Moreover, the distance between each row of bonding pads and the corresponding electrode pattern is the shortest in terms of placement,
The length of each metal wire is minimal, and
Their lengths are approximately equal.

As described above, according to the above-mentioned means, the length of each metal wire connected to the semiconductor chip is short and the lengths are substantially equal to each other. Therefore, the vibration of the metal wire and the influence of self-heating due to energization are caused. Can be significantly removed, and the lifespan of these metal wires can be improved as compared with known ones, and a small-sized and highly reliable power semiconductor device can be obtained.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings.

1A and 1B are structural views showing a first embodiment of a power semiconductor device according to the present invention. FIG. 1A is a top view and FIG. 1B is a top view of the line AA '. Cross section of
(C) is a perspective view showing an external lead-out terminal connecting portion, and shows an example in which a semiconductor chip constitutes a diode chip.

1A to 1C, 1 is a supporting substrate, 2 is a diode chip (semiconductor chip), 3 is an insulating plate, 4 is a cathode electrode pattern, 5a is a first anode electrode pattern, and 5b is A second anode electrode pattern,
6 is a cathode terminal, 7a is a first anode terminal, 7b is a second anode terminal, 8 is a metal wire, 9 is a metal foil, 1
Reference numerals 0, 11, and 13 are solder layers, and 12 is a solder stop slit.

The support substrate 1 is a metal substrate which also serves as a heat dissipation plate. The insulating plate 3 is a substrate made of an insulating material such as aluminum nitride (AlN) and alumina (Al ₂ O ₃ ), and nickel (N
i) It is joined by a solder layer 10 via a metal foil 9 made of plated copper (Cu), and insulates between the supporting substrate 1 and each electric component or electric circuit portion mounted on the insulating plate 3. . Cathode electrode pattern 4, first anode electrode pattern 5a, second anode electrode pattern 5
Each of b is joined to the insulating plate 3 by a metal brazing material or the like, and the cathode electrode pattern 4 is arranged in the central portion, and the first anode electrode pattern 5a and the second anode electrode pattern 5b are arranged on both sides thereof. It In the diode chip 2, the cathode side is joined to the cathode electrode pattern 4 via the solder layer 11, and two rows of anode bonding pads arranged in parallel are evenly provided so that the current is uniform in the element of the diode chip 2. There is. The cathode terminal 6 is bonded via the solder layer 13 in the middle of the exposed end surface of the cathode electrode pattern 4, and the first anode terminal 7a is formed.
Is also bonded to the exposed end of the first anode electrode pattern 5a via the solder layer 13 as well, and the second anode terminal 7b is also connected to the exposed end of the second anode electrode pattern 5b by the same solder layer 13. Are joined through. Between the first anode electrode pattern 5a and the anode bonding pad on one side closer to it, and between the second anode electrode pattern 5b and the anode bonding pad on the other side closer to it, Each of the metal wires 8 is bridge-connected so as to connect the shortest distance. Also,
On the cathode electrode pattern 4 near the portion where the cathode terminal 6 is joined, on the first anode electrode pattern 5a near the portion where the first anode terminal 7a is joined, and on the portion where the second anode terminal 7b is joined. Solder stop slits 12 are provided on the second anode electrode patterns 5b close to each other, and the cathode terminals 6, the first anode terminals 7a, and the second anode terminals 7b are connected to the cathode electrode patterns 4, the first anodes. When soldering to the electrode pattern 5a and the second anode electrode pattern 5b, the solder is the cathode electrode pattern 4, the first anode electrode pattern 5a,
It is prevented from flowing out to the second anode electrode pattern 5b. Although not shown in FIGS. 1A to 1C, the diode chip 2, the cathode electrode pattern 4, the first anode electrode pattern 5a, the second anode electrode pattern 5b, and the like are not shown in the supporting substrate 1. A cathode external lead-out terminal connected to the cathode terminal 4 and an anode external lead-out terminal connected to the first and second anode terminals 5a and 5b, respectively, which are sealed in an insulating container in a state of being joined to and are provided. In the state, it is formed into a modular structure.

According to the above structure, one row of anode bonding pads and the first anode electrode pattern 5a provided on the anode side of the diode chip 2 and the other row of the anode bonding pads and the second anode electrode are provided. Both patterns 5b are in a parallel state,
In addition, since they are arranged close to each other, the metal wires 8 respectively connected between the anode bonding pads on one row and the first anode electrode pattern 5a, and
The metal wires 8 connected between the anode bonding pad on the other row and the second anode electrode pattern 5b can be of substantially the same length, and the length can be minimized. be able to. In other words, the length of these metal wires 8 is
It is less than half the length of one side.

As described above, according to this embodiment, the length of each metal wire 8 connected to the diode chip 2 can be made the shortest and substantially the same, so that the inductance value and the effective resistance value can be reduced. Each metal wire 8
It is possible to eliminate the variation in the amount of current flowing between the metal wires 8 and reduce and equalize the occurrence of deterioration due to self-heating, expand the mutual intervals of the metal wires 8 and reduce the occurrence of vibrations caused by electromagnetic induction between the metal wires 8. By arranging the metal wires 8 so that they do not overlap and are at the same height, it is possible to reduce the deterioration caused by the occurrence of vibrations.
The life of the can be extended reliably compared to known ones,
It is possible to obtain a highly reliable power semiconductor device regardless of the area of the diode chip 2.

Next, FIG. 2 is a structural view showing a second embodiment of a power semiconductor device according to the present invention, where (a) is a top view and (b) is a top view thereof. 2 is a cross-sectional view of the line portion, and (c) is a circuit diagram showing an electrical equivalent circuit.
It shows an example in which one semiconductor chip constitutes an insulated gate bipolar transistor chip (IGBT chip) and a diode chip, respectively.

In FIGS. 2A to 2C, 4'is a collector electrode pattern / cathode electrode pattern (hereinafter referred to as collector electrode pattern), and 6'is a collector terminal / cathode terminal (hereinafter referred to as collector terminal). , 14 is an IGBT chip (semiconductor chip), 15a
Is a first emitter electrode pattern / first anode electrode pattern (hereinafter, referred to as a first emitter electrode pattern), and 15b is a second emitter electrode pattern / second anode electrode pattern (hereinafter, referred to as a second emitter electrode pattern). Of the emitter electrode pattern), 16 is a gate electrode pattern, 17 is a plurality of emitter bonding pads, 18 is a gate bonding pad, and 19a is a first emitter terminal and a first anode terminal (hereinafter, referred to as a first emitter terminal). , 19b is a second emitter terminal and a second anode terminal (hereinafter, referred to as a second emitter terminal), 20 is a gate terminal, and others are shown in FIGS. 1 (a) to 1 (c). The same components as those shown in FIG. The power semiconductor device of the second embodiment is equivalent to the IG as shown in FIG.
A diode is connected in parallel between the collector and the emitter of the BT.

Then, the insulating plate 3 is bonded onto the supporting substrate 1 by the solder layer 10 via the metal foil 9. Insulation plate 3
The collector electrode pattern 4 ′, the first and second emitter electrode patterns 15a and 15b, and the gate electrode pattern 16 are bonded to each other on the upper side, and the collector electrode pattern 4 ′ is arranged in the center part, and one of the long side parts The first emitter electrode pattern 15a is disposed on the side of, the second emitter electrode pattern 15b is disposed on the other side of the long side portion thereof, and the gate electrode pattern 16 is disposed on one side of the short side portion thereof. It Cathode side of diode chip 2 and IG
The collector side of each of the BT chips 14 is bonded to the collector electrode pattern 4'via the solder layer 11. In the diode chip 2, two rows of anode bonding pads arranged in parallel are evenly provided so that the current is uniform in the element of the diode chip 2. The IGBT chip 14 is
Although not shown in FIGS. 2A to 2C, the entire emitter cell is divided into a plurality of IGBT cells, and two rows of emitter bonding pads 17 are arranged in parallel corresponding to each IGBT cell.
, And a gate bonding pad 18 common to each IGBT cell is provided. The collector terminal 6'is formed on the solder layer 1 in the middle of the exposed end surface of the collector electrode pattern 4 '.
3, the first emitter terminal 19a is joined to the center of the first emitter electrode pattern 15a via the solder layer 13. The second emitter terminal 19b has a second
Is bonded to the center of the emitter electrode pattern 15b via the solder layer 13, and the gate terminal 20 is bonded to the end of the gate electrode pattern 16 via the solder layer 13. The first emitter electrode pattern 15a is provided on the diode chip 2 side.
The metal wire 8 is shortest between the second emitter electrode pattern 15b and the other side anode bonding pad on the side closer to the second emitter electrode pattern 15b. A bridge connection is made to connect the distance. Also, on the IGBT14 side,
1st emitter electrode pattern 15a and 1 on the side close to it
Between the emitter bonding pad 17 in one row, and between the second emitter electrode pattern 15b and the emitter bonding pad 17 in the other row near the second emitter electrode pattern 15b,
Further, the metal wires 8 are bridge-connected between the gate electrode pattern 16 and the gate bonding pad 18 so as to connect the shortest distance. In addition, this FIG.
Although not shown in (a) to (c), the diode chip 2 and the IGBT chip 14 and the first and second chips are also shown.
The emitter electrode patterns 15a and 15b, the gate electrode pattern 16 and the like are sealed in an insulating container in a state of being bonded to the support substrate 1 and are connected to the collector terminal 4 ', collector external lead-out terminals, first and second Emitter terminal 19
A module structure is formed in a state where an emitter external lead terminal connected to each of a and 19b and a gate external lead terminal connected to the gate terminal 20 are provided.

According to the above structure, on the diode chip 2 side, the anode bonding pad and the first emitter electrode pattern 15a in one row and the anode bonding pad and the second emitter electrode pattern 15b in the other row are all formed. , In a parallel state and in a closely arranged state, and on the IGBT chip 14 side, the emitter bonding pad 17 and the first emitter electrode pattern 15a in one row, the emitter bonding pad 17 in the other row, and Since the second emitter electrode patterns 15b are both in a parallel state and in a closely arranged state, and the gate bonding pad 18 and the gate electrode pattern 16 are also in a closely arranged state, One row of anode bonding pads and the first Jitter electrode metal wires 8 are connected between the patterns 15a, the anode bonding pad and the second emitter electrode pattern 15 in the other row
b, the metal wires 8 connected to each of them, the emitter bonding pads 17 of one row and the metal wires 8 connected to each of the first emitter electrode patterns 15a, the emitter bonding pads 17 of the other row, and A metal wire 8 and a gate bonding pad 1 which are respectively connected to the second emitter electrode pattern 15b.
8 and the metal wire 8 connected between the gate electrode pattern 16 and the metal wire 8 may have substantially the same length,
In addition, their length can be minimized.

As described above, according to this embodiment, the lengths of the metal wires 8 connected to the diode chip 2 and the IGBT chip 14 can be made the shortest and substantially the same. In the same manner as in the above example, the difference in the inductance value or the effective resistance value is minimized to eliminate the variation in the amount of current between the metal wires 8, and the occurrence of deterioration due to self-heating can be reduced and made uniform. The mutual spacing can be expanded to reduce the occurrence of vibrations due to electromagnetic induction occurring between the metal wires 8, so that the metal wires 8 do not overlap each other.
Moreover, by arranging them at the same height, it becomes possible to reduce the deterioration due to the occurrence of vibration, and it is possible to extend the life of each metal wire 8 more reliably than that of a known one, and to reduce the area of the diode chip 2. A highly reliable power semiconductor device can be obtained regardless of its size.

Further, according to this embodiment, the metal wire 8 connected to the emitter bonding pad 17 and the gate bonding pad 1 on the IGBT chip 14 side.
Since the connection arrangement is such that the metal wires 8 connected to 8 are substantially orthogonal to each other, when each metal wire 8 is energized,
Mutual interference is less likely to occur between the metal wire 8 connected to the emitter bonding pad 17 and the metal wire 8 connected to the gate bonding pad 18,
It is possible to prevent malfunction due to noise or the like, and further, the first and second emitter terminals 19a, 1
Since 9b is provided between the diode chip 2 and the IGBT chip 14, the overall size of the power semiconductor device can be reduced.

Next, FIG. 3 is a top view showing a third embodiment of the power semiconductor device according to the present invention. The diode chip 2 and the IGBT of the second embodiment shown in FIG.
It shows an example in which two parts each including the chip 14 are arranged in parallel.

In FIG. 3, the same components as those shown in FIG. 2 are designated by the same reference numerals.

In the third embodiment, two parts (power semiconductor units), which are the diode chip 2 and the IGBT chip 14 shown in the second embodiment, are arranged in parallel on the same supporting substrate 1. They are connected and arranged, and constitute one power semiconductor device having a large current capacity.

The configuration and operation of the third embodiment are as follows.
Since it is apparent from the above description of the configuration and operation of the second embodiment, the description of the configuration and operation of the third embodiment will be omitted.

According to the third embodiment, in addition to the effect that can be expected in the second embodiment, if the number of power semiconductor units connected in parallel is increased, the power semiconductor can be increased without increasing the number of external terminals. An effect that the current capacity of the device can be increased stepwise can be expected.

Next, FIG. 4 is a top view showing a fourth embodiment of the power semiconductor device according to the present invention. In the power semiconductor device of the third embodiment shown in FIG.
This is an example in which the emitter electrode patterns of the power semiconductor units arranged adjacent to each other are shared to form a common electrode pattern.

In FIG. 4, 15 'is a common common emitter electrode pattern and anode electrode pattern, and 19'
Is a common emitter terminal, 20 'is a common gate terminal, and other components that are the same as those shown in FIG. 3 are denoted by the same reference numerals.

The fourth embodiment differs from the third embodiment shown in FIG. 3 in that the first high power semiconductor unit is arranged on the right side and the second high power semiconductor unit is arranged on the left side. The component parts and circuit parts of the part adjacent to the unit are shared. That is, the second emitter electrode pattern 15b of the first high power semiconductor unit and the first emitter electrode pattern 15a of the second high power semiconductor unit are commonly used as a common emitter electrode pattern 15 ', and further, The second emitter terminal 19b of the first high power semiconductor unit and the first emitter terminal 19a of the second high power semiconductor unit are commonly used, and the common emitter terminal 19 'is used.
And the gate terminal 20 of the first high power semiconductor unit and the gate terminal 2 of the second high power semiconductor unit.
0 is commonly used to form a common gate terminal 20 '. Since the configuration of the fourth embodiment is the same as the configuration of the third embodiment except for these configurations, further description of the configuration of the fourth embodiment will be omitted.

The operation of the fourth embodiment is almost the same as the operation of the third embodiment, and moreover, it is obvious from the description of the operation of the second embodiment already given. The description of the operation of the fourth embodiment will be omitted.

According to the fourth embodiment, in addition to the effects expected from the third embodiment, the common emitter electrode pattern 1
The width of 5'is set to the first and second emitter electrode patterns 15
If it is configured to be wider than the widths of a and 15b, the bridging connection of the metal wire 8 between the common emitter electrode pattern 15 'and the anode bonding pads of the diode chip 2 arranged on both sides thereof, and the common connection Emitter electrode pattern 15 'and IGBT chips 1 arranged on both sides thereof
It is possible to simultaneously perform the bridging connection of the metal wire 8 with the emitter bonding pad 17 of No. 4, and the overall configuration is simpler and the size can be reduced as compared with the third embodiment. Can be expected.

Next, FIG. 5 is a top view showing a fifth embodiment of the power semiconductor device according to the present invention, in which three semiconductor chips are arranged in the power semiconductor device. One is an IGBT chip, and the other one is a diode chip.

In FIG. 5, 21 is a second IGBT chip, 23 is a gate electrode pattern, 24 is a second emitter bonding pad, 25 is a second gate bonding pad, and other components shown in FIG. The same components as those of the elements are designated by the same reference numerals.

In the fifth embodiment, the second IGBT chip 21 is additionally arranged in the second embodiment shown in FIG. 2, and the arrangement positions of some of the components are accompanied by the additional arrangement. Etc. have been changed. That is, the second IGBT chip 24 is arranged between the diode chip 2 and the IGBT chip 14, and the first emitter electrode pattern 15a and the second emitter electrode pattern 15a are provided on both sides of the second IGBT chip 24. 15b are arranged respectively. The gate electrode pattern 23 is the second emitter electrode pattern 15
It is arranged in a position parallel to b. In this case, although not shown in FIG. 5, the second IGBT chip 24 is entirely divided into a plurality of IGBT cells, and two rows of the second emitter bonding pads 24 corresponding to the IGBT cells are formed.
Are provided so as to be parallel to the first emitter electrode pattern 15a and the second emitter electrode pattern 15b,
At the same time, one gate bonding pad 25 common to these IGBT cells is provided. Between the first emitter electrode pattern 15a and the second emitter bonding pad 24 on one side closer thereto, and between the second emitter electrode pattern 15b and the second emitter bonding on the other side closer thereto. The metal wires 8 are bridge-connected to the pads 24 so as to be connected to each other at the shortest distance, and the gate electrode pattern 23 and the IGBT chip 14 are connected.
The metal wire 8 is bridge-connected to the gate bonding pad 18 of the second IGBT chip 24 and to the gate bonding pad 25 of the second IGBT chip 24. In addition, the second IGBT chip 2
In accordance with the additional arrangement of No. 4, the first emitter electrode pattern 1
5a and the anode bonding pad on one side of the diode chip 2 and between the second emitter electrode pattern 15b and the anode bonding pad on the other side of the diode chip 2 respectively. About twice as many metal wires 8 as the number of the metal wires 8 connected to the same place in this embodiment are bridge-connected. The configuration of the fifth embodiment is the same as the configuration of the second embodiment except for these components, so further description of the configuration of the fifth embodiment will be omitted.

The operation of the fifth embodiment is based on the IGBT chip 1
4 and the second IGBT chip 24 are connected in parallel, and the current capacity of this IGBT chip portion is slightly different from the second embodiment, but the second embodiment already described. Since it is obvious from the description of the operation of the example, the description of the operation of the fifth embodiment will be omitted.

According to the fifth embodiment, in addition to the effects expected from the second embodiment, the two IGBT chips 1 during operation are also provided.
4 and the second IGBT chip 24, there is no imbalance in the current flowing through each IGBT cell, the difference in temperature change due to heat generation of the metal wire 8 connected to each IGBT cell can be reduced, and the life of the solder layer 11 varies. Besides, the gate electrode pattern 23 is arranged in parallel with the second emitter electrode pattern 15b, so that the length direction of the power semiconductor device having the module structure (the length of the gate electrode pattern 23 etc. In the case where there is a limitation in the direction), the gate electrode 20 can be made common and the overall configuration can be made small, and the second emitter can be made smaller than the metal wire 8 connected to the gate electrode pattern 23 and having a small current capacity. Metal wire 8 with a large current capacity connected to the electrode pattern 15b
It can be expected that the effect of effectively preventing the deterioration can be expected.

Next, FIG. 6 is a structural view showing a sixth embodiment of the power semiconductor device according to the present invention, in which (a) is its top view and (b) is its top view. FIG. 3 is a cross-sectional view of the line portion of FIG. 2, in order to secure the insulating state of each electrode pattern of the second embodiment shown in FIG. 2, a second insulating plate is provided between the insulating plate 3 and each electrode pattern. Is arranged.

In FIGS. 6A and 6B, 26 is a second
Is an insulating plate, 27 is a solder layer, 28 is a second metal layer,
In addition, the same components as those shown in FIG. 2 are designated by the same reference numerals.

In the sixth embodiment, when the first and second emitter electrode patterns 15a and 15b in the second embodiment are formed on the insulating plate 3, in order to secure the insulation characteristic,
The second insulating plate 26 is arranged in between. That is,
The second metal layer 2 made of copper (Cu) foil or the like is formed on the insulating plate 3.
8 is joined, a second insulating plate 26 is joined and arranged on the second metal layer 28 via a solder layer 27, and further, a first insulating plate 26 is placed on the second insulating plate 26 via a solder layer 27. And the second
The emitter electrode patterns 15a and 15b are arranged in a junction. The configuration of the sixth embodiment is the same as the configuration of the second embodiment except for these components, so further description of the configuration of the sixth embodiment will be omitted.

The operation of the sixth embodiment is naturally obvious from the above-described explanation of the operation of the second embodiment.
The description of the operation of the embodiment is omitted.

According to the sixth embodiment, in addition to the effect that can be expected in the second embodiment, there is an effect that the insulation characteristics of the first and second emitter electrode patterns 15a and 15b with respect to the support substrate 1 are improved. Can be expected.

In the sixth embodiment, the second insulating plate 26 is used as the first and second emitter electrode patterns 15
Although the example in which the second insulating plate 26 is disposed in the a and 15b is described, the second insulating plate 26 may be similarly disposed in the gate electrode pattern 16.

In addition, in the sixth embodiment, when the anode current capacity of the diode chip 2 and the emitter current capacity of the IGBT chip 14 are large and heat is dissipated from the first and second emitter electrode patterns 15a and 15b, etc. , Second
Since the insulating plate 26 of FIG. 2 interferes with this heat radiation function, the second and third emitter electrode patterns 15a and 15b are not provided with the second.
Of the gate electrode pattern 1 without interposing the insulating plate 26 of
You may make it arrange | position the 2nd insulating plate 26 only in 6.

Further, FIG. 7 shows the IGBT chip 14 (and / or the second embodiment) in each of the second to sixth embodiments.
FIG. 6 is a top view showing another example of the arrangement state of each IGBT cell of the IGBT chip 24) of FIG.

In FIG. 7, the same components as those shown in FIG. 2 are designated by the same reference numerals.

In the seventh embodiment, the first two rows of emitter bonding pads 17 are formed on the first emitter electrode pattern 15a side of the IGBT chip 14 in parallel with the first emitter electrode pattern 15a. ,Also,
The IGBT cells are arranged on the second emitter electrode pattern 15b side so that the second two rows of the emitter bonding pads 17 are formed in parallel to the second emitter electrode pattern 15b, and are shared by the respective IGBT cells. The gate bonding pad 18 is formed in a substantially central portion.
Then, the first emitter electrode pattern 15a and the first 2
The metal wires 8 are bridge-connected to the emitter bonding pads 17 in the rows, and the metal wires 8 are also bridged to the second emitter electrode patterns 15b and the emitter bonding pads 17 in the second two rows. The metal wire 8 is also bridge-connected and also bridge-connected between the gate electrode pattern 16 and the common gate bonding pad 18.

In this case, each of the metal wires 8 is connected to the first and second rows of the emitter bonding pads 17, and the first and second emitter electrode patterns 1 are formed.
The length of the one connected to the emitter bonding pad 17 on the side closer to 5a and 15b is longer than the length connected to the emitter bonding pad 17 on the side far from the first and second emitter electrode patterns 15a and 15b. Although it is slightly longer than the above, it cannot be said that there is a large variation between the lengths of the metal wires 8 as a whole, and the IGBT chip 14 (shown in FIG. And / or it can be used in the same manner as the second IGBT chip 24) to exert the same function.

In each of the above-described embodiments, an example in which only the diode chip 2 is used as the semiconductor chip, and the diode chip 2 and one or more IGBT chips 1 are used.
However, the power semiconductor device of the present invention is not limited to the example using the diode chip 2 or the IGBT chips 14 and 24 as a semiconductor chip, and is known. Needless to say, a chip having another function of, for example, a GTO (gate turn off) thyristor chip may be used. In the power semiconductor device of the present invention, the number of semiconductor chips used is
The number of semiconductor chips is not limited to the number shown in each of the embodiments, and any number of semiconductor chips can be used.

[0055]

As described above, according to the present invention,
A plurality of rows of bonding pads 17 are arranged and formed on the semiconductor chips 2, 14, 24 in parallel, and the semiconductor chips are provided on both sides of the semiconductor chips 2, 14, 24 substantially parallel to the plurality of rows of bonding pads 17. 2, 14, 2
4 corresponding to the first and second electrode patterns 5a, 5b,
15a, 15b, 22a, 22b are respectively arranged, and between the first electrode patterns 5a, 15a, 22a and at least one row of bonding pads 17 arranged in proximity to the first electrode patterns 5a, 15a, 22a, Since the metal wires 8 are bridge-connected between the second electrode patterns 5b, 15b, 22b and at least one row of the bonding pads 17 arranged in the vicinity of the second electrode patterns 5b, 15b, 22b, respectively. , Semiconductor chips 2, 1
When viewed from 4, 24, the metal wires 8 are led out to both sides of the semiconductor chips 2, 14, 24, and moreover, the bonding pads 17 in each row and the corresponding electrode patterns 5 are formed.
The distance between a, 5b, 15a, 15b, 22a, and 22b is the shortest in terms of placement, the length of each metal wire 8 is minimum, and their lengths are substantially equal. There is.

According to the present invention, the semiconductor chip 2,
The length of each metal wire 8 connected to 14, 24 is short,
In addition, since they are substantially equal to each other, it is possible to largely eliminate the influence of vibration generation in the metal wire 8 and self-heating due to energization, and the life of these metal wires 8 is significantly improved as compared with the known ones. Therefore, there is an effect that it is possible to obtain a power semiconductor device having a small size and high reliability as a whole.

[Brief description of drawings]

FIG. 1 is a structural diagram showing a first embodiment of a power semiconductor device according to the present invention.

FIG. 2 is a structural diagram showing a second embodiment of the power semiconductor device according to the present invention.

FIG. 3 is a top view showing a third embodiment of the power semiconductor device according to the present invention.

FIG. 4 is a top view showing a fourth embodiment of the power semiconductor device according to the present invention.

FIG. 5 is a top view showing a fifth embodiment of the power semiconductor device according to the present invention.

FIG. 6 is a structural diagram showing a sixth embodiment of the power semiconductor device according to the present invention.

FIG. 7 is a top view showing another example of the arrangement state of each IGBT cell of the IGBT chip in each of the second to sixth embodiments.

FIG. 8 is a configuration diagram showing an example of known means for preventing an imbalance of current amounts in a semiconductor chip.

FIG. 9 is a top view showing an example of an arrangement of known power semiconductor devices having a modular structure.

[Explanation of symbols]

 1 Supporting Substrate 2 Diode Chip (Semiconductor Chip) 3 Insulating Plate 4 Cathode Electrode Pattern 4'Collector Electrode Pattern / Cathode Electrode Pattern 5a First Anode Electrode Pattern 5b Second Anode Electrode Pattern 6 Cathode Terminal 6'Collector Terminal / Cathode Terminal 7a First Anode Terminal 7b Second Anode Terminal 8 Metal Wire 9 Metal Foil 10, 11, 13, 27 Solder Layer 12 Solder Stop Slit 14 IGBT Chip (Semiconductor Chip) 15a First Emitter Electrode Pattern 15b Second Emitter Electrode pattern 15 'Common emitter electrode pattern 16 Gate electrode pattern 17 Emitter bonding pad 18 Gate bonding pad 19a First emitter terminal / first anode terminal 19b Second emitter terminal / second anode terminal 9'Common emitter terminal 20 Gate terminal 20 'Common gate terminal 21 Second IGBT chip 23 Gate electrode pattern 24 Second emitter bonding pad 25 Second gate bonding pad 26 Second insulating plate 28 Second metal layer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Shigeki Sekine, Inventor Shigaki Sekine, 1-1, Omika-cho, Hitachi-shi, Ibaraki Hitachi Research Laboratory, Hitachi Ltd. (72) Inventor Shinya Koike, 3-chome, Saiwaicho, Hitachi, Tokyo No. 1 Hitachi Ltd., Hitachi Works (72) Inventor Hideya Kokubun 3-10-2 Bentencho, Hitachi City, Tokyo Hitachi, Haramachi Electronics Co., Ltd.

Claims (8)

[Claims] 1. One or more semiconductor chips having a plurality of bonding pads, one or more electrode patterns provided in the vicinity of the semiconductor chips, a plurality of bonding pads of the semiconductor chip, and the electrodes corresponding thereto. A plurality of metal wires bridge-connected to a pattern, wherein the one or more semiconductor chips and the one or more electrode patterns are arranged on a common supporting substrate, A plurality of rows of bonding pads are arranged and formed in parallel on the semiconductor chip, and first and second electrode patterns corresponding to the semiconductor chips are arranged on both sides of the semiconductor chip substantially parallel to the bonding pads of each row. Between the first electrode pattern and at least one row of bonding pads adjacent to the first electrode pattern, and A power semiconductor device characterized in that a metal wire is bridgingly connected between the second electrode pattern and at least one row of bonding pads adjacent to the second electrode pattern. 2. A single bonding pad is provided on the semiconductor chip, and a third electrode pattern is arranged on one side of the semiconductor chip orthogonal to the arrangement direction of the first and second electrode patterns. The power semiconductor device according to claim 1, wherein the metal wire is bridge-connected between the bonding pad and the third electrode pattern. 3. A single bonding pad is provided on the semiconductor chip, and a third bonding pad is provided outside one of the first and second electrode patterns in parallel with the first and second electrode patterns. 2. The power semiconductor device according to claim 1, wherein the electrode pattern is arranged, and the metal wire is bridge-connected between the single bonding pad and the third electrode pattern. 4. The semiconductor chip comprises a voltage control type transistor, and the independent bonding pad and the third electrode pattern are for control electrodes of the voltage control type transistor. Through 3
The power semiconductor device according to any one of 1. 5. The two or more semiconductor chips are arranged in parallel on the common support substrate, and the first and second electrode patterns are arranged on both sides of these semiconductor chips, respectively. 1. The power semiconductor device according to 1. 6. Two or more of the semiconductor chips are arranged in parallel on the common support substrate, one of two electrode patterns provided between two semiconductor chips adjacent to each other is omitted, and the other of the two is arranged as the above-mentioned. The power semiconductor device according to claim 1, wherein the power semiconductor device is shared by two semiconductor chips. 7. At least one of the first to third electrode patterns has a high insulation resistance structure which is arranged on the supporting substrate via an additional insulating plate. Item 2. The power semiconductor device according to Item 1. 8. The semiconductor chip comprises a voltage control type transistor, and only the third electrode pattern for a control electrode of the voltage control type transistor is disposed on the supporting substrate via the additional insulating plate. The power semiconductor device according to claim 1, wherein the power semiconductor device has an insulating structure.