JP2001007275A - Semiconductor device and test method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is assembled into a package that is so structured as to be tested as well as a wafer is tested even after a product is finished and a test method of the same. SOLUTION: A package opening 9 is provided so as to make all or some of test terminals 2 formed on the semiconductor device chip 10 exposed or a contact electrically connected to a test chip terminal is provided. The test terminals 2 are used only when a wafer is tested and serve as chip terminals which are not brought into contact when packaging is carried out. A pad or a contact is required to be sealed up with a sealing insulating resin 7 so as to improve a semiconductor device in reliability when packaging is carried out, and a product can be tested as well as a wafer is tested by partially removing the sealing insulating resin 7. A nearly-finished product can be tested through the same way as a wafer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device assembled in a package having a structure capable of performing a test equivalent to a wafer test even after a product is completed, and a test method therefor.

[0002]

2. Description of the Related Art In a semiconductor device, a designing process for designing a semiconductor device, a wafer forming process for growing a semiconductor single crystal such as silicon in an ingot and slicing the same to obtain a wafer, forming a thin film on the wafer, and oxidizing the wafer. A product is obtained through a wafer processing step of forming a plurality of semiconductor elements (semiconductor chips, hereinafter referred to as chips) on a wafer by performing processing, doping, etc., an assembling step of separating and packaging chips from the wafer, and an inspection step. .

FIG. 8 shows a conventional BGA (Ball Grid Array).
FIG. 1 is a plan view of a semiconductor device sealed with a type package, and a cross-sectional view taken along a line AA ′ in the plan view.
For example, two rows of external connection terminals 101 electrically connected to an integrated circuit inside the chip are formed in a central region of a main surface of a semiconductor substrate 100 such as silicon constituting the chip. If the semiconductor device is a memory, this 2
A fuse element group may be arranged and formed between the external connection terminals 101 in a column. The main surface of the chip 100 is covered with a BGA type package 103. The BGA type package 103 includes, for example, an insulating sheet 103a of polyimide or the like and an insulating protective sheet 103b. On one surface of the insulating sheet 103a, a conductor wiring 108 such as a copper foil pattern is formed, and a conductor wiring 108 is formed.
And an external electrode 104 such as a solder ball that is electrically connected to an external circuit. Conductor wiring 10
8 is protected by a protection sheet 103b. The back surface of the insulating sheet 103a is affixed to the main surface of the chip 100, thereby protecting the main surface. The package 103 has an opening 105 formed in a central region of the main surface of the chip 100. And this opening 1
At 05, the leads 106 connected to the two rows of pad-shaped external connection terminals 101 and the conductor wiring 108 and bonded to the external connection terminals 101 are exposed. The opening 105 is sealed with an insulating resin sealing body 107 such as an epoxy resin after the conductor wiring 108 is bonded.

[0004]

Generally, various characteristics such as electric characteristics, temperature characteristics, and frequency characteristics are different between a chip in a wafer state and a device completed product in which the chip is separated from the wafer and assembled into a package. Further, in a process of assembling into a package or in a burn-in process performed on a completed device, a change in characteristics or a failure may occur in a chip. However,
After assembling the package by sealing the chip with resin with an insulator or attaching an elastic sheet with external electrodes such as solder balls to the chip, the test chip terminals are sealed and the wafer The same test as the state (corresponding to the current die-sword test) cannot be performed,
Therefore, at present, the degree of freedom of the test is reduced.

[0005] In addition, since a test using a test pad cannot be performed in a package state, if a chip defect is found in a package state, it is determined whether screening has been performed due to the defect, that is, after performing the packaging, It was difficult to analyze whether it was a deterioration failure caused by packaging or a burn-in test, or whether the screening was not completed. Therefore, when such a defect is exchanged and repaired by screening or fuse cutting in a test, the defect has to be reproduced in a package state, and such a test item must be added to check the progress. Of course, this leads to an increase in test time. If this is not permissible, screening will be performed by product testing. The present invention has been made in view of the above circumstances, and provides a semiconductor device assembled in a package having a structure capable of performing a test equivalent to a wafer test even after a product is completed, and a method of testing the semiconductor device.

[0006]

According to the present invention, a package opening for exposing a test terminal is present on all or a part of a test terminal formed on a chip of a semiconductor device. Or the presence of a contact portion that is electrically connected to the test chip terminal. The test terminal is a chip terminal that is used only during a wafer test and is not contacted during packaging. In order to increase reliability, this pad or contact part must be sealed with an insulator during packaging, but after sealing, by removing this insulator partially, it is the same as during wafer testing Can be performed on products. Small opening,
If the effect of this opening or contact on the package before and after encapsulation is small due to the small contact area, etc., various characteristics such as electrical characteristics, temperature characteristics, and frequency characteristics equivalent to those of the completed package Can be expected, and a wafer test can be performed in a state close to a finished product.

That is, a semiconductor device according to the present invention comprises: a semiconductor chip having an external connection terminal and at least one test terminal formed on a main surface; and a semiconductor chip formed on the main surface and covering the external terminal and the test terminal. An insulating sealing body to protect;
A first feature is that the insulating sealing body has an opening embedded therein so that at least one of the test terminals is disposed therein. Further, the semiconductor device of the present invention includes a semiconductor chip having an external connection terminal and at least one test terminal formed on a main surface thereof, and an insulating chip formed on the main surface and covering and protecting the external terminal and the test terminal. A sealing body, and an insulator embedded in an opening formed in the insulating sealing body, wherein the test terminal and the external connection terminal are arranged in the opening. The feature is.
A fuse element electrically connected to an integrated circuit inside the semiconductor chip may be formed on the main surface, and the fuse element may be arranged in the opening. The insulator embedded in the opening may be softer than the insulating sealing body.

In the method of testing a semiconductor device according to the present invention, an external connection terminal and at least one test terminal are formed on a semiconductor chip on a main surface, and an insulating seal for covering and protecting the external terminal and the test terminal. Forming an opening in the body such that at least one of the test terminals is disposed therein; testing the semiconductor chip through the test terminal in the opening; And a step of sealing the opening by embedding an insulator in the substrate, and a step of covering a contact portion of the test terminal with an insulator. A fuse element electrically connected to an integrated circuit inside the semiconductor chip is further formed on the main surface, and the external connection terminal or the fuse element and the external connection terminal are arranged in the opening. You may be.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 1 and FIG.
An example will be described. FIG. 1 is a plan view of a semiconductor device sealed with a BGA type package and FIG.
FIG. 2 is a cross-sectional view of a semiconductor device illustrating a test method along a line A-A ′. For example, two rows of external connection terminals electrically connected to an integrated circuit inside the chip are formed in a central area of a main surface of a semiconductor substrate 10 made of silicon or the like constituting the chip. A pad-shaped non-connection chip terminal 2 for testing is provided on the main surface of the chip 10.
Are formed at appropriate positions. When the semiconductor device is a memory or the like, a fuse element group may be formed between the two rows of external connection terminals 1 in some cases. Chip 10 main surface is BG
It is covered with an A type package 3. This B
The GA type package 3 includes an insulating sheet 3a and an insulating protective sheet 3b. On one surface of the insulating sheet 3a, a conductor wiring 8 such as a copper foil pattern is formed and connected to the conductor wiring 8, so that an external circuit is formed. An external electrode 4 such as a solder ball electrically connected to the external electrode 4 is formed. The conductor wiring 8 is protected by the protection sheet 3b. The back surface of the insulating sheet 3a is attached to the main surface of the chip 10, thereby protecting the main surface. The external connection terminal 1 and the conductor wiring 8 are electrically connected by a lead or a wire 6.

An opening 5 is formed in the package 3 in a central region of the main surface of the chip 10. Then, the lead 6 connected to the external connection terminal 1 group and the conductor wiring 8 and bonded to the tip of the external connection terminal 1 is exposed in the opening 5. The group of external connection terminals 1 in the opening 5 is formed and arranged in the external connection terminal area. An opening 9 is formed at an appropriate position in the package 3 so that the non-connection chip terminal 2 is disposed inside. The non-connection chip terminals 2 in the opening 9 are formed and arranged in the non-connection chip terminal area. The opening 5 is provided with an insulating sealing body 7 such as an epoxy resin after the conductor wiring 8 is bonded.
The opening 9 is sealed with an insulating sealing body 11 such as an epoxy resin. The sealing body 7 of the opening 5 and the sealing body 11 of the opening 9 may be made of the same material or different from each other. It is clear that the workability is higher when the materials are the same. In this embodiment, the opening in which the non-connection chip terminals for testing are arranged is provided in a region where the external electrodes of the solder balls exist. In FIG. 1, the opening, the external connection terminal, and the non-connection chip terminal are illustrated in a large size for the sake of convenience of viewing. The area is smaller,
The opening is opened as much as necessary to contact the external connection terminal and the non-connection chip terminal. With such a configuration, when the package is assembled with the opening part opened, characteristics equivalent or similar to those of the finished product can be obtained.

The test non-connection chip terminal is first tested before sealing the opening with an insulating sealing body, and then sealing the opening. Also, in order to make contact after the non-connection chip terminal is sealed with an insulating sealing body, use an insulating sealing body that can be melted with a chemical or the like, remove the insulating sealing body with a chemical or the like, and reduce contact with the needle. And test. Alternatively, as shown in FIG. 2, various test methods are possible, such as making contact by piercing a needle using a softer insulator than the package. FIG. 2 is a sectional view of a semiconductor substrate (chip) showing a state of a non-connected chip terminal portion. An opening 9 is formed at an appropriate position in the package 3 for covering and protecting the main surface of the semiconductor substrate 10 so that the non-connection chip terminal 2 is disposed inside. The non-connection chip terminals 2 in the opening 9 are formed and arranged in a non-connection chip terminal region as shown in FIG. The opening 9 is sealed with an insulating sealing body 14 such as an epoxy resin. Sealing body 14
Are made of an insulator softer than the package 3. The probe 15 is passed through the sealing body 14 to connect the non-connected chip terminals 2.
Contact. And then test. In this embodiment, the workability is improved because the sealing body is not removed during the test.

Next, a second embodiment will be described with reference to FIG. FIG. 3 is a plan view of the semiconductor device and FIG.
It is sectional drawing of the part which follows the A 'line. The package of this embodiment includes a resin sealing body 23 such as an epoxy resin. A group of external connection terminals 21 electrically connected to an integrated circuit inside the chip is formed in a peripheral area of a main surface of a semiconductor substrate 20 such as silicon constituting the chip. On the main surface of the chip 20, pad-shaped non-connection chip terminals 22 for testing are formed at appropriate positions. The main surface of the chip 20 is TSOP (Thin Small Outline Packag
e) It is covered with a resin sealing body 23 which is a type package. This resin sealing body 23 is formed by a normal molding method using a molding device. In this embodiment, external leads 24 obtained from a lead frame are used as external electrodes instead of the solder bowl used in the BGA type package shown in FIG. The chip 20 is mounted on a lead frame (not shown).
Is connected to the external connection terminal 21 with a bonding wire 26 such as an aluminum wire, and in this state, the lead frame is mounted on a mold of a molding apparatus such that the external lead end is exposed. Then, a resin sealing body 23 is formed by filling a mold with resin by a transfer molding method.

An opening 28 is formed in the resin sealing body 23 at a predetermined position on the main surface of the chip 20. The non-connection chip terminals 22 in the opening 28 are formed and arranged in the non-connection chip terminal area 25. The opening 28 is sealed with an insulating sealing body 27 such as an epoxy resin. The opening 28 is formed so that such an opening is formed when it is molded by a mold, or the opening is formed by etching or the like after forming a resin sealing body having no opening. In this state, a test using test terminals equivalent to the wafer test can be performed. The opening is sealed with an insulating resin sealing body after the test test. In the figure, the fuse region and the opening are shown large for the sake of convenience.
In order to make contact after sealing the chip terminal with an insulator, as in the first embodiment, use an insulative resin sealed body that can be melted with a chemical or the like, remove this with a chemical or the like, and contact the needle. do. Alternatively, as shown in FIG. 2, a contact can be made by piercing a needle using a soft insulator.

Next, a third embodiment will be described with reference to FIGS. FIG. 4 is a plan view of a semiconductor device sealed with a BGA type package, and AA ′ in this plan view.
FIG. 5 is a cross-sectional view of a semiconductor device illustrating a test method along a line. An external connection terminal 31 electrically connected to an integrated circuit inside the chip is provided in a central area of a main surface of a semiconductor substrate 30 such as silicon constituting the chip.
Groups are formed. On the main surface of the chip 30, pad-shaped non-connection chip terminals 32 for testing are formed at appropriate positions. When the semiconductor device is a memory or the like, the main surface of the chip 30 is covered with a BGA type package 33. This BGA type package 33
Is composed of an insulating sheet 33a and an insulating protective sheet 33b. On one surface of the insulating sheet 33a, a conductor wiring 38 such as a copper foil pattern is formed and connected to the conductor wiring 38 to be electrically connected to an external circuit. External electrodes 34 such as solder balls to be formed are formed. The conductor wiring 38
It is protected by the protection sheet 33b. Insulation sheet 3
The back surface of 3a is attached to the main surface of the chip 30,
This protects the main surface. The external connection terminal 31 and the conductor wiring 38 are electrically connected by a lead or a wire 36. In addition, on the surface of the insulating sheet 33a where the conductor wiring 38 is formed, the conductor wiring 18 made of the same copper foil pattern is formed, and the pad-shaped contact portion 16 connected to the conductor wiring 18 is formed. . The conductor wiring 18 is covered and protected by the protection sheet 33b, but the contact portion 16 is
b. Therefore, the contact portion 16
Are protected by an insulator 17 made of an insulating sheet or a dip resin. The unconnected chip terminals 32 and the conductor wirings 18 are electrically connected by leads or wires 13.

An opening 35 is formed in the package 33 in a central region of the main surface of the chip 30. The opening 35 has a group of external connection terminals 31 and conductor wiring 38.
And the lead 36 bonded to the tip of the external connection terminal 31 is exposed. Opening 35
Are formed and arranged, for example, in the external connection terminal area. An opening 39 is formed at an appropriate position in the package 33 so that the non-connection chip terminal 32 is disposed inside. The non-connection chip terminals 32 in the opening 39 are formed and arranged in the non-connection chip terminal area.
The opening 35 is sealed with an insulating sealing body 37 such as an epoxy resin after the conductor wiring 38 is bonded, and the opening 39 is sealed with an insulating sealing body 12 such as an epoxy resin. I have. The sealing body 37 of the opening 35 and the sealing body 12 of the opening 39 may be made of the same material or different from each other. It is clear that the workability is higher when the materials are the same. In this embodiment, the opening in which the non-connection chip terminals for testing are arranged is provided in a region where the external electrodes of the solder balls exist. In FIG. 4, the opening, the external connection terminal, and the non-connection chip terminal are illustrated in a large size for the sake of convenience of viewing, but the area of the external connection terminal region and the non-connection chip terminal region is actually smaller, and the opening is Open as much as necessary to make contact with external connection terminals and unconnected chip terminals.
With such a configuration, when the package is assembled with the opening part opened, characteristics equivalent or similar to those of the finished product can be obtained.

The test non-connection chip terminal is first tested before sealing the contact portion with an insulator, and then sealing the opening. In order to make a contact after sealing the contact portion with an insulator, use an insulator that can be melted with a chemical or the like, remove the insulating material with a chemical or the like, touch the needle, and then seal again. Various test methods are possible. In this way, by covering the contact portion with the insulator, there is no need to worry about leakage to the external connection terminal for test, and reliability can be improved. As shown in FIG.
In the case of performing a test test using a non-connecting chip terminal for testing, measurement is performed by taking a contact with a probe 15 having an appropriate shape before covering the contact portion 16 of the non-connecting chip terminal 32 with an insulator. Thereafter, this is covered and protected by an insulator 17 (FIG. 5A). Another method is to cover and protect the contact portion 16 with a soft insulator 17a such as a silicone resin. Thereafter, the probe 15 is applied to the contact portion 16 by penetrating the insulator 17a, thereby making contact and measuring (FIG. 5B). At this time, the insulator 17a is removed by a chemical before measurement.
Alternatively, it may be peeled off by scratching. In addition, the shape of the insulator is drawn thicker than it actually is, but in reality, the thickness is such that it does not hinder the solder ball when it is welded and mounted on a wiring board.

Next, a fourth embodiment will be described with reference to FIGS. FIG. 6 is a perspective view of the wafer in which the chip region is formed, and an enlarged perspective view of the wafer in which the chip region is enlarged and the main surface shows the wiring. FIG. 7 is along the line AA ′ in FIG. 6B. It is sectional drawing of a part. In this embodiment, the contact portion of the non-connection chip terminal has a structure separated from the non-connection chip terminal on the insulating sheet. The chip area 40a is formed, and the silicon wafer 40 partitioned for each chip area by the dicing line is packaged as shown in FIG. 6B. That is, the main surface of the wafer 40 is
It is covered with the protection sheet 43b.

FIG. 7 is a sectional view of a semiconductor device sealed with a BGA type package. On a main surface of a semiconductor substrate 40a made of silicon or the like constituting a chip, a group of external connection terminals 41 and test non-connection chip terminals 42 electrically connected to an integrated circuit inside the chip is formed in a central region thereof. I have. That is, as shown in FIG. 6B, a plurality of external connection terminal / non-connection chip terminal regions 54 are formed in the central region on the main surface of the chip 30. Further, a fuse region 55 is formed between the regions 54, and a fuse element group is formed in this region. The main surface of the chip 40a is covered with a BGA type package 43. The package 43 includes, for example, an insulating sheet 43a of polyimide or the like and an insulating protective sheet 43b. On one surface of the insulating sheet 43a, a conductor wiring 48 such as a copper foil pattern is formed and connected to the conductor wiring 48. An external electrode 44 such as a solder ball electrically connected to an external circuit is formed. The conductor wiring 48 is protected by the protection sheet 43b. Insulating sheet 43
The back surface of a is attached to the main surface of the chip 40a,
This protects the main surface. The external connection terminal 41 and the conductor wiring 48 are electrically connected by a lead or a wire 46.

On the surface of the insulating sheet 43a where the conductor wiring 48 is formed, a conductor wiring 53 composed of the same copper foil pattern is formed, and a pad-shaped contact portion 50 connected to the conductor wiring 53 is formed. Have been. The conductor wiring 53 is covered and protected by the protection sheet 43b, but the contact portion 50 is exposed from the protection sheet 43b. Therefore, the contact portion 50 is protected by the insulator 51 made of an insulating sheet or a dip resin. The non-connection chip terminal 42 and the conductor wiring 53 are electrically connected by a lead or a wire 52. An opening 45 is formed in the package 43 in a central region of the main surface of the chip 40a. The external connection terminal 31 and the non-connection chip terminal 42, the leads or wires 46 and 52, and the fuse element are formed and arranged inside the opening 35. External connection terminal 4 of opening 45
1 and the non-contact chip terminal 42 are formed and arranged in the external connection terminal / non-contact chip terminal area 54, and the fuse element
It is formed in the fuse region 55. The opening 45 is sealed with an insulating sealing body 47 such as epoxy resin after the leads or wires 46 and 52 are bonded.

In FIG. 6, the opening, the external connection terminal, and the non-connection chip terminal are shown in a large size for the sake of simplicity. Are open as much as necessary to contact the external connection terminals and the non-connection chip terminals. With such a configuration, when the package is assembled with the opening portion opened, characteristics equivalent or similar to those of the finished product can be obtained. In this embodiment, an assembling step of cutting out a completed device from a wafer after assembling the package is employed. FIG. 6 shows a wafer in a process in which an opening and a contact portion of a test chip terminal are sealed with an insulating resin, and the finished product is cut out by a dicing line. In this way, if the fuse element can be cut after packaging and the packaging and burn-in tests are performed before the test, the wafer test can be performed closer to the finished product after the deterioration of the characteristics due to these. it can. Furthermore, when assembling into a package in the wafer state and finally taking the assembly process of cutting out the device finished product, if redundancy repair by fuse cut, fuse trimming for characteristic change etc. should be finally performed, It is also possible to simplify or eliminate the current die / sword test.

Further, since the finished product is sealed with an insulator, there is no problem in terms of reliability. Further, even in the case of a product test or when a defective product returns, all tests (characteristic test, product test, etc.) can be performed by removing the insulator covering the opening or the contact portion. Therefore, the feedback of the failure analysis is made more efficient. Even if a defect occurs in a product test or a market defect occurs, a wafer test can be performed as it is, so that the cause can be easily analyzed. If it does not fail in the wafer test, it means that screening has not been completed, and it is necessary to change or add test items.If it does not fail in the wafer test, it is due to deterioration because it is due to deterioration. Review will be required.

[0022]

As described above, according to the present invention, the test under the same conditions can be performed in both the wafer state and the package state, the correlation between the tests in each process can be easily obtained, the feedback can be easily performed, the test efficiency and the test efficiency can be improved. It leads to an improvement in yield.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device sealed with a BGA type package of the present invention, and a cross-sectional view of a portion along a line AA ′ in the plan view.

FIG. 2 is a cross-sectional view of a semiconductor device illustrating a test method of the present invention.

FIG. 3 is a plan view of a semiconductor device of the present invention and FIG.
Sectional drawing of the part which follows the A 'line.

FIG. 4 is a plan view of a semiconductor device sealed with a BGA type package of the present invention, and a cross-sectional view of a portion taken along line AA ′ in the plan view.

FIG. 5 is a sectional view of a semiconductor device illustrating a test method of the present invention.

FIG. 6 is a perspective view of a wafer in which a chip region is formed according to the present invention and an enlarged perspective view of the wafer in which the chip region is enlarged and a main surface is shown with wiring.

FIG. 7 is a cross-sectional view of a portion along the line AA ′ in FIG. 6 (b).

FIG. 8 is a plan view of a semiconductor device sealed with a conventional BGA type package, and a cross-sectional view of a portion along a line AA 'in the plan view.

[Explanation of symbols]

1, 21, 31, 41, 101 ... external connection terminals,
2, 22, 32, 42 ... non-contact chip terminals for testing, 3, 23, 33, 43, 103 ... packages,
3a, 33a, 43a, 103a ... insulating sheet, 3
b, 33b, 43b, 103b ... Protective sheet, 4,
34, 44, 104 ... external electrodes (solder balls),
5, 9, 28, 35, 39, 45, 105 ... opening, 6, 13, 36, 46, 52, 106 ... lead or wire, 7, 11, 12, 14, 27, 37,
47 ... insulating sealing body, 8, 18, 38, 48, 5
3, 108 ... conductor wiring, 10, 20, 30, 40
a, 100: chip (semiconductor substrate), 15: probe, 16: contact part, 17, 17a ...
Insulator, 24 ... external lead (external electrode), 25
... non-contact chip terminal area, 26 ... bonding wire, 40 ... wafer, 54 ... external connection terminal / non-contact chip terminal, 55 ... fuse area.

Claims (6)

[Claims] A semiconductor chip having an external connection terminal and at least one test terminal formed on a main surface thereof; and an insulating sealing body formed on the main surface and covering and protecting the external terminal and the test terminal. And an insulator in which an opening formed in the insulating sealing body is embedded so that at least one of the test terminals is disposed therein. 2. A semiconductor chip having an external connection terminal and at least one test terminal formed on a main surface thereof, and an insulating sealing body formed on the main surface and covering and protecting the external terminal and the test terminal. And an insulator embedded in an opening formed in the insulating sealing body, wherein the test terminal and the external connection terminal are disposed in the opening. 3. A fuse element electrically connected to an integrated circuit in the semiconductor chip is formed on the main surface, and the fuse element is disposed in the opening. The semiconductor device according to claim 1. 4. The insulator embedded in the opening is softer than the insulating sealing body or can be removed from the opening. 3. The semiconductor device according to claim 1. 5. A step of forming an external connection terminal and at least one test terminal on a semiconductor chip on a main surface, an insulating sealing body for covering and protecting the external terminal and the test terminal, Forming an opening such that at least one of the terminals is disposed; testing the semiconductor chip through the test terminal in the opening; and embedding an insulator in the opening to form the opening. A method for testing a semiconductor device, comprising: sealing a portion; and covering the test terminal with a contact portion insulator. 6. A fuse element electrically connected to an integrated circuit inside the semiconductor chip is further formed on the main surface, and the external connection terminal or the fuse element and the external connection terminal are formed in the opening. The test method for a semiconductor device according to claim 5, wherein the test method is arranged in a unit.